Can bus circuit, can bus communication method and device, readable storage medium

Abstract

The application provides a CAN bus circuit, a CAN bus communication method and device, and a readable storage medium.The CAN bus circuit comprises a plurality of processors, a first diode, an anode of which is connected with a data receiving port of a first processor in the plurality of processors, and a cathode of which is connected with a data sending port of the first processor, a second diode, an anode of which is connected with a data receiving port of a second processor in the plurality of processors, and a cathode of which is connected with a data sending port of the second processor, a third diode, an anode of which is connected with a data receiving port of a third processor in the plurality of processors, and a cathode of which is connected with a data sending port of the third processor, and a pull-up resistor, a first end of which is connected with a power supply, and a second end of which is connected with the anodes of the first diode, the second diode and the third diode and the data receiving ports of each processor.Thus, the three diodes and the pull-up resistor are used to replace the CAN drive chip in the traditional CAN bus circuit, so that the hardware cost of the CAN bus communication is reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a CAN bus circuit, a CAN bus communication method and apparatus, and a readable storage medium. Background Technology

[0002] In home energy storage product projects, there are scenarios where multiple CAN bus modules are connected in parallel via CAN (Controller Area Network). Currently, to improve communication speed, communication between two or more MCUs (Micro Control Units) or CPUs (Central Processing Units) on the same CAN bus module or between multiple CAN bus modules typically uses CAN interface communication.

[0003] Specifically, such as Figure 2 As shown, communication between two or more MCUs or CPUs is achieved through an external CAN driver chip. However, the high cost of CAN driver chips increases the hardware cost of CAN bus communication. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0005] Therefore, the first aspect of the present invention is to provide a CAN bus circuit.

[0006] The second aspect of the present invention is to provide a CAN bus communication method.

[0007] The third aspect of the present invention is to provide a CAN bus communication device.

[0008] A fourth aspect of the invention is to provide another CAN bus communication device.

[0009] The fifth aspect of the present invention is to provide a readable storage medium.

[0010] In view of the above, according to one aspect of the present invention, a CAN bus circuit is provided, the circuit comprising: a plurality of processors, each processor including a data transmission port for transmitting signals and a data reception port for receiving signals; a first diode, the anode of the first diode being connected to the data reception port of the first processor among the plurality of processors, and the cathode of the first diode being connected to the data transmission port of the first processor; a second diode, the anode of the second diode being connected to the data reception port of the second processor among the plurality of processors, and the cathode of the second diode being connected to the data transmission port of the second processor; a third diode, the anode of the third diode being connected to the data reception port of the third processor among the plurality of processors, and the cathode of the third diode being connected to the data transmission port of the third processor; and a pull-up resistor, the first end of the pull-up resistor being connected to a power supply, and the second end of the pull-up resistor being connected to the anode of the first diode, the anode of the second diode, the anode of the third diode, and the data reception port of each processor.

[0011] Specifically, the CAN bus circuit provided by the present invention includes multiple processors, a first diode, a second diode, a third diode, and a pull-up resistor.

[0012] Each processor includes a data transmission port for sending signals and a data reception port for receiving signals.

[0013] Furthermore, the multiple processors include a first processor, a second processor, and a third processor.

[0014] Furthermore, the anode of the first diode is connected to the data receiving port of the first processor, the data receiving port of the second processor, and the data receiving port of the third processor, and the cathode of the first diode is connected to the data transmitting port of the first processor.

[0015] Furthermore, the anode of the second diode is connected to the data receiving port of the second processor, the data receiving port of the first processor, and the data receiving port of the third processor, and the cathode of the second diode is connected to the data transmitting port of the second processor.

[0016] Furthermore, the anode of the third diode is connected to the data receiving port of the third processor, the data receiving port of the first processor, and the data receiving port of the second processor, and the cathode of the third diode is connected to the data transmitting port of the third processor.

[0017] Furthermore, the first end of the pull-up resistor is connected to the power supply, and the second end of the pull-up resistor is connected to the anode of the first diode, the anode of the second diode, the anode of the third diode, the data receiving port of the first processor, the data receiving port of the second processor, and the data receiving port of the third processor.

[0018] In this way, the data receiving ports of multiple processors are connected, and the signal levels of the data receiving ports of multiple processors are consistent.

[0019] Understandably, in traditional CAN bus circuits, communication between two or more MCUs or CPUs is achieved through an external CAN driver chip. However, in a CAN network architecture with a single CAN bus module, due to the low signal interference and short line length on the same CAN bus module, the differential level interference immunity requirement of the CAN driver chip is not significant. Therefore, if the loopback function provided by the CAN driver chip can be implemented, an external CAN driver chip can be eliminated.

[0020] Based on this, the present invention provides a CAN bus circuit. During the operation of the CAN bus circuit, the loopback function provided by the CAN driver chip in the traditional CAN bus circuit is realized through a first diode, a second diode, a third diode, and a pull-up resistor. In this way, the CAN driver chip in the traditional CAN bus circuit can be replaced by three diodes and one pull-up resistor, reducing the hardware cost of CAN bus communication, improving the cost competitiveness of the CAN bus circuit, and reducing the layout and wiring density of the CAN bus circuit.

[0021] The CAN bus circuit according to the present invention may also have the following additional technical features:

[0022] In some technical solutions, optionally, when the first processor sends a low-level signal, the second processor sends a high-level signal, and the third processor does not send a signal, the receiving signal level of the data receiving ports of the first processor, the second processor, and the third processor is pulled low by the first diode.

[0023] In this technical solution, during the operation of the CAN bus circuit, when the data transmission port of the first processor sends a low-level signal, the data transmission port of the second processor sends a high-level signal, and the data transmission port of the third processor does not transmit signals, the first diode can pull down the level of the received signal at the data receiving ports of the first, second, and third processors. Specifically, the high-level signal transmitted by the data transmission port of the second processor will not affect the low level of the received signal at the data receiving port due to the reverse cutoff of the second diode.

[0024] In some technical solutions, optionally, if the levels of the transmitted signal and the received signal of any processor are inconsistent, the data transmission port of any processor shall stop transmitting signals.

[0025] In this technical solution, during the operation of the CAN bus circuit, for any processor, the data receiving port of the processor detects whether the level of the transmitted signal and the received signal of each processor are consistent. If the level of the transmitted signal and the received signal of the processor are inconsistent, it indicates that a race conflict has occurred on the CAN communication bus. At this time, the data transmitting port of the processor will stop transmitting signals and only receive external signals through the data receiving port.

[0026] In some technical solutions, optionally, if the levels of the transmitting and receiving signals of any processor are consistent, the data transmitting port of any processor continues to transmit signals until a CAN frame is completely transmitted.

[0027] In this technical solution, during the operation of the CAN bus circuit, for any processor, the data receiving port of the processor detects whether the level of the transmitted signal and the received signal of each processor are consistent. If the level of the transmitted signal and the received signal of the processor are consistent, the data transmitting port of the processor will continue to transmit the signal until a complete CAN frame is transmitted.

[0028] In some technical solutions, optionally, multiple processors receive CAN frames through a data receiving port, and multiple processors parse CAN frames, but only the processor corresponding to the CAN frame address responds to the CAN frame.

[0029] In this technical solution, each processor receives CAN frames through a data receiving port, and each processor parses CAN frames. However, only the processor corresponding to the CAN frame address responds to the received CAN frame among the multiple processors.

[0030] According to a second aspect of the present invention, a CAN bus communication method is proposed, which is applied to the CAN bus circuit in any of the above-mentioned technical solutions. The method includes: controlling a first processor to send a low-level signal, a second processor to send a high-level signal, and a third processor not to send a signal, so as to pull down the level of the received signal of each processor; comparing the received signal and the transmitted signal of each processor to obtain the signal comparison result corresponding to each processor; and controlling the signal transmission state of each processor according to the signal comparison result of each processor.

[0031] Specifically, in the CAN bus communication method provided by this invention, during the operation of the CAN bus circuit, the first processor is controlled to send a low-level signal, the second processor sends a high-level signal, and the third processor does not send a signal, so as to pull down the level of the received signal of each processor through the first diode in the CAN bus circuit. Further, the levels of the received signal and the transmitted signal of each processor are compared to obtain the signal comparison result corresponding to each processor, and then the signal transmission state of each processor is controlled according to the signal comparison result of each processor. In this way, the loopback function provided by the CAN driver chip can be realized without the need for a CAN driver chip, reducing the hardware cost of CAN bus communication, improving the cost competitiveness of the CAN bus circuit, and reducing the layout and wiring density of the CAN bus circuit.

[0032] The CAN bus communication method according to the present invention may also have the following additional technical features:

[0033] In some technical solutions, optionally, the signal transmission state of each processor is controlled according to the signal comparison result of each processor, including: controlling the processor to stop transmitting signals when the level of the processor's transmitted signal is inconsistent with the level of the received signal; and controlling the processor to continue transmitting signals when the level of the processor's transmitted signal is consistent with the level of the received signal, until a CAN frame is completely transmitted.

[0034] In this technical solution, during the process of controlling the signal transmission state of each processor based on the signal comparison results of each processor, for each processor, if the level of the processor's transmitted signal and the level of the received signal are inconsistent, the processor is controlled to stop transmitting signals; and if the level of the processor's transmitted signal and the level of the received signal are consistent, the processor is controlled to continue transmitting signals until a complete CAN frame is transmitted.

[0035] Specifically, during the operation of the CAN bus circuit, when the first processor sends a low-level signal, the second processor sends a high-level signal, and the third processor does not send any signals, the second processor's received signal is low. Since the levels of the second processor's transmitted and received signals are inconsistent, the second processor will stop sending signals and only receive external signals. Furthermore, when the first processor's received signal is low, and the levels of the first processor's transmitted and received signals are consistent, the first processor will continue sending signals until a complete CAN frame is transmitted.

[0036] In some technical solutions, optionally, each processor receives and parses the CAN frame, but only the processor corresponding to the CAN frame address responds to the CAN frame.

[0037] In this technical solution, each processor receives CAN frames through a data receiving port, and each processor parses CAN frames. However, only the processor corresponding to the CAN frame address responds to the received CAN frame among the multiple processors.

[0038] According to a third aspect of the present invention, a CAN bus communication device is provided, which is applied to the CAN bus circuit in any of the above-described technical solutions. The device includes: a control unit, which controls a first processor to send a low-level signal, a second processor to send a high-level signal, and a third processor not to send a signal, so as to pull down the level of the received signal of each processor; a processing unit, which compares the received signal and the transmitted signal of each processor to obtain a signal comparison result corresponding to each processor; and the control unit is further configured to control the signal transmission state of each processor according to the signal comparison result of each processor.

[0039] The CAN bus communication device provided by this invention includes a control unit and a processing unit. During the operation of the CAN bus circuit, the control unit controls the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor to not send a signal, thereby pulling down the received signal level of each processor through a first diode in the CAN bus circuit. Further, the processing unit compares the received signal and the transmitted signal level of each processor to obtain the signal comparison result for each processor. The control unit then controls the signal transmission state of each processor based on the signal comparison result. In this way, the loopback function provided by the CAN driver chip can be achieved without the need for a CAN driver chip, reducing the hardware cost of CAN bus communication, improving the cost competitiveness of the CAN bus circuit, and simultaneously reducing the layout and wiring density of the CAN bus circuit.

[0040] According to a fourth aspect of the present invention, another CAN bus communication device is provided, comprising a processor and a memory, wherein the memory stores a program or instructions executable on the processor, and when the program or instructions are executed by the processor, implement the steps of the CAN bus communication method as described in any of the above-described technical solutions. Therefore, the CAN bus communication device proposed in the fourth aspect of the present invention possesses all the beneficial effects of the CAN bus communication method in any of the technical solutions of the second aspect described above, and will not be elaborated further here.

[0041] According to a fifth aspect of the present invention, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the CAN bus communication method as described in any of the above-described technical solutions. Therefore, the readable storage medium proposed in the fifth aspect of the present invention possesses all the beneficial effects of the CAN bus communication method in any of the technical solutions of the second aspect described above, and will not be elaborated further here.

[0042] Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention. Attached Figure Description

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0044] Figure 1 A schematic diagram of the CAN bus circuit according to an embodiment of the present invention is shown;

[0045] Figure 2 A schematic diagram of the CAN bus circuit of the relevant technology is shown;

[0046] Figure 3 A flowchart of the CAN bus circuit according to an embodiment of the present invention is shown;

[0047] Figure 4 A flowchart illustrating the CAN bus communication method according to an embodiment of the present invention is shown;

[0048] Figure 5 One of the structural block diagrams of a CAN bus communication device according to an embodiment of the present invention is shown;

[0049] Figure 6 The second structural block diagram of the CAN bus communication device according to an embodiment of the present invention is shown.

[0050] Figure label:

[0051] 100 CAN bus circuit, 102 first diode, 104 first processor, 106 second diode, 108 second processor, 110 third diode, 112 third processor, 114 pull-up resistor, 116 power supply. Detailed Implementation

[0052] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0053] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0054] The following is combined Figures 1 to 6 The CAN bus circuit, CAN bus communication method and device, and readable storage medium provided in this application will be described in detail through specific embodiments and application scenarios.

[0055] In one embodiment of the present invention, a CAN bus circuit is provided, such as... Figure 1 As shown, the CAN bus circuit 100 includes multiple processors, a first diode 102, a second diode 106, a third diode 110, and a pull-up resistor 114.

[0056] Each processor includes a data transmission port (TXD) for transmitting signals and a data reception port (RXD) for receiving signals.

[0057] Furthermore, the multiple processors include a first processor 104, a second processor 108, and a third processor 112.

[0058] Furthermore, the anode of the first diode 102 is connected to the data receiving port of the first processor 104, the data receiving port of the second processor 108, and the data receiving port of the third processor 112, and the cathode of the first diode 102 is connected to the data transmitting port of the first processor 104.

[0059] Furthermore, the anode of the second diode 106 is connected to the data receiving port of the second processor 108, the data receiving port of the first processor 104, and the data receiving port of the third processor 112, and the cathode of the second diode 106 is connected to the data transmitting port of the second processor 108.

[0060] Furthermore, the anode of the third diode 110 is connected to the data receiving port of the third processor 112, the data receiving port of the first processor 104, and the data receiving port of the second processor 108, and the cathode of the third diode 110 is connected to the data transmitting port of the third processor 112.

[0061] Furthermore, the first end of the pull-up resistor 114 is connected to the power supply 116, and the second end of the pull-up resistor 114 is connected to the anode of the first diode 102, the anode of the second diode 106, the anode of the third diode 110, the data receiving port of the first processor 104, the data receiving port of the second processor 108, and the data receiving port of the third processor 112.

[0062] In this way, the data receiving ports of multiple processors are connected, and the signal levels of the data receiving ports of multiple processors are consistent.

[0063] Understandably, in a traditional CAN bus circuit 100, communication between two or more MCUs or CPUs is achieved through an external CAN driver chip. However, in a CAN network architecture with a single CAN bus module, due to the low signal interference and short line length on the same CAN bus module, the differential level interference immunity requirement of the CAN driver chip is not significant. Therefore, if the loopback function provided by the CAN driver chip can be implemented, an external CAN driver chip is unnecessary.

[0064] Based on this, the present invention provides a CAN bus circuit 100. During the operation of the CAN bus circuit 100, the loopback function provided by the CAN driver chip in the traditional CAN bus circuit 100 is realized through the first diode 102, the second diode 106, the third diode 110, and the pull-up resistor 114. In this way, the CAN driver chip in the traditional CAN bus circuit 100 can be replaced by three diodes and one pull-up resistor 114, which reduces the hardware cost of CAN bus communication, improves the cost competitiveness of the CAN bus circuit 100, and reduces the layout and wiring density of the CAN bus circuit 100.

[0065] In practical applications, the processor mentioned above can be either an MCU or a CPU; no specific restrictions are made here.

[0066] In some embodiments of the present invention, optionally, during the operation of the CAN bus circuit 100, when the data transmission port of the first processor 104 sends a low-level signal, the data transmission port of the second processor 108 sends a high-level signal, and the data transmission port of the third processor 112 does not send any signals, the first diode 102 can pull down the level of the received signal at the data receiving ports of the first processor 104, the second processor 108, and the third processor 112. Specifically, for the high-level signal sent by the data transmission port of the second processor 108, since the second diode 106 is reverse-biased, it will not affect the low level of the received signal at the data receiving port.

[0067] In some embodiments of the present invention, optionally, during the operation of the CAN bus circuit 100, for any processor, the data receiving port of the processor detects whether the level of the transmitted signal and the received signal of each processor are consistent. If the level of the transmitted signal and the received signal of the processor are inconsistent, it indicates that a race conflict has occurred on the CAN communication bus. At this time, the data transmitting port of the processor will stop transmitting signals and only receive external signals through the data receiving port.

[0068] Specifically, during the operation of the CAN bus circuit 100, when the data transmission port of the first processor 104 sends a low-level signal, the data transmission port of the second processor 108 sends a high-level signal, and the data transmission port of the third processor 112 does not send any signals, the receiving signal of the data receiving port of the second processor 108 is low-level. Since the levels of the transmission signal and the receiving signal of the second processor 108 are inconsistent, the data transmission port of the second processor 108 will stop sending signals and only receive external signals through the data receiving port.

[0069] In some embodiments of the present invention, optionally, during the operation of the CAN bus circuit 100, for any processor, the data receiving port of the processor detects whether the level of the transmitted signal and the received signal of each processor are consistent. If the level of the transmitted signal and the received signal of the processor are consistent, the data transmitting port of the processor will continue to transmit the signal until a complete CAN frame is transmitted.

[0070] Specifically, during the operation of the CAN bus circuit 100, when the data transmission port of the first processor 104 sends a low-level signal, the data transmission port of the second processor 108 sends a high-level signal, and the data transmission port of the third processor 112 does not send any signals, the receiving signal of the data receiving port of the first processor 104 is low-level. The transmission signal and the receiving signal of the first processor 104 are at the same level, and the data transmission port of the first processor 104 will continue to send signals until a complete CAN frame is sent.

[0071] In some embodiments of the present invention, optionally, each processor receives CAN frames through a data receiving port, and each processor parses CAN frames; however, only the processor corresponding to the CAN frame address among the multiple processors responds to the received CAN frame.

[0072] In summary, such as Figure 3 As shown, the workflow of the CAN bus circuit 100 provided by the present invention may specifically include the following steps 202 to 216:

[0073] Step 202: The data transmission port of the first processor sends a low-level signal, the data transmission port of the second processor sends a high-level signal, and the data transmission port of the third processor does not send a signal.

[0074] Step 204: The receive signals of the data receive ports of the first processor, the second processor, and the third processor are pulled low.

[0075] Step 206: Determine if the received signal of the data receiving port of the first processor is consistent with the transmitted signal of the data transmitting port. If yes, proceed to step 210; otherwise, proceed to step 214.

[0076] Step 208: Determine if the received signal of the data receiving port of the second processor is consistent with the transmitted signal of the data transmitting port. If yes, proceed to step 210; otherwise, proceed to step 216.

[0077] Step 210: The data transmission port continues to send signals;

[0078] Step 212, CAN frame transmission complete;

[0079] Step 214: The data transmission port of the first processor stops transmitting signals;

[0080] Step 216: The data transmission port of the second processor stops transmitting signals.

[0081] In one embodiment of the present invention, a CAN bus communication method is also proposed, applied to the CAN bus circuit in any of the above embodiments, such as... Figure 4 As shown, the CAN bus communication method may specifically include the following steps 302 to 306:

[0082] Step 302: Control the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor not to send a signal, so as to lower the level of the received signal of each processor;

[0083] Step 304: Compare the received signal and the transmitted signal of each processor to obtain the signal comparison result for each processor;

[0084] Step 306: Control the signal transmission status of each processor based on the signal comparison results of each processor.

[0085] In the CAN bus communication method provided by this invention, during the operation of the CAN bus circuit, the first processor is controlled to send a low-level signal, the second processor sends a high-level signal, and the third processor does not send a signal, so as to pull down the level of the received signal of each processor through the first diode in the CAN bus circuit. Further, the levels of the received signal and the transmitted signal of each processor are compared to obtain the signal comparison result corresponding to each processor, and then the signal transmission state of each processor is controlled according to the signal comparison result. In this way, the loopback function provided by the CAN driver chip can be realized without the need for a CAN driver chip, reducing the hardware cost of CAN bus communication, improving the cost competitiveness of the CAN bus circuit, and reducing the layout and wiring density of the CAN bus circuit.

[0086] In some embodiments of the present invention, step 306 may optionally include steps 306a and 306b as described below:

[0087] Step 306a: If the levels of the processor's transmitted signal and received signal are inconsistent, control the processor to stop transmitting signals;

[0088] Step 306b: If the levels of the processor's transmit signal and receive signal are consistent, control the processor to continue transmitting signals until a CAN frame is transmitted.

[0089] In this embodiment, during the process of controlling the signal transmission state of each processor based on the signal comparison results of each processor, for each processor, if the level of the processor's transmitted signal and the level of the received signal are inconsistent, the processor is controlled to stop transmitting signals; and if the level of the processor's transmitted signal and the level of the received signal are consistent, the processor is controlled to continue transmitting signals until a complete CAN frame is transmitted.

[0090] Specifically, during the operation of the CAN bus circuit, when the first processor sends a low-level signal, the second processor sends a high-level signal, and the third processor does not send any signals, the second processor's received signal is low. Since the levels of the second processor's transmitted and received signals are inconsistent, the second processor will stop sending signals and only receive external signals. Furthermore, when the first processor's received signal is low, and the levels of the first processor's transmitted and received signals are consistent, the first processor will continue sending signals until a complete CAN frame is transmitted.

[0091] In some embodiments of the present invention, optionally, each processor receives and parses the CAN frame, but only the processor corresponding to the CAN frame address responds to the CAN frame.

[0092] In this embodiment, each processor receives CAN frames through a data receiving port, and each processor parses CAN frames. However, only the processor corresponding to the CAN frame address responds to the received CAN frame.

[0093] In one embodiment of the present invention, a CAN bus communication device is also provided, applied to the CAN bus circuit in any of the above embodiments. For example... Figure 5 As shown, Figure 5 A structural block diagram of a CAN bus communication device 400 according to an embodiment of the present invention is shown. Specifically, the CAN bus communication device 400 may include a control unit 402 and a processing unit 404.

[0094] Control unit 402 is used to control the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor not to send a signal, so as to pull down the level of the received signal of each processor;

[0095] The processing unit 404 is used to compare the received signal and the transmitted signal of each processor to obtain the signal comparison result corresponding to each processor;

[0096] The control unit 402 is also used to control the signal transmission status of each processor based on the signal comparison results of each processor.

[0097] The CAN bus communication device 400 provided in this embodiment of the invention includes a control unit 402 and a processing unit 404. During the operation of the CAN bus circuit, the control unit 402 controls the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor to not send a signal, thereby pulling down the level of the received signal of each processor through the first diode in the CAN bus circuit. Further, the processing unit 404 compares the levels of the received signal and the transmitted signal of each processor to obtain the signal comparison result corresponding to each processor. The control unit 402 then controls the signal transmission state of each processor according to the signal comparison result of each processor. In this way, the loopback function provided by the CAN driver chip can be realized without the need for a CAN driver chip, reducing the hardware cost of CAN bus communication, improving the cost competitiveness of the CAN bus circuit, and reducing the layout and wiring density of the CAN bus circuit.

[0098] In some embodiments of the present invention, optionally, the processing unit 404 is specifically configured to: control the processor to stop sending signals when the levels of the processor's transmitted signal and received signal are inconsistent; and control the processor to continue sending signals when the levels of the processor's transmitted signal and received signal are consistent, until a CAN frame is completely sent.

[0099] In some embodiments of the present invention, optionally, each processor receives and parses the CAN frame, but only the processor corresponding to the CAN frame address responds to the CAN frame.

[0100] In one embodiment of the present invention, another CAN bus communication device is also proposed. For example... Figure 6 As shown, Figure 6 A structural block diagram of a CAN bus communication device 500 provided in an embodiment of the present invention is shown. The CAN bus communication device 500 includes:

[0101] Memory 502, which stores programs or instructions;

[0102] Processor 504, when executing the above program or instructions, implements the steps of the CAN bus communication method as described in any of the above embodiments.

[0103] The CAN bus communication device 500 provided in this embodiment includes a memory 502 and a processor 504. When the program or instructions in the memory 502 are executed by the processor 504, they implement the steps of the CAN bus communication method as described in any of the above embodiments. Therefore, the CAN bus communication device 500 has all the beneficial effects of the CAN bus communication method in any of the above embodiments, which will not be repeated here.

[0104] Specifically, the memory 502 and the processor 504 can be connected via a bus or other means. The processor 504 may include one or more processing units, and the processor 504 may be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other chips.

[0105] In one embodiment of the present invention, a readable storage medium is also provided. A program or instructions are stored thereon, which, when executed by a processor, implement the steps of the CAN bus communication method as described in any of the above embodiments.

[0106] The readable storage medium provided in this embodiment of the invention, when the program or instructions stored therein are executed by a processor, can implement the steps of the CAN bus communication method as described in any of the above embodiments. Therefore, this readable storage medium possesses all the beneficial effects of the CAN bus communication method in any of the above embodiments, which will not be elaborated further here.

[0107] Specifically, the aforementioned readable storage medium can include any medium capable of storing or transmitting information. Examples of readable storage media include electronic circuits, semiconductor memory devices, read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), flash memory, erasable ROM (EROM), magnetic tape, floppy disk, optical disk, hard disk, fiber optic media, radio frequency (RF) links, optical data storage devices, etc. Code segments can be downloaded via computer networks such as the Internet and intranets.

[0108] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, unless otherwise expressly specified and limited. The terms "connection," "installation," and "fixing," etc., should be interpreted broadly. For example, "connection" can mean a fixed connection, a detachable connection, or an integral connection; it can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0109] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A CAN bus circuit, characterized in that, include: Multiple processors, each processor including a data transmission port for sending signals and a data reception port for receiving signals; A first diode, wherein the anode of the first diode is connected to the data receiving port of a first processor among a plurality of processors, and the cathode of the first diode is connected to the data transmitting port of the first processor; The second diode has its anode connected to the data receiving port of the second processor among a plurality of processors, and its cathode connected to the data transmitting port of the second processor. A third diode, wherein the anode of the third diode is connected to the data receiving port of the third processor among a plurality of processors, and the cathode of the third diode is connected to the data transmitting port of the third processor; Pull-up resistor, the first end of which is connected to the power supply, and the second end of which is connected to the anode of the first diode, the anode of the second diode, the anode of the third diode, and the data receiving port of each processor; When the first processor sends a low-level signal, the second processor sends a high-level signal, and the third processor does not send a signal, the first diode pulls down the level of the received signal at the data receiving port of the first processor, the second processor, and the third processor. The receiving signal at the data receiving port of the second processor is low.

2. The CAN bus circuit according to claim 1, characterized in that, If the levels of the transmitted and received signals of any processor are inconsistent, the data transmission port of any processor shall stop transmitting signals.

3. The CAN bus circuit according to claim 1, characterized in that, If the levels of the transmitting and receiving signals of any processor are consistent, the data transmitting port of any processor continues to transmit signals until a CAN frame is completely transmitted.

4. The CAN bus circuit according to any one of claims 1 to 3, characterized in that, Multiple processors receive CAN frames through data receiving ports, and multiple processors parse the CAN frames, but only the processor corresponding to the CAN frame address responds to the CAN frame.

5. A CAN bus communication method, characterized in that, The CAN bus communication method, applied to any one of claims 1 to 4, comprises: The system controls the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor to not send a signal, in order to pull down the level of the received signal of each processor. By comparing the received and transmitted signals of each processor, the signal comparison result for each processor is obtained; Based on the signal comparison results of each processor, control the signal transmission state of each processor.

6. The CAN bus communication method according to claim 5, characterized in that, The step of controlling the signal transmission state of each processor based on the signal comparison result of each processor includes: If the levels of the processor's transmitted signal and received signal are inconsistent, the processor is controlled to stop transmitting signals. If the levels of the processor's transmit and receive signals are consistent, the processor continues to transmit signals until a CAN frame is completed.

7. The CAN bus communication method according to claim 5, characterized in that, Each processor receives and parses a CAN frame, but only the processor corresponding to the CAN frame address responds to the CAN frame.

8. A CAN bus communication device, characterized in that, The CAN bus communication device, applied to any one of claims 1 to 4, comprises: The control unit is used to control the first processor to send a low-level signal, the second processor to send a high-level signal, and the third processor to not send a signal, so as to pull down the level of the received signal of each processor; The processing unit is used to compare the received signal and the transmitted signal of each processor to obtain the signal comparison result corresponding to each processor; The control unit is also used to control the signal transmission state of each processor based on the signal comparison result of each processor.

9. A CAN bus communication device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the CAN bus communication method as described in any one of claims 5 to 7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the CAN bus communication method as described in any one of claims 5 to 7.

Images