Scrambling payload and preamble in 10SPE with synchronous and self-synchronous scrambling

Abstract

An apparatus includes an encoder circuit and a scrambler circuit configured to receive a frame, the frame including a preamble and a payload. The scrambler circuit is further configured to scramble content of a frame including the payload and at least a portion of the preamble, provide synchronization information having a result of scrambling the content, and transmit the result of scrambling the content to the encoder circuit.

Description

[0001] This invention patent application is a divisional application of the invention patent application with international application number PCT / US2019 / 019711, international application date February 27, 2019, application number 201980015122.9 entering the Chinese national phase, and name “Encrypting Payload and Preamble in 10SPE Using Synchronous and Self-synchronous Scrambling”.

[0002] priority

[0003] This application claims priority to U.S. Provisional Application No. 62 / 635,859, filed on February 27, 2018, and U.S. Provisional Application No. 62 / 637,656, filed on March 2, 2018, the contents of which are hereby incorporated in their entirety. Technical Field

[0004] The present disclosure relates to Ethernet communications, and more particularly to serial communications and scrambling payload and preamble using synchronous and self-synchronizing scrambling in IEEE 802.3cg communications, which are also known as single twisted pair Ethernet, 10SPE, or 10BASE-T1S. Background Art

[0005] 10SPE is a proposed standard currently under revision and development. 10SPE defines Ethernet LANs, access LANs, and metropolitan area networks. Ethernet operates at a selected operating speed; and uses a common media access control (MAC) specification and a management information base (MIB). The carrier sense multiple access with collision detection (CSMA / CD) MAC protocol specifies shared medium (half-duplex) operation as well as full-duplex operation. The speed-specific media independent interface (MII) provides the architecture and optional implementation-specific interface to the selected physical layer entity (PHY). The physical layer encodes frames for transmission and decodes received frames with the modulation specified for the operating speed, transmission medium, and supported link length. Other specified capabilities include: control and management protocols, and the provision of power over the selected twisted pair PHY type.

[0006] 10SPE specifies additions and appropriate modifications to IEEE Standard 802.3 to add 10Mb / s physical layer (PHY) specifications and operating management parameters over single balanced twisted pair copper cabling, and an associated optional power supply. Summary of the invention

[0007] Embodiments of the present disclosure may include a device. The device may include an encoder circuit and a scrambler circuit. The scrambler circuit may be configured to receive a frame. The frame may include a preamble and a payload. The scrambler circuit may be configured to scramble the content of the frame including at least a portion of the payload and the preamble, provide synchronization information with the result of scrambling the content, and send the result of scrambling the content to the encoder circuit. In conjunction with any of the above embodiments, the synchronization information may include data from the start or completion of scrambling in the scrambler circuit. In conjunction with any of the above embodiments, the synchronization information may include data from a shift register of the scrambler circuit. In conjunction with any of the above embodiments, the scrambler circuit may be further configured to replace the data field of the frame with the synchronization information. In conjunction with any of the above embodiments, the scrambler circuit may be further configured to replace the data field of the preamble of the frame with the synchronization information.

[0008] Embodiments of the present disclosure include manufacturing articles. The article may include machine-readable instructions on a non-transitory machine-readable medium. When loaded and executed by a processor, the instructions may cause the processor to receive a frame. The frame may include a preamble and a payload. The instructions may cause the processor to scramble the content of the frame including at least a portion of the payload and the preamble, provide synchronization information with the result of scrambling the content, and send the result of scrambling the content to an encoder circuit. In conjunction with any of the above embodiments, the synchronization information may include data from the start or completion of scrambling in the scrambler circuit. In conjunction with any of the above embodiments, the synchronization information may include data from a shift register of the scrambler circuit. In conjunction with any of the above embodiments, the instructions may cause the processor to replace the data field of the frame with the synchronization information. In conjunction with any of the above embodiments, the instructions may cause the processor to replace the data field of the preamble of the frame with the synchronization information.

[0009] Embodiments of the present disclosure may include other devices. The device may include a decoder circuit and a descrambler circuit. The descrambler circuit may be configured to receive a frame from the decoder circuit, the frame including a preamble and a payload. The descrambler circuit may be further configured to identify synchronization information in the frame, and use the synchronization information to descramble the content of the frame including at least a portion of the payload and the preamble. In conjunction with any one of the above embodiments, the synchronization information may include data from the start or completion of scrambling to generate a frame. In conjunction with any one of the above embodiments, the synchronization information may include data from a shift register of a scrambler circuit that generates a frame. In conjunction with any one of the above embodiments, the descrambler circuit may be further configured to identify a data field of a frame replaced by the synchronization information. In conjunction with any one of the above embodiments, the descrambler circuit may be further configured to use the synchronization information to fill the shift register of the descrambler circuit.

[0010] Embodiments of the present disclosure may include other articles of manufacture. Articles of manufacture may include machine-readable instructions on a non-transitory machine-readable medium. When loaded and executed by a processor, the instructions may cause the processor to receive a frame from a decoder circuit, the frame including a preamble and a payload. Articles of manufacture may also include instructions configured to cause the processor to identify synchronization information in the frame, and to descramble the content of the frame including at least a portion of the payload and the preamble using the synchronization information. In conjunction with any of the above embodiments, the synchronization information may include data from the start or completion of scrambling to generate a frame. In conjunction with any of the above embodiments, the synchronization information may include data from a shift register of a scrambler circuit that generates a frame. In conjunction with any of the above embodiments, articles of manufacture may also include instructions configured to cause the processor to identify a data field of a frame replaced by the synchronization information. In conjunction with any of the above embodiments, articles of manufacture may also include instructions configured to fill a shift register of a descrambler circuit with the synchronization information.

[0011] Embodiments of the present disclosure may include a device. The device may include a processor and any of the articles disclosed above.

[0012] Embodiments of the present disclosure may include a system. The system may include any of the devices or apparatuses disclosed above.

[0013] Embodiments of the present disclosure may include a method. The method may include operations performed by any of the apparatuses, processors, systems, or devices disclosed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is an illustration of a system for scrambling a payload and a preamble in a packetized data communication system according to an embodiment of the present disclosure.

[0015] Figure 2 is a more detailed illustration of a system for scrambling a payload and a preamble in a packetized data communication system according to an embodiment of the present disclosure.

[0016] Figure 3 is a diagram of a data frame (eg, a MAC frame) according to an embodiment of the present disclosure.

[0017] Figure 4 is a diagram of a PHY frame according to an embodiment of the present disclosure.

[0018] Figure 5 is a more detailed illustration of a portion of a 10SPE communication flow, data packet, or frame that may be scrambled according to an embodiment of the present disclosure.

[0019] Figure 6is another more detailed illustration of a portion of a 10SPE communication flow, data packet, or frame that may be scrambled according to an embodiment of the present disclosure.

[0020] Figure 7 is another more detailed illustration of a system for scrambling a payload and a preamble in a packetized data communication system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Figure 1 is a diagram of a system for scrambling a payload and a preamble during communications according to an embodiment of the present disclosure. System 100 may be implemented using analog circuitry, digital circuitry, instructions executed by a processor, or any suitable combination thereof.

[0022] The system 100 may include two or more suitable electronic devices 120, 122 in digital communication with each other. The electronic devices 120, 122 may be implemented similarly or differently from each other. The electronic devices 120, 122 may include, for example, computers, laptops, servers, blade computers, smart phones, routers, other network devices, tablets, mobile devices, or any other suitable devices.

[0023] Electronic devices 120, 122 can communicate through network 106. Network 106 can be implemented in any suitable manner. In one embodiment, network 106 can be a packetized network. In another embodiment, network 106 can be a 10SPE network. Electronic devices 120, 122 can communicate through network 106 using exchanged data packets. The data stream to be exchanged between electronic devices 120, 122 can be divided into such data packets. In addition to other fields, a separate data packet may include a preamble and a payload. The preamble can define a variety of characteristics about the packet, such as sender, destination, synchronization, seed, frame status and other information. In one embodiment, network 106 can be a 10SPE system, wherein the packet is exchanged via the 10SPE protocol.

[0024] Each of the electronic devices 120, 122 may include one or more processors 128, 130, one or more memories 132, 134 communicatively coupled to such processors, and a network stack 124, 126, respectively. Data to be sent between the electronic devices 120, 122 may originate from an application having instructions stored in the memory 132, 134 and executed on the processor 128, 130. Data to be sent between the electronic devices 120, 122 may originate from other networked devices, which will be propagated to the other of the electronic devices 120, 122 through one of the electronic devices 120, 122. Data to be sent or received between the electronic devices 120, 122 may be identified by software or hardware in the network stack 124, 126. In a layered network model, the network stack 124, 126 may implement one or more such layers.

[0025] The electronic device 120 may include a transceiver 102. The electronic device 122 may include a transceiver 104. These elements described as respective transceivers 102, 104 may be configured to send and receive data over the network 106. Thus, the transceiver 102 may also be configured to perform the operations of the transceiver 104, and vice versa.

[0026] In one embodiment, the transceiver 102 and the transceiver 104 may implement the PHY layer of the network communication between the electronic devices 120 and 122. The transceiver 102 and the transceiver 104 may be implemented by hardware, instructions executed by a processor, or any suitable combination thereof. The transceiver 102 and the transceiver 104 may be implemented in a network interface card, an integrated circuit, a system on a chip (SoC), or other suitable form factors. The transceiver 102 may be configured to convert data to be sent to the transceiver 104 into packets and send such packets to the transceiver 104. The transceiver 104 may be configured to convert data received from the transceiver 102 and make such data available to the rest of the electronic device 122. The data to be sent may be received as a transceiver 102 in the form of, for example, a MAC frame. The result of the processing of the transceiver 102 may be a 10SPE frame based on such input.

[0027] In one embodiment, the transceiver 102 may be configured to scramble one or more portions of the payload and preamble of packets sent to the electronic device 122. The transceiver 104 may be configured to descramble portions of the received payload and preamble.

[0028] The system 100 may be configured to perform scrambling to randomize the data. Randomization of the data may remove data-dependent patterns. Data-dependent patterns may include, for example, long strings of zeros, long strings of one bits, or other repeating strings of bits. Such data patterns may cause the network 106 or the electronic device 122 to emit strong interfering tones. The system 100 may perform scrambling to randomize the data and thereby reduce the tones.

[0029] The system 100 may be configured to perform scrambling on any suitable network protocol. The system 100 may be configured to perform scrambling on packetized network communications. The system 100 may be configured to perform scrambling on a portion of a payload and a preamble of a packetized network communications protocol frame. Scrambling may be performed on a combined set of portions of the payload and preamble. The portion of the preamble to be scrambled may be a subset, where some of the preamble is not scrambled. The system 100 may be configured to perform scrambling on a 10SPE frame. The system 100 may be configured to perform associated descrambling of a frame.

[0030] Figure 2 is a more detailed illustration of a system 100 for scrambling a payload and a preamble in a packetized data communication system according to an embodiment of the present disclosure.

[0031] The transceiver 102 may receive data or frames to be sent to the transceiver 104 from other parts of the electronic device 120. The transceiver 102 may include a 4B5B encoder 208 configured to perform 4B / 5B encoding or block encoding. Any other suitable encoding may be used. In 10SPE communication, 4B / 5B encoding or block encoding may be specified. The 4B5B encoder 208 may be implemented by any suitable combination of circuits or instructions executed by a processor. The 4B / 5B encoding may be performed according to a table or definition specified in the 10SPE standard. The data to be sent to the transceiver 104 may first be encoded using the 4B5B encoder 208.

[0032] The transceiver 102 may include a scrambler 210. The scrambler 210 may be configured to scramble a portion of a frame received from the 4B5B encoder 208. The scrambler 210 may be implemented by any suitable combination of circuits or instructions executed by a processor. The scrambler 210 may scramble data received from the 4B5B encoder 208.

[0033] The transceiver 102 may include a differential Manchester encoding (DME) encoder 212. The DME encoder 212 may be configured to further encode the data received from the scrambler 210. The DME encoder 212 may be implemented by any suitable combination of circuits or instructions executed by a processor. The DME encoder 212 may receive the scrambled data from the scrambler 210. The result from the DME encoder 212 may be sent to the transceiver 104.

[0034] The transceiver 104 may include a DEM decoder 214. The DME decoder may be configured to decode the operation of the DME encoder 212 and may be implemented by any suitable combination of circuitry or instructions executed by a processor.

[0035] The transceiver 104 may include a descrambler 216. The descrambler 216 may be configured to descramble the data in a complementary manner to the way the scrambler 210 scrambled the data, and may be implemented by any suitable combination of circuits or instructions executed by a processor. The descrambler 216 may receive already decoded data to be descrambled from the DME encoder 212.

[0036] The transceiver 104 may include a 4B5B decoder 218. The 4B5B decoder 218 may be configured to perform decoding corresponding to the encoding performed by the 4B5B encoder 208 and may be implemented by any suitable combination of circuitry or instructions executed by a processor. The 4B5B decoder may receive data that has been descrambled from the descrambler 216.

[0037] In addition to the payload of the data stream or frame, embodiments of the present disclosure may also apply scrambling to a combination of a portion of the preamble.

[0038] Figure 3 3 is an illustration of a data frame 300 (e.g., a MAC frame) according to an embodiment of the present disclosure. The data frame 300 may be in a form generated by a portion of the network stack 124, 126 representing other portions of the electronic device 120, 122, such as an application running thereon. The data frame 300 may illustrate the form of a frame arriving at the encoder 208 and generated by the decoder 218. After conversion by the encoder 208 and before conversion by the decoder 218, the data frame 300 may be converted into a PHY frame, such as Figures 4 to 6 Those shown in .

[0039] The data frame 300 may include a start frame delimiter (SFD) field 316. The data frame 300 may include a payload field 318 including data to be transmitted to the other of the electronic devices 120, 122 via the respective transceiver 102, 104. The data frame 300 may include a cyclic redundancy check (CRC) field 320 based on the contents of the payload field 318. Prior to the SFD field 316, the data frame 300 may include other fields 302, 304, 306, 308, 310, 312, 314.

[0040] Figure 4is an illustration of a PHY frame 400 according to an embodiment of the present disclosure. The PHY frame 400 may be generated by the encoder 208 and decoded by the decoder 218. The PHY frame 400 may represent the result of encoding the data frame 300. The PHY frame 400 may be the result of encoding a MAC data frame.

[0041] The PHY frame 400 may include a PHY frame payload 406. The PHY frame payload 406 may include content from or derived from the payload 318 of the data frame 300. Additionally, the PHY frame payload 406 may include content from or derived from the fields 306, 308, 310, 312, 314, 316, 320 of the data frame 300.

[0042] The PHY frame 400 may include fields 402, 404. Fields 402 (labeled JJ) and 404 (labeled JK) may be octets or words defined by the 4B / 5B encoding scheme in the 10SPE standard. These fields may be generated by the encoder 208 and interpreted by the decoder 218.

[0043] The PHY frame 400 may include a CRC / H / T / R field 408. The CRC / H / T / R field 408 may include a cyclic redundancy check (CRC), checksum, or other calculation result of a mathematical operation performed on the PHY frame payload 406 or a portion thereof. The CRC / H / T / R field 408 may also include or follow an H / T / R designation that indicates one of three conditions: ESD (end of stream delimiter); ESDOK (end of stream delimiter ok); or ESDERR (end of stream delimiter error).

[0044] In one embodiment, some or all of the PHY frame payload field 406 may be scrambled for 10SPE communication. Such scrambling may be performed by the scrambler circuit 210. Once scrambled and transmitted, the scrambled portion of the PHY frame payload field 406 may be descrambled by the descrambler 216. In order to successfully descramble the received PHY frame 400, the descrambler 216 in the receiver may need to be synchronized with the scrambler 210. The descrambler 216 may start from a seed from the scrambler 210 or also used by the scrambler 210. The descrambler 216 and the scrambler 210 may use one or more techniques to share such a seed or other starting point so that scrambling and descrambling are synchronized.

[0045] In one embodiment, the data scrambling between the scrambler 210 and the descrambler 216 can be performed in a self-synchronous manner. In the self-synchronous case, the scrambler 210 and the descrambler 216 can each use a predetermined known initial data set. The predetermined known initial data set can be loaded into the scrambler or descrambler circuit before operation. In this case, the scrambler 210 and the descrambler 216 can be reset to the initial data set each time they operate. Therefore, each time a frame is transmitted or received, the scrambler 210 and the descrambler 216 can be initialized to a known fixed state (such as an initial data set).

[0046] In some other cases, the PHY frame 400 may indicate whether to reset to a known initial data set, or whether to continue using the last state of the shift register (or other mechanism) of the scrambler and descrambler circuit. The sender of the PHY frame 400 may mark such names in the PHY frame 400. When the scrambler 210 uses the existing or latest state of its register to start scrambling subsequent information, this may be considered as a continued rotation in the frame. The scrambler 210 and the descrambler 216 may be configured to perform continued rotation in the frame after the initial data set is loaded. The continued rotation in the frame may be performed at a predetermined or selected number of frames, time, until timeout, or at the request of the scrambler 210 or the descrambler 216.

[0047] In another embodiment, the data scrambling between the scrambler 210 and the descrambler 216 can be performed in a synchronous scrambling manner. In the case of synchronous scrambling, the PHY frame 400 may include an initial data set, a seed, or a continuous data set to be loaded by the descrambler 216 to synchronously descramble the payload. The initial data set, the seed, or the continuous data set may be provided by the scrambler 210. In the case of synchronous scrambling of sending seeds, in subsequent transmission and reception operations, the scrambler 210 and the descrambler 216 may be configured to continue rotating in the frame, wherein the scrambler 210 and the descrambler 210 use the existing or latest state of their respective registers to start scrambling or descrambling subsequent frames. The continued rotation in the frame can be performed for a predetermined or selected number of frames, time, until timeout, or according to the request of the scrambler 210 or the descrambler 216. In addition, the descrambler 216 can become synchronized with the scrambler 210 by the scrambler 210 feeding its register group information (when scrambling is completed) to the descrambler 216. The scrambler 210 may accomplish this by providing such register set information in the PHY frame 400. Once the descrambler 216 receives the complete set of register set information, the two entities may be considered synchronized. This process may be referred to as training the descrambler 216. More than one PHY frame 400 may need to be sent to fully train the descrambler 216. The PHY frame 400 may include data or fields with seed transmissions to train the descrambler 216.

[0048] In one embodiment, a portion of the PHY frame payload 406 may be scrambled. In another embodiment, a portion of the CRC / H / T / R field 408 may be scrambled. Figure 5 and Figure 6 An example of a portion of the PHY frame payload 406 that may be scrambled is shown in FIG.

[0049] Figure 5 5 is a more detailed illustration of a portion of a 10SPE communication flow, data packet, or frame 500 that may be scrambled according to an embodiment of the present disclosure. Frame 500 may illustrate a more specific example or exemplary constituent elements of PHY frame 400. Frame 500 may illustrate information sent from transceiver to transceiver or from sender to receiver. The information may be further reconstructed or analyzed at such transceiver or receiver. In this case, frame 500 may illustrate such information as it is received and analyzed. Scrambling may be performed by scrambler 210, and descrambling may be performed by descrambler 216.

[0050] Portions of a 10SPE communication stream, data packet, or frame may include portions of a preamble. All or part of a 10SPE preamble may be Figure 5 The preamble may include fields 502, 504, 506, 508, 510, 512, 514. In various implementations, more or fewer fields may be included.

[0051] The portion of the SPE10 communication flow, data packet, or frame may include a start frame delimiter (SFD) field 516. The preamble may or may not include the SFD field 516. The portion of the SPE10 communication flow, data packet, or frame may include a payload field 518. The payload field 518 may be of a suitable size, may be variable, and may not necessarily be the same size as the payload field 518. Figure 3 The other fields in the SFD field 516 may be scrambled. The SFD field 516 may indicate the start of a payload or data.

[0052] Portions of the SPE10 communication stream, data packet, or frame may include a frame check sequence or CRC / H / T / R field 516. The CRC / H / T / R field 520 may include a cyclic redundancy check (CRC), checksum, or other calculation result of a mathematical operation performed on the payload field 518. The CRC / H / T / R field 516 may also include or follow an H / T / R designation, which indicates one of the following three conditions: ESD (end of stream delimiter); ESDOK (end of stream delimiter ok); or ESDERR (end of stream delimiter error). In one embodiment, the CRC / H / T / R field 516 may also be scrambled. In another embodiment, the H / T / R designation may also be scrambled.

[0053] The preamble may be configured to perform synchronization between a sender and a receiver of Ethernet data. The preamble may indicate the end of header information.

[0054] In 10SPE, the contents of payload 518 may be scrambled. In one embodiment, Figure 5 A portion of the preamble shown may also be scrambled. Scrambling of a portion of the preamble may be performed with scrambling of the payload 518. However, not all of the preamble may be scrambled. In another embodiment, one or more of fields 506, 508, 510, 512, 514 may be scrambled. In another embodiment, fields JJ502 and JJ504 may not be scrambled. In various embodiments, scrambling of the SFD field 516 may be performed or omitted. Figure 5 In the example of , fields 506, 508, 510, 512, 514, 516, 518, and 520 may be scrambled. The preamble may include an additional field before field 502, which is not shown and is not scrambled.

[0055] Fields 502 (labeled JJ) and 504 (labeled JK) may be octets or words defined by the 4B / 5B encoding scheme in the 10SPE standard.

[0056] Fields 506, 508, 510, 512, 514 can be fields after words defined by 4B / 5B coding scheme. In one embodiment, each of fields 506, 508, 510, 512, 514 can include the data of hexadecimal value 55 or "01010101" bytes. In one embodiment, all fields after the 4B / 5B coding scheme field can be scrambled. In another embodiment, a portion of fields after following the 4B / 5B coding scheme field can be scrambled. In another embodiment, all fields of the preamble with a fixed value can be scrambled. In another embodiment, a portion of fields of the preamble with a fixed value can be scrambled. In another embodiment, all fields of the preamble with a hexadecimal value of 55 can be scrambled. In another embodiment, a portion of fields of the preamble with a hexadecimal value of 55 can be scrambled.

[0057] Scrambling may be performed in any suitable manner. Scrambling may be performed by a coding algorithm comprising instructions executed by a processor based on a polynomial. Scrambling may be represented by a polynomial such as

[0058] x 15 +x 4 +1

[0059] The scrambling polynomial may represent a transfer function showing the scrambling result. Scrambling may be implemented by a series of linear feedback shift registers (LFSRs). The scrambler initial state or set may be given by the set [001010011000001]. These may represent the initial values ​​of the LFSR. The scrambler 210 and the descrambler 216 may include circuits, LFSRs or other elements in a corresponding arrangement so that the use of the same initial state, set or data will produce corresponding results. Therefore, when the scrambler 210 and the descrambler 216 each have the same data set for the same scrambling polynomial, the scrambler 210 and the descrambler 216 may scramble and descramble the same content.

[0060] As described above, scrambling may be performed on a combination of a defined portion of the preamble and the payload, and further, the payload may have a varying length. Although the payload field 518 may have a varying length, the payload field 518 may be, for example, one of 60, 160, 170, 342, or 1460 bits. The spectral resolution bandwidth (RBW) may be 10 kHz-100 kHz.

[0061] All data after field JK504 to field 520 may be scrambled. Such data may include an End of Stream Delimiter (ESD) field and ESDOK / ESDERR elements. Descrambling may be initiated after receiving the K of field JK504.

[0062] In one embodiment, JJ field 502 and JK field 504 may not be scrambled. These eight-bit bytes may not be scrambled because they are used for clock and data recovery (CDR). These eight-bit bytes can be used for the fast locking in CDR. In various embodiments, the scrambling of the part of the preamble for CDR can be omitted. In such embodiments, scrambling can be initiated for the field after the field for CDR. In another embodiment, five eight-bit bytes or fields 506,508,510,512,514 can be scrambled together with the preamble in a single scrambler. It is not necessary to change the 10SPE frame format or the PHY layer collision avoidance scheme.

[0063] The initial data set [001010011000001] can be considered as the seed for scrambling / descrambling. Figure 5 In the example, the initial data set may be predetermined and known to each of the scrambler 210 and the descrambler 216. Figure 5 When the packets are scrambled as shown, synchronous scrambling may be performed. After each frame is transmitted and received, the scrambler 210 and descrambler 216 may be reset to a known initial data set.

[0064] Figure 66 is another more detailed illustration of a portion of a 10SPE communication flow, data packet, or frame that may be scrambled according to an embodiment of the present disclosure. Frame 600 may illustrate another more specific example or exemplary constituent element of PHY frame 400. Where appropriate, frame 600 is illustrated using the nomenclature of frame 500. As described above, frame 600 may be scrambled in the same manner as frame 500 may be scrambled.

[0065] In one embodiment, frame 600 may be configured to be scrambled in a self-synchronous manner. In another embodiment, frame 600 may be configured to be selectively scrambled in a self-synchronous manner or in a synchronous manner.

[0066] To accomplish this, the frame 600 may include synchronization information. The synchronization information may include information for the scrambler 210. The scrambler 210 may utilize such information to synchronize itself. The information may include a seed, continuation data, or other data from the start or completion of the LFSR or other circuitry of the scrambler 210 used to scramble the frame 600 or accompanying frames.

[0067] Frame 600 may replace one or more fields of the preamble to include a synchronization symbol (SS) or other information. For example, frame 600 may include SS field 602 and SS field 604. These fields may replace the field containing "55" data. Fields 602, 604 shown at specific positions within the preamble may be located at any suitable position within the preamble. The number of fields that may be used may correspond to the size of the circuit and LFSR of scrambler 210. For example, if scrambler 210 includes a 16-bit LFSR, a 16-bit synchronization symbol may be included in frame 600. The 16-bit synchronization symbol may be divided into two octets and placed in SS fields 602, 604. Fields 602, 604 may be ordered from the least significant byte to the most significant byte, or from the most significant byte to the least significant byte.

[0068] The scrambler 210 may be configured to set the fields 602, 604 using either the random seed that it has used itself or the last scrambler state of the previous frame processed by the scrambler 210. If a random seed is used, the scrambler 210 may be configured to reset, initialize, and scramble the frame using the same random seed. If the last scrambler state is used, the scrambler 210 may be configured to rotate the frame.

[0069] In one embodiment, SS fields (such as fields 602, 604) may not be scrambled along with the rest of the payload and preamble.

[0070] If the scrambler 210 and the descrambler 216 are to be operated in a self-synchronizing mode, the frame 600 may still be used. In this case, the fields 602, 604 may include training data for the descrambler 216.

[0071] Other methods may not scramble the portion of the preamble containing the hexadecimal value 55 because such a field is not a repeating string of ones or zeros.

[0072] Figure 7 is another more detailed illustration of a system 100 for scrambling a payload and a preamble in a packetized data communication system according to an embodiment of the present disclosure. Figure 7 Shown with Figure 2 However, according to the embodiments of the present disclosure, Figure 7 Presents different arrangements or configurations Figure 2 Specifically, Figure 2 In contrast, the location of the 4B5B encoder 208 may be swapped with the scrambler 210 in the transceiver 102. Figure 2 In comparison, the location of the 4B5B decoder 218 may be swapped with the descrambler 216 in the transceiver 104 .

[0073] Thus, the scrambler 210 may scramble data to be sent to the transceiver 104 before encoding the data to be sent to the transceiver 104 using the 4B5B encoder 208. The scrambled data may be passed to the 4B5B encoder 208. Once encoded, the 4B5B encoder 208 may pass the result to the DEM encoder 212. In the transceiver 104, the data decoded from the DEM decoder 214 may be passed to the 4B5B decoder 218. Once decoded, the 4B5B decoder 218 may pass its result to the descrambler 216, which may descramble the result.

[0074] By performing 4B5B encoding before scrambling, Figure 3-6 Compared to the structure shown in FIG. 4B , the resulting frame may have changes in its structure. For example, the relative position of fields 402, 404 or 502, 504 may change. However, all or part of the fields following the 4B / 5B coding scheme field in such a frame may be scrambled. In addition, regardless of the position of fields 402, 404, 502, 504, in addition to the payload of the data stream or frame, embodiments of the present disclosure may also apply scrambling to a combination of parts of the preamble.

[0075] The present disclosure has been described according to one or more embodiments, and it should be understood that many equivalents, alternatives, variations and modifications are possible and within the scope of the present disclosure, except those explicitly stated. Although the present disclosure is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and described in detail herein. However, it should be understood that the description of specific exemplary embodiments herein is not intended to limit the present disclosure to the specific forms disclosed herein.

Claims

1. A method comprising: receiving a frame, the frame comprising a preamble and a payload; scrambling contents of the frame including at least a portion of the preamble and the payload; providing synchronization information to a result of scrambling the content; as well as The result of scrambling the content is sent to the encoder circuit.

2. The method according to claim 1, characterized in that The synchronization information includes data from the start or completion of scrambling in the scrambler circuit.

3. The method according to claim 1, characterized in that The synchronization information includes data from a shift register of a scrambler circuit.

4. The method according to claim 1, characterized in that: Also included is replacing a data field of the frame with the synchronization information.

5. The method according to claim 1, characterized in that Also included is replacing a data field of the preamble of the frame with the synchronization information.

6. A method comprising: receiving a frame from a decoder circuit, the frame comprising a preamble and a payload; identifying synchronization information in the frame; as well as Content of the frame, including at least a portion of the preamble and the payload, is descrambled using the synchronization information.

7. The method according to claim 6, characterized in that The synchronization information includes data from the start or completion of scrambling used to generate the frame.

8. The method according to claim 6, characterized in that The synchronization information includes data from a shift register of a scrambler circuit that generates the frame.

9. The method according to claim 6, characterized in that Also included is identifying a data field of the frame that is replaced by the synchronization information.

10. The method according to claim 6, characterized in that Also included is populating a shift register of a descrambler circuit with the synchronization information.

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