A method, system and FPGA for fast finding the best phase of Ethernet based on FPGA

Abstract

The application belongs to the technical field of embedded development, and specifically discloses a method and system for quickly finding the best phase of Ethernet based on FPGA and FPGA. Through the application, the FPGA Ethernet project is constructed to work in different data delay units and clock delay units; through the packet loss test of the FPGA Ethernet project, the data boundary delay unit and the clock boundary delay unit of stable data transmission and reception from packet loss and error to no packet loss and error are found out; the taps of the reference clock delay during the unstable phase are calculated and superimposed to the data boundary delay unit and the clock boundary delay unit to obtain the best phase of data and the best phase of clock in Ethernet data communication. The application finds out the boundary phase (the data boundary delay unit and the clock boundary delay unit) through the packet loss test, and then determines the best phase, and the precision requirement of the measuring instrument is not high, and the cost is reduced to the level of 100,000.

Description

Technical Field

[0001] This application belongs to the field of embedded development technology, and more specifically, relates to a method, system and FPGA for quickly finding the optimal phase of Ethernet based on FPGA. Background Technology

[0002] Ethernet interfaces are widely used in network communication, industrial control, and data transmission. They are characterized by simple interfaces, high communication speeds, long transmission distances, and stable performance. Furthermore, they can be freely defined and configured through programming to achieve desired functions and enable high-speed remote communication. However, in daily hardware design and development, issues such as unequal PCB trace lengths and poor clock quality can lead to clock phase discrepancies between the Ethernet receiver's clock and the data.

[0003] The existing technology uses an oscilloscope to directly measure the deviation between the two clocks; however, this method requires extremely high precision from the measuring instrument and is costly. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a method, system, and FPGA for quickly finding the optimal phase of Ethernet based on FPGA, aiming to solve the problems of high equipment accuracy and high cost in existing Ethernet data communication phase deviation measurement methods.

[0005] To achieve the above objectives, in a first aspect, this application provides a method for quickly finding the optimal phase of an Ethernet network based on an FPGA, the method comprising:

[0006] Build an FPGA Ethernet project that can operate in different data delay units and clock delay units;

[0007] By conducting packet loss tests on FPGA Ethernet projects, we identified the data boundary delay unit and clock boundary delay unit from stable data transmission and reception without packet loss or errors to a point where packets are lost or incorrect.

[0008] The reference clock delay taps during the phase instability period are calculated and superimposed on the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication.

[0009] Preferably, the construction of the FPGA Ethernet project is specifically as follows:

[0010] Call the IDELAYE2 primitive to set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD";

[0011] Connect the IDELAYE2 port IDATAIN to the external clock rgmii_rxc, the port DATAOUT to the Ethernet IP rgmii_rxc to output rgmii_rxc_dly, the port CNTVALUEIN to the VIO IP delay_clk_cnt, and the port LD to the VIO IP delay_en.

[0012] Connect the rgmii_rx_data in the Ethernet IP to the external rgmii_rx_data.

[0013] Preferably, the operation is made to work in different data delay units and clock delay units, specifically as follows:

[0014] Make three copies of the FPGA Ethernet project and constrain the clock delay of the Ethernet reception to 0 units, 12 units, and 31 units respectively, to obtain projects with data delays of 0 units, 12 units, and 31 units.

[0015] After power-on, the engineering firmware with data delays of 0 units, 12 units, and 31 units is downloaded to the FPGA. Different delay_clk_cnt values ​​are set on the FPGA's VIO IP visualization interface. After setting, delay_en is triggered to perform packet loss tests.

[0016] Preferably, when the data delay unit is fixed, the delay_clk_cnt is changed using a binary search method.

[0017] Preferably, the criteria for determining the data boundary delay unit and clock boundary delay unit from packet loss / error to stable data transmission and reception without packet loss / error are as follows:

[0018] If Tdelay_clk_cnt and Tdelay_clk_cnt-1 experience packet loss, Tdelay_clk_cnt-2 experiences packet loss, and Tdelay_clk_cnt+1 and Tdelay_clk_cnt+2 do not experience packet loss, then Tdata_delay and Tdelay_clk_cnt are the Ethernet data boundary delay unit and clock boundary delay unit, respectively.

[0019] Preferably, the steps for calculating the reference clock delay during phase instability are as follows:

[0020] The delay resolution is calculated as delay_resolution = 1 / (32*2*f)*1000000 (ps).

[0021] Calculate the reference clock delay during phase instability Where f represents the reference clock frequency, and the safe distance ranges from [3 taps, 5 taps].

[0022] Preferably, the superposition of data boundary delay units and clock boundary delay units yields the optimal data phase and clock phase in Ethernet data communication, as detailed below:

[0023] If the sum of the data boundary delay units and clock boundary delay units is within the range of 0 to 31, then the sum is the optimal phase of the data and the optimal phase of the clock. Otherwise, subtract a certain value from the sum to make it within the range of 0 to 31. The value after subtracting this value is the optimal phase of the data and the optimal phase of the clock.

[0024] Preferably, the method further includes:

[0025] In the FPGA Ethernet engineering constraints document, the optimal phase constraints for clock and data are fixed, and the IDELAY_TYPE in IDELAYE2 is set from the variable delay "VAR_LOAD" to "FIXED".

[0026] To achieve the above objectives, in a second aspect, this application provides an FPGA including an FPGA Ethernet engineering constraint file, wherein the optimal phase of the data and the optimal phase of the clock in the PGA Ethernet engineering constraint file are obtained by the method described in the first aspect.

[0027] To achieve the above objectives, in a third aspect, this application provides a system for quickly finding the optimal phase of an Ethernet network based on an FPGA, comprising: an FPGA, an Ethernet PHY, an RJ45 connector, and a network tester;

[0028] The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to an RJ45 connector; the other end of the RJ45 connector is connected to a network tester.

[0029] The FPGA is equipped with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2.

[0030] The network tester performs high-volume, full-load data transmission with the FPGA, while simultaneously performing packet loss tests on the FPGA.

[0031] The system determines the optimal Ethernet phase according to the method described in the first aspect.

[0032] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0033] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art:

[0034] This application provides a method for quickly finding the optimal phase in Ethernet communication based on FPGA. It involves constructing an FPGA Ethernet project and operating it with different data delay units and clock delay units. Through packet loss testing of the FPGA Ethernet project, the data boundary delay units and clock boundary delay units are identified from the point of packet loss / error to the point of stable data transmission and reception without packet loss / error. The reference clock delay taps during the phase instability period are calculated and superimposed onto the data boundary delay units and clock boundary delay units to obtain the optimal data phase and clock phase in Ethernet data communication. This application identifies the boundary phases (data boundary delay units and clock boundary delay units) through packet loss testing, thereby determining the optimal phase. It does not require high precision measurement instruments and reduces costs to the tens of thousands level. Attached Figure Description

[0035] Figure 1 This is a flowchart of a method for quickly finding the optimal Ethernet phase based on FPGA, provided in an embodiment of this application.

[0036] Figure 2 This is a block diagram of the hardware system structure required for implementation provided in the embodiments of this application.

[0037] Figure 3 This is a flowchart of the preparation stage provided in the embodiments of this application.

[0038] Figure 4 This is a flowchart of the testing phase provided in the embodiments of this application.

[0039] Figure 5 This is a flowchart of the process for calculating and fixing the optimal phase provided in the embodiments of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0041] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0042] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0043] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0045] First, the technical terms involved in the embodiments of this application will be introduced.

[0046] IDELAYE2 Primitive: IDELAYE2 is a built-in primitive in Xilinx FPGAs used to provide precise input signal delay control. It features 31 programmable delay taps, suitable for fine-tuning high-speed digital signals to meet timing requirements. IDELAYE2 can operate independently on each pin of the FPGA, supporting various operating modes including fixed delay, variable delay, variable loading, and pipeline mode. Furthermore, IDELAYE2 can be automatically calibrated via the IDELAYCTRL module to reduce the impact of process, voltage, and temperature variations.

[0047] Setting IDELAY_TYPE to "VAR_LOAD" enables IDELAY2 timing in loadable variable delay mode. When IDELAY_TYPE is set to "FIXED", it means the delay is fixed and will not change at runtime. This mode is suitable for scenarios where dynamic delay adjustment is not required.

[0048] IDATAIN: One of the data input ports for IDELAYE2, the IDELAY data input from IBUF.

[0049] DATAOUT: One of the output ports of IDELAYE2, receiving delayed data from one of the two data input ports.

[0050] Port CNTVALUEIN: A calculator value from the FPGA logic used to dynamically load tap values.

[0051] Port LD: In VAR_LOAD mode, load the value of CNTVALUEIN.

[0052] The tri_mac IP, or Tri-Mode Ethernet MAC IP, is a hardware module for Ethernet communication interfaces in FPGAs. It supports different Ethernet speeds, including 10 / 100Mb / s, 1Gb / s, 2.5Gb / s, or 10 / 100 / 1000Mb / s adaptive types. The Tri-Mode Ethernet MAC IP core is typically embedded in the FPGA to implement Ethernet communication functionality. It is responsible for data encapsulation and decapsulation at the MAC layer, as well as data transmission with the PHY layer.

[0053] FPGA Ethernet engineering typically refers to the design and development process of implementing Ethernet communication functionality on an FPGA (Field-Programmable Gate Array). Ethernet is a local area network (LAN) technology widely used for data communication. It conforms to the IEEE 802.3 standard and supports various speeds, such as 10 Mbit / s, 100 Mbit / s, 1000 Mbit / s (Gigabit Ethernet), and even higher. Implementing Ethernet functionality on an FPGA usually involves the following key components: the MAC (Media Access Control) layer, the PHY (Physical Layer) layer, interface circuitry, communication protocols, and debugging and testing.

[0054] A VIO (Virtual Input / Output) IP core is a very useful debugging tool. It allows designers to monitor and drive signals inside an FPGA in real time via a JTAG interface. The number and bit width of the input and output ports can be configured to suit different debugging needs. Because the VIO core is synchronized with the design being monitored and driven, clock constraints applied to the design also apply to the VIO.

[0055] Next, the technical solutions provided in the embodiments of this application will be described.

[0056] like Figure 1 As shown, this application provides a method for quickly finding the optimal phase of an Ethernet network based on an FPGA. The method includes:

[0057] Build an FPGA Ethernet project that can operate in different data delay units and clock delay units;

[0058] By conducting packet loss tests on FPGA Ethernet projects, we identified the data boundary delay unit and clock boundary delay unit from stable data transmission and reception without packet loss or errors to a point where packets are lost or incorrect.

[0059] The reference clock delay taps during the phase instability period are calculated and superimposed on the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication.

[0060] Preferably, the construction of the FPGA Ethernet project is specifically as follows:

[0061] Call the IDELAYE2 primitive to set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD";

[0062] Connect the IDELAYE2 port IDATAIN to the external clock rgmii_rxc, the port DATAOUT to the Ethernet IP rgmii_rxc to output rgmii_rxc_dly, the port CNTVALUEIN to the VIO IP delay_clk_cnt, and the port LD to the VIO IP delay_en.

[0063] Connect the rgmii_rx_data in the Ethernet IP to the external rgmii_rx_data.

[0064] Preferably, the operation is made to work in different data delay units and clock delay units, specifically as follows:

[0065] Make three copies of the FPGA Ethernet project and constrain the clock delay of the Ethernet reception to 0 units, 12 units, and 31 units respectively, to obtain projects with data delays of 0 units, 12 units, and 31 units.

[0066] After power-on, the engineering firmware with data delays of 0 units, 12 units, and 31 units is downloaded to the FPGA. Different delay_clk_cnt values ​​are set on the FPGA's VIO IP visualization interface. After setting, delay_en is triggered to perform packet loss tests.

[0067] In addition to delays of 0 units, 12 units, and 31 units, this application also supports other combinations, as long as the front, middle, and back segments are covered simultaneously, such as 1 unit, 15 units, and 30 units.

[0068] Preferably, when the data delay unit is fixed, the delay_clk_cnt is changed using a binary search method.

[0069] Preferably, the criteria for determining the data boundary delay unit and clock boundary delay unit from packet loss / error to stable data transmission and reception without packet loss / error are as follows:

[0070] If Tdelay_clk_cnt and Tdelay_clk_cnt-1 experience packet loss, Tdelay_clk_cnt-2 experiences packet loss, and Tdelay_clk_cnt+1 and Tdelay_clk_cnt+2 do not experience packet loss, then Tdata_delay and Tdelay_clk_cnt are the Ethernet data boundary delay unit and clock boundary delay unit, respectively.

[0071] Preferably, the steps for calculating the reference clock delay during phase instability are as follows:

[0072] The delay resolution is calculated as delay_resolution = 1 / (32*2*f)*1000000 (ps).

[0073] Calculate the reference clock delay during phase instability Where f represents the reference clock frequency, and the safe distance ranges from [3 taps, 5 taps].

[0074] Preferably, the superposition of data boundary delay units and clock boundary delay units yields the optimal data phase and clock phase in Ethernet data communication, as detailed below:

[0075] If the sum of the data boundary delay units and clock boundary delay units is within the range of 0 to 31, then the sum is the optimal phase of the data and the optimal phase of the clock. Otherwise, subtract a certain value from the sum to make it within the range of 0 to 31. The value after subtracting this value is the optimal phase of the data and the optimal phase of the clock.

[0076] Preferably, the method further includes:

[0077] In the FPGA Ethernet engineering constraints document, the optimal phase constraints for clock and data are fixed, and the IDELAY_TYPE in IDELAYE2 is set from the variable delay "VAR_LOAD" to "FIXED".

[0078] This application provides an FPGA, which includes an FPGA Ethernet engineering constraint file, wherein the optimal phase of the data and the optimal phase of the clock in the PGA Ethernet engineering constraint file are obtained by the method described above.

[0079] This application provides a system for quickly finding the optimal phase of an Ethernet network based on an FPGA, including: an FPGA, an Ethernet PHY, an RJ45 connector, and a network tester;

[0080] The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to an RJ45 connector; the other end of the RJ45 connector is connected to a network tester.

[0081] The FPGA is equipped with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2.

[0082] The network tester performs high-volume, full-load data transmission with the FPGA, while simultaneously performing packet loss tests on the FPGA.

[0083] The system determines the optimal Ethernet phase according to the method described above.

[0084] Example

[0085] This embodiment utilizes the VIO IP in the FPGA CHIPSICOPE to modify the delay parameter `delay_clk_cnt` in the primitive `IDELAY2` on a computer interface. Then, a network tester determines the optimal delay time through high-volume, full-load Ethernet communication, thereby calculating the optimal phase. Specifically, the received Ethernet data is fixed at three different delay units: 0, 12, and 31. The FPGA's built-in primitive `IDELAY2` is used to delay the Ethernet receive clock `rgmii_rxc`, with `IDELAY_TYPE` set to "VAR_LOAD" mode. The delayed `rgmii_rxc_dly` is connected to the Ethernet IP (tri_mac). The delay parameter `delay_clk_cnt` and the delay switch `delay_en` in the primitive are connected to the CHIPSICOPE's VIO. By setting different delay units from 0 to 31 on the CHIPSICOPE interface, Ethernet data transmission and reception are tested. This allows the identification of the boundary delay unit between packet loss / error and stable data transmission and reception without packet loss / error. Then, by combining the chip's own delay resolution (delay_resolution), the stable communication data obtained through testing, and the clock delay unit (boundary phase), the optimal phase is calculated. Finally, the calculated optimal phase between the Ethernet receiver data and the clock is executed via commands in the FPGA constraint file. By using CHIPSCOPE VIO and IDELAYE2, the delay between data and the clock is dynamically adjusted, improving stability, reliability, flexibility, and monitorability.

[0086] like Figure 2As shown, the hardware system required for implementation in this embodiment includes: an FPGA, an Ethernet PHY, an RJ45 connector, and a network tester. The FPGA controls the Ethernet PHY, and one end of the PHY is connected to the RJ45 connector; the other end of the RJ45 connector is connected to the network tester. This embodiment uses an 88E1111 as the Ethernet PHY. After the hardware is prepared, the specific implementation of the solution involves the following steps:

[0087] Step 1: Build an FPGA Ethernet project

[0088] like Figure 3 As shown, in the FPGA Ethernet project, the IDELAYE2 primitive is instantiated (called), and the delay mode IDELAY_TYPE in IDELAYE2 is set to "VAR_LOAD".

[0089] Connect the IDELAYE2 data port IDATAIN to the external clock rgmii_rxc, the IDELAYE2 output port DATAOUT to the FPGA rgmii_rxc_dly, the IDELAYE2 port CNTVALUEIN to the delay_clk_cnt in VIO, the IDELAYE2 port LD to the delay_en in VIO, and simultaneously connect the FPGA rgmii_rxc_dly to the rgmii_rxc in tri_macIP.

[0090] After completing the FPGA project, copy the FPGA Ethernet project three times and constrain the clock delay of the Ethernet reception to 0 units, 12 units, and 31 units respectively.

[0091] Step 2: Find the boundary phase

[0092] like Figure 4 As shown, connect the RJ45 port to the test port of the network tester using a gigabit Ethernet cable, and connect the control port of the network tester to the network port of the computer using a gigabit Ethernet cable. After preparation, power on the board (including the FPGA hardware system) and the network tester.

[0093] After power-on, the engineering firmware with a data delay of 0 units is downloaded to the SRAM in the FPGA. Then, using a binary search method, delay_clk_cnt is set on the CHIPSCOPE interface of the FPGA, which triggers delay_en.

[0094] The binary search method works as follows: IDELAYE2 has 31 delays. First, the delay is set at 16 delay taps, and a packet loss test is performed. If no packet loss occurs, the tap value for no packet loss is calculated around tap 16. If packet loss occurs, the delay is set at tap 8 or 24, and the packet loss test is performed again. If no packet loss occurs, the tap value for no packet loss is calculated; if packet loss occurs, it is set at tap 4 or 28, and so on. Using the binary search method to calculate the clock delay range is faster.

[0095] Then, use a network tester to perform data transmission and reception to observe whether packet loss occurs. If packet loss or errors still occur after searching through all 31 clock delay units in a project with a data delay of 0 units, switch to a project with a data delay of 12 or 31 units. Continue this process until the clock phases Tdelay_clk_cnt and Tdelay_clk_cnt-1 are found to have no packet loss, Tdelay_clk_cnt-1 has packet loss, Tdelay_clk_cnt-2 has packet loss, Tdelay_clk_cnt+1 has no packet loss, and Tdelay_clk_cnt+2 has no packet loss. At this point, the Ethernet data delay units Tdata_delay and Tdelay_clk_cnt are the boundary phases of the Ethernet network.

[0096] Step 3: Calculate the optimal phase

[0097] After identifying the boundary phases of Ethernet, it is necessary to calculate the optimal phase for stable Ethernet communication. For example... Figure 5 As shown, since the RGMII_RXC clock of Gigabit Ethernet is 125MHz, one cycle is 8ns, half a cycle is 4ns, and phase instability usually occurs around the middle of half a cycle, which is 2ns in a quarter cycle.

[0098] Calculate the delay resolution (delay_resolution). The formula is as follows:

[0099] delay_resolution=1 / (32*2*f)*1000000(ps)

[0100] The reference clock frequency f is in MHz.

[0101] When f = 200MHz, delay_resolution = 78ps (Note: the calculated value is 78.125ps, but it will be rounded down to 78ps); when f = 300MHz, delay_resolution = 52ps.

[0102] The calculated tap value (2ns / 78ps) between them is 25.64. The safe distance ranges from 3 to 5 taps, and after removing the unstable values ​​at the beginning and end (including the safe distance), it is rounded to 22 taps.

[0103] Add 22 taps to the boundary values ​​Tdata_delay and Tdelay_clk_cnt tested in step two. If the values ​​of Tdata_delay_tap and Tdelay_clk_cnt_tap are within the range of 0 to 31 after the addition, then these values ​​are the optimal phases Tdata_delay_best and Tdelay_clk_cnt_best. If the values ​​of Tdata_delay_tap and Tdelay_clk_cnt_tap are outside the range of 0 to 31 after the addition, subtract a certain value from both Tdata_delay_tap and Tdelay_clk_cnt_tap to bring their values ​​within the range of 0 to 31. The values ​​after subtracting this value are the optimal ranges Tdata_delay_best and Tdelay_clk_cnt_best.

[0104] Fourth, fixed phase

[0105] In the FPGA Ethernet project constraint file, fix the optimal phase constraints for clock and data, and simultaneously set IDELAY_TYPE in IDELAYE2 from the variable delay "VAR_LOAD" to "FIXED". Regenerate a new project file. This will find the optimal phase, enabling stable and reliable network communication.

[0106] It is understood that the detailed functional implementation of each of the above units / modules can be found in the description in the aforementioned method embodiments, and will not be repeated here.

[0107] It should be understood that the above-described device is used to execute the methods in the above embodiments. The implementation principle and technical effect of the corresponding program modules in the device are similar to those described in the above methods. The working process of the device can be referred to the corresponding process in the above methods, and will not be repeated here.

[0108] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0109] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0110] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0111] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0112] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0113] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0114] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for quickly finding the optimal phase of an Ethernet network based on an FPGA, characterized in that, The method includes: Build an FPGA Ethernet project that can operate in different data delay units and clock delay units; By conducting packet loss tests on FPGA Ethernet projects, we identified the data boundary delay unit and clock boundary delay unit from stable data transmission and reception without packet loss or errors to a point where packets are lost or incorrect. The reference clock delay taps during the phase instability period are calculated and superimposed on the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication. The criteria for determining the data boundary delay unit and clock boundary delay unit from packet loss / error to stable data transmission and reception without packet loss / error are as follows: When the data delay unit is fixed at... In the case of, if , Packet loss Packet loss No packet loss If no packets are lost, then and This refers to the data boundary delay unit and clock boundary delay unit in Ethernet. The specific steps for calculating the reference clock delay during phase instability are as follows: Calculate the delay resolution ; Calculate the reference clock delay during phase instability ; in, The reference clock frequency is indicated, and the safe distance ranges from [3 taps, 5 taps].

2. The method as described in claim 1, characterized in that, The specific steps for constructing the FPGA Ethernet project are as follows: Call the IDELAYE2 primitive to set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD"; Connect the IDELAYE2 port IDATAIN to the external clock rgmii_rxc, the port DATAOUT to the Ethernet IP rgmii_rxc to output rgmii_rxc_dly, the port CNTVALUEIN to the VIO IP delay_clk_cnt, and the port LD to the VIO IP delay_en. Connect the rgmii_rx_data in the Ethernet IP to the external rgmii_rx_data.

3. The method as described in claim 2, characterized in that, The following details how it is made to work in different data delay units and clock delay units: Make three copies of the FPGA Ethernet project and constrain the clock delay of the Ethernet reception to 0 units, 12 units, and 31 units respectively, to obtain projects with data delays of 0 units, 12 units, and 31 units. After power-on, the engineering firmware with data delays of 0 units, 12 units, and 31 units is downloaded to the FPGA. Different delay_clk_cnt values ​​are set on the FPGA's VIO IP visualization interface. After setting, delay_en is triggered to perform packet loss tests.

4. The method as described in claim 3, characterized in that, With a fixed data delay unit, a binary search method is used to change delay_clk_cnt.

5. The method as described in claim 1, characterized in that, The superposition of data boundary delay units and clock boundary delay units yields the optimal data phase and clock phase in Ethernet data communication, as detailed below: If the sum of the data boundary delay units and clock boundary delay units is within the range of 0 to 31, then the sum is the optimal phase of the data and the optimal phase of the clock. Otherwise, subtract a certain value from the sum to make it within the range of 0 to 31. The value after subtracting this value is the optimal phase of the data and the optimal phase of the clock.

6. The method according to any one of claims 1 to 5, characterized in that, The method also includes: In the FPGA Ethernet engineering constraints document, the optimal phase constraints for clock and data are fixed, and the IDELAY_TYPE in IDELAYE2 is set from "VAR_LOAD" to "FIXED".

7. An FPGA, characterized in that, The FPGA includes an FPGA Ethernet engineering constraint file, wherein the optimal phase of the data and the optimal phase of the clock in the FPGA Ethernet engineering constraint file are obtained by the method described in any one of claims 1 to 6.

8. A system for rapidly finding the optimal phase of an Ethernet network based on an FPGA, characterized in that, include: FPGA, ETHERNETPHY, RJ45 connectors, and network testers; The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to an RJ45 connector; the other end of the RJ45 connector is connected to a network tester. The FPGA is equipped with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2. The network tester performs high-volume, full-load data transmission with the FPGA, while simultaneously performing packet loss tests on the FPGA. The system determines the optimal Ethernet phase according to the method described in any one of claims 1 to 6.

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