Method of manufacturing semiconductor device and semiconductor device

Abstract

A method of manufacturing a semiconductor device and a semiconductor device. In one embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers alternating with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming a first spacer on the sidewalls of the dummy gate stack, and forming a second spacer over the sidewalls of the dummy gate stack. Growing an epitaxial source / drain region extending through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on a first portion of the epitaxial source / drain region, forming a coating on the metal-semiconductor alloy region, and during the formation of the metal-semiconductor alloy region and the coating, forming a second portion of the epitaxial source / drain region. A remaining layer is formed on the sidewalls of the first spacer, and a wet cleaning process is performed to selectively etch the remaining layer from the sidewalls of the first spacer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices having alloy regions and contacts over source / drain regions and methods of making the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate, and patterning the various material layers using lithography to form a plurality of circuit components and a plurality of elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing feature size, which allows more components to be integrated within a given area. However, as the minimum feature size decreases, other problems arise that should be solved. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a multilayer stack above a semiconductor substrate, the multilayer stack comprising a plurality of sacrificial layers alternating with a plurality of channel layers; forming a dummy gate stack above a top surface and a plurality of sidewalls of the multilayer stack; forming a plurality of first spacers on the plurality of sidewalls of the dummy gate stack; growing an epitaxial source / drain region extending through the plurality of sacrificial layers and the plurality of channel layers, wherein the epitaxial source / drain region is adjacent to the dummy gate stack; forming a metal-semiconductor alloy region on a plurality of first portions of the epitaxial source / drain region; forming a coating on the metal-semiconductor alloy region, wherein during the formation of the metal-semiconductor alloy region and the coating, a residual layer is formed on a plurality of sidewalls of the first spacers; and performing a wet cleaning process to selectively etch the residual layer from the sidewalls of the first spacers while leaving the metal-semiconductor alloy region and the coating on the first portions of the epitaxial source / drain region.

[0005] Other embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: sequentially depositing a first sacrificial layer and a first channel layer over a semiconductor substrate; patterning the first sacrificial layer, the first channel layer, and the semiconductor substrate to form a fin structure protruding from the semiconductor substrate; forming a plurality of isolation regions on opposite sides of the fin structure, wherein the fin structure protrudes above a plurality of top surfaces of the isolation regions; forming a first source / drain region in the fin structure, the first source / drain region extending through the first sacrificial layer and the first channel layer; forming an insulating fin extending into the fin structure and isolating a first portion of the fin structure from a second portion of the fin structure; forming a metal-semiconductor alloy region over the first source / drain region; forming a coating over the metal-semiconductor alloy region, wherein during the formation of the coating and the metal-semiconductor alloy region, a residual layer is formed on a top surface of the insulating fin and a plurality of top surfaces of the isolation region; and performing a wet etching process to selectively etch the residual layer from the top surface of the insulating fin and a plurality of top surfaces of the isolation region.

[0006] Still other embodiments of the present disclosure provide a semiconductor device comprising: a gate structure, a plurality of source / drain regions, a first channel layer, a plurality of internal spacers, a metal-semiconductor alloy region, and a coating. The gate structure is above a semiconductor substrate. A plurality of source / drain regions are above the semiconductor substrate and on opposite sides of the gate structure. The first channel layer is disposed between the plurality of source / drain regions and above the semiconductor substrate. A plurality of internal spacers are between a first end of the first channel layer and the semiconductor substrate, wherein the gate structure fills a space between the internal spacers. A metal-semiconductor alloy region is above a top surface and a plurality of sidewalls of each of the source / drain regions. A coating is above the metal-semiconductor alloy region, wherein a material of the metal-semiconductor alloy region and a material of the coating are different. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be seen in the following detailed description and in conjunction with the accompanying Figure 1 Please read together for the best understanding. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a nanostructure field-effect transistor (nano-FET) is depicted in a three-dimensional view according to some embodiments;

[0009] Figures 2 to 24C are cross-sectional and top views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments;

[0010] FIG. 25A to FIG. 28D are cross-sectional views of further intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0011]

Explanation of symbols

[0012] 50:Substrate

[0013] 50N: n-type region

[0014] 50P: p-type region

[0015] 52: Multi-layer stacking

[0016] 52A: first semiconductor layer

[0017] 52B: Second semiconductor layer

[0018] 54:Semiconductor fins

[0019] 56: Nanostructure

[0020] 56A: First Nanostructure

[0021] 56B: Second Nanostructure

[0022] 60A: Groove

[0023] 60B: Groove

[0024] 62: Fin structure

[0025] 62N: Fin structure

[0026] 62P: Fin structure

[0027] 66: Dielectric layer

[0028] 68: Dielectric wall

[0029] 72: Virtual dielectric layer

[0030] 74: dummy gate layer

[0031] 76: Mask layer

[0032] 78: Isolation Area

[0033] 80: Fork-shaped sheet structure

[0034] 88: Channel area

[0035] 92: Virtual dielectric

[0036] 94: dummy gate

[0037] 96: Mask

[0038] 97: Fin spacer

[0039] 98: Gate spacer

[0040] 99: Gate spacer

[0041] 102: Source / drain recess

[0042] 104: Internal spacer

[0043] 106: Source / drain region

[0044] 106A: first semiconductor material layer

[0045] 106B: second semiconductor material layer

[0046] 112: Contact etching stop layer

[0047] 114: First interlayer dielectric

[0048] 116: First hard mask layer

[0049] 117: Second hard mask layer

[0050] 118: Groove

[0051] 119: Dielectric layer

[0052] 120: Gate structure

[0053] 120A: Gate structure

[0054] 120B: Gate structure

[0055] 121: concave part

[0056] 122: Gate dielectric

[0057] 124: Gate electrode

[0058] 125: Metal-Semiconductor Alloy Region

[0059] 126: Coating

[0060] 127: Remaining layer

[0061] 128: Wet cleaning process

[0062] 129: Contact Etch Stop Layer

[0063] 130: Dielectric layer

[0064] 134: Opening

[0065] 136: Etching stop layer

[0066] 138: Second interlayer dielectric

[0067] 139: Gate contact opening

[0068] 140: Gate contact

[0069] 141: Source / drain contact opening

[0070] 142: Source / drain contact

[0071] 143: Groove

[0072] 144: Dielectric layer

[0073] AA: Cross section

[0074] BB: Cross section

[0075] CC: Cross-section

[0076] H1: Height

[0077] H2: Height

[0078] H3: Height

[0079] H4: Height

[0080] H5: Height

[0081] T1: Thickness

[0082] T2: Thickness

[0083] T3:Thickness

[0084] T4:Thickness

[0085] W1: Width

[0086] W2: Width

[0087] W3: Width

[0088] W4: Width

[0089] W5: Width

[0090] W6: Width

[0091] W7: Width

[0092] XX: Cross section DETAILED DESCRIPTION

[0093] The disclosure that follows provides many different implementations or embodiments to implement the different features of the disclosure. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not restrictive. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0094] Additionally, to facilitate describing the relationship of one element or feature to another element or feature as depicted in the figures, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0095] Various embodiments provide semiconductor devices with improved performance and methods for forming the same. The semiconductor device may be a nanostructured field effect transistor (nano-FET), which may be a nanosheet field-effect transistor (NSFET), a nanowire field-effect transistor (NWFET), a gate-all-around field-effect transistor (GAAFET), a forksheet field-effect transistor, or the like. These embodiments provide methods for planarizing multiple top surfaces of a gate stack and an adjacent interlayer dielectric (ILD) layer, and for removing the interlayer dielectric layer to form multiple first openings that expose the top and side surfaces of the source / drain region below a layer of the nanostructured field effect transistor. A plasma deposition process is then performed to sequentially form a titanium silicide (TiSi) layer and a titanium silicon nitride (TiSiN) layer over the exposed top and side surfaces of the source / drain region. A wet etching process is then performed to selectively etch the TiSiN and titanium nitride (TiN) formed during the plasma deposition process from multiple surfaces of the gate stack and other structures, while leaving the TiSi layer and TiSiN layer above the source / drain region. The wet etching process is performed using sulfuric acid (H2SO4) as an etchant. Multiple advantageous features of one or more embodiments disclosed herein may allow for an increase in the effective area of ​​the TiSi / TiSiN bilayer on the source / drain region, which contacts the subsequently formed source / drain contacts. This results in a reduction in the contact resistance between the source / drain contacts and the source / drain region. As a result, there is a more efficient flow of current through the source / drain contacts, minimizing power dissipation at the source / drain contacts, and improving output resistance (RO), allowing the semiconductor device to drive or deliver power to a load without significant voltage or current losses. Further, the use of a wet etching process allows selective etching of TiSiN and titanium nitride (TiN) formed during the plasma deposition process from the surface of the gate stack and other structures (e.g., the sidewalls of the first opening) while minimizing etching damage to the TiSi layer and the TiSiN layer above the source / drain region. As a result, source-drain contacts having lower contact resistance can be subsequently formed and have unimpeded electrical contact with the source / drain region, which further leads to improved device performance and device yield.

[0096] Figure 1 An example of a simplified nanostructure field effect transistor is depicted in accordance with some implementations. Figure 1The three-dimensional cross-sectional view omits some features of the nanostructure field effect transistor for clarity. In the illustrated embodiment, the nanostructure field effect transistor is a fork-shaped sheet field effect transistor. However, the nanostructure field effect transistor may also be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate all-around field effect transistor (GAAFET), or the like.

[0097] The nanostructure field effect transistor includes a plurality of nanostructures 56 above a substrate 50, for example extending from the substrate 50 above a semiconductor fin 54. The nanostructure 56 is a semiconductor layer that serves as a channel region for the nanostructure field effect transistor. An isolation region 78, such as a shallow trench isolation (STI) region, is disposed above the substrate 50 and adjacent to the semiconductor fin 54. Although the isolation region 78 is described / illustrated as being separated from the substrate 50, the term "substrate" as used herein may refer to a separate substrate 50 or a combination of the substrate 50 and the isolation region 78. In addition, although the semiconductor fin 54 is illustrated as a single continuous material with the substrate 50, the semiconductor fin 54 and / or the substrate 50 may include a single material or multiple materials. In this case, the semiconductor fin 54 refers to a portion that extends above the adjacent plurality of isolation regions 78 and extends between the adjacent plurality of isolation regions 78.

[0098] The gate structure 120 surrounds the nanostructure 56 and is disposed above the semiconductor fin 54. The gate structure 120 includes a gate dielectric 122 and a gate electrode 124. The gate dielectric 122 is along the top surface, sidewalls, and bottom surface of the nanostructure 56, and may extend along the sidewalls and / or above the top surface of the semiconductor fin 54. The gate dielectric 122 may also extend along the top surface of the isolation region 78. The gate electrode 124 is on the gate dielectric 122. The epitaxial source / drain regions 106 are disposed on opposite sides of the gate structure 120. In embodiments where multiple transistors are formed, the epitaxial source / drain regions 106 may be shared between the respective transistors. One or more interlayer dielectric (ILD) layers (discussed in more detail below) are formed over the epitaxial source / drain regions 106 and / or gate structure 120 through which multiple contacts are formed to the epitaxial source / drain regions 106 and gate electrode 124 (discussed in more detail below).

[0099] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N includes an n-type device, such as an NMOS transistor, for example, an n-type nanostructure field effect transistor, and the p-type region 50P includes a p-type device, such as a PMOS transistor, for example, a p-type nanostructure field effect transistor. In the illustrated embodiment, the nanostructure field effect transistor is a fork-type field effect transistor. In a fork-type field effect transistor, both the n-type device and the p-type device are integrated in the same fork-type structure. The dielectric wall 68 separates the semiconductor fins 54, nanostructures 56, and epitaxial source / drain regions 106 for the n-type device from the semiconductor fins 54, nanostructures 56, and epitaxial source / drain regions 106 for the p-type device. The gate structure 120 extends along three sides of each nanostructure 56. The fork-type field effect transistor allows n-type devices and p-type devices to be formed close to each other and allows multiple gate structures 120 for these devices to be physically and electrically coupled to each other, thereby reducing the number of gate contacts used in the CMOS process.

[0100] Figure 1 Reference cross sections used in subsequent figures are further depicted. Cross section AA is along the longitudinal axis of gate structure 120. Cross section BB is along the longitudinal axis of nanostructure 56 and in the direction of current flow, for example, between multiple epitaxial source / drain regions 106. In addition, cross section BB is perpendicular to cross section AA. Cross section CC is parallel to cross section AA and extends through epitaxial source / drain regions 106. For clarity, subsequent figures refer to these reference cross sections.

[0101] Figures 2 to 24C are cross-sectional views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments. Specifically, the fabrication of device layers of a nanostructured field effect transistor is depicted, and the nanostructured field effect transistor is described in the context of a fork-type field effect transistor. FIG. 25A to FIG. 28D are cross-sectional views of various intermediate stages in the fabrication of semiconductor devices according to other embodiments. In particular, the fabrication of device layers of nanostructured field effect transistors is depicted, and the nanostructured field effect transistors are described in the context of nanosheet field effect transistors (NSFETs). Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A ,and Fig.28A It is along Figure 1 Multiple cross-sectional views shown with reference to section AA in FIG. Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B ,and Fig.28B It is along Figure 1 Multiple cross-sectional views shown with reference to section BB in FIG. Fig. 9C , Fig. 10C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.25D , Fig.26C , Fig.26D , Fig.27C , Fig.27D , Fig.28C ,and Fig.28D It is along Figure 1 Multiple cross-sectional views shown in reference section CC.

[0102] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, and the semiconductor substrate may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, a semiconductor on insulator substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0103] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanostructure field effect transistor, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanostructure field effect transistor. The n-type region 50N may (or may not) be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P.

[0104] A multilayer stack 52 is formed over the substrate 50 . The multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed of a first semiconductor material, and the second semiconductor layers 52B are formed of a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50 .

[0105] In the illustrated embodiment, as described in more detail later, the first semiconductor layer 52A (e.g., also referred to as a sacrificial layer) will be removed, and the second semiconductor layer 52B (e.g., also referred to as a channel layer) will be patterned to form a channel region for a nanostructure field effect transistor in both the n-type region 50N and the p-type region 50P. In such multiple embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. The first semiconductor layer 52A is a dummy layer that will be removed in subsequent processing to expose the top and bottom surfaces of the second semiconductor layer 52B. The first semiconductor material of the first semiconductor layer 52A is a material with high etching selectivity relative to the etching of the second semiconductor layer 52B, such as silicon germanium. The second semiconductor material of the second semiconductor layer 52B is a material suitable for both n-type devices and p-type devices, such as silicon.

[0106] In another embodiment (not shown separately), the first semiconductor layer 52A is patterned to form a channel region for the nanostructure field effect transistor in one type of region (e.g., the p-type region 50P), and the second semiconductor layer 52B is patterned to form a channel region for the nanostructure field effect transistor in another type of region (e.g., the n-type region 50N). The first semiconductor material of the first semiconductor layer 52A can be a material suitable for a p-type device, such as silicon germanium (e.g., Si x Ge 1-x , where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layer 52B can be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can have a high etching selectivity relative to each other, so that the first semiconductor layer 52A can be removed in the n-type region 50N without significantly removing the second semiconductor layer 52B, and the second semiconductor layer 52B can be removed in the p-type region 50P without significantly removing the first semiconductor layer 52A.

[0107] In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 52A and three second semiconductor layers 52B. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 52A and second semiconductor layers 52B. Each layer of the multilayer stack 52 may be grown via a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited via a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. In some embodiments, some layers of the multilayer stack 52 are formed to be thinner than other layers of the multilayer stack 52.

[0108] exist Figure 3 In the embodiment, a plurality of etched grooves 60A and 60B are formed in the substrate 50 and the multilayer stack 52 to form a plurality of fin structures 62 (e.g., a fin structure 62N in the n-type region 50N and a fin structure 62P in the p-type region 50P). The plurality of fin structures 62 each include a semiconductor fin 54 and a nanostructure 56. The semiconductor fin 54 is a semiconductor strip patterned in the substrate 50. The nanostructure 56 includes a remaining portion of the multilayer stack 52 on the semiconductor fin 54. Specifically, the nanostructure 56 includes alternating first nanostructures 56A and second nanostructures 56B. The first nanostructure 56A and the second nanostructure 56B are formed by the remaining portions of the first semiconductor layer 52A and the second semiconductor layer 52B, respectively. In the illustrated embodiment, the plurality of second nanostructures 56B are each disposed between two first nanostructures 56A. The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof, and may be performed using an etch mask having a pattern of the fin structure 62. The etching may be anisotropic.

[0109] The fin structure 62 may be patterned by any suitable method. For example, the fin structure 62 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the pattern to be created to have, for example, a smaller pitch (smaller than the pitch obtained using a single direct photolithography process). For example, in one embodiment, a sacrificial layer is formed above the substrate, and the sacrificial layer is patterned using a photolithography process. A plurality of spacers are formed along the side of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure 62.

[0110] The width W1 of each of the plurality of fin structures 62 may be in a range from 8 nanometers to 20 nanometers. For illustrative purposes, the plurality of fin structures 62 in the n-type region 50N and the p-type region 50P are depicted as having substantially equal widths. In some embodiments, the fin structures 62 in one region (e.g., the n-type region 50N) may be wider or narrower than the fin structures 62 in another region (e.g., the p-type region 50P).

[0111] The plurality of fin structures 62 are formed into a plurality of adjacent pairs of fin structures. Each pair of fin structures 62 will be used to form a fork-type field effect transistor. One fin structure 62N in each pair will be used to form an n-type device, and the other fin structure 62P in each pair will be used to form a p-type device. The fin structures 62N and 62P in each pair can be separated by corresponding grooves 60A. A dielectric wall (discussed in more detail below) will be formed in the groove 60A between each pair of fin structures 62N and 62P, thereby providing electrical isolation between multiple nanostructure field effect transistors of different types to be formed in the fin structures 62N and 62P. Multiple adjacent pairs of fin structures 62 (not shown in the figure) are separated by corresponding grooves 60B. The width of each of the plurality of grooves 60B may be greater than the width of the groove 60A, so that the plurality of adjacent pairs of fin structures 62 are separated farther than the fin structures 62N and 62P in each pair.

[0112] exist Figure 4, a dielectric layer 66 is then formed over the substrate 50 and the fin structures 62 and in the trenches 60A and 60B. For example, the dielectric layer 66 may be formed on the sidewalls of each of the plurality of fin structures 62 and on the bottom surfaces of the plurality of trenches 60A and 60B. The dielectric layer 66 may be formed of a low-k dielectric material, such as silicon nitride, silicon carbonitride, or the like, and the deposition of the dielectric layer 66 may be via a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0113] Because trenches 60A, 60B have different widths, trenches 60A, 60B are trench filled with different amounts of dielectric material. Because trench 60A has a narrower width, trench 60A is completely filled (or overfilled) with dielectric layer 66. However, because trench 60B has a larger width, trench 60B is not completely filled with dielectric layer 66. In other words, after depositing dielectric layer 66, trench 60A is filled (or overfilled), but some portions of trench 60B remain unfilled.

[0114] exist Figure 5 In the embodiment of the present invention, the dielectric layer 66 is etched back to remove some parts of the dielectric layer 66. Specifically, multiple parts of the dielectric layer 66 in the trench 60B and above the fin structure 62 are removed via back etching, thereby re-forming the trench 60B. The dielectric layer 66 is etched back using an acceptable etching technique, such as using an etching process that is selective to the dielectric layer 66 (e.g., etching the material of the dielectric layer 66 at a faster rate than the material of the fin structure 62 and the substrate 50). After the back etching is completed, the remaining part of the dielectric layer 66 is in the trench 60A. The remaining part of the dielectric layer 66 forms a dielectric wall 68, which separates the fin structures 62N and 62P in each pair of fin structures 62. The dielectric wall 68 may partially or completely fill the trench 60A. Each of the plurality of dielectric walls 68 may have a width W2 in the range of from 5 nanometers to 20 nanometers. In one embodiment, each of the plurality of dielectric walls 68 may have a height H1 in a range from 50 nanometers to 200 nanometers. In one embodiment, each of the plurality of dielectric walls 68 may have a length L1 in a range from 10 nanometers to 80 nanometers, wherein the length L1 is along the longitudinal axis of the dielectric wall 68, and the longitudinal axis is perpendicular to the axis of the measured width W2. After the dielectric layer 66 is formed and the back etching is completed, the fork-shaped sheet structure 80 extends from the substrate 50. The plurality of fork-shaped sheet structures 80 each include a dielectric wall 68 and a pair of a plurality of fin structures 62, and the dielectric wall 68 is disposed between these fin structures 62.

[0115] As described above, although one n-type region 50N and one p-type region 50P are depicted, the substrate 50 may include any desired number of such regions. Each fork-shaped sheet structure 80 is disposed at the boundary of the n-type region 50N and the p-type region 50P. In addition, the fin structures 62N, 62P of each fork-shaped sheet structure 80 may alternate. In other words, each n-type region 50N may include a first fin structure 62N from a first fork-shaped sheet structure 80, and include a second fin structure 62N from a second fork-shaped sheet structure 80.

[0116] exist Figure 6 In the embodiment of the present invention, an insulating material is formed over the substrate 50, the fin structure 62, and the dielectric wall 68. The insulating material also fills the trench 60B. The insulating material may be an oxide, such as silicon oxide, nitride, the like, or a combination thereof, and the insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material includes silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not illustrated separately) may be first formed along the top surface of the substrate 50, the sidewalls and top surface of the fin structure 62, and the top surface of the dielectric wall 68. Thereafter, a filling material may be formed over the liner, such as one of the multiple insulating materials previously described. Insulating material may be deposited over the fin structures 62 and the dielectric walls 68 such that excess insulating material covers the fin structures 62 and the dielectric walls 68 .

[0117] The insulating material is then recessed to form an isolation region 78. The isolation region 78 is adjacent to each fork-shaped sheet structure 80. The insulating material is recessed so that multiple upper portions of the multiple fin structures 62 and the dielectric wall 68 protrude from between the adjacent multiple isolation regions 78. For example, a portion of the semiconductor fin 54 and the corresponding nanostructure 56 of each fin structure 62 are higher than the isolation region 78. In addition, the top surface of the isolation region 78 may have a flat surface, a convex surface, a concave surface (e.g., a concave), or a combination thereof as shown. Through appropriate etching, the top surface of the isolation region 78 may be formed to be flat, convex, and / or concave. The isolation region 78 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin structure 62 and the dielectric wall 68). The isolation region 78 may also be referred to as a shallow trench isolation (STI) region.

[0118] The process previously described is only one embodiment of how to form the semiconductor fins 54 and the nanostructures 56. In some embodiments, a mask and epitaxial growth process may be used to form the semiconductor fins 54 and the nanostructures 56. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a plurality of trenches may be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure may be epitaxially grown in the trenches, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the semiconductor fins 54 and the nanostructures 56. The epitaxial structure may include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid previous and / or subsequent implantation, although in situ doping and implantation doping may be used together. A removal process may be performed to remove some of the epitaxially grown material from the desired area.

[0119] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 72 is formed over the isolation region 78, the fin structure 62, and the dielectric wall 68. For example, the dummy dielectric layer 72 may be formed on multiple sidewalls of the semiconductor fin 54 and the nanostructure 56. The dummy dielectric layer 72 is also formed on the top surface of the topmost nanostructure 56 of each fin structure 62, as well as on the top surface of the isolation region 78 and the top surface of the dielectric wall 68. The dummy dielectric layer 72 may be formed of silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then planarized, for example, by chemical mechanical polishing (CMP). The dummy gate layer 74 may be formed of a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The material deposited on the dummy gate layer 74 may be deposited via chemical vapor deposition, physical vapor deposition (PVD), sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 74 may be formed of other materials having high etch selectivity for etching of insulating materials (e.g., isolation regions 78 and / or dummy dielectric layers 72). A mask layer 76 may be deposited over the dummy gate layer 74. The mask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this embodiment, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 78 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 78. In another embodiment, the dummy dielectric layer 72 only covers the fin structure 62.

[0120] exist FIG. 8A to FIG. 8B In the embodiment of the present invention, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 96. Fig. 8A An n-type region 50N and an adjacent p-type region 50P are shown, and Figure 8BEither the n-type region 50N or the p-type region 50P may be shown unless otherwise specified. The pattern of the mask 96 is then transferred to the dummy gate layer 74 and the dummy dielectric layer 72 to form the dummy gate 94 and the dummy dielectric 92, respectively. The dummy gate 94 covers multiple portions of the multiple nanostructures 56, which will be exposed in subsequent processing to form multiple channel regions. Specifically, the dummy gate 94 extends along the portion of the nanostructure 56 that will be used to form the channel region 88. The pattern of the mask 96 can be used to physically separate multiple adjacent dummy gates 94. The dummy gate 94 may also have a longitudinal direction that is substantially perpendicular (within process variations) to the longitudinal direction of the fin structure 62. After patterning, the mask 96 can be optionally removed, for example via an acceptable etching technique. Each dummy gate 94 and its corresponding dummy dielectric 92 form a dummy gate stack. Multiple adjacent dummy gate stacks may have different widths. For example, as in Figure 8B As shown in , the first dummy gate stack may have a width W3, and the second dummy gate stack adjacent to the first dummy gate stack may have a width W4, wherein the width W4 is greater than the width W3.

[0121] A gate spacer 98 is then formed over the fin structure 62, for example, on the exposed sidewalls of the mask 96, the dummy gate 94, and the dummy dielectric 92. The gate spacer 98 may be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be a low dielectric constant dielectric material, such as silicon carbon nitride, silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbon nitride, or the like. Acceptable deposition processes for forming insulating materials include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The gate spacer 98 may be formed of a single layer of insulating material or a multilayer of insulating material. In some embodiments, each of the gate spacers 98 includes a multilayer of silicon oxycarbon nitride, wherein each layer may have a different composition of silicon oxycarbon nitride. In some embodiments, each of the gate spacers 98 includes a layer of silicon oxide disposed between two layers of silicon nitride. Other spacer structures may be formed. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as reactive ion etching, neutral beam etching, or the like. After etching, the gate spacer 98 may have straight sidewalls or curved sidewalls.

[0122] Prior to the formation of the gate spacer 98, implantation may be performed for the lightly doped source / drain (LDD) region. In various embodiments with different device types, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the fin structure 62 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the fin structure 62 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any one of phosphorus, arsenic, antimony, or the like, and the p-type impurity may be any one of boron, boron fluoride, indium, or the like. The lightly doped source / drain region may have a density of about 10 15 cm -3 to about 10 19 cm -3 Annealing may be used to repair implant damage and activate implanted impurities. During implantation, channel region 88 remains covered by dummy gate 94 so that channel region 88 remains substantially free of impurities implanted in the lightly doped source / drain regions.

[0123] Note that the above disclosure generally describes processes for forming spacers and lightly doped source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of multiple steps may be used (e.g., additional spacers may be formed and removed, etc.), and / or the like. Further, different structures and steps may be used to form n-type and p-type devices.

[0124] After forming the gate spacers 98, source / drain recesses 102 are then formed in the fin structure 62. In the illustrated embodiment, the source / drain recesses 102 extend through the nanostructures 56 to expose the semiconductor fins 54 and the isolation regions 78. The source / drain recesses 102 may also extend into the semiconductor fins 54. In other words, the source / drain recesses 102 may be formed only in the nanostructures 56, or may also be formed to extend into the semiconductor fins 54. In various embodiments, the source / drain recesses 102 in the fin structure 62 may extend to the top surface of the semiconductor fin 54 without etching the semiconductor fin 54; the semiconductor fin 54 may be etched so that the bottom surface of the source / drain recesses 102 in the fin structure 62 is disposed below the top surface of the isolation regions 78; or the like. The source / drain recesses 102 may be formed using an acceptable etching process, such as an etching process that is selective to the fin structure 62 (e.g., selectively etches the material of the semiconductor fins 54 and the nanostructures 56 at a faster rate than the material of the dielectric walls 68). Therefore, after the source / drain recesses 102 are formed, the dielectric walls 68 are retained. During the etching process for forming the source / drain recesses 102, the gate spacers 98 and the mask 96 collectively cover portions of the fin structure 62. A timed etching process may be used to stop etching the source / drain recesses 102 after the source / drain recesses 102 reach a desired depth. In one embodiment, after the source / drain recesses 102 are formed, the channel region 88 disposed between adjacent multiple source / drain recesses 102 may have a width W5 in the range of from 10 nanometers to 80 nanometers.

[0125] A plurality of internal spacers 104 are optionally formed on the sidewalls of the plurality of remaining portions of the plurality of first nanostructures 56A, such as those sidewalls exposed by the source / drain recesses 102. As will be discussed in more detail below, source / drain regions will subsequently be formed in the source / drain recesses 102, and the first nanostructures 56A will subsequently be replaced with corresponding gate structures. The internal spacers 104 act as isolation features between the subsequently formed source / drain regions and the subsequently formed gate structures. Further, the internal spacers 104 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for subsequently forming gate structures).

[0126] As one embodiment of forming the internal spacers 104, the source / drain recesses 102 may be extended. Specifically, portions of the sidewalls of the plurality of first nanostructures 56A exposed by the source / drain recesses 102 may be recessed. Although the sidewalls of the plurality of first nanostructures 56A are depicted as straight, the sidewalls may be concave or convex. Recessing the sidewalls may be performed via an acceptable etching process, such as an etching process that is selective to the material of the first nanostructures 56A (e.g., selectively etching the material of the first nanostructures 56A at a faster rate than the material of the second nanostructures 56B and the semiconductor fins 54). The etching may be isotropic. For example, when the semiconductor fins 54 and the second nanostructures 56B are formed of silicon and the first nanostructures 56A are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas, such as hydrogenfluoride (HF) gas. In some embodiments, the same etching process may be performed continuously to form the source / drain recess 102 and recess the sidewalls of the first nanostructure 56A. In some embodiments, the etching process for recessing the sidewalls may also trim (e.g., reduce the thickness) the etched portions of the second nanostructure 56B. The formation of multiple internal spacers 104 may then be performed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material may be a low dielectric constant dielectric material, such as silicon carbon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbon nitride, or the like. Acceptable deposition processes for forming insulating materials include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as reactive ion etching, neutral beam etching, or the like. Although the outer sidewalls of the inner spacer 104 are depicted as being flush with the sidewalls of the gate spacer 98, the outer sidewalls of the inner spacer 104 may extend beyond the sidewalls of the gate spacer 98 or be recessed relative to the sidewalls of the gate spacer 98. In other words, the inner spacer 104 may partially fill, completely fill, or overfill the sidewall recess. Furthermore, although the sidewalls of the inner spacer 104 are depicted as being straight, the sidewalls of the inner spacer 104 may be concave or convex.

[0127] exist 9A to 9C, an epitaxial source / drain region 106 is formed in the source / drain recess 102. The epitaxial source / drain region 106 is formed in the source / drain recess 102 so that each of the plurality of dummy gates 94 is disposed between the corresponding plurality of adjacent pairs of epitaxial source / drain regions 106. In some embodiments, the gate spacer 98 and the inner spacer 104 are used to separate the dummy gate 94 and the first nanostructure 56A from the epitaxial source / drain region 106, respectively, by an appropriate lateral distance so that the epitaxial source / drain region 106 does not short-circuit the gate of the subsequently formed nanostructure field effect transistor. The epitaxial source / drain region 106 may be formed to contact the inner spacer 104 (if present) and may extend beyond the sidewalls of the second nanostructure 56B. The epitaxial source / drain region 106 may exert stress on the second nanostructure 56B, thereby improving performance.

[0128] The epitaxial source / drain regions 106 formed in the n-type region 50N may be formed by covering the p-type region 50P. Then, the epitaxial source / drain regions 106 are epitaxially grown in the source / drain recesses 102 in the n-type region 50N. The epitaxial source / drain regions 106 may include any acceptable material suitable for n-type nanostructure field effect transistors. For example, the epitaxial source / drain regions 106 in the n-type region 50N may include a material that applies tensile strain on the channel region 88, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 106 in the n-type region 50N may have surfaces that protrude from corresponding surfaces of the fin structure 62 and may have multiple crystal planes.

[0129] The epitaxial source / drain regions 106 formed in the p-type region 50P may be formed by covering the n-type region 50N. Then, the epitaxial source / drain regions 106 are epitaxially grown in the source / drain recesses 102 in the p-type region 50P. The epitaxial source / drain regions 106 may include any acceptable material suitable for a p-type nanostructure field effect transistor. For example, the epitaxial source / drain regions 106 in the p-type region 50P may include a material that applies compressive strain on the channel region 88, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain regions 106 in the p-type region 50P may have surfaces that protrude from corresponding surfaces of the fin structure 62 and may have multiple crystal planes.

[0130] The epitaxial source / drain regions 106, second nanostructures 56B, and / or semiconductor fins 54 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a thickness of about 10 19 cm-3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 106 may be in-situ doped during growth.

[0131] As a result of the epitaxial process used to form the epitaxial source / drain regions 106, the upper surface of the epitaxial source / drain regions 106 has a plurality of crystal planes that extend laterally outward beyond the surface of the fin structure 62 (e.g., at Fig. 9C ). After the epitaxial process is completed, the adjacent multiple epitaxial source / drain regions 106 of the adjacent multiple fin structures 62 (e.g., the fork-shaped fin structure 80) remain separated by the dielectric wall 68, so that the merging of the multiple epitaxial source / drain regions 106 is avoided. Therefore, the multiple epitaxial source / drain regions 106 each have a straight bottom surface (contacting the semiconductor fin 54), a straight sidewall (contacting the dielectric wall 68), a crystal-faceted side surface (facing away from the dielectric wall 68), and a crystal-faceted top surface (facing away from the substrate 50).

[0132] The epitaxial source / drain region 106 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 106 may include a first semiconductor material layer 106A and a second semiconductor material layer 106B. Any number of semiconductor material layers may be used for the epitaxial source / drain region 106. Each of the first semiconductor material layer 106A and the second semiconductor material layer 106B may be formed of different semiconductor materials and / or may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 106A may have a dopant concentration that is less than the dopant concentration of the second semiconductor material layer 106B. In multiple embodiments in which the epitaxial source / drain region 106 includes two semiconductor material layers, the first semiconductor material layer 106A may grow from the fin structure 62 and the second semiconductor material layer 106B may grow from the first semiconductor material layer 106A. In one embodiment, a height H2 of each of the plurality of epitaxial source / drain regions 106 from a highest point of the epitaxial source / drain region 106 to a bottom surface of the epitaxial source / drain region 106 is in a range from 40 nanometers to 80 nanometers.

[0133] exist FIG. 10A to FIG. 10CIn the embodiment of the present invention, gate spacers 99 may be formed on the exposed sidewalls of gate spacers 98 and on the top surface of epitaxial source / drain regions 106. Gate spacers 99 may be formed by conformally forming an insulating material and then etching the insulating material. The insulating material may be formed on the top surface and sidewalls of the epitaxial source / drain regions 106, on the top surface and sidewalls of gate spacers 98, and on the top surface of mask 96 (if present) or the top surface of dummy gate 94. The insulating material may be a low dielectric constant dielectric material such as silicon carbon nitride, silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbon nitride, or the like. Acceptable deposition processes for forming the insulating material include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch, such as reactive ion etching, neutral beam etching, or the like, which removes portions of the insulating material from the top surface and sidewalls of the epitaxial source / drain regions 106, the top surface of the gate spacer 98, and the top surface of the mask 96. After performing the etching process, the gate spacer 99 remains on the sidewalls of the gate spacer 98 and on portions of the top surface of the epitaxial source / drain regions 106.

[0134] Further references FIG. 10A to FIG. 10C , and then a first interlayer dielectric (ILD) 114 is formed over the epitaxial source / drain regions 106, dielectric walls 68, isolation regions 78, gate spacers 98, gate spacers 99, mask 96 (if present), or dummy gate 94. The first interlayer dielectric 114 may be formed by depositing a dielectric material over the epitaxial source / drain regions 106, dielectric walls 68, isolation regions 78, gate spacers 98, gate spacers 99, mask 96 (if present), or dummy gate 94. Acceptable dielectric materials may include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides such as silicon nitride; or the like. Other insulating materials may be used. Deposition may be via any suitable method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. Other acceptable processes may be used to form the dielectric material.

[0135] In some embodiments, a contact etch stop layer (CESL) 112 is disposed between the first interlayer dielectric 114 and the epitaxial source / drain regions 106, the dielectric wall 68, the mask 96 (if present) or the dummy gate 94, the gate spacer 98, the gate spacer 99, and the isolation region 78. The contact etch stop layer 112 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etch selectivity relative to the etching of the first interlayer dielectric 114.

[0136] exist FIG. 11A to FIG. 11B In the process, planarization of the first interlayer dielectric 114 is performed. Planarization may be performed by any suitable method, such as chemical mechanical polishing, an etch back process, a combination thereof, or the like. The planarization process makes the top surface of the first interlayer dielectric 114 flush with the top surface of the mask 96 (if present) or the dummy gate 94. The planarization process may also remove the mask 96 and portions of the gate spacers 98 and the gate spacers 99 along the sidewalls of the mask 96. After the planarization process, the top surfaces of the first interlayer dielectric 114, the contact etch stop layer 112, the gate spacers 98, the gate spacers 99, and the mask 96 (if present) or the dummy gate 94 are coplanar (within process variations). Accordingly, the top surface of the mask 96 (if present) or the top surface of the dummy gate 94 is exposed through the first interlayer dielectric 114. In the illustrated embodiment, the mask 96 is retained, and the planarization process causes the top surface of the first interlayer dielectric 114 to be flush with the top surface of the mask 96 .

[0137] FIG. 12A to FIG. 13B A process is shown for dividing each of the fin structures 62N, 62P and the corresponding dummy gate 94 thereover in a pair of fin structures 62 into a plurality of segments electrically insulated from each other. This is accomplished by forming a dielectric layer 119 (also referred to as a dielectric fin or an insulating fin) between adjacent segments in the plurality of segments.

[0138] exist FIG. 12A to FIG. 12BIn the process, a first hard mask layer 116 and a second hard mask layer 117 are sequentially formed over the first interlayer dielectric 114, the mask 96 (if present) or the dummy gate 94, the contact etch stop layer 112, the gate spacer 98, and the gate spacer 99. In some embodiments, the first hard mask layer 116 is a metal hard mask layer and the second hard mask layer 117 is a dielectric hard mask layer. In subsequent processing, the pattern is transferred to the first hard mask layer 116 using various photolithography and etching techniques. The first hard mask layer 116 can then be used as an etch mask for etching the underlying structures (e.g., the mask 96 (if present), the dummy gate 94, the dummy dielectric 92, the nanostructure 56, and the semiconductor fin 54). The first hard mask layer 116 can be a mask material, such as titanium nitride, titanium oxide, the like, or a combination thereof. The first hard mask layer 116 may be formed using a process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, the like, or a combination thereof.

[0139] A second hard mask layer 117 is deposited over the first hard mask layer 116. The second hard mask layer 117 can be used as a mask pattern for the first hard mask layer 116. In subsequent processing steps, the second hard mask layer 117 is patterned to form a plurality of patterns, which can then be transferred to the first hard mask layer 116. The second hard mask layer 117 can be a mask material such as silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), SiO x C y , the like, or a combination thereof. Forming the second hard mask layer 117 may use a process such as chemical vapor deposition, atomic layer deposition, the like, or a combination thereof. In an example embodiment, the first hard mask layer 116 includes titanium nitride, and the second hard mask layer 117 includes silicon nitride.

[0140] Next, a patterned photoresist layer is formed over the first hard mask layer 116 and the second hard mask layer 117. The pattern of the patterned photoresist layer may include openings in the photoresist layer. The pattern in the photoresist layer is transferred to the first hard mask layer 116 and the second hard mask layer 117 using a suitable method, such as one or more anisotropic etching processes. As a result, a pattern (e.g., including an opening) is formed in the first hard mask layer 116 and the second hard mask layer 117, which exposes a portion of the mask 96 (if present) or the dummy gate 94.

[0141] Further references FIG. 12A to FIG. 12B, an etching process is performed using the first hard mask layer 116 and the second hard mask layer 117 as etching masks to form trenches 118. During the etching process, portions of the mask 96 (if present), the dummy gate 94, the dummy dielectric 92, the nanostructure 56, the semiconductor fins 54, and the dielectric walls 68 are removed. This means that the trench 118 extends through the dielectric walls 68 of the fork-shaped sheet structure 80 and this pair of fin structures 62. The trench 118 may extend through the adjacent plurality of gate spacers 98 and be disposed between the adjacent plurality of gate spacers 98, and may also extend through the nanostructure 56. The trench 118 may also extend through the semiconductor fins 54. The etching process may be an anisotropic etching process. The trench 118 separates the first portion of each of the plurality of fin structures 62N, 62P in a pair of fin structures 62 and the corresponding dummy gate 94 thereon from the second portion of each of the plurality of fin structures 62N, 62P in the pair of fin structures 62 and the corresponding dummy gate 94 thereon. Fig. 12B Although not explicitly shown in the figure, the first portion of each of the plurality of fin structures 62N, 62P of the pair of fin structures 62 and the second portion of each of the plurality of fin structures 62N, 62P of the pair of fin structures 62 are located on opposite sides of the trench 118. In one embodiment, the trench 118 extends into the isolation region 78, and the bottom of the trench 118 further extends into the substrate 50.

[0142] exist Fig. 12B The shapes and depths of the grooves 118 illustrated in FIG. 1 are non-limiting embodiments, and other shapes and depths for the grooves 118 are also possible and fully within the scope of the present disclosure. For example, the grooves 118 may extend into the isolation region 78 but not into the substrate 50. As another example, the grooves 118 may be larger than in FIG. Fig. 12B , so that a portion of the gate spacer 98 is also removed by an anisotropic etching process (e.g., a plasma process). As yet another embodiment, in Fig. 12B , the cross-section of the groove 118 is depicted as having a U-shaped bottom, although other shapes for the bottom portion of the groove 118 are also possible, such as a V-shape or a rectangle.

[0143] Next, in FIG. 13A to FIG. 13B In the process, a dielectric layer 119 (hereinafter also referred to as an insulating layer) is formed over the gate spacer 98, the gate spacer 99, the mask 96 (if present) or the dummy gate 94, the first interlayer dielectric 114, the contact etch stop layer 112, and in the trench 118 so as to fill the trench 118. In some embodiments, the dielectric layer 119 is formed as a conformal layer that is deposited on the sidewalls and the bottom surface of the trench 118 until the trench 118 is filled.

[0144] In the illustrated embodiment, the dielectric layer 119 may include silicon nitride, silicon oxide, or the like, and the dielectric layer 119 may be formed using a plasma enhanced atomic layer deposition (PEALD) process, an atomic layer deposition process, a chemical vapor deposition process, or the like. In this manner, during the formation of the trench 118, the removed portions of the mask 96 (if present), the dummy gate 94, the dummy dielectric 92, the nanostructure 56, the semiconductor fin 54, and the dielectric wall 68 are replaced with the dielectric layer 119. The dielectric layer 119 isolates the first portion of each of the plurality of fin structures 62N, 62P in the pair of fin structures 62 and the corresponding dummy gate 94 above from the second portion of each of the plurality of fin structures 62N, 62P in the pair of fin structures 62 and the corresponding dummy gate 94 above.

[0145] After the formation of the dielectric layer 119, a removal process is applied to the dielectric layer 119 to remove excess material of the dielectric layer 119 above the mask 96 (if present) or the dummy gate 94. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like. The planarization process exposes the mask 96 (if present) or the dummy gate 94 so that after the planarization process is completed, the mask 96 (if present) or the dummy gate 94, the gate spacer 98, the gate spacer 99, the contact etch stop layer 112, the remaining portion of the dielectric layer 119 in the trench 118, and the first interlayer dielectric 114 are coplanar (within process variations). After the planarization process, the remaining portion of the dielectric layer 119 in the trench 118 may also be subsequently referred to as a dielectric fin, an insulating fin, or a fin isolation structure.

[0146] exist FIG. 14A to FIG. 15B , mask 96 (if present), dummy gate 94, dummy dielectric 92, and first nanostructure 56A are removed and replaced with gate structure 120. Gate structure 120 includes gate dielectric 122 and gate electrode 124 on gate dielectric 122. Gate structure 120 may also be referred to as a "gate stack."

[0147] exist FIG. 14A to FIG. 14BIn the etching process, the mask 96 (if present) and the dummy gate 94 are removed to form a plurality of recesses 121. Portions of the dummy dielectric 92 in the recesses 121 may also be removed. In some embodiments, the dummy gate 94 is removed via an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 94 at a faster rate than the first interlayer dielectric 114, the dielectric layer 119, the gate spacer 98, and the gate spacer 99. During the removal, the dummy dielectric 92 may be used as an etch stop layer when etching the dummy gate 94. Then, after the removal of the dummy gate 94, the dummy dielectric 92 may be removed. Each recess 121 exposes and / or over a plurality of portions of the second nanostructure 56B that serve as the channel region 88. Portions of the second nanostructure 56B that are to function as the channel region 88 are disposed between adjacent pairs of the epitaxial source / drain regions 106 .

[0148] The remaining portions of the first nanostructure 56A are then removed to expand the recess 121. Removal of the plurality of remaining portions of the first nanostructure 56A may be via an acceptable etching process that selectively etches the material of the first nanostructure 56A at a faster rate than the material of the second nanostructure 56B, the semiconductor fin 54, the isolation region 78, and the dielectric wall 68. The etching may be isotropic. For example, when the semiconductor fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. After removal of the first nanostructure 56A and expansion of the recess 121, each second nanostructure 56B may have a thickness T1 in the range of from 4 nanometers to 15 nanometers. In one embodiment, a height H3 between a bottom surface of a first one of the second nanostructures 56B and a top surface of a second one of the second nanostructures 56B, wherein the second one of the second nanostructures 56B is adjacent to and vertically below the first one of the second nanostructures 56B, is in a range from 5 nanometers to 15 nanometers. In one embodiment, a height H4 between a top surface of a topmost one of the second nanostructures 56B and a top surface of the semiconductor fin 54, wherein the semiconductor fin 54 is vertically below the topmost one of the second nanostructures 56B, is in a range from 40 nanometers to 80 nanometers.

[0149] exist FIG. 15A to FIG. 15B, a gate dielectric 122 and a gate electrode 124 are formed to replace the gate. The gate dielectric 122 is conformally deposited in the recess 121, for example, on the top surface and sidewalls of the semiconductor fin 54 and on the top surface, sidewalls and bottom surface of the second nanostructure 56B. The gate dielectric 122 can also be deposited on the top surface of the isolation region 78 and on the sidewalls and top surface of the dielectric wall 68.

[0150] The gate dielectric 122 includes one or more dielectric layers, such as oxides, metal oxides, metal silicates, the like, or combinations thereof. In some embodiments, the gate dielectric 122 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric 122 includes a high-k dielectric material, and in these embodiments, the gate dielectric 122 may have a dielectric constant value (k value) greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 122 may be multilayered. For example, in some embodiments, the gate dielectrics 122 may each include an interfacial layer of silicon oxide formed by thermal oxidation or chemical oxidation, and a metal oxide layer above the interfacial layer. The formation method of the gate dielectric 122 may include molecular-beam deposition (MBD), atomic layer deposition, plasma enhanced chemical vapor deposition, and the like.

[0151] A plurality of gate electrodes 124 are respectively deposited on the plurality of gate dielectrics 122 and fill the plurality of remaining portions of the plurality of recesses 121. The gate electrode 124 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single-layer gate electrode 124 is depicted, the gate electrode 124 may include any number of liner layers, any number of work function tuning layers, and filling materials. Any combination of the plurality of layers constituting the gate electrode 124 may be deposited in a plurality of regions between each of the plurality of second nanostructures 56B, and in a plurality of regions between the semiconductor fins 54 and the second nanostructures 56B. In addition, different recesses 121 may be filled with different numbers of liner layers, work function tuning layers, and filling materials to allow the formation of gate stacks with different widths. For example, as in Fig.15A and in Fig. 15BAs shown in , a first recess 121 having a width W3 is filled with a gate dielectric 122 and a gate electrode 124, and a second recess 121 having a width W4 is filled with a gate dielectric 122 and a gate electrode 124, wherein the width W4 is greater than the width W3. Compared with the first recess 121, the second recess 121 may be filled with one or more additional liner layers, work function adjustment layers, and filling materials, such as tungsten or the like. The formation method of the gate electrode 124 may include atomic layer deposition, plasma enhanced chemical vapor deposition, and the like.

[0152] After filling of the recesses, a planarization process such as chemical mechanical polishing may be performed to remove excess portions of gate dielectric 122 and gate electrode 124 material above the top surfaces of first interlayer dielectric 114, gate spacers 98, gate spacers 99, contact etch stop layer 112, and dielectric layer 119. The remaining portions of gate dielectric 122 and gate electrode 124 material thus form a replacement gate structure 120 of the resulting nanostructured field effect transistor.

[0153] The formation of the gate dielectrics 122 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the plurality of gate dielectrics 122 in each region are formed of the same material, and the formation of the plurality of gate electrodes 124 may occur simultaneously, such that the plurality of gate electrodes 124 in each region are formed of the same material. For example, in the illustrated embodiment, the gate electrodes 124 comprising the same material are formed in the n-type region 50N and the p-type region 50P. In some embodiments, the plurality of gate dielectrics 122 in each region may be formed via different processes, such that the gate dielectrics 122 may be different materials, and / or the plurality of gate electrodes 124 in each region may be formed via different processes, such that the gate electrodes 124 may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0154] Further references Fig.15A and Fig. 15B , multiple gate electrodes 124 around the channel region 88 of the same fork-shaped sheet structure 80 can be physically and electrically coupled. Such coupling may be advantageous in some complementary metal oxide semiconductor (CMOS) processes. For example, when the nanostructure field effect transistor is used to form an inverter, a gate, a memory, and the like, directly connecting the gate electrode 124 may allow the number of gate contacts to be reduced.

[0155] exist FIG. 16A to FIG. 16CIn one embodiment, the first interlayer dielectric 114 and the contact etch stop layer 112 are removed to form a plurality of openings 134, which expose the top and side surfaces of the epitaxial source / drain regions 106. In one embodiment, the openings 134 may also expose portions of the plurality of sidewalls of the semiconductor fins 54. The openings 134 may be formed using acceptable photolithography and etching techniques. Multiple etching steps may be used to form the openings 134. In one embodiment, an etching process (e.g., a dry etching process) may be performed using HF gas, NH3 gas, CH3F, C4F6, or the like as an etchant to selectively remove the first interlayer dielectric 114 and the contact etch stop layer 112. The etching process may be selective to the first interlayer dielectric 114 and the contact etch stop layer 112 (e.g., etching the material of the first interlayer dielectric 114 and the contact etch stop layer 112 at a faster rate than the material of the gate spacers 98, the gate spacers 99, the isolation regions 78, the gate dielectric 122, the gate electrode 124, and the epitaxial source / drain regions 106). Removing the first interlayer dielectric 114 and the contact etch stop layer 112 in the manner described above allows for exposure of a greater surface area of ​​the epitaxial source / drain regions 106 (e.g., the exposed surface area increases in the range of from 20 percent to 30 percent).

[0156] A number of advantages can be achieved by performing the planarization process described above to remove excess portions of the material of the gate dielectric 122 and the gate electrode 124 (excess portions of these materials are above the top surfaces of the first interlayer dielectric 114, the gate spacers 98, the gate spacers 99, the contact etch stop layer 112, and the dielectric layer 119) and forming the replacement gate structure 120. An etching process is then performed after the planarization process, wherein the etching process is performed using HF gas, NH3 gas, CH3F, C4F6, or the like as an etchant to remove the planarized first interlayer dielectric 114 and the contact etch stop layer 112 so as to form the opening 134 and expose the top and side surfaces of the epitaxial source / drain region 106. These advantages include allowing a larger surface area of ​​the epitaxial source / drain region 106 to be exposed through the opening 134, allowing the subsequently formed metal-semiconductor alloy region 125 and the coating 126 (such as FIG. 17A to FIG. 17C ) can be formed over a larger surface area of ​​the epitaxial source / drain region 106 (e.g., an increase in surface area ranging from 20% to 30%). These advantages include providing a greater surface area between subsequently formed source / drain contacts 142 (e.g., FIG. 24A to FIG. 24C) and the epitaxial source / drain regions 106. As a result, there is a more efficient flow of current through the source / drain contacts 142, minimizing power dissipation at the source / drain contacts 142 and improving output resistance (RO), allowing power to be delivered to the load without significant voltage or current losses. This therefore leads to improved device performance.

[0157] exist FIG. 17A to FIG. 17C In the embodiment of the present invention, a plurality of metal-semiconductor alloy regions 125 are formed in the plurality of openings 134 on the portions of the plurality of epitaxial source / drain regions 106 exposed by the openings 134. The metal-semiconductor alloy regions 125 may be silicide regions formed of a metal silicide (e.g., titanium silicide (TiSi), or the like). The metal-semiconductor alloy regions 125 may be formed on the exposed planar top and side surfaces of the epitaxial source / drain regions 106, such that the plurality of metal-semiconductor alloy regions 125 are disposed on the entire sidewalls of each of the plurality of epitaxial source / drain regions 106, wherein the sidewalls extend from the bottommost surface of the epitaxial source / drain regions 106 to the highest point of the epitaxial source / drain regions 106. The metal-semiconductor alloy region 125 is also disposed on the sidewalls of each of the plurality of epitaxial source / drain regions 106, the sidewalls extending from the highest point of the epitaxial source / drain region 106 to the highest point of the interface between the epitaxial source / drain region 106 and the dielectric wall 68. In one embodiment, the metal-semiconductor alloy region 125 may have a thickness T2 in a range from 2 nanometers to 4 nanometers.

[0158] To form the metal-semiconductor alloy region 125, a deposition process is performed, which is previously performed at FIG. 16A to FIG. 16CA thin layer of titanium is deposited over the structure shown in . The deposition process may be performed using a physical vapor deposition process, a chemical vapor deposition process, or the like. During the deposition process, titanium tetrachloride (TiCl4), or the like, may be used as a precursor gas for depositing the titanium layer. The titanium layer is deposited on portions of the epitaxial source / drain regions 106 exposed by the openings 134, and on the dielectric walls 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation regions 78, and on multiple top surfaces of the gate spacers 98, and on the top surface and sidewalls of the gate spacers 99. During the deposition process, a first plasma treatment is simultaneously performed to provide a more energetic and controlled environment for the reaction between the titanium atoms in the titanium layer and the silicon from the epitaxial source / drain regions 106. The first plasma treatment promotes the silicidation process and the formation of the metal-semiconductor alloy region 125. In one embodiment, the metal-semiconductor alloy region 125 comprises titanium silicide (TiSi), or the like. The first plasma treatment may include exposing the titanium layer to a nitrogen (N2) or ammonia (NH3) plasma.

[0159] After the deposition process and the first plasma treatment are performed, and after the metal-semiconductor alloy region 125 is formed on the portion of the epitaxial source / drain region 106, a second plasma treatment may be performed, including exposing the metal-semiconductor alloy region 125 to a nitrogen (N2) or ammonia (NH3) plasma. In one embodiment, the first plasma treatment and the second plasma treatment may be the same. During the second plasma treatment, the metal-semiconductor alloy region 125 may react with the nitrogen species in the nitrogen (N2) or ammonia (NH3) plasma to form a coating 126 over the metal-semiconductor alloy region 125. The coating 126 may include titanium silicon nitride (TiSiN), or the like. In one embodiment, the coating 126 may have a thickness T3 in the range from 1 nanometer to 4 nanometers.

[0160] A number of advantages can be achieved by forming a metal-semiconductor alloy region 125 (comprising TiSi) and a coating 126 (comprising TiSiN) on the portion of the epitaxial source / drain region 106 exposed by the opening 134, wherein the metal-semiconductor alloy region 125 has a thickness T2 in the range of from 2 nm to 4 nm and the coating 126 has a thickness T3 in the range of from 1 nm to 4 nm. These include reducing the potential for interference between subsequently formed source / drain contacts 142 (such as at FIG. 24A to FIG. 24C) and the epitaxial source / drain region 106. As a result, there is a more efficient flow of current through the source / drain contact 142, minimizing power dissipation at the source / drain contact 142, and improving the output resistance (RO), allowing the nanostructured field effect transistor to drive or deliver power to a load without significant voltage or current losses. For example, forming the metal-semiconductor alloy region 125 with a thickness of less than 2 nanometers will result in a contact resistance between the subsequently formed source / drain contacts 142 (as shown in FIG. 24A to FIG. 24C ) and the epitaxial source / drain region 106, resulting in a low efficiency of current flowing through the source / drain contact 142 and insufficient improvement in device performance. In contrast, forming the metal-semiconductor alloy region 125 with a thickness greater than 4 nanometers will not result in a subsequent formation of a source / drain contact 142 (as shown in FIG. FIG. 24A to FIG. 24C The contact resistance between the epitaxial source / drain regions 106 is further significantly reduced, resulting in increased manufacturing costs without improving device performance.

[0161] Further, forming the metal-semiconductor alloy region 125 and coating 126 over a larger exposed surface area of ​​the epitaxial source / drain region 106 (e.g., an increase in exposed surface area in the range of 20 percent to 30 percent) has additional advantages. These include an increase in the effective area of ​​the metal-semiconductor alloy region 125 and coating 126 over the epitaxial source / drain region 106 (e.g., an increase in area in the range of 20 percent to 30 percent), which allows for a greater degree of separation between subsequently formed source / drain contacts 142 (e.g., FIG. 24A to FIG. 24C ) and the epitaxial source / drain regions 106. As a result, there is an even more efficient flow of current through the source / drain contacts 142, further minimizing power dissipation at the source / drain contacts 142, and further improving the output resistance (RO), allowing the nanostructure field effect transistor to be driven or deliver power to a load with even lower voltage or current losses.

[0162] Further advantages may be achieved by forming a coating 126 over the metal-semiconductor alloy region 125. These include the coating 126 preventing oxidation of the surface of the underlying metal-semiconductor alloy region 125, which could result in degradation of electrical performance and increase the potential for interference between subsequently formed source / drain contacts 142 (e.g., FIG. 24A to FIG. 24C) and the epitaxial source / drain regions 106. As a result, device performance is enhanced and device yield is improved. For example, forming the coating 126 with a thickness of less than 1 nanometer will result in insufficient protection against oxidation of the underlying metal-semiconductor alloy region 125, and this will result in electrical performance degradation and inter-connection between the subsequently formed source / drain contacts 142 (as shown in FIG. 24A to FIG. 24C The contact resistance between the epitaxial source / drain regions 106 and the epitaxial source / drain regions 106 increases. Relatively speaking, forming the coating 126 with a thickness greater than 4 nanometers will not result in any further improvement in preventing oxidation of the underlying metal-semiconductor alloy region 125, resulting in increased manufacturing costs.

[0163] In one embodiment, the combined thickness T4 of the metal-semiconductor alloy region 125 and the coating 126 may be in a range from 3 nm to 8 nm. The thicknesses T2, T3, and T4 may be varied by adjusting a number of specific process parameters of the deposition process, the first plasma treatment, and the second plasma treatment, such as power, gas composition, pressure, and treatment time.

[0164] As a result of the deposition process described above, a titanium layer is also deposited on the dielectric walls 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation regions 78, multiple top surfaces of the gate spacers 98, and the top surfaces and sidewalls of the gate spacers 99. As a result of the first plasma treatment and the second plasma treatment, the titanium layer on the dielectric walls 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation regions 78, multiple top surfaces of the gate spacers 98, and the top surfaces and sidewalls of the gate spacers 99 reacts with nitrogen species in the nitrogen (N2) or ammonia (NH3) plasma to form a residual layer 127. This residual layer 127 is unintentionally formed on the dielectric walls 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation regions 78, multiple top surfaces of the gate spacers 98, and the top surfaces and sidewalls of the gate spacers 99. For example, this remaining layer 127 is also formed along the sidewalls in the opening 134. The material composition of the remaining layer 127 may vary based on the specific structure on which the remaining layer 127 is formed, because the material composition of the remaining layer 127 is affected by the underlying materials that interact with it during the first plasma treatment and the second plasma treatment. The remaining layer 127 may include titanium silicon nitride (TiSiN), titanium nitride (TiN), combinations thereof, or the like. For example, in one embodiment, a first portion of the remaining layer 127 on the top surface of the gate electrode 124 may include TiN. In one embodiment, a second portion of the remaining layer 127 on the dielectric wall 68, the gate dielectric 122, the dielectric layer 119, the isolation region 78, multiple top surfaces of the gate spacer 98, and on the top surface and sidewalls of the gate spacer 99 (e.g., the sidewalls in the opening 134) may include TiSiN.

[0165] exist 18A to 18CIn the embodiment of the present invention, a wet cleaning process 128 is performed to selectively remove (e.g., via etching) the remaining layer 127 from the dielectric wall 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation region 78, multiple top surfaces of the gate spacer 98, and the top surface and sidewalls (e.g., the sidewalls within the opening 134) of the gate spacer 99, while leaving the metal-semiconductor alloy region 125 and the coating 126 on the epitaxial source / drain region 106. During the wet cleaning process 128, the metal-semiconductor alloy region 125 and the coating 126 disposed above the epitaxial source / drain region 106 are not removed (e.g., have a much lower etching rate than the remaining layer 127). For example, the ratio of the etching rate of the remaining layer 127 relative to the etching rate of the metal-semiconductor alloy region 125 and the coating 126 is in the range of from 4 to 8.7. In this manner, TiN and TiSiN of the remaining layer 127 are preferentially removed using the wet cleaning process 128, and as a result of the wet cleaning process 128, the metal-semiconductor alloy region 125 (e.g., comprising TiSi) and the coating 126 (e.g., comprising TiSiN) disposed above the epitaxial source / drain regions 106 remain substantially intact on the epitaxial source / drain regions 106.

[0166] The wet cleaning process 128 may be a wet etching process, which includes removing the previously FIG. 17A to FIG. 17C The structure shown in (e.g., including the remaining layer 127) is exposed to sulfuric acid (H2SO4) at a temperature in the range of 130°C to 230°C. In one embodiment, the sulfuric acid may have a concentration in the range of from 85 weight percent to 90 weight percent. In other embodiments, the wet etching process includes removing the previously FIG. 17A to FIG. 17C The structure shown in FIG. 1 (eg, including the remaining layer 127 ) is exposed to sulfuric acid (H 2 SO 4 ) at a temperature greater than 130° C., wherein the sulfuric acid has a concentration greater than 90 weight percent. The wet cleaning process 128 may be performed for a duration ranging from 5 seconds to 60 seconds.

[0167] In an alternative embodiment, the wet cleaning process 128 may include a wet etching process, including removing the previously FIG. 17A to FIG. 17C The structure shown in (e.g., including the residual layer 127) is exposed to a sulfonic acid (e.g., methanesulfonic acid (CH3SO3H), N-sulfonic acid (N-SO3H), benzenesulfonic acid (C6H5SO3H), chlorosulfonic acid (HSO3Cl), or the like) or a derivative thereof (e.g., benzenesulfonyl chloride (C6H5SO2Cl), sulfonamide, or the like).

[0168] Advantages may be achieved by selectively removing the remaining layer 127 from the dielectric wall 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation region 78, the top surfaces of the gate spacers 98, and the top surfaces and the top surfaces of the sidewalls (e.g., the sidewalls within the opening 134) of the gate spacers 99 by performing the wet cleaning process 128, while leaving the metal-semiconductor alloy region 125 and the coating 126 on the epitaxial source / drain region 106. The wet cleaning process 128 is performed using sulfuric acid (H2SO4) as an etchant, and the wet cleaning process 128 is performed when the sulfuric acid (H2SO4) is at a temperature ranging from 130° C. to 230° C. The sulfuric acid (H2SO4) may have a concentration ranging from 85 weight percent to 90 weight percent. These advantages include a wet cleaning process 128 that allows selective etching of titanium silicon nitride (TiSiN) and titanium nitride (TiN) remaining layers 127 (e.g., on the sidewalls in opening 134) formed during the formation of the metal-semiconductor alloy regions 125 and coating 126 on the epitaxial source / drain regions 106 while minimizing etching damage to the metal-semiconductor alloy regions 125 (including TiSi) and coating 126 (including TiSiN). As a result, the source / drain contacts 142 (such as at FIG. 24A to FIG. 24C ) and subsequently formed source / drain contact openings 141 (as shown in FIG. 23A to FIG. 23C ) can be formed to have a larger width to ensure lower contact resistance, better electrical contact, and a larger contact surface area between the epitaxial source / drain regions 106 and the source / drain contacts 142. This is because there is no residual layer 127 on the sidewalls of the opening 134, which would hinder the subsequent formation of the source / drain contact openings 141 and the source / drain contacts 142, and would hinder the electrical contact between the epitaxial source / drain regions 106 and the source / drain contacts 142. This therefore leads to enhanced device performance and improved device yield. Further, the removal of the residual layer 127 on the top surface of the gate dielectric 122 and the gate electrode 124 ensures better electrical contact between the gate electrode 124 and the subsequently formed gate contact 140 (as shown in FIG. 24A to FIG. 24C ).

[0169] exist FIG. 19A to FIG. 19C In the process, a dielectric layer 130 is deposited on the previously 18A to 18C, such as over dielectric wall 68, gate dielectric 122, gate electrode 124, dielectric layer 119, isolation region 78, gate spacer 98, and gate spacer 99. Dielectric layer 130 is also deposited over multiple metal-semiconductor alloy regions 125 and multiple coatings 126 in multiple openings 134, and on sidewalls within multiple openings 134 so as to fill multiple openings 134. Dielectric layer 130 may include silicon oxide, silicon nitride, or the like. Depositing dielectric layer 130 may use any suitable method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition, or the like.

[0170] After the deposition of dielectric layer 130, a planarization process is performed to make the top surface of dielectric layer 130 flush with the top surfaces of gate dielectric 122, gate electrode 124, dielectric layer 119, gate spacer 98, and gate spacer 99. The planarization process may be a chemical mechanical polishing process, or the like.

[0171] In some embodiments, a contact etch stop layer (CESL) 129 is disposed between the dielectric layer 130 and the coating 126. In addition, the contact etch stop layer 129 can be disposed between the dielectric layer 130 and the sidewalls of the gate spacer 99. The contact etch stop layer 129 can include a dielectric material, such as silicon oxynitride, or the like, which has a high etch selectivity to the etching of the dielectric layer 130.

[0172] FIG. 20A to FIG. 21D A process is depicted for dividing a gate structure 120 (including a gate dielectric 122 and a gate electrode 124) into a plurality of gate structures 120 (or a plurality of gate structure segments). Thus, the plurality of gate structures 120 of adjacent plurality of nanostructure field effect transistors can be separately controlled. Dividing the gate structure 120 includes forming a gate isolation structure extending through the gate structure 120 such that the gate isolation structure cuts the gate structure 120 into at least two gate structures 120. The gate isolation structure is formed by patterning a trench in the gate structure 120 and forming a dielectric material in the trench. In this manner, the gate isolation structure can be disposed between a first gate structure 120 and a second gate structure 120 on both sides of the gate isolation structure.

[0173] exist FIG. 20A to FIG. 20BIn the embodiment, trench 143 is formed through gate structure 120 (including gate dielectric 122 and gate electrode 124). Trench 143 may also be formed through gate spacer 98, gate spacer 99, contact etch stop layer 129, and dielectric layer 130 adjacent to gate structure 120. Trench 143 may extend completely through gate structure 120 and partially into isolation region 78. In one embodiment, trench 143 may extend completely through isolation region 78 and expose the top surface of substrate 50. Although in Fig. 20A and Fig. 20B In the figure, the trench 143 is shown to be formed in the p-type region 50P, but the trench 143 may be formed in either the n-type region 50N or the p-type region 50P. FIG. 19A to FIG. 19C A first hard mask layer and a second hard mask layer may be sequentially formed over the structure shown in , using processes such as chemical vapor deposition, atomic layer deposition, or the like. In some embodiments, the first hard mask layer is a metal hard mask layer (e.g., comprising titanium nitride, or the like), and the second hard mask layer is a dielectric hard mask layer (e.g., comprising silicon nitride, or the like). In subsequent processing, various photolithography and etching techniques are used to transfer the pattern to the first hard mask layer and the second hard mask layer. Then, an etching process is performed using the first hard mask layer as an etching mask to etch the underlying structure (e.g., gate structure 120, gate spacer 98, gate spacer 99, contact etch stop layer 129, and dielectric layer 130) to form trench 143. The etching process used to form trench 143 may be anisotropic. For example, the etching process may be dry etching, such as reactive ion etching, neutral beam etching, or the like. The trench 143 is formed to divide the gate structure 120 into at least two gate structures 120. For example, the trench 143 may divide the gate structure 120 into a gate structure 120A and a gate structure 120B (which are subsequently Fig.21D 1 ). In a top view, trench 143 may also be wider than gate structure 120, so that trench 143 is formed in gate spacer 98, gate spacer 99, contact etch stop layer 129, and dielectric layer 130. Trench 143 is formed to a size large enough to electrically isolate first gate structure 120 from second gate structure 120.

[0174] exist Fig. 20A The shape and depth of the groove 143 shown in the figure are non-limiting embodiments, and other shapes and depths of the groove 143 are also feasible and fully included in the scope of the present disclosure.

[0175] Next, in FIG. 21A to FIG. 21D In the embodiment, the dielectric layer 144 is formed on the previously Fig. 20A and Fig. 20B, for example, over gate dielectric 122 , gate electrode 124 , dielectric layer 119 , contact etch stop layer 129 , dielectric layer 130 , gate spacer 98 , gate spacer 99 , and in trench 143 , so as to fill trench 143 . Fig.21D Draw along the Fig. 21B A top view of section XX shown in FIG. 14A . In some embodiments, dielectric layer 144 is formed as a conformal layer that is deposited on the sidewalls and bottom surface of trench 143 until trench 143 is filled.

[0176] In the illustrated embodiment, the dielectric layer 144 may include silicon nitride, silicon oxide, or the like, and may be formed using a plasma enhanced atomic layer deposition (PEALD) process, an atomic layer deposition process, a chemical vapor deposition process, or the like.

[0177] After the formation of the dielectric layer 144, a removal process is applied to the dielectric layer 144 to remove excess material of the dielectric layer 144. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like. After the planarization process, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacers 98, the top surfaces of the gate spacers 99, and the top surface of the remaining portion of the dielectric layer 144 in the trench 143 are coplanar (within process variations). After the planarization process, the remaining portion of the dielectric layer 144 in the trench 143 may also be subsequently referred to as a gate isolation structure. Fig.21D The dielectric layer 144 is depicted dividing the gate structure 120 into two gate structures 120. For example, the dielectric layer 144 can divide the gate structure 120 into a gate structure 120A and a gate structure 120B on both sides of the dielectric layer 144.

[0178] In an alternative embodiment, the above FIG. 20A to FIG. 21D The process for forming the dielectric layer 144 (eg, gate isolation structure) described in FIG. 12A to FIG. 13B For example, in embodiments where dielectric layer 144 is formed simultaneously with dielectric layer 119, or where opening 134 is formed (previously in FIG. 16A to FIG. 16C ) and the metal-semiconductor alloy region 125 and the coating 126 (previously described in FIG. 17A to FIG. 17CIn the embodiment where the dielectric layer 144 is formed prior to the wet cleaning process 128 (described in the prior art), the formation of the metal-semiconductor alloy region 125 and the coating 126 results in the formation of a residual layer 127 (comprising TiSiN) on the top surface of the dielectric layer 144. 18A to 18C During the epitaxial deposition (described in ), the remaining layer 127 (comprising TiSiN) on the top surface of the dielectric layer 144, and on multiple top surfaces of the dielectric wall 68, the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation region 78, the gate spacer 98, and on the top surface and sidewalls of the gate spacer 99 (e.g., the sidewalls within the opening 134) is selectively removed, while leaving the metal-semiconductor alloy region 125 and the coating 126 on the epitaxial source / drain region 106.

[0179] exist FIG. 22A to FIG. 22C In the embodiment of the present invention, the second interlayer dielectric 138 is deposited over the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacer 98, the gate spacer 99, and the dielectric layer 144. In some embodiments, the second interlayer dielectric 138 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric 138 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like. The second interlayer dielectric 138 can be formed by any suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flowable chemical vapor deposition, or the like.

[0180] In some embodiments, an etch stop layer (ESL) 136 is formed between the second interlayer dielectric 138 and the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacer 98, the gate spacer 99, and the dielectric layer 144. The etch stop layer 136 may be formed of a dielectric material having a high etch selectivity to the etching of the second interlayer dielectric 138, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and the etch stop layer 136 may be formed by any suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or the like.

[0181] exist FIG. 23A to FIG. 23C, a source / drain contact opening 141 is formed in the second interlayer dielectric 138, the etch stop layer 136, the dielectric layer 130, and the contact etch stop layer 129. The source / drain contact opening 141 exposes the coating layer 126 on the underlying metal-semiconductor alloy region 125, wherein the coating layer 126 and the underlying metal-semiconductor alloy region 125 are disposed on the top surface and side surfaces having a crystal plane of the epitaxial source / drain region 106. For example, the source / drain contact opening 141 exposes the coating layer 126, wherein the coating layer 126 and the underlying metal-semiconductor alloy region 125 are disposed on the entirety of the sidewalls of each of the plurality of epitaxial source / drain regions 106, wherein the sidewalls extend from the bottommost surface of the epitaxial source / drain region 106 to the highest point of the epitaxial source / drain region 106. In addition, the exposed coating 126 and the underlying metal-semiconductor alloy region 125 are also disposed on the sidewalls of each of the plurality of epitaxial source / drain regions 106 , which sidewalls extend from the highest point of the epitaxial source / drain region 106 to the highest point of the interface between the epitaxial source / drain region 106 and the dielectric wall 68 .

[0182] Acceptable photolithography and etching techniques may be used to form the source / drain contact openings 141. Multiple etching steps may be used to form the source / drain contact openings 141. As described above, the contact etch stop layer 129 is formed of a material having a high etching selectivity relative to the etching of the dielectric layer 130. One of the multiple etching steps used to form the source / drain contact openings 141 is an etching process that is selective to the dielectric layer 130 (e.g., the material of the dielectric layer 130 is etched at a faster rate than the material of the contact etch stop layer 129). Therefore, the aspect ratio of the lower portion of the source / drain contact openings 141 may be increased, helping to ensure that a sufficient area of ​​the coating 126 disposed on the top and side surfaces of the epitaxial source / drain region 106 having a crystal plane is exposed through the source / drain contact openings 141.

[0183] In the illustrated embodiment, a patterning method may be used such that some of the dielectric layer 130 remains in the Fig. 23B In another embodiment, the source / drain contact openings 141 are formed in a self-aligned patterning method so that Fig. 23B All dielectric layers 130 in the cross section are removed. Fig. 23B and Fig.23C In the embodiment shown in , the source / drain contact openings 141 do not extend into the coating 126. In another embodiment, the etching of the coating 126 can be performed so that the source / drain contact openings 141 partially extend into the coating 126.

[0184] A number of advantages are achieved by forming source / drain contact openings 141 so that coating 126 is exposed, and then forming source / drain contacts 142 in source / drain contact openings 141 (e.g., FIG. 24A to FIG. 24C ). The metal-semiconductor alloy region 125 and coating 126 are disposed over a larger surface area of ​​the epitaxial source / drain region 106 (e.g., an increase in effective surface area in the range of from 20 percent to 30 percent) and then in contact with subsequently formed source / drain contacts 142. These advantages include allowing for a substantially uniform surface area between subsequently formed source / drain contacts 142 (e.g., in FIG. 24A to FIG. 24C ) and the epitaxial source / drain regions 106. As a result, there is a more efficient flow of current through the source / drain contacts 142, minimizing power dissipation at the source / drain contacts 142 and improving output resistance (RO), allowing the nanostructured field effect transistor to drive or deliver power to a load without significant voltage or current losses.

[0185] Further references FIG. 23A to FIG. 23C A gate contact opening 139 is also formed which extends through the second interlayer dielectric 138 and the etch stop layer 136. The gate contact opening 139 may be formed using acceptable photolithography and etching techniques, and may expose the top surface of the gate electrode 124.

[0186] exist FIG. 24A to FIG. 24C, source / drain contacts 142 are formed in source / drain contact openings 141, and gate contact 140 is formed in gate contact openings 139. A liner (e.g., a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in source / drain contact openings 141 and gate contact openings 139. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The deposition liner may be via a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, ruthenium, cobalt, copper, molybdenum, nickel, a combination thereof, or the like. The deposition conductive material may be via atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. A planarization process such as chemical mechanical polishing may be performed to remove excess material from the top surface of the second interlayer dielectric 138. The remaining liner and conductive material in the source / drain contact opening 141 and the gate contact opening 139 form the source / drain contact 142 and the gate contact 140, respectively. After the formation is completed, the top surfaces of the second interlayer dielectric 138, the source / drain contact 142, and the gate contact 140 are coplanar (within process variations). In other embodiments, the gate contact opening 139 and the gate contact 140 may be formed before, simultaneously with, or after the source / drain contact opening 141 and the source / drain contact 142.

[0187] FIG. 25A to FIG. 28D are various views of various intermediate stages in the fabrication of a nanostructured field effect transistor according to alternative embodiments. The fabrication of a nanostructured field effect transistor is described in the context of nanosheet field effect transistors (NSFETs). Unless otherwise noted, the same reference numerals in this embodiment (and in the embodiments discussed subsequently) represent the same elements in the fabrication of a nanostructured field effect transistor. Figures 1 to 24C Similar components are formed by similar processes in the multiple embodiments shown in FIG. Accordingly, the process steps and applicable materials are not repeated here.

[0188] Fig.25A , Fig.26A , Fig.27A and Fig.28A It is along Figure 1 A cross-sectional view shown at reference section AA in FIG. Fig.25B , Fig.26B , Fig.27B and Fig.28B It is along Figure 1 A cross-sectional view shown at reference section BB in FIG. Fig.25C , Fig.25D , Fig.26C , Fig.26D , Fig.27C , Fig.27D , Fig.28C and Fig.28D It is along Figure 1 A cross-sectional view shown by reference section CC in FIG.

[0189] FIG. 25A to FIG. 25D An embodiment is shown in which a plurality of initial steps are performed in Figures 1 to 15B The initial steps shown in are basically the same, but the steps in Figure 4 and Figure 5 , the process steps for forming the dielectric wall 68 are shown in . In this way, the dielectric wall 68 for separating the adjacent fin structures 62N, 62P in a pair of fin structures 62 is not formed, and the trench is set between the adjacent multiple fin structures 62. Instead of using the dielectric wall 68, the isolation region 78 and the gate structure 120 (for example, including the gate dielectric 122 and the gate electrode 124) are subsequently formed in this trench between the adjacent multiple fin structures 62. The gate dielectric 122 is conformally deposited on the top surface and sidewalls of the semiconductor fin 54 and on the top surface, sidewalls and bottom surface of the second nanostructure 56B. The gate electrode 124 is also deposited over the gate dielectric 122 so that the gate structure 120 surrounds each second nanostructure 56B.

[0190] In one embodiment, each of the plurality of second nanostructures 56B may have a width W6 ranging from 10 nm to 50 nm. In one embodiment, the channel region 88 disposed between adjacent plurality of epitaxial source / drain regions 106 may have a width W7 ranging from 10 nm to 80 nm.

[0191] Further references FIG. 25A to FIG. 25D , using the previous FIG. 16A to FIG. 16C , the first interlayer dielectric 114 and the contact etch stop layer 112 are removed to form openings 134 that expose top and side surfaces of the epitaxial source / drain regions 106 having crystal planes. The etching process used may be selective to the first interlayer dielectric 114 and the contact etch stop layer 112 (e.g., etching the material of the first interlayer dielectric 114 and the contact etch stop layer 112 at a faster rate than the material of the gate spacers 98, the gate spacers 99, the isolation regions 78, the gate dielectric 122, the gate electrode 124, and the epitaxial source / drain regions 106). Each of the plurality of epitaxial source / drain regions 106 may have a bottom portion disposed between the plurality of fin spacers 97. The fin spacers 97 may be formed simultaneously with the formation of the gate spacers 98, using the same etching process as previously described in. FIG. 8A to FIG. 8BAn insulating material is deposited and then etched to form gate spacers 98 and fin spacers 97 using similar processes and materials as described in .

[0192] Due to the epitaxial process used to form the epitaxial source / drain regions 106 (previously 9A to 9C As a result of the epitaxial source / drain region 106, the upper surface of the epitaxial source / drain region 106 has a plurality of crystal planes that extend laterally outward beyond the sidewalls of the semiconductor fin 54 and the second nanostructure 56B. In some embodiments, these crystal planes result in the merging of adjacent multiple epitaxial source / drain regions 106 above the adjacent multiple semiconductor fins 54, as shown by Fig.25C In other embodiments, as shown by Fig.25D As shown, after the epitaxial process is completed, adjacent multiple epitaxial source / drain regions 106 remain separated. In the illustrated embodiment, fin spacers 97 are formed on the top surface of the isolation region 78 to block epitaxial growth. In some other embodiments, fin spacers 97 may not be formed. In one embodiment, the height H5 between the top surface of the topmost one of the second nanostructures 56B and the top surface of the semiconductor fin 54 is in the range of from 40 nanometers to 80 nanometers, wherein the semiconductor fin 54 is vertically below the topmost one of the second nanostructures 56B.

[0193] After removal of the first interlayer dielectric 114 and the contact etch stop layer 112 to form the openings 134, the exposed portion of each of the plurality of epitaxial source / drain regions 106 includes a top surface and sidewalls of the epitaxial source / drain regions 106, wherein each of the plurality of sidewalls extends from the top surface of the epitaxial source / drain regions 106 to a bottom point of the sidewall that is just above the top surface of the corresponding fin spacer 97. Removing the first interlayer dielectric 114 and the contact etch stop layer 112 in the manner described above allows a larger surface area of ​​the epitaxial source / drain regions 106 to be exposed (e.g., an increase in exposed surface area in the range of 20 percent to 30 percent).

[0194] Several advantages can be achieved by using the same FIG. 15A to FIG. 15BThe replacement gate structure 120 is formed by similar processes and similar materials as described in . These processes include performing a planarization process to remove multiple excess portions of the material of the gate dielectric 122 and the gate electrode 124, which are above multiple top surfaces of the first interlayer dielectric 114, the gate spacer 98, the gate spacer 99, the contact etch stop layer 112, and the dielectric layer 119, and then performing an etching process, using HF gas, NH3 gas, CH3F, C4, F6, or the like as an etchant, to remove the first interlayer dielectric 114 and the contact etch stop layer 112 so as to form an opening 134 and expose the top and side surfaces of the epitaxial source / drain region 106 having a crystal plane. These advantages include allowing a larger surface area of ​​the epitaxial source / drain region 106 to be exposed through the opening 134, so that the subsequently formed metal-semiconductor alloy region 125 and the coating 126 (as in FIG. 26A to FIG. 26D ) can be formed over a larger surface area of ​​the epitaxial source / drain regions 106 (e.g., an increase in surface area ranging from 20 percent to 30 percent). These advantages include the possibility of having a substantially lower surface area between subsequently formed source / drain contacts 142 (e.g., FIG. 28A to FIG. 28D ) and the epitaxial source / drain regions 106. As a result, there is a more efficient flow of current through the source / drain contacts 142, minimizing power dissipation at the source / drain contacts 142 and improving the output resistance (RO), allowing power to be delivered to the load without significant voltage or current losses. This therefore leads to improved device performance.

[0195] exist FIG. 26A to FIG. 26D In the embodiment of the present invention, a plurality of metal-semiconductor alloy regions 125 are formed in the openings 134 and are located on the portions of the plurality of epitaxial source / drain regions 106 exposed by the plurality of openings 134. The metal-semiconductor alloy regions 125 are formed using the same method as previously described. FIG. 17A to FIG. 17C The metal-semiconductor alloy region 125 may be formed on the exposed planar top and side surfaces of the epitaxial source / drain regions 106, such that the metal-semiconductor alloy region 125 is disposed on the top surface and sidewalls of each of the plurality of epitaxial source / drain regions 106, wherein each of the plurality of sidewalls extends from the top surface of the epitaxial source / drain regions 106 to a bottom point of the sidewall that is just above the top surface of the corresponding fin spacer 97. In one embodiment, the metal-semiconductor alloy region 125 may have a thickness T2 in a range from 2 nanometers to 4 nanometers.

[0196] After the formation of the metal-semiconductor alloy region 125, the FIG. 17A to FIG. 17CA coating 126 is formed over the metal-semiconductor alloy region in the opening 134 using a similar process and similar materials as described in . In one embodiment, the coating 126 may have a thickness T3 in a range from 1 nm to 4 nm.

[0197] A number of advantages can be achieved by forming a metal-semiconductor alloy region 125 (comprising TiSi) and a coating 126 (comprising TiSiN) on the portion of the epitaxial source / drain region 106 exposed by the opening 134, wherein the metal-semiconductor alloy region 125 has a thickness T2 in the range of from 2 nm to 4 nm and the coating 126 has a thickness T3 in the range of from 1 nm to 4 nm. These include the formation of a subsequently formed source / drain contact 142 (e.g., FIG. 28A to FIG. 28D ) and the epitaxial source / drain region 106. As a result, there is a more efficient flow of current through the source / drain contact 142, minimizing power dissipation at the source / drain contact 142, and improving the output resistance (RO), allowing the nanostructured field effect transistor to drive or deliver power to a load without significant voltage or current losses. For example, forming the metal-semiconductor alloy region 125 with a thickness of less than 2 nanometers will result in a reduction in the contact resistance between the subsequently formed source / drain contacts 142 (as shown in FIG. 28A to FIG. 28D ) and the epitaxial source / drain regions 106, resulting in a low efficiency of current flowing through the source / drain contacts 142 and insufficient improvement in device performance. In contrast, forming the metal-semiconductor alloy region 125 with a thickness greater than 4 nanometers will not result in a poor resistance reduction between the subsequently formed source / drain contacts 142 (as shown in FIG. 28A to FIG. 28D Any further significant reduction in the contact resistance between the epitaxial source / drain regions 106 results in an increase in manufacturing cost without improvement in device performance.

[0198] Further, forming the metal-semiconductor alloy region 125 and coating 126 over a larger exposed surface area of ​​the epitaxial source / drain region 106 (e.g., an increase in exposed surface area in the range of 20 percent to 30 percent) has additional advantages. These include an increase in the effective area of ​​the metal-semiconductor alloy region 125 and coating 126 over the epitaxial source / drain region 106 (e.g., an increase in area in the range of 20 percent to 30 percent), which allows for a greater degree of separation between subsequently formed source / drain contacts 142 (e.g., FIG. 28A to FIG. 28D) and the epitaxial source / drain regions 106. As a result, there is an even more efficient flow of current through the source / drain contacts 142, further minimizing power dissipation at the source / drain contacts 142, and further improving the output resistance (RO), allowing the nanostructured field effect transistor to drive or deliver power to a load with even lower voltage or current losses.

[0199] Further advantages may be achieved by forming a coating 126 over the metal-semiconductor alloy region 125. These include a coating 126 that prevents oxidation of the surface of the underlying metal-semiconductor alloy region 125, which could result in degradation of electrical properties and increase the risk of interference between subsequently formed source / drain contacts 142 (e.g., in FIG. 28A to FIG. 28D ) and the epitaxial source / drain regions 106. As a result, device performance is enhanced and device yield is improved. For example, forming the coating 126 with a thickness of less than 1 nanometer will result in insufficient protection against oxidation of the underlying metal-semiconductor alloy region 125, which will result in degradation of electrical performance and resistance between subsequently formed source / drain contacts 142 (as shown in FIG. 28A to FIG. 28D The contact resistance between the epitaxial source / drain regions 106 and the epitaxial source / drain regions 106 increases. Relatively speaking, forming the coating 126 with a thickness greater than 4 nanometers will not result in any further improvement in preventing oxidation of the underlying metal-semiconductor alloy region 125, resulting in increased manufacturing costs.

[0200] In one embodiment, the combined thickness T4 of the metal-semiconductor alloy region 125 and the coating 126 may be in the range of 3 nm to 8 nm. The thicknesses T2, T3, and T4 may be varied by adjusting a number of specific process parameters of the deposition process, the first plasma treatment, and the second plasma treatment, such as power, gas composition, pressure, and treatment time.

[0201] As a result of the process used to form the metal-semiconductor alloy region 125 and the coating 126, the remaining layer 127 (previously FIG. 17A to FIG. 17C134 , the gate spacer 97 may be formed on the sidewalls of the fin spacer 97, on the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation region 78, multiple top surfaces of the gate spacer 98, and on the top surface and sidewalls of the gate spacer 99. For example, this remaining layer 127 is also formed along the sidewalls in the opening 134. The remaining layer 127 may include titanium silicon nitride (TiSiN), titanium nitride (TiN), a combination thereof, or the like. In one embodiment, a first portion of the remaining layer 127 on the top surface of the gate electrode 124 may include TiN. In one embodiment, a second portion of the remaining layer 127 on the gate dielectric 122, the dielectric layer 119, the isolation region 78, multiple top surfaces of the gate spacer 98, on the sidewalls of the fin spacer 97, and on the top surface and sidewalls of the gate spacer 99 (e.g., the sidewalls in the opening 134) may include TiSiN.

[0202] exist FIG. 27A to FIG. 27D In the embodiment of the present invention, a wet cleaning process 128 is performed to selectively remove (e.g., via etching) the remaining layer 127 from the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation region 78, multiple top surfaces of the gate spacer 98, the sidewalls of the fin spacer 97, and the top surface and sidewalls of the gate spacer 99 (e.g., the sidewalls within the opening 134), while leaving the metal-semiconductor alloy region 125 and the coating layer 126 on the epitaxial source / drain region 106. During the wet cleaning process 128, the metal-semiconductor alloy region 125 and the coating layer 126 disposed above the epitaxial source / drain region 106 are not removed (e.g., have a much lower etching rate than the remaining layer 127). For example, the ratio of the etching rate of the remaining layer 127 relative to the etching rate of the metal-semiconductor alloy region 125 and the coating layer 126 is in a range from 4 to 8.7. In this manner, TiN and TiSiN of the remaining layer 127 are preferentially removed using the wet cleaning process 128, while the metal-semiconductor alloy region 125 (e.g., comprising TiSi) and the coating 126 (e.g., comprising TiSiN) disposed above the epitaxial source / drain regions 106 remain substantially intact as a result of the wet cleaning process 128.

[0203] The wet cleaning process 128 may be a wet etching process, which includes removing the previously FIG. 26A to FIG. 26D The structure shown in (e.g., including the remaining layer 127) is exposed to sulfuric acid (H2SO4) at a temperature ranging from 130°C to 230°C. In one embodiment, the sulfuric acid may have a concentration ranging from 85 weight percent to 90 weight percent. In other embodiments, the wet etching process includes removing the previously FIG. 26A to FIG. 26DThe structure shown in FIG. 1 (eg, including the remaining layer 127 ) is exposed to sulfuric acid (H 2 SO 4 ) at a temperature greater than 130° C., wherein the sulfuric acid has a concentration greater than 90 weight percent. The wet cleaning process 128 may be performed for a duration ranging from 5 seconds to 60 seconds.

[0204] In alternative embodiments, the wet cleaning process 128 may include a wet etching process, wherein the wet etching process includes removing the previously FIG. 26A to FIG. 26D The structure shown in (e.g., including the residual layer 127) is exposed to a sulfonic acid (e.g., methanesulfonic acid (CH3SO3H), N-sulfonic acid (N-SO3H), benzenesulfonic acid (C6H5SO3H), chlorosulfonic acid (HSO3Cl), or the like) or a derivative thereof (e.g., benzenesulfonyl chloride (C6H5SO2Cl), sulfonamide, or the like).

[0205] Advantages may be achieved by performing a wet cleaning process 128 to selectively remove the remaining layer 127 from the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the isolation regions 78, the top surfaces of the gate spacers 98, the sidewalls of the fin spacers 97, and the top surfaces and sidewalls of the gate spacers 99 (e.g., the sidewalls within the opening 134), while leaving the metal-semiconductor alloy region 125 and the coating 126 on the epitaxial source / drain regions 106. The wet cleaning process 128 is performed using sulfuric acid (H2SO4) as an etchant, and the wet cleaning process 128 is performed when the sulfuric acid (H2SO4) is at a temperature in a range from 130° C. to 230° C. The sulfuric acid (H2SO4) may have a concentration in a range from 85 wt % to 90 wt %. These advantages include that the wet cleaning process 128 allows selective etching of titanium silicon nitride (TiSiN) and titanium nitride (TiN) of the remaining layer 127 (e.g., on the sidewalls in the opening 134) formed during the formation of the metal-semiconductor alloy region 125 and the coating 126 on the epitaxial source / drain region 106, while minimizing etching damage to the metal-semiconductor alloy region 125 (including TiSi) and the coating 126 (including TiSiN). As a result, the subsequently formed source / drain contact openings for the source / drain contacts 142 (e.g., in FIG. 28A to FIG. 28D) can be formed to have a larger width to ensure lower contact resistance, better electrical contact, and a larger contact surface area between the epitaxial source / drain regions 106 and the source / drain contacts 142. This is because there is no residual layer 127 on the sidewalls of the opening 134, which would hinder the subsequent formation of the source / drain contact openings and the source / drain contacts 142, and would hinder the electrical contact between the epitaxial source / drain regions 106 and the source / drain contacts 142. This therefore leads to enhanced device performance and improved device yield. Further, the removal of the residual layer 127 on the top surface of the gate dielectric 122 and the top surface of the gate electrode 124 ensures better electrical contact between the gate electrode 124 and the subsequently formed gate contact 140 (as shown in FIG. 28A to FIG. 28D ).

[0206] exist FIG. 28A to FIG. 28D In the process, a dielectric layer 130 is deposited on the previously FIG. 27A to FIG. 27D , such as over gate dielectric 122, gate electrode 124, dielectric layer 119, isolation region 78, gate spacer 98, and gate spacer 99. Dielectric layer 130 is also deposited over metal-semiconductor alloy region 125 and coating 126 in opening 134, and on the sidewalls within opening 134 to fill opening 134. Deposition of dielectric layer 130 may be performed using the same techniques as previously described. FIG. 19A to FIG. 19C Similar processes and similar materials described in.

[0207] After the deposition of dielectric layer 130, a planarization process is performed to level the top surface of dielectric layer 130 and top surfaces of gate dielectric 122, gate electrode 124, dielectric layer 119, gate spacer 98, and gate spacer 99. The planarization process may be a chemical mechanical polishing process, or the like.

[0208] In some embodiments, a contact etch stop layer (contact etch stop layer) 129 is disposed between the dielectric layer 130 and the coating layer 126. In addition, the contact etch stop layer 129 can be disposed between the dielectric layer 130 and the sidewalls of the gate spacer 99. The contact etch stop layer 129 can be formed using the same method as previously described. FIG. 19A to FIG. 19C Similar processes and similar materials described in.

[0209] After performing the planarization process described above to flatten the top surfaces of the dielectric layer 130, a process is performed to divide the gate structure 120 (including the gate dielectric 122 and the gate electrode 124) into a plurality of gate structures 120 (or a plurality of gate structure segments), as previously described in FIG. 20A to FIG. 21DThe gate structure 120 is divided into two gate structures 120 by forming a dielectric layer 144 (hereinafter also referred to as a gate isolation structure) extending through the gate structure 120, so that the dielectric layer 144 cuts the gate structure 120 into at least two gate structures 120. The dielectric layer 144 is formed by patterning the trenches 143, using the same method as previously described. Fig. 20A and Fig. 20B Then, using the same process, similar materials, and similar etchants as previously described in FIG. 21A to FIG. 21D A dielectric layer 144 is formed in the trench 143 using similar processes and similar materials as described in . In this manner, the dielectric layer 144 can be disposed between the first gate structure 120 and the second gate structure 120 on either side of the dielectric layer 144 .

[0210] After the formation of the dielectric layer 144, a removal process is applied to the dielectric layer 144 to remove excess material of the dielectric layer 144. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like. After the planarization process, the top surfaces of the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacers 98, the gate spacers 99, and the remaining portion of the dielectric layer 144 in the trench 143 are coplanar (within process variations).

[0211] After the formation of the dielectric layer 144 in the trench 143, and after performing the removal process described above to remove excess material of the dielectric layer 144, a second interlayer dielectric 138 is deposited over the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacers 98, the gate spacers 99, and the dielectric layer 144. In some embodiments, the second interlayer dielectric 138 is a flowable film formed via a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric 138 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, which can be formed via any suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flowable chemical vapor deposition, or the like.

[0212] In some embodiments, an etch stop layer (ESL) 136 is formed between the second interlayer dielectric 138 and the gate dielectric 122, the gate electrode 124, the dielectric layer 119, the contact etch stop layer 129, the dielectric layer 130, the gate spacer 98, the gate spacer 99, and the dielectric layer 144. The etch stop layer 136 may be formed of a dielectric material having a high etch selectivity to the etching of the second interlayer dielectric 138, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or the like.

[0213] After the formation of the etch stop layer 136 and the second interlayer dielectric 138, the same method as previously described is used. FIG. 23A to FIG. 23C The source / drain contact openings are formed in the second interlayer dielectric 138, the etch stop layer 136, the dielectric layer 130, and the contact etch stop layer 129 using a process and an etchant similar to those used to form the source / drain contact openings 141 described in . The source / drain contact openings expose the coating 126 on the underlying metal-semiconductor alloy region 125, wherein the coating 126 and the underlying metal-semiconductor alloy region 125 are disposed on the top surface and side surfaces of the epitaxial source / drain region 106 having a crystal plane. For example, the source / drain contact openings expose the coating 126, wherein the coating 126 and the underlying metal-semiconductor alloy region 125 are disposed on the top surface and sidewalls of each of the plurality of epitaxial source / drain regions 106, wherein each of the plurality of sidewalls extends from the top surface of the epitaxial source / drain region 106 to a bottom point of the sidewall that is just above the top surface of the corresponding fin spacer 97.

[0214] Acceptable photolithography and etching techniques may be used to form the source / drain contact openings. Multiple etching steps may be used to form the source / drain contact openings. As described above, the contact etch stop layer 129 is formed of a material having a high etch selectivity relative to the etching of the dielectric layer 130. One of the multiple etching steps used to form the source / drain contact openings is an etching process that is selective to the dielectric layer 130 (e.g., etching the material of the dielectric layer 130 at a faster rate than the material of the contact etch stop layer 129). Therefore, the aspect ratio of the lower portion of the source / drain contact opening may be increased, helping to ensure that a sufficient area of ​​the coating 126 disposed on the top surface and the surface side of the epitaxial source / drain region 106 having a crystal plane is exposed through the source / drain contact opening.

[0215] In the illustrated embodiment, a patterning method may be used such that some of the dielectric layer 130 remains in the Fig.28B In another embodiment, the source / drain contact openings are formed in a self-aligned patterning method so that Fig.28B In the cross section of FIG. 1 , all of the dielectric layer 130 is removed. In one embodiment, the source / drain contact openings do not extend into the coating 126. In another embodiment, the etching of the coating 126 may be performed such that the source / drain contact openings partially extend into the coating 126.

[0216] A number of advantages are achieved by forming source / drain contact openings so that coating 126 is exposed and then forming source / drain contacts 142 (described later) in the source / drain contact openings. Metal-semiconductor alloy regions 125 and coating 126 are disposed over a larger surface area of ​​epitaxial source / drain regions 106 (e.g., an increase in effective surface area in the range of 20 percent to 30 percent) and then in contact with subsequently formed source / drain contacts 142. These advantages include allowing for reduced contact resistance between subsequently formed source / drain contacts 142 (described later) and epitaxial source / drain regions 106. As a result, there is more efficient current flow through source / drain contacts 142, minimizing power dissipation at source / drain contacts 142, and improving output resistance (RO), allowing the nanostructure field effect transistor to drive or deliver power to a load without significant voltage or current losses.

[0217] Further references FIG. 28A to FIG. 28D A gate contact opening is also formed which extends through the second interlayer dielectric 138 and the etch stop layer 136. The gate contact opening may be formed using acceptable photolithography and etching techniques, and may expose the top surface of the gate electrode 124.

[0218] After the formation of the source / drain contact openings and the gate openings, source / drain contacts 142 are formed in the source / drain contact openings, and gate contacts 140 are formed in the gate contact openings. A liner (e.g., a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the source / drain contact openings and the gate contact openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The deposition of the liner may be via a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. The conductive material may be tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like. The deposition of the conductive material may be via atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. A planarization process such as chemical mechanical polishing may be performed to remove excess material from the top surface of the second interlayer dielectric 138. The remaining liner and conductive material in the source / drain contact openings and in the gate contact openings form source / drain contacts 142 and gate contacts 140, respectively. After the formation is completed, the top surfaces of the second interlayer dielectric 138, the source / drain contacts 142, and the gate contacts 140 are coplanar (within process variations). In other embodiments, the gate contact openings and the gate contacts 140 may be formed before, simultaneously with, or after the source / drain contact openings and the source / drain contacts 142.

[0219] Several embodiments of the present disclosure have some advantageous features. These embodiments include planarizing multiple top surfaces of the gate stack and adjacent interlayer dielectric (ILD) layers, and removing the interlayer dielectric to form multiple first openings, which expose the top surface and side surface of the source / drain region below one layer of the nanostructure field effect transistor. A plasma deposition process is then performed to sequentially form a titanium silicide (TiSi) layer and a titanium silicon nitride (TiSiN) layer above the exposed top surface and side surface of the source / drain region. A wet etching process is then performed to selectively etch the TiSiN and titanium nitride (TiN) formed during the plasma deposition process from the surface of the gate stack and other structures, while leaving the TiSi layer and TiSiN layer above the source / drain region. The wet etching process is performed using sulfuric acid (H2SO4) as an etchant. One or more embodiments disclosed herein may allow for an increase in the effective area of ​​the TiSi / TiSiN bilayer on the source / drain region, which contacts the subsequently formed source / drain contacts. This results in a reduced contact resistance between the source / drain contacts and the source / drain regions. As a result, there is a more efficient flow of current through the source / drain contacts, minimizing power dissipation at the source / drain contacts, and improving output resistance (RO), thereby allowing the semiconductor device to drive or deliver power to a load without significant voltage or current loss. Further, the use of a wet etching process allows TiSiN and titanium nitride (TiN) formed during the plasma deposition process to be selectively etched from the surface of the gate stack and other structures (e.g., the sidewalls of the first opening), while minimizing etching damage to the TiSi layer and TiSiN layer above the source / drain region. As a result, a source-drain contact with a lower contact resistance can be subsequently formed and has unimpeded electrical contact with the source / drain region, which further leads to improved device performance and device yield.

[0220] According to one embodiment, a method includes forming a multilayer stack above a semiconductor substrate, the multilayer stack including multiple sacrificial layers alternating with multiple channel layers; forming a dummy gate stack above the top surface and sidewalls of the multilayer stack; forming multiple first spacers on multiple sidewalls of the dummy gate stack; growing an epitaxial source / drain region extending through the multiple sacrificial layers and the multiple channel layers, wherein the epitaxial source / drain region is adjacent to the dummy gate stack; forming a metal-semiconductor alloy region on multiple first portions of the epitaxial source / drain region; forming a coating on the metal-semiconductor alloy region, wherein during the formation of the metal-semiconductor alloy region and the coating, a residual layer is formed on multiple sidewalls of the multiple first spacers; and performing a wet cleaning process to selectively etch the residual layer from the multiple sidewalls of the multiple first spacers while leaving the metal-semiconductor alloy region and the coating on the multiple first portions of the epitaxial source / drain region. In one embodiment, the method further includes depositing a first interlayer dielectric (ILD) over the epitaxial source / drain region; and before forming the metal-semiconductor alloy region and the coating, removing the first interlayer dielectric to form a first opening, the first opening exposing a plurality of first portions of the epitaxial source / drain region in the first opening. In one embodiment, the method further includes removing a sacrificial layer and a dummy gate stack to form a first recess before removing the first interlayer dielectric to form the first opening; forming a gate stack in the first recess; and performing a planarization process to make the top surface of the first interlayer dielectric flush with the top surface of the gate stack. In one embodiment, during the formation of the metal-semiconductor alloy region and the coating, a residual layer is also formed on the top surface of the gate stack, and wherein during the wet cleaning process, the residual layer on the top surface of the gate stack is selectively etched. In one embodiment, the residual layer includes titanium silicon nitride (TiSiN) or titanium nitride (TiN). In one embodiment, performing the wet cleaning process includes exposing the residual layer to sulfuric acid (H2SO4). In one embodiment, during the wet cleaning process, the temperature of sulfuric acid (H2SO4) is in a range from 130° C. to 230° C. In one embodiment, during the wet cleaning process, the concentration of sulfuric acid (H2SO4) is in a range from 85 weight percent to 90 weight percent. In one embodiment, the metal-semiconductor alloy region includes titanium silicide (TiSi), and the coating includes titanium silicon nitride (TiSiN).

[0221] According to one embodiment, a method includes sequentially depositing a first sacrificial layer and a first channel layer over a semiconductor substrate; patterning the first sacrificial layer, the first channel layer, and the semiconductor substrate to form a fin structure protruding from the semiconductor substrate; forming a plurality of isolation regions on opposite sides of the fin structure, wherein the fin structure protrudes above a plurality of top surfaces of the isolation regions; forming a first source / drain region in the fin structure, the first source / drain region extending through the first sacrificial layer and the first channel layer; forming an insulating fin extending into the fin structure and isolating a first portion of the fin structure from a second portion of the fin structure; forming a metal-semiconductor alloy region over the first source / drain region; forming a coating over the metal-semiconductor alloy region, wherein during the formation of the coating and the metal-semiconductor alloy region, a residual layer is formed on the top surface of the insulating fin and the top surface of the isolation region; and performing a wet etching process to selectively etch the residual layer from the top surface of the insulating fin and the top surface of the isolation region. In one embodiment, the method further comprises forming a first portion of a gate stack adjacent to a first source / drain region, a plurality of first spacers being disposed on a plurality of sidewalls of the first portion of the gate stack, wherein the first portion of the gate stack is disposed above the first channel layer; and replacing the first sacrificial layer with a second portion of the gate stack, wherein during the formation of the metal-semiconductor alloy region and the coating, a residual layer is also formed on a top surface of the first portion of the gate stack and on sidewalls of the first spacers. In one embodiment, during a wet etching process, the residual layer on the top surface of the first portion of the gate stack and on sidewalls of the first spacers is selectively etched, and wherein the wet etching process comprises exposing the residual layer to an etchant comprising H2SO4. In one embodiment, the residual layer comprises titanium silicon nitride (TiSiN) or titanium nitride (TiN). In one embodiment, forming the metal-semiconductor alloy region comprises performing a deposition process to deposit a titanium layer above the first source / drain region; and during the deposition process, performing a first plasma treatment to expose the titanium layer to a nitrogen (N2) or ammonia (NH3) plasma. In one embodiment, the thickness of the metal-semiconductor alloy region is in a range from 2 nanometers to 4 nanometers, and the thickness of the coating is in a range from 1 nanometer to 4 nanometers.

[0222] According to one embodiment, a semiconductor device includes a gate structure above a semiconductor substrate; source / drain regions above the semiconductor substrate and on multiple opposite sides of the gate structure; a first channel layer disposed between the source / drain regions and above the semiconductor substrate; an internal spacer between a first end of the first channel layer and the semiconductor substrate, wherein the gate structure fills the space between the multiple internal spacers; a metal-semiconductor alloy region above the top surface and sidewalls of each of the multiple source / drain regions; and a coating above the metal-semiconductor alloy region, wherein the material of the metal-semiconductor alloy region and the material of the coating are different. In one embodiment, the metal-semiconductor alloy region includes titanium silicide (TiSi), and wherein the coating includes titanium silicon nitride (TiSiN). In one embodiment, the thickness of the metal-semiconductor alloy region is in a range from 2 nanometers to 4 nanometers. In one embodiment, the thickness of the coating is in a range from 1 nanometer to 4 nanometers. In one embodiment, the semiconductor device also includes source / drain contacts above and electrically connected to multiple corresponding source / drain regions among the multiple source / drain regions, wherein each source / drain contact partially extends into a coating disposed above the corresponding source / drain contact.

[0223] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purpose as the embodiments introduced herein, and / or to achieve the same advantages. Those skilled in the art will also appreciate that such equal constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method includes: forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers alternating with a plurality of channel layers; forming a dummy gate stack over a top surface and sidewalls of the multilayer stack; forming a plurality of first spacers on a plurality of sidewalls of the dummy gate stack; growing an epitaxial source / drain region extending through the plurality of sacrificial layers and the plurality of channel layers, wherein the epitaxial source / drain region is adjacent to the dummy gate stack; forming a metal-semiconductor alloy region on the plurality of first portions of the epitaxial source / drain regions; forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on the sidewalls of the first spacers; as well as A wet cleaning process is performed to selectively etch the remaining layer from the sidewalls of the first spacers while leaving the metal-semiconductor alloy region and the coating on the first portions of the epitaxial source / drain regions.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Also includes: depositing a first interlayer dielectric over the epitaxial source / drain regions; and Before forming the metal-semiconductor alloy region and the coating layer, the first interlayer dielectric is removed to form a first opening exposing the first portions of the epitaxial source / drain regions in the first opening.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Performing the wet cleaning process includes exposing the remaining layer to sulfuric acid.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The metal-semiconductor alloy region comprises titanium silicide, and the coating comprises titanium silicon nitride.

5. A method for manufacturing a semiconductor device, characterized in that: The method includes: sequentially depositing a first sacrificial layer and a first channel layer on a semiconductor substrate; patterning the first sacrificial layer, the first channel layer, and the semiconductor substrate to form a fin structure protruding from the semiconductor substrate; forming a plurality of isolation regions on opposite sides of the fin structure, wherein the fin structure protrudes above a plurality of top surfaces of the plurality of isolation regions; forming a first source / drain region in the fin structure, the first source / drain region extending through the first sacrificial layer and the first channel layer; forming an insulating fin extending into the fin structure and isolating a first portion of the fin structure from a second portion of the fin structure; forming a metal-semiconductor alloy region above the first source / drain region; forming a coating layer over the metal-semiconductor alloy region, wherein a residual layer is formed on a top surface of the insulating fin and a plurality of top surfaces of the plurality of isolation regions during the formation of the coating layer and the metal-semiconductor alloy region; as well as A wet etching process is performed to selectively etch the remaining layer from the top surface of the insulating fin and top surfaces of the isolation regions.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Also includes: forming a first portion of a gate stack adjacent to the first source / drain region, a plurality of first spacers disposed on a plurality of sidewalls of the first portion of the gate stack, wherein the first portion of the gate stack is disposed above the first channel layer; as well as The first sacrificial layer is replaced with a second portion of the gate stack, wherein the remaining layer is also formed on a top surface of the first portion of the gate stack and on multiple sidewalls of the first spacer during the formation of the metal-semiconductor alloy region and the coating.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: Forming the metal-semiconductor alloy region comprises: performing a deposition process to deposit a titanium layer over the first source / drain region; and During the deposition process, a first plasma treatment is performed to expose the titanium layer to nitrogen or ammonia plasma.

8. A semiconductor device, characterized in that: Include: a gate structure on a semiconductor substrate; a plurality of source / drain regions over the semiconductor substrate and on opposing sides of the gate structure; a first channel layer disposed between a plurality of source / drain regions and above the semiconductor substrate; a plurality of internal spacers between the first end of the first channel layer and the semiconductor substrate, wherein the gate structure fills a space between the plurality of internal spacers; a metal-semiconductor alloy region over a top surface and sidewalls of each of the plurality of source / drain regions; as well as A coating is over the metal-semiconductor alloy region, wherein a material of the metal-semiconductor alloy region and a material of the coating are different.

9. The semiconductor device according to claim 8, wherein: The metal-semiconductor alloy region comprises titanium silicide, and wherein the coating comprises titanium silicon nitride.

10. The semiconductor device according to claim 8, wherein Also includes: A source / drain contact is disposed over and electrically connected to a plurality of corresponding source / drain regions of the plurality of source / drain regions, wherein each source / drain contact partially extends into the coating disposed over the corresponding source / drain contact.

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