Solar cell and manufacturing method thereof, photovoltaic module

Abstract

The application discloses a solar cell and a manufacturing method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate, the semiconductor substrate has a first surface and a second surface opposite to each other, and a first semiconductor layer is arranged on the first surface. The first semiconductor layer comprises a first part and a second part adjacent to the first part along a second direction. The crystallization degree of the first part is greater than that of the second part. The first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon. By arranging a reasonable crystallization area and an amorphous area on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized by the higher crystallization degree of the first part, the cell efficiency is improved, and the passivation effect of the second part is ensured by the lower crystallization degree of the second part, so that electric leakage is prevented.

Description

[0001] This application claims priority to Chinese Patent Application No. 202411017051.5, filed on July 26, 2024, entitled “A Solar Cell and a Method for Manufacturing the Same Thereof, and a Photovoltaic Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaic technology, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0003] In solar cell structures, laser treatment is used to process the semiconductor layers on the textured surface. Some of these semiconductor layers contain hydrogen, which heats up after absorbing light, causing hydrogen to escape and increasing effective doping. Furthermore, laser treatment can reduce the contact resistance of the solar cell, thereby reducing energy loss during current collection and improving cell efficiency. However, if the laser-treated area is not properly managed, it can lead to a higher risk of leakage in certain areas of the solar cell, affecting its efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, to reduce contact resistance, decrease leakage risk, and improve battery efficiency.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] A first semiconductor layer is disposed on a first surface. The first semiconductor layer includes a first portion and a second portion adjacent to the first portion along a second direction. The crystallinity of the first portion is greater than that of the second portion. The first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0009] With the above technical solution, a crystalline structure is formed in the first portion of the first semiconductor layer, resulting in a portion that is both crystalline and non-crystalline. The first portion is not entirely crystalline; it is mostly amorphous, with only a portion forming a crystalline structure, such as nanocrystals. The second portion of the first semiconductor layer, adjacent to the first portion along the second direction, is not crystalline and retains its original amorphous structure. (It should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallinity or crystalline content of the nanocrystalline silicon or microcrystalline silicon in the second portion remains unchanged.) This results in the overall crystallinity of the first portion of the first semiconductor layer being greater than that of the second portion. It is understandable that, all other things being equal, the smaller the degree of crystallinity of the semiconductor layer, the smaller the grains within it, potentially exhibiting the disordered nature of amorphous silicon. Smaller grains in the semiconductor layer result in more interfaces between the grains, leading to higher resistance at the grain interfaces. Therefore, the crystalline structure in the first portion of the first semiconductor layer reduces the contact resistance, thereby reducing the contact resistance between the first portion and the conductive material (transparent conductive layer or electrode), and thus facilitating the reduction of transport losses of charge carriers collected in the first semiconductor layer to the conductive material. Simultaneously, the degree of crystallinity in the second portion of the first semiconductor layer is less than that in the first portion, ensuring the passivation effect of the second portion adjacent to the first portion along the second direction, reducing recombination at the edge of the first semiconductor layer. That is, for back-contact solar cells, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the lower degree of crystallinity in the second portion ensures the passivation effect and prevents leakage between the second portion and the second semiconductor layer. As can be seen, by setting reasonable crystalline and amorphous regions on the first semiconductor layer, the higher degree of crystallinity in the first portion optimizes the overall cell efficiency of the solar cell, improving cell efficiency, while the lower degree of crystallinity in the second portion ensures the passivation effect and prevents leakage.

[0010] In one implementation, the solar cell further includes a second semiconductor layer disposed on the first surface. The first and second semiconductor layers are arranged adjacent to each other along a second direction, and the first and second semiconductor layers have different conductivity types. Along the second direction, the second portion is closer to the second semiconductor layer than the first portion. The second semiconductor layer has an adjacent side close to the first semiconductor layer. Using this technical solution, for a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallinity to ensure passivation, preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.

[0011] In one implementation, along a second direction, the second portion extends from the edge of the first portion to near the adjacent side, but does not contact the adjacent side. With this technical solution, the second portion does not contact the second semiconductor layer, and the distance between the second portion and the second semiconductor layer is relatively large, which helps to further reduce the risk of leakage between the second portion and the second semiconductor layer.

[0012] In one implementation, along a second direction, the second portion extends from the edge of the first portion to an adjacent side and contacts the adjacent side. Using this technical solution, the second portion is stacked with at least a portion of the adjacent side of the second semiconductor layer. The second portion has a lower degree of crystallinity, allowing weaker currents to be transmitted through the second portion and the adjacent side of the second semiconductor layer. When the solar cell is shaded, the current can form a leakage path through the second portion and the adjacent side of the second semiconductor layer, preventing the shaded cell from becoming a load that consumes the energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0013] In one implementation, along the second direction, the edge of the first portion is at least 20 μm away from the adjacent side. This arrangement ensures that the first portion, which has strong transmission circuit capabilities, is spaced far from the second semiconductor layer, reducing the risk of leakage between the first portion and the second semiconductor layer.

[0014] In one implementation, a portion of the second part is disposed on the second semiconductor layer to form a stacked portion, and the second part extends from the edge of the first part to the stacked portion along a second direction. This technical solution, by extending the second part from the edge of the first part to the stacked portion, increases the current transmission capability between the second part and the second semiconductor layer. When the solar cell is shaded, current can form a leakage path through the second part and the surface of the second semiconductor layer facing away from the semiconductor substrate. This leakage path has a stronger current transmission capability, further reducing the risk of hot spots.

[0015] In one implementation, the width of the second portion along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. With this setting, if the second portion is too large, for example, greater than 500 μm, it will significantly obstruct the second semiconductor layer, hindering effective current collection and resulting in an excessively large leakage path and substantial battery efficiency loss. If the second portion is too small, for example, less than 20 micrometers, the laser will be difficult to control and may irradiate other parts (such as the second semiconductor layer), causing damage to those parts.

[0016] In one implementation, the solar cell further includes a first transparent conductive layer covering the first semiconductor layer, wherein the projection of the first portion onto the semiconductor substrate lies entirely within the projection of the first transparent conductive layer onto the semiconductor substrate. This configuration, by incorporating the first transparent conductive layer, enhances the carrier transport capability of the first semiconductor layer, enabling the formation of good ohmic contact with the electrodes and improving conductivity. The first portion, having a crystalline structure, does not extend beyond the boundary of the first transparent conductive layer, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer, improving conductivity, and ultimately increasing cell efficiency.

[0017] In one implementation, along the second direction, the first transparent conductive layer extends to an adjacent side or to a second portion located above the second semiconductor layer. This configuration allows the first transparent conductive layer to cover a larger area of ​​the first semiconductor layer, further improving conductivity.

[0018] In one implementation, the solar cell further includes a second transparent conductive layer covering the second semiconductor layer; a PN isolation region is located between the second transparent conductive layer and the first transparent conductive layer, and the PN isolation region is situated on the second semiconductor layer. Electrical insulation between the P-region and the N-region is achieved through the PN isolation region. The projection of the first portion lies within the boundary of the first transparent conductive layer; therefore, the first portion will not enter the boundary of the PN isolation region, and the irradiation range of the laser will not enter the PN isolation region. Since the PN isolation region lacks a crystalline structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region is guaranteed.

[0019] In one implementation, a portion of the second part is disposed on the second semiconductor layer to form a stacked portion, and a PN isolation region is disposed on the stacked portion.

[0020] In one implementation, the solar cell further includes a third semiconductor layer disposed on the second surface. The material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, and the conductivity type of the third semiconductor layer is different from that of the first semiconductor layer. With this configuration, when the third semiconductor layer includes an amorphous silicon layer, both sides of the semiconductor substrate are provided with a full-surface amorphous silicon layer, and both amorphous silicon layers can form heterojunction structures, thereby forming a bifacial heterojunction cell. When the third semiconductor layer includes polycrystalline silicon, a polycrystalline silicon passivation structure can be formed on the second surface, and an amorphous silicon layer or a nanocrystalline silicon layer passivation structure can be formed on the first surface, thereby forming a bifacial hybrid cell. As long as an amorphous silicon layer and / or a nanocrystalline silicon layer are present, bifacial heterojunction cells and bifacial hybrid cells can also be applied to the cell structure in this application where the edges are amorphous and the middle region has a crystalline structure, to improve cell efficiency.

[0021] In one implementation, both the first and second parts extend in strip-like shapes along a first direction, and the first and second directions intersect. Specifically, the first and second parts are arranged in approximately parallel strip-like shapes, so that they can gradually move along the first direction during laser irradiation, which facilitates the formation of laser irradiation on the first part.

[0022] In one implementation, the contact resistance of the first part is less than that of the second part. Since the first part can have a crystalline structure and the second part has an amorphous structure, the effective doping of the crystalline structure of the first part is increased, which reduces the contact resistance of the first part relative to the second part. This reduces the energy loss during the current collection process of the first part and improves the battery efficiency.

[0023] In one implementation, the first part extends along a first direction to the edge of the first surface, thereby maximizing the area of ​​the first part, reducing contact resistance, and improving current collection capability.

[0024] In one implementation, the second part surrounds the first part. This arrangement results in a lower degree of crystallinity in the second part surrounding the first part, further reducing the risk of leakage and ensuring the photoelectric conversion efficiency of the solar cell.

[0025] In one implementation, the first part is made of amorphous silicon and nanocrystalline silicon, while the second part is made of amorphous silicon. This allows the second part to have better passivation. By setting appropriate crystalline and amorphous regions on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, thus improving the overall cell efficiency.

[0026] In one implementation, the semiconductor substrate includes a recessed portion on a first surface, the recessed portion being recessed towards a second surface relative to the remainder of the first surface, with a first portion located within the recessed portion. This configuration, where the recessed portion is formed by etching to the surface of the semiconductor substrate, typically has a textured surface. Placing the first portion, which is made of amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon, within the recessed portion increases the contact area of ​​the first portion, facilitating current collection.

[0027] A photovoltaic module includes a solar cell, wherein the solar cell is any one of the solar cells described above.

[0028] Since the photovoltaic module uses the solar cells of any of the first aspects or above, the photovoltaic module has the same beneficial effects as the first aspect, which will not be elaborated here.

[0029] This invention also provides a method for manufacturing a solar cell, comprising:

[0030] A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces;

[0031] A first semiconductor layer is formed on the first surface, the first semiconductor layer comprising at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0032] A laser is used to irradiate a first portion of the first semiconductor layer, while the second portion of the first semiconductor layer is not irradiated, resulting in a higher degree of crystallinity in the first portion than in the second portion; the first and second regions are adjacent to each other along a second direction. In this technical solution, a laser is used to crystallize the region corresponding to the first portion of the first semiconductor layer, increasing the degree of crystallinity, while the region corresponding to the second portion of the first semiconductor layer adjacent to the first portion is not irradiated by the laser, retaining its amorphous structure. (It should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallinity or crystallineity of the nanocrystalline silicon or microcrystalline silicon in the second portion remains unchanged.) This results in an overall higher degree of crystallinity in the first portion of the first semiconductor layer than in the second portion. It is understood that, all other things being equal, the lower the degree of crystallinity of the semiconductor layer, the smaller the grains in the semiconductor layer, even exhibiting the disorder of amorphous silicon material. Smaller grains in the semiconductor layer result in more interfaces between the grains, leading to a higher resistance at the grain interfaces. Therefore, the crystalline structure in the first portion of the first semiconductor layer reduces the contact resistance, thereby reducing the contact resistance between the first portion and the conductive material (transparent conductive layer or electrode), and thus facilitating the reduction of transport losses of charge carriers collected in the first semiconductor layer to the conductive material. Simultaneously, the degree of crystallinity in the second portion of the first semiconductor layer is less than that in the first portion, ensuring the passivation effect of the second portion adjacent to the first portion along the second direction, reducing recombination at the edge of the first semiconductor layer. That is, for back-contact solar cells, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the lower degree of crystallinity in the second portion ensures the passivation effect and prevents leakage between the second portion and the second semiconductor layer. As can be seen, by setting reasonable crystalline and amorphous regions on the first semiconductor layer, the higher degree of crystallinity in the first portion optimizes the overall cell efficiency of the solar cell, improving cell efficiency, while the lower degree of crystallinity in the second portion ensures the passivation effect and prevents leakage.

[0033] In one implementation, the first semiconductor layer is an amorphous silicon layer. After the first portion is irradiated with a laser, some of the amorphous silicon layer crystallizes to form nanocrystals. Since the first semiconductor layer is amorphous silicon, the portion not irradiated by the laser has a better passivation effect, and the insulation effect in the isolation region is also better.

[0034] In one implementation, before irradiating the first portion with a laser, a second semiconductor layer is formed on the first surface. The first and second semiconductor layers are arranged adjacent to each other along a second direction. The first and second semiconductor layers have different conductivity types, and the second semiconductor layer has an adjacent side close to the first semiconductor layer. Compared to the first portion, the second portion is closer to the second semiconductor layer. For a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallinity to ensure the passivation effect of the second portion, preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.

[0035] In one implementation, the first portion extends along a first direction and has a strip-like shape. Irradiating the first portion with a laser includes: the laser irradiates the first portion along the first direction, and along a second direction, the starting or ending position of the laser is at a first distance from the adjacent side. The end of the second portion facing away from the first portion also has a certain distance from the adjacent side. The second portion does not contact the second semiconductor layer, and the large distance between the second portion and the second semiconductor layer helps to further reduce the risk of leakage between the second portion and the second semiconductor layer.

[0036] In one implementation, the starting or ending position of the laser beam along the first direction is a second distance from the boundary of the first semiconductor layer. The second distance is the extension distance of the second portion along the first direction. The second distance ensures that the two ends of the first semiconductor layer along the first direction are not irradiated by the laser, thus preserving the amorphous structure and guaranteeing the passivation effect at the edge portion, thereby reducing recombination at the edge portion.

[0037] In one implementation, the second distance is greater than the first distance.

[0038] In one implementation, the wavelength of the laser is 325 nm to 532 nm; and / or, the energy density of the laser is 200 mJ / cm². 2 ~6000mJ / cm 2 By setting this wavelength range, the laser can be absorbed by the amorphous semiconductor layer, which is beneficial for achieving crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the tip of the textured structure will be too high, thus affecting the passivation of the tip region of the textured structure. If the laser energy density is too low, the energy accumulation time will be too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, selecting a laser energy density within this range allows only the tip of the textured structure to reach a high temperature, achieving morphological changes and forming a crystalline structure. Attached Figure Description

[0039] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0040] Figure 1 A schematic diagram of a solar cell provided in an embodiment of this application;

[0041] Figure 2 A schematic diagram of another solar cell provided in an embodiment of this application;

[0042] Figure 3 This is a partial schematic diagram of the arrangement of the transparent conductive layer on the first surface of a solar cell according to an embodiment of the present invention;

[0043] Figure 4 Provided for the embodiments of this application Figure 3 A magnified view of a portion of the image;

[0044] Figure 5 for Figure 4 A schematic cross-sectional view of section BB in the diagram;

[0045] Figure 6 for Figure 4 A schematic cross-sectional view of section AA in the diagram;

[0046] Figures 7-18 A schematic flowchart illustrating the steps of a method for manufacturing a solar cell according to an embodiment of the present invention;

[0047] Figure 19 A schematic diagram comparing EL test images of a solar cell provided in an embodiment of the present invention and a conventional solar cell with a crystallization region;

[0048] Figure 20 A schematic diagram comparing the P-region contact resistance of a solar cell provided in an embodiment of the present invention and a conventional solar cell without a crystallization region;

[0049] Figure 21 This is a schematic diagram of the crystallization of the top of the pyramid provided in an embodiment of the present invention.

[0050] Figure label:

[0051] 100 is the first semiconductor layer, 1 is the first strip, 11 is the first part, 12 is the second part, 13 is the intrinsic amorphous silicon layer, 14 is the p-type amorphous silicon layer, 15 is the stacked part, 2 is the second semiconductor layer, 21 is the tunneling oxide layer, 22 is the n-type doped polycrystalline silicon layer, 23 is the intrinsic polycrystalline silicon layer, 24 is the phosphosilicate glass layer, 25 is the silicon nitride mask layer, 3 is the edge isolation region, 4 is the first gate electrode, 5 is the second gate electrode, 6 is the semiconductor substrate, 7 is the transparent conductive layer, 71 is the first transparent conductive layer, 72 is the second transparent conductive layer, 73 is the third transparent conductive layer, 8 is the passivation layer, 9 is the antireflection layer, and 10 is the PN isolation region. Detailed Implementation

[0052] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0055] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0057] like Figures 1-6 As shown, an embodiment of the present invention provides a solar cell, including a semiconductor substrate 6 and a first semiconductor layer 100; wherein the semiconductor substrate 6 has a first surface and a second surface facing each other; the first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 includes a first portion 11 and a second portion 12, wherein the first portion 11 and the second portion 12 are adjacent to each other along a second direction. That is, along the second direction, both sides of the first portion 11 are adjacent to the second portion 12, or one side of the first portion 11 is adjacent to the second portion 12.

[0058] The degree of crystallization in the first part 11 is greater than that in the second part 12. The first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; that is, the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first semiconductor layer 100 can also be any combination of two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. The degree of crystallization of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon can be improved after laser crystallization. For example, when the first semiconductor layer 100 is an amorphous silicon layer, in the laser-crystallized portion, some of the amorphous silicon layer will crystallize to form nanocrystals. Nanocrystalline silicon refers to a crystallization structure where most of the grain size is at the nanometer scale, for example, grain size below 200 nm. When the first semiconductor layer 100 includes a nanocrystalline silicon layer or microcrystalline silicon, the crystallinity or degree of crystallization of the first semiconductor layer 100 will increase in the laser-crystallized portion.

[0059] In practical applications, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate 6. For example, the semiconductor substrate 6 can be a silicon substrate. Alternatively, the semiconductor substrate 6 can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 can be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0060] Secondly, the semiconductor substrate 6 has a first surface and a second surface that are opposite to each other. The first surface of the semiconductor substrate 6 may correspond to the light-facing surface of the solar cell, and the second surface of the semiconductor substrate 6 may correspond to the back-lighting surface of the solar cell; or, the first surface of the semiconductor substrate 6 may also correspond to the back-lighting surface of the solar cell, and the second surface of the semiconductor substrate 6 may correspond to the light-facing surface of the solar cell.

[0061] With the above technical solution, a crystalline structure is formed in the first portion 11 of the first semiconductor layer 100, resulting in a crystalline part and an uncrystalline part within the first portion 11. The first portion 11 is not entirely crystalline; it is mostly amorphous, with only a portion forming a crystalline structure, such as nanocrystals. The second portion 12 of the first semiconductor layer 100, adjacent to the first portion 11 along the second direction, is not crystalline, retaining its original amorphous structure. (It should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallinity or crystalline content of the nanocrystalline silicon or microcrystalline silicon in the second portion 12 remains unchanged.) This results in a higher overall degree of crystallinity in the first portion 11 than in the second portion 12. It is understandable that, all other things being equal, the lower the degree of crystallinity of the semiconductor layer, the smaller the grains within it, potentially exhibiting the disordered nature of amorphous silicon. Smaller grains in the semiconductor layer result in more interfaces between the grains, leading to a higher resistance at the grain interfaces. Therefore, the crystallization structure in the first portion 11 of the first semiconductor layer 100 reduces the contact resistance and the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby reducing the transport loss of charge carriers collected in the first semiconductor layer 100 to the conductive material. Simultaneously, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor layer, and the lower degree of crystallization of the second portion 12 ensures the passivation effect of the second portion 12 and prevents leakage between the second portion 12 and the second semiconductor layer 2. As can be seen from the above, by setting reasonable crystallized and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized by utilizing the higher degree of crystallization of the first part 11, thereby improving the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 ensures the passivation effect of the second part 12 and prevents leakage.

[0062] It is understandable that, in the case where at least a portion of the first surface of the semiconductor substrate 6 is textured, multiple pyramid-like structures are formed on the textured surface. For example... Figure 21As shown, the first semiconductor layer 100 is conformally disposed on the textured surface. The degree of crystallization of the portion of the first semiconductor layer 100 covering at least part of the top of the pyramid-like structure is greater than the degree of crystallization of the other portion of the first semiconductor layer 100 covering the base of the pyramid-like structure. When observing the degree of crystallization of the first semiconductor layer 100, if the observed area is too small, observing only the base region of the pyramid-like structure will not accurately determine the degree of crystallization. Therefore, the observed area should at least include one pyramid-like structure. Preferably, the observed area should be greater than or equal to 5*5μm. 2 This is to prevent the crystallization degree of the first semiconductor layer 100 from being inaccurately obtained by only observing the base region of the pyramid-like structure.

[0063] In some possible implementations, the contact resistance of the first portion 11 is less than that of the second portion 12. Since the first portion 11 has a crystalline structure or a higher degree of crystallinity, while the second portion 12 has an amorphous structure or a lower degree of crystallinity, the effective doping of the first portion 11 is increased. This, relative to the second portion 12, can reduce the contact resistance of the first portion 11, thereby reducing energy loss during current collection in the first portion 11 and improving battery efficiency. For example, such as... Figure 20 As shown, when the first semiconductor layer 100 is disposed in the P region, it can be seen from the comparison of the P region contact resistance of the cell in the amorphous region and the cell in the crystalline region that the overall contact resistance of the solar cell with the first part 11 in the first semiconductor layer 100 is less than the overall contact resistance of the solar cell without the first part 11 in the first semiconductor layer 100.

[0064] like Figure 1 As shown, in this embodiment, the solar cell further includes a second semiconductor layer 2 disposed on the first surface. The first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction, that is, the solar cell is a back-contact solar cell. Both the first semiconductor layer 100 and the second semiconductor layer 2 are disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. Figures 4-5 As shown, the second semiconductor layer 2 has an adjacent side close to the first semiconductor layer 100. Along the second direction, the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. To achieve the arrangement of P-regions and N-regions on the first surface, the first semiconductor layer 100 is one of P-regions and N-regions, and the second semiconductor layer 2 is the other of P-regions and N-regions.

[0065] Using the above technical solution, for back-contact solar cells, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2. The crystallinity of the second part 12 is smaller to ensure the passivation effect of the second part 12, prevent leakage between the second part 12 and the second semiconductor layer 2, and reduce the photoelectric conversion efficiency of the solar cell.

[0066] In the above technical solutions, such as Figure 1 As shown, the first semiconductor layer 100 may include a plurality of first strip-shaped portions 1 extending along a first direction, and the second semiconductor layer 2 may include a plurality of second strip-shaped portions extending along the first direction. The first strip-shaped portions 1 and the second strip-shaped portions are arranged alternately along a second direction, and the first and second directions intersect. In this embodiment, the first strip-shaped portion 1 extends entirely along the first direction, and the width direction of the first strip-shaped portion 1 is the same as that of the second direction. Along the width direction of the first strip-shaped portion 1, the first strip-shaped portion 1 includes a first portion 11 and a second portion 12 that are adjacent to each other. That is, the first portion 11 and the second portion 12 are arranged adjacent to each other along the width direction of the first strip-shaped portion 1, and the second portion 12 is arranged closer to the second strip-shaped portion. The second portion 12 is located between the first portion 11 and the second strip-shaped portion, thereby preventing leakage between the second portion 12 and the second strip-shaped portion. In this embodiment, in the structure of the first strip-shaped portion 1, the second portion 12 can be arranged on both sides of the first portion 11 along the second direction, further reducing the risk of leakage.

[0067] like Figure 1 and Figure 2 As shown, in this embodiment, both the first part 11 and the second part 12 are strip-shaped extending along the first direction, and the first and second directions intersect. Specifically, the first part 11 and the second part 12 are arranged in approximately parallel strip shapes, so that they can gradually move along the first direction during laser irradiation, which is beneficial for the formation of laser irradiation on the first part 11.

[0068] like Figure 5 As shown, in some embodiments, along the second direction, the second portion 12 extends from the edge of the first portion 11 to near the adjacent side, but does not contact the adjacent side. Specifically, the second portion 12 extends from the edge of the first portion 11 to... Figure 5 Within the S3 region, that is, the end of the second part 12 facing away from the first part 11 has a certain distance from the adjacent side. With this technical solution, the second part 12 does not contact the second semiconductor layer 2, and the distance between the second part 12 and the second semiconductor layer 2 is large, which helps to further reduce the leakage current risk between the second part 12 and the second semiconductor layer 2.

[0069] like Figure 5As shown, in some other embodiments, along a second direction, the second portion 12 extends from the edge of the first portion 11 to an adjacent side and contacts the adjacent side. Specifically, the second portion 12 extends from the edge of the first portion 11 to... Figure 5 Within region S2, the end of the second part 12 facing away from the first part 11 contacts the adjacent side, and the second part 12 is stacked with at least a portion of the adjacent side. Using this technical solution, the second part 12 is stacked with at least a portion of the adjacent side of the second semiconductor layer 2. The second part 12 has a lower degree of crystallinity, allowing weaker currents to be transmitted through the second part 12 and the adjacent side of the second semiconductor layer 2. When the solar cell is shaded, the current can form a leakage path through the second part 12 and the adjacent side of the second semiconductor layer 2, preventing the shaded cell from becoming a load that consumes the energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0070] Furthermore, in the above technical solution, along the second direction, the distance between the edge of the first portion 11 and the adjacent side is greater than or equal to 20 μm. This arrangement ensures that the first portion 11, with its strong transmission circuit capability, is spaced far from the second semiconductor layer 2, reducing the risk of leakage between the first portion 11 and the second semiconductor layer 2. For example, the distance between the edge of the first portion 11 and the adjacent side is 20 μm, 22 μm, 24 μm, 25 μm, 50 μm, 70 μm, 100 μm, etc.

[0071] like Figure 5 As shown, in some embodiments, a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form a stacked portion 15, that is, a portion of the second portion 12 extends to the upper side of the second semiconductor layer 2, and the portion of the second portion 12 located on the side of the second semiconductor layer 2 opposite to the semiconductor substrate 6 constitutes the stacked portion 15. Along the second direction, the second portion 12 extends from the edge of the first portion 11 to the stacked portion 15. Specifically, the second portion 12 extends from the edge of the first portion 11 to... Figure 5 Within region S1, the end of the second portion 12 facing away from the first portion 11 contacts the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6. Since the current transmission capability of the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is stronger than that of the adjacent side, in this technical solution, extending the second portion 12 from the edge of the first portion 11 to the stacked portion 15 increases the current transmission capability between the second portion 12 and the second semiconductor layer 2. When the solar cell is shaded, current can form a leakage path through the second portion 12 and the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6. This leakage path has a stronger current transmission capability, further reducing the risk of hot spots.

[0072] In some embodiments, the width of the second portion 12 along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. For example... Figure 5 As shown, along the second direction, the extension distance of the second portion 12 is less than or equal to 500 μm and greater than or equal to 20 μm. With this setting, if the width of the second portion 12 is too large, for example, greater than 500 μm, it will significantly obstruct the second semiconductor layer 2, failing to form an effective current collection area for the second semiconductor layer 2, and the leakage channel will be too large, resulting in significant battery efficiency loss. If the width of the second portion 12 is too small, for example, less than 20 μm, it will be difficult to control the crystallization process, such as laser processing, potentially affecting other parts (e.g., the second semiconductor layer 2) and causing damage. For example, the width of the second portion 12 along the second direction can be 100 μm, 90 μm, 80 μm, etc. Preferably, the width of the second portion 12 along the second direction is greater than or equal to 100 μm and less than or equal to 400 μm. This design allows the second portion 12 to at least partially contact the second semiconductor layer 2 to form a leakage channel, while avoiding excessive overlap with the second semiconductor layer 2, which would reduce the current collection area of ​​the second semiconductor layer 2.

[0073] like Figure 3 and Figure 4 As shown, in some possible implementations, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, with the projection of the first portion 11 onto the semiconductor substrate 6 completely within the projection of the first transparent conductive layer 71 onto the semiconductor substrate 6. This configuration, by providing the first transparent conductive layer 71, improves the carrier transport capability of the first semiconductor layer 100, enabling good ohmic contact with the electrodes and improving conductivity. The first portion 11, having a crystalline structure, does not extend beyond the boundary of the first transparent conductive layer 71, thereby reducing contact resistance within the effective conductive area of ​​the first transparent conductive layer 71, improving conductivity, and increasing cell efficiency.

[0074] like Figure 5 As shown, further, in the above technical solution, along the second direction, the first transparent conductive layer 71 extends to the adjacent side or extends to the second portion 12 located above the second semiconductor layer 2. Specifically, along the second direction, the first transparent conductive layer 71 can extend to, for example... Figure 5 Within region S2, or, the first transparent conductive layer 71 may extend to, as shown in the image. Figure 5 Within the S1 region. This configuration allows the first transparent conductive layer 71 to cover a larger area of ​​the first semiconductor layer 100, further improving conductivity.

[0075] like Figures 3-4As shown, in some embodiments, the solar cell further includes a second transparent conductive layer 72, which covers the second semiconductor layer 2; a PN isolation region 10 is provided between the second transparent conductive layer 72 and the first transparent conductive layer 71, and the PN isolation region 10 is located on the second semiconductor layer 2. With the above technical solution, electrical insulation between the P-region and the N-region is achieved through the PN isolation region 10. The projection of the first portion 11 is located within the boundary of the first transparent conductive layer 71; therefore, the first portion 11 will not enter the boundary of the PN isolation region 10, and the irradiation range of the laser will not enter the PN isolation region 10. Since the PN isolation region 10 does not have a crystalline structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region 10 is guaranteed.

[0076] like Figures 3-4 As shown, the solar cell may further include a third transparent conductive layer 73, which covers the second portion 12. In this embodiment, a first transparent conductive layer 71 covers the first portion 11, and an edge isolation region 3 is provided between the first transparent conductive layer 71 and the third transparent conductive layer 73.

[0077] like Figures 5-7 As shown, the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 can be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layers can be single-layer thin films or multilayer thin films.

[0078] For example, such as Figure 5 As shown, a portion of the second part 12 is disposed on the second semiconductor layer 2 to form a stacked portion 15, and a PN isolation region 10 is disposed on the stacked portion 15. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polysilicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form the stacked portion 15. In this case, the PN isolation region 10 spans across the stacked portion 15. The width of the stacked portion 15 needs to be reasonably set, for example, it can be in the range of 100-300 μm, so as to achieve the balance between leakage channel and current collection as described above. The width of the second part 12 directly affects the width of the stacked portion 15. Since the first part 11 has a certain distance from the adjacent side of the second semiconductor layer 2, the width of the stacked portion 15 should be in the range of 100-300 μm.

[0079] In some embodiments, when the first side of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, i.e., when the solar cell is a back-contact cell, the second semiconductor layer 2 may include amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon. The second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, except that the conductivity type is different. That is, the second semiconductor layer 2 also has a first portion 11 and a second portion 12 that are adjacent to each other along the second direction. The first portion 11 of the second semiconductor layer 2 may be entirely laser-crystallized, or it may not be entirely laser-crystallized. Referring to the description of the first portion 11 of the first semiconductor layer 100 above, it will not be repeated here.

[0080] For example, taking the first semiconductor layer 100 corresponding to the P-region and the second semiconductor layer 2 corresponding to the N-region as an example, the first semiconductor layer 100 may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked together, and the second semiconductor layer 2 may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked together. Both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are disposed close to the semiconductor substrate 6. Of course, the conductivity types of the first semiconductor layer 100 and the second semiconductor layer 2 can be interchanged, which will not be elaborated further.

[0081] With this configuration, for the first semiconductor layer 100 and the second semiconductor layer 2, which have different conductivity types, disposed on the first side, both the first semiconductor layer 100 and the second semiconductor layer 2 can form heterojunction structures, forming a heterojunction back contact battery with both P-region and N-region heterojunction structures on the back side. This has the advantages of heterojunction structures, such as good passivation effect, high conversion efficiency, long service life, and low manufacturing energy consumption. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the heterojunction back contact battery can also be applied to the battery structure in this application where the edges are amorphous and the middle region is crystalline, in order to improve battery efficiency.

[0082] like Figures 1-6 As shown, in some embodiments, when the first side of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back contact cell, the second semiconductor layer 2 can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed. The second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.

[0083] For example, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface. The tunneling oxide layer 21 is disposed close to the semiconductor substrate 6. Taking the second semiconductor layer 2 corresponding to the N-region and the first semiconductor layer 100 corresponding to the P-region as an example, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22. The first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface. The intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P-region and the first semiconductor layer 100 corresponds to the N-region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0084] This configuration, by setting a second semiconductor layer 2 and a first semiconductor layer 100 with different conductivity types on the first surface, forms a hybrid back contact battery with both a tunneling passivation contact structure and a heterojunction structure on the back side. The first semiconductor layer 100 is a heterojunction structure. This battery combines the advantages of high conversion efficiency, good stability, and low Auger recombination of the tunneling passivation contact structure with the advantages of good passivation effect, high conversion efficiency, long lifespan, and low fabrication energy consumption of the heterojunction structure. As long as an amorphous silicon layer and / or a nanocrystalline silicon layer is present, the hybrid back contact battery can also be applied to the battery structure in this application where the edges are amorphous and the central region is crystalline, to improve battery efficiency. Of course, when the second semiconductor layer 2 is made of other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, back contact batteries with different structures in the P-region and N-region can be formed.

[0085] In other embodiments, the solar cell further includes a third semiconductor layer disposed on the second surface. The material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, and the conductivity type of the third semiconductor layer is different from that of the first semiconductor layer 100. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer can also form a heterojunction structure. The structure of the third semiconductor layer can be similar to that of the first semiconductor layer 100, also having a first portion 11 and a second portion 12, wherein the crystallinity of the first portion 11 is greater than that of the second portion 12.

[0086] In one example, assuming the first semiconductor layer 100 has a P-type conductivity and the third semiconductor layer has an N-type conductivity, the first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer positioned close to the first surface. The third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, with the third intrinsic amorphous silicon layer positioned close to the second surface, forming a bifacial heterojunction solar cell. Of course, the first semiconductor layer 100 can also have an N-type conductivity and the third semiconductor layer can have a P-type conductivity, which will not be elaborated further.

[0087] In another example, a polycrystalline silicon layer is disposed on the second surface. The third semiconductor layer can then form a tunneling passivation contact structure. Specifically, the first semiconductor layer 100 has a P-type conductivity, and the third semiconductor layer has an N-type conductivity. The first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface. The first intrinsic amorphous silicon layer is disposed close to the first surface. The third semiconductor layer includes an N-type doped polycrystalline silicon layer disposed on the second surface. A tunneling oxide layer is also disposed between the N-type doped polycrystalline silicon layer and the second surface. The tunneling oxide layer and the N-type doped polycrystalline silicon layer constitute a tunneling passivation contact structure. The third semiconductor layer can be partially disposed on the second surface, for example, it can be arranged in multiple strips, forming a poly-finger structure. Doped field regions can be selectively formed on the substrate between the poly-fingers. Alternatively, the third semiconductor layer can be formed entirely on the second surface, with a thicker portion in the metallized contact area and a thinner portion in the non-metallized area. The first semiconductor layer 100 can be a heterojunction structure, thus forming a bifacial hybrid solar cell. Of course, the conductivity type of the first semiconductor layer 100 can also be N-type, and the conductivity type of the third semiconductor layer can be P-type, which will not be elaborated further.

[0088] Bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to cell structures in this application where the degree of crystallization in the first part 11 is greater than that in the second part 12, as long as they have an amorphous silicon layer, a nanocrystalline silicon layer, and / or a microcrystalline silicon layer, in order to improve cell efficiency.

[0089] In some possible implementations, such as Figure 1 As shown, the first portion 11 extends along the first direction to the edge of the first surface. That is, along the first direction, both ends of the first portion 11 extend to the edge of the first surface of the semiconductor substrate 6. This maximizes the area of ​​the first portion 11, reduces contact resistance, and improves current collection capability. It should be noted that because the portion of the first semiconductor layer 100 near the edge of the semiconductor substrate 6 has large defects, poor passivation effect, large leakage current, and severe recombination, the portion of the first portion 11 near the edge of the first surface of the semiconductor substrate 6 may not be used as a current collection area.

[0090] In some other possible implementations, such as Figure 2 As shown, the second part 12 can surround the first part 11. Specifically, regardless of whether it is along the first direction or the second direction, the second part 12 is provided on both sides of the first part 11, and the second part 12 completely surrounds the first part 11. With this arrangement, the crystallinity of the second part 12 surrounding the first part 11 is relatively low, which can further reduce the risk of leakage and ensure the photoelectric conversion efficiency of the solar cell.

[0091] In the above technical solution, the first part 11 is rectangular and the second part 12 is annular. That is, the first part 11 located in the middle region is rectangular, and the second part 12 located in the edge region is annular. The first semiconductor layer 100 can cover the entire first surface in a continuous, one-sided structure. In this case, the first semiconductor layer 100 can form one side of a bifacial solar cell, which can be a P-region or an N-region. Since the first semiconductor layer 100 includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer 100 can form a heterojunction structure.

[0092] In the above technical solution, along the direction from the first part 11 to the second part 12 and perpendicular to the side length of the semiconductor substrate 6, the width of the second part is 0.3mm to 12mm. That is, a 0.3mm to 12mm edge area is reserved around the first part 11 without laser crystallization treatment. If the width of the second part 12 is too wide, the area of ​​the first part 11 with the crystallized structure of the entire solar cell will be small, resulting in a smaller reduction in series resistance and a larger loss during current collection. If the width of the second part 12 is too small, on the one hand, the edge of the first semiconductor layer 100 is thinner due to the limitations of the coating process; on the other hand, the angle of laser irradiation at the edge of the solar cell will be larger, causing a deviation in the energy distribution within the laser spot, which may result in some areas having excessively high laser energy density and damaging the passivation of the first semiconductor layer 100 at the edge. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the width of the second part 12 is selected to be 0.3mm to 12mm.

[0093] Furthermore, the width of the second portion 12 is 0.3mm to 3mm. This further increases the area of ​​the first portion 11 of the first semiconductor layer 100, reduces contact resistance, and improves battery efficiency. Specifically, the width of the second portion 12 can be 0.3mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, etc.

[0094] For example, for a first semiconductor layer 100 including a plurality of first strip portions 1, the extension length of the second portion 12 at both ends of the first strip portion 1 along the extension direction (first direction) of the first strip portion 1 is 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (second direction) of the plurality of first strip portions 1, the crystallization degree of the two first strip portions 1 near the two side edges of the first surface is the same as the crystallization degree of the second portion 12.

[0095] Optionally, the material of the first part 11 includes at least one of amorphous silicon and nanocrystalline silicon. That is, the first part 11 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon. After laser crystallization, the degree of crystallization can be improved. For example, when the first semiconductor layer 100 is an amorphous silicon layer, in the laser-crystallized portion, some of the amorphous silicon layer will crystallize to form nanocrystals. When the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystals, the crystallinity or degree of crystallization of the first semiconductor layer 100 in the laser-crystallized portion will increase.

[0096] The material of the second part 12 can be amorphous silicon to give the second part 12 a better passivation effect. By setting reasonable crystalline and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0097] In some embodiments, when the first semiconductor layer 100 includes a plurality of first strip-shaped portions 1 extending along a first direction, and the second semiconductor layer 2 includes a plurality of second strip-shaped portions extending along the first direction, the crystallization degree of at least one first strip-shaped portion 1 near the edge of the first surface is the same as the crystallization degree of the second portion 12 along the second direction. With this configuration, for the strip-shaped first strip-shaped portions 1, the plurality of first strip-shaped portions 1 are arranged along the second direction, and in this arrangement direction, the entire area of ​​at least one first strip-shaped portion 1 near the edge of the first surface has the same crystallization degree as the second portion 12. That is, at least one first strip-shaped portion 1 near the edge is not subjected to laser crystallization processing, while the remaining first strip-shaped portions 1 only form amorphous second portions 12 at their two side edges in the second direction, thus realizing the setting of an amorphous structure at both side edges of the first semiconductor layer 100.

[0098] For example, in the second direction, the crystallization degree of the entire area of ​​the two strip portions located on the two edges of the first surface is the same as the crystallization degree of the second part 12, or near the edge of each first surface, two or three equal numbers of the first strip portions 1 are reserved with the same crystallization degree as the second part 12.

[0099] like Figure 5 and Figure 6As shown, in some possible implementations, the semiconductor substrate 6 includes a recessed portion on a first surface, the recessed portion including sidewalls and a bottom wall, the recessed portion being recessed relative to the remainder of the first surface toward a second surface, and a first portion 11 being located within the recessed portion. This configuration, where the recessed portion is formed by etching to the surface of the semiconductor substrate 6, typically has a textured structure. Providing the first portion 11, which is made of amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon, within the recessed portion increases the contact area of ​​the first portion 11, facilitating current collection.

[0100] In some embodiments, the side of the semiconductor substrate 6 with the amorphous semiconductor layer has a textured structure. The amorphous semiconductor layer conforms to the textured structure, which has a light-trapping effect, increasing light collection and enabling better contact with the electrode. During laser crystallization of the first portion 11 of the first semiconductor layer 100, laser light irradiates the textured structure of the first portion 11, reaching the crystallization temperature and causing a localized area of ​​the first portion 11 to form a crystalline microcrystalline or nanocrystalline structure. Thus, the crystallized region possesses both an amorphous and crystalline structure. While the crystalline structure reduces contact resistance, it also reduces passivation, potentially increasing recombination and negatively impacting photoelectric efficiency. Therefore, by forming a crystalline structure in a localized area of ​​the textured structure, the factors of contact resistance and passivation can be balanced, optimizing battery efficiency.

[0101] like Figure 19 As shown, in this embodiment, EL (Electroluminescent) testing of the solar cell is a method for detecting internal defects in the solar cell. In the image obtained from the EL test, the brightness of the first part 11, which has a relatively high degree of crystallinity, is greater than the brightness of the second part 12, which has a relatively low degree of crystallinity. Under the same conditions, the EL test on the solar cell shows that the brightness of the first part 11 is greater than that of the second part 12, indicating that the contact resistance of the first part 11 is smaller than that of the second part 12. When the solar cell is energized for testing, the electroluminescence brightness of the first part 11, with its lower contact resistance, is greater, while the electroluminescence brightness of the second part 12 is lower. Figure 19 The image of solar cell B shows that the brightness of the first part 11 is greater than that of the second part 12. Comparing it with the image of solar cell C reveals that the brightness of solar cell C is uniform across its entire surface, and its overall brightness is lower than that of solar cell B, indicating that solar cell C has a higher overall contact resistance.

[0102] In some possible implementations, the solar cell further includes a first grid electrode 4 extending along a first direction, the first grid electrode 4 being conductively disposed on a first portion 11 of the first semiconductor layer 100. The extension direction of the first grid electrode 4 is consistent with the extension direction of the first strip portion 1, and it can collect both the charge carriers of the first portion 11 and a portion of the second portion 12 on the same first semiconductor layer 100, thus improving the charge carrier collection capability of the first grid electrode 4 for the first semiconductor layer 100.

[0103] For a solar cell having a second semiconductor layer 2, the solar cell further includes a second grid electrode 5 conductively disposed on the second semiconductor layer 2, the extension direction of the second grid electrode 5 being along a first direction and consistent with the extension direction of the second semiconductor layer 2. In the case of having a first transparent conductive layer 71 and a second transparent conductive layer 72, the first grid electrode 4 is disposed on the first transparent conductive layer 71, and the second grid electrode 5 is disposed on the second transparent conductive layer 72.

[0104] Furthermore, in this embodiment, along the second direction, the ratio of the width of the first gate electrode 4 to the width of the first portion 11 is 10% to 120%, specifically 10%, 30%, 50%, 80%, 100%, 120%, etc. The ratio of the width of the first gate electrode 4 to the width of the middle portion is selected based on the material and carrier transport capability of the first semiconductor layer 100. If the carrier transport capability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion is increased to increase the contact area between the first gate electrode 4 and the middle portion, reducing the contact resistance. Conversely, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be decreased to save electrode material while meeting current collection requirements.

[0105] For example, the width of the first gate electrode 4 can be 30 μm to 600 μm: specifically, when the first gate electrode 4 is prepared by screen printing, the width of the first gate electrode 4 is 30 μm to 80 μm; when the first gate electrode 4 is prepared by deposition methods such as electroplating, the width of the first gate electrode 4 is 100 μm to 600 μm. The width of the middle portion is 200 μm to 700 μm. A suitable width of the first gate electrode 4 is selected based on the width of the middle portion and the electrode preparation process.

[0106] Furthermore, in the case where the solar cell includes a first transparent conductive layer 71, the first grid electrode 4 extends along a first direction and is disposed on the first transparent conductive layer 71; along a second direction, the width of the first grid electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion. For example, the width of the first transparent conductive layer 71 is 120 μm to 800 μm, the width of the first portion 11 is 200 μm to 700 μm, and the ratio of the width of the first transparent conductive layer 71 to the width of the first portion 11 is 1.2 to 1.5. A suitable width of the first transparent conductive layer 71 is selected based on the width of the first portion 11, and a suitable width of the first grid electrode 4 is selected based on the width of the first portion 11, the width of the first transparent conductive layer 71, and the electrode fabrication process. With this configuration, the first grid electrode 4 can be disposed directly opposite the first portion 11, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion, thereby improving current collection capability.

[0107] Based on the solar cells described in any of the above embodiments, this invention also provides a photovoltaic module, including the solar cells described in any of the above embodiments.

[0108] Since the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the solar cell described above, and will not be described in detail here.

[0109] This invention also provides a method for manufacturing a solar cell, which can prepare such a solar cell. Figures 1-6 The solar cell described in any of the above embodiments, and the method for manufacturing the solar cell includes the following steps:

[0110] Step S100: A semiconductor substrate 6 is provided, the semiconductor substrate 6 having a first side and a second side opposite to each other.

[0111] Step S200: A first semiconductor layer 100 is formed on the first surface, the first semiconductor layer 100 including at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0112] In step S300, a laser is used to irradiate the first portion 11 of the first semiconductor layer 100, while the second portion 12 of the first semiconductor layer 100 is not irradiated, such that the crystallization degree of the first portion 11 is greater than that of the second portion 12; the first portion 11 and the second portion 12 are adjacent to each other along the second direction.

[0113] In the above technical solution, a laser is used to crystallize the region corresponding to the first portion 11 of the first semiconductor layer 100, thereby increasing the degree of crystallization. The region corresponding to the second portion 12 of the first semiconductor layer 100, adjacent to the first portion 11, is not irradiated with a laser, retaining its amorphous structure. (It should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon in the second portion 12 remains unchanged.) This results in the overall degree of crystallization of the first portion 11 of the first semiconductor layer 100 being greater than the overall degree of crystallization of the second portion 12. It is understandable that, all other things being equal, the lower the degree of crystallization of the semiconductor layer, the smaller the grains in the semiconductor layer, even exhibiting the disordered nature of amorphous silicon material. The smaller the grains in the semiconductor layer, the more interfaces between the grains, resulting in a higher resistance at the grain interfaces. Therefore, the crystallization structure in the first portion 11 of the first semiconductor layer 100 reduces the contact resistance and the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby reducing the transport loss of charge carriers collected in the first semiconductor layer 100 to the conductive material. Simultaneously, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor layer, and the lower degree of crystallization of the second portion 12 ensures the passivation effect of the second portion 12 and prevents leakage between the second portion 12 and the second semiconductor layer 2. As can be seen from the above, by setting reasonable crystallized and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized by utilizing the higher degree of crystallization of the first part 11, thereby improving the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 ensures the passivation effect of the second part 12 and prevents leakage.

[0114] Furthermore, before irradiating the first part 11 with a laser, the following steps are also included:

[0115] In step S201, a second semiconductor layer 2 is formed on the first surface. The first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the second semiconductor layer 2 has an adjacent side close to the first semiconductor layer 100. Compared with the first portion 11, the second portion 12 is closer to the second semiconductor layer 2.

[0116] In this embodiment, the solar cell is a back-contact solar cell, with both the first semiconductor layer 100 and the second semiconductor layer 2 disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 disposed adjacent to each other along the second direction. Figures 4-5 As shown, the second semiconductor layer 2 has an adjacent side close to the first semiconductor layer 100, and the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. In order to realize the arrangement of P-regions and N-regions on the first surface, the first semiconductor layer 100 is one of P-regions and N-regions, and the second semiconductor layer 2 is the other of P-regions and N-regions.

[0117] Using the above technical solution, for back-contact solar cells, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2. The crystallinity of the second part 12 is smaller to ensure the passivation effect of the second part 12, prevent leakage between the second part 12 and the second semiconductor layer 2, and reduce the photoelectric conversion efficiency of the solar cell.

[0118] In some possible implementations, the first semiconductor layer 100 includes an amorphous silicon layer. After the middle portion is irradiated with a laser, a portion of the amorphous silicon layer crystallizes to form nanocrystals. Since the first semiconductor layer 100 uses an amorphous silicon layer, the portion not irradiated by the laser has a better passivation effect, and the insulation effect in the PN isolation region 10 is also better.

[0119] Furthermore, if the first portion 11 extends along the first direction and has a strip-like shape, then step S300, which involves irradiating the first portion 11 with a laser, specifically includes the following steps:

[0120] In step S301, the laser irradiates the first part 11 along the first direction, and along the second direction, the starting or ending position of the laser has a first distance from the adjacent side.

[0121] When the above technical solution is adopted, the second part 12 extends from the edge of the first part 11 to, as shown in the figure Figure 5 Within region S3, the first distance is the width of region S3 along the second direction, meaning there is a certain distance between the end of the second part 12 away from the first part 11 and the adjacent side. The second part 12 does not contact the second semiconductor layer 2, and the distance between the second part 12 and the second semiconductor layer 2 is relatively large, which helps to further reduce the leakage current risk between the second part 12 and the second semiconductor layer 2.

[0122] Furthermore, along the first direction, the starting or ending position of the laser is at a second distance from the boundary of the first semiconductor layer 100. Specifically, the second distance is the extension distance of the second portion 12 along the first direction. The second distance prevents the first semiconductor layer 100 from being irradiated by laser at both ends along the first direction, thus preserving its amorphous structure. Due to the non-uniformity of the laser beam across its entire width and the non-uniformity of the thickness of the first semiconductor layer 100, when the laser acts on the edge portion of the first semiconductor layer 100, it will damage the passivation of the edge portion, thereby increasing the recombination at the edge portion. Therefore, this application does not form a crystalline structure at both ends of the first semiconductor layer 100 by laser, but retains the amorphous structure at both ends of the first semiconductor layer 100, thereby ensuring the passivation effect at the edge portion and reducing the recombination at the edge portion.

[0123] In the above embodiments, the second distance is greater than the first distance, that is, the width of the second portion 12 along the first direction (the second portion immediately adjacent to the first portion along the second direction) is greater than the width of the second portion along the second direction. For example, the first distance is less than or equal to 500 μm, and the second distance is 0.3-12 mm.

[0124] In some embodiments, the wavelength of the laser is 325 nm to 532 nm, specifically, the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and / or, the energy density of the laser is 200 mJ / cm². 2 ~6000mJ / cm 2 Specifically, the energy density of the laser can be 200 mJ / cm². 2 500mJ / cm 2 1000mJ / cm 2 2000mJ / cm 2 3000mJ / cm 2 5000mJ / cm 2 6000mJ / cm 2 The laser pulse width can be on the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is beneficial for achieving crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the tip of the textured structure will be too high, thus affecting the passivation of the tip region of the textured structure. If the laser energy density is too low, the energy accumulation time will be too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, selecting a laser energy density within this range allows only the tip of the textured structure to reach a high temperature, achieving morphological changes and forming a crystalline structure.

[0125] like Figures 7-18As shown, this embodiment provides a specific fabrication process for a solar cell. Taking the fabrication of a hybrid back-contact cell with a tunneling passivation contact structure and a heterojunction structure on the back side as an example, the fabrication process of this back-contact cell is as follows:

[0126] Step 1: As Figure 7 As shown, the silicon wafer is polished and cleaned. Specifically, the silicon wafer is put into a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer. The polishing morphology of both sides is controlled by controlling the temperature, time and chemical concentration. The resulting silicon wafer is used as a semiconductor substrate 6. The semiconductor substrate 6 can be an n-type, p-type or intrinsic silicon substrate.

[0127] Step 2: As Figure 8 As shown, a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the back surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 can be formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition. Alternatively, the tunneling oxide layer 21 can be generated by a high-temperature reaction between oxygen and the semiconductor substrate 6, or by a wet chemical method, such as the reaction of silicon with ozone or the oxidation reaction of silicon with nitric acid. The thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, optionally 1.4 nm, and the thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, optionally 120 nm.

[0128] Step 3: As Figure 9 As shown, the intrinsic polycrystalline silicon layer 23 is doped to form an n-type doped polycrystalline silicon layer 22 by high-temperature diffusion, and a phosphorus-containing oxide layer, namely a phosphorus silicon glass layer 24, is generated. The doping concentration of the n-type doped polycrystalline silicon layer 22 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0129] Step 4: As Figure 10 As shown, the phosphorus silicate glass layer 24 formed after phosphorus diffusion is removed by HF solution.

[0130] Step 5: As Figure 11 As shown, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. The silicon nitride mask layer 25 serves two purposes: firstly, it acts as a hydrogen source to provide hydrogen atoms at the interface between the crystalline silicon and the tunneling oxide layer 21, passivating dangling bonds, and also passivating some defects within the crystalline silicon. Secondly, it acts as a mask to protect the N-region film layer during subsequent P-region patterning.

[0131] Step 6: As Figure 12As shown, the P-region is patterned using laser technology. The laser ablates all P-region film layers down to the semiconductor substrate 6. The laser can be a 532nm laser, and the pulse width can be either nanosecond or picosecond. Optionally, a 532 picosecond laser is used.

[0132] Step 7: As Figure 13 As shown, the exposed semiconductor substrate 6 in the P-region is texturized using a wet etching process to obtain a textured structure, such as a pyramid structure. Then, the silicon nitride mask layer 25 is removed. The wet etching process serves two purposes: first, it removes the damaged layer from the laser-treated semiconductor substrate 6 in the P-region, performing interface cleaning; second, it removes the silicon nitride mask layer 25 deposited in the N-region.

[0133] Step 8: As Figure 14 As shown, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the back surface of the entire semiconductor substrate 6 to form a p-region emitter. The thickness of the intrinsic amorphous silicon layer 13 is 2 nm to 20 nm, optionally 8 nm; the thickness of the p-type amorphous silicon layer 14 is 5 nm to 50 nm, optionally 15 nm. Simultaneously, a passivation layer 8 and an antireflection layer 9 are sequentially deposited on the front surface of the semiconductor substrate 6. The antireflection layer 9 is one or more of silicon nitride, silicon oxide, and silicon oxynitride layers, and the passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0134] Step 9: As Figure 15 As shown, a laser process is used to pattern the N-region, removing the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polycrystalline silicon layer 22, exposing the n-type doped polycrystalline silicon layer 22. An oxide layer is formed on the n-type doped polycrystalline silicon layer 22, which is subsequently removed by a wet etching process. The laser can be a 355nm or 532nm laser, with pulse widths selectable in the nanosecond or picosecond range; optionally, a 532 picosecond laser is used. The wet etching process can employ a chain-type equipment, with the semi-finished product facing upwards and protected by a water film. The back side contacts an HF solution to remove the oxide layer and the silicon nitride deposited around it.

[0135] Step 10: As Figure 15As shown, a laser process is used to irradiate the region corresponding to the first part 11 of the p-type amorphous silicon layer 14 in the P-region, causing the p-type amorphous silicon layer 14 to form a first part 1111 with a crystalline structure. The edge of the p-type amorphous silicon layer 14 along the second direction is not irradiated by the laser, retaining its original amorphous structure and forming the second part 12. The laser can be a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser; optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves along the extension direction of the p-type amorphous silicon layer 14 for irradiation. It should be noted that the laser processes in steps nine and ten can be performed in the same step, without any order. To save laser processing time, the crystallization process is performed after the P-region patterning is completed by laser irradiation.

[0136] Step 11: As Figure 16 As shown, a transparent conductive layer 7 is deposited on the back surface of the semiconductor substrate 6. This layer can be one or more of the following: fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide, either in a stacked or monolayer configuration. Optionally, an indium tin oxide film layer can be used.

[0137] Step 12: As Figure 17 As shown, the transparent conductive layer 7 on the N-region and P-region is disconnected to form a PN isolation region 10. This allows the transparent conductive layer 7 to form a first transparent conductive layer 71 on the P-region and a second transparent conductive layer 72 on the N-region, achieving insulation between the P-region and the N-region. The transparent conductive layer 7 is disconnected near the edge of the semiconductor substrate 6 in the N-region and P-region, forming a third transparent conductive layer 73 on the edge. The PN isolation region 10 located between the P-region and the N-region spans the overlapping region between the N-region and the P-region, as well as part of the P-region, to achieve better insulation.

[0138] Step 13: As Figure 18 As shown, a first gate electrode 4 and a second gate electrode 5 are deposited and formed on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively, wherein the two ends of the first gate electrode 4 extend to the following... Figure 1 The second part 12 on both sides shown. The materials of the first gate electrode 4 and the second gate electrode 5 can be one or more combinations of silver, copper, and aluminum.

[0139] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solar cell, characterized by, The solar cell comprises: a semiconductor substrate having opposite first and second faces; a first semiconductor layer disposed on the first face, the first semiconductor layer having an N-type or P-type conductivity, the first semiconductor layer comprising a first portion and a second portion adjacent to the first portion along a second direction, the first portion having a higher degree of crystallization than the second portion, the first semiconductor layer comprising at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; a second semiconductor layer disposed on the first face, the first semiconductor layer and the second semiconductor layer being arranged adjacent to each other along the second direction, the first semiconductor layer and the second semiconductor layer having different conductivities; and the second portion being closer to the second semiconductor layer than the first portion along the second direction; the second semiconductor layer has an adjacent side surface close to the first semiconductor layer; wherein, along the second direction, the second portion extends from an edge of the first portion to close to the adjacent side surface but does not contact the adjacent side surface, or the second portion extends from the edge of the first portion to the adjacent side surface and contacts the adjacent side surface; along the second direction, the edge of the first portion is greater than or equal to 20 μm away from the adjacent side surface; a width of the second portion along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm.

2. The solar cell according to claim 1, characterized in that, a part of the second portion is disposed on the second semiconductor layer to form a superposed portion, and along the second direction, the second portion extends from the first portion to the superposed portion.

3. The solar cell according to claim 1, characterized in that, The solar cell further comprises a first transparent conductive layer covering the first semiconductor layer, a projection of the first portion on the semiconductor substrate is entirely within a projection of the first transparent conductive layer on the semiconductor substrate.

4. The solar cell according to claim 3, characterized in that, along the second direction, the first transparent conductive layer extends to the adjacent side surface or to the second portion above the second semiconductor layer.

5. The solar cell according to claim 3, wherein The solar cell further comprises a second transparent conductive layer covering the second semiconductor layer; the second transparent conductive layer and the first transparent conductive layer have a PN isolation region therebetween, the PN isolation region being on the second semiconductor layer.

6. The solar cell according to claim 5, characterized in that, a part of the second portion is disposed on the second semiconductor layer to form a superposed portion, and the PN isolation region is disposed on the superposed portion.

7. The solar cell of claim 1, wherein The solar cell further comprises a third semiconductor layer disposed on the second face, a material of the third semiconductor layer comprising at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, the third semiconductor layer having a different conductivity from the first semiconductor layer.

8. The solar cell of claim 1, wherein, The first portion and the second portion both extend in a first direction in a strip shape, the first direction and the second direction intersecting each other.

9. The solar cell of claim 1, wherein, The first portion has a lower contact resistance than the second portion.

10. The solar cell of claim 1, wherein, The first portion extends to an edge of the first face along the first direction.

11. The solar cell of claim 1, wherein, The second portion surrounds the first portion.

12. The solar cell of claim 1, wherein, The first portion comprises amorphous silicon and nanocrystalline silicon, and the second portion comprises amorphous silicon.

13. The solar cell of claim 1, wherein, The semiconductor substrate includes a recessed portion on the first surface, the recessed portion is recessed toward the second surface relative to the rest of the first surface, and the first portion is located within the recessed portion.

14. A photovoltaic module comprising a solar cell, characterized in that, The solar cell is the solar cell according to any one of claims 1-13.

15. A method of fabricating a solar cell as described in claim 1, wherein, Comprising: Providing a semiconductor substrate having opposite first and second surfaces; Forming a first semiconductor layer on the first surface, the first semiconductor layer having an N-type or P-type conductivity, and the first semiconductor layer including at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; Irradiating a first portion of the first semiconductor layer with a laser and not irradiating a second portion of the first semiconductor layer, so that the first portion has a higher degree of crystallization than the second portion; The first portion and the second portion are adjacent along a second direction.

16. The method of producing a solar cell according to claim 15, wherein The first semiconductor layer is an amorphous silicon layer, and after irradiating the first portion with the laser, a portion of the amorphous silicon layer is partially crystallized to form nanocrystalline grains.

17. The method of producing a solar cell according to claim 15, wherein Before irradiating the first portion with the laser, the method further includes forming a second semiconductor layer on the first surface, the first semiconductor layer and the second semiconductor layer being arranged adjacent along a second direction, the first semiconductor layer and the second semiconductor layer having different conductivities, and the second semiconductor layer having an adjacent side surface close to the first semiconductor layer, and the second portion is closer to the second semiconductor layer than the first portion.

18. The method of producing a solar cell according to claim 17, wherein The first portion extends along a first direction and has a strip shape, and irradiating the first portion with the laser includes: the laser irradiating the first portion along the first direction, and along the second direction, a starting or ending position of the laser has a first distance from the adjacent side surface.

19. The method of producing a solar cell according to claim 18, wherein Along the first direction, a starting or ending position of the laser has a second distance from a boundary of the first semiconductor layer.

20. The method of producing a solar cell according to claim 19, wherein The second distance is greater than the first distance.

21. The method of producing a solar cell according to claim 15, wherein The wavelength of the laser is 325nm-532nm; and / or the energy density of the laser is 200 mJ / cm 2 6000 mJ / cm 2 .

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