Solar cells and photovoltaic modules

Abstract

The present application provides a solar cell and a photovoltaic module, belonging to the technical field of solar cells. The above-mentioned solar cell includes: a semiconductor substrate having opposite first and second surfaces, and a plurality of first side surfaces adjacent between the first and second surfaces; a passivated contact structure at least located on a part of the first surface of the semiconductor substrate, the passivated contact structure including an interface passivation layer and a first doped semiconductor layer stacked in sequence; wherein, in the direction from the first surface to the second surface, the first side surface includes a first region and a second region adjacent in sequence, and the first region protrudes in a direction away from the first side surface compared with the second region; the first doped semiconductor layer is also located on a part of the surface of the first region, and the first doped semiconductor layer located on the first region is integrally continuous with the first doped semiconductor layer located on the first surface; a part of the surface of the first region adjacent to the second region is not covered with the first doped semiconductor layer.

Description

Technical Field

[0001] At least one embodiment of the present application relates to a solar cell, and particularly to a solar cell and a photovoltaic module. Background Art

[0002] In related technologies, a solar cell includes an N-type region and a P-type region. A certain degree of electrical isolation is required between the N-type region and the P-type region. Generally, processes such as wet etching can be used to separate the N-type region and the P-type region, but the existing methods are not perfect, and there is still a risk of leakage between the front and back surfaces of the solar cell.

[0003] Meanwhile, during the production and handling process, the edges of the cells are extremely prone to rubbing against each other, resulting in the peeling or scratching of the passivation film layer, and the substrate is exposed on the outside. In this case, the surface passivation layer is damaged, which will lead to a weakening of the cell passivation performance, thus affecting the cell performance. Summary of the Invention

[0004] In view of this, it is necessary to provide a solar cell and a photovoltaic module formed by the solar cell to address the defects of solar cells in related technologies.

[0005] According to an embodiment of one aspect of the present application, a solar cell is provided, including:

[0006] A semiconductor substrate having opposite first and second surfaces, and a plurality of first side surfaces adjacent between the first and second surfaces;

[0007] A passivated contact structure at least on a part of the first surface of the semiconductor substrate, the passivated contact structure including an interface passivation layer and a first doped semiconductor layer stacked in sequence;

[0008] Wherein, in the direction from the first surface to the second surface, the first side surface includes a first region and a second region adjacent in sequence. The first region protrudes in a direction away from the first side surface compared to the second region; the first doped semiconductor layer is also located on a part of the surface of the first region, and the first doped semiconductor layer located on the first region is integrally continuous with the first doped semiconductor layer located on the first surface; a part of the surface of the first region adjacent to the second region is not covered with the first doped semiconductor layer.

[0009] According to an embodiment of another aspect of the present application, a photovoltaic module is provided, including the above-mentioned solar cell.

[0010] According to the solar cell provided in the above embodiments of the present application, in the direction parallel to the first surface, at least one first region of the first side surface protrudes in the direction away from the first side surface compared to the second region, which is beneficial to increasing the effective area of the passivation contact structure on the first surface, improving the passivation contact performance of the first surface, enhancing the carrier collection efficiency, and further improving the efficiency of the solar cell.

[0011] According to the solar cell provided in the above embodiments of the present application, in the direction parallel to the first surface, at least one first region of the first side surface protrudes in the direction away from the first side surface compared to the second region. Since there is a certain distance between the surface of the protruding part of the first region and the surface of the first side surface, the electrical isolation between the front and back surfaces of the battery (the spatial electrical isolation distance between the first surface and the second surface) can be enhanced, and the risk of leakage between the front and back surfaces can be reduced. At the same time, during the preparation of the electrode, it can also effectively prevent the paste used for preparing the electrode from leaking and spreading over a larger range on the side surface of the battery, causing serious losses to the electrical performance of the battery. Moreover, due to the protrusion of the first region, the damage to the performance of the solar cell caused by scratching can be reduced.

[0012] According to the solar cell provided in the above embodiments of the present application, the first doped semiconductor layer is also located on a part of the surface of the first region, which can increase the effective area of the passivation contact structure and improve the carrier collection efficiency while reducing the leakage risk. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application and do not limit the present application.

[0014] Figure 1 It is a schematic cross-sectional view of a solar cell in the related art;

[0015] Figure 2 It is a partial schematic cross-sectional view of a solar cell in the related art;

[0016] Figure 3 It is a top view schematic diagram of a semiconductor substrate provided by an embodiment of the present application;

[0017] Figure 4 It is a schematic cross-sectional view of a solar cell provided by an embodiment of the present application;

[0018] Figure 5 It is a partial schematic cross-sectional view of a solar cell provided by an embodiment of the present application;

[0019] Figure 6 It is a schematic cross-sectional view of a solar cell provided by another embodiment of the present application;

[0020] Figure 7 Schematic cross-sectional view of a solar cell provided by another embodiment of the present application;

[0021] Figure 8 Scanning electron microscope image of the first side of a solar cell provided by another embodiment of the present application;

[0022] Figure 9 Schematic partial cross-sectional view of a solar cell provided by yet another embodiment of the present application;

[0023] Figure 10 Scanning electron microscope image of the first side of a solar cell provided by yet another embodiment of the present application;

[0024] Figure 11 Schematic partial cross-sectional view of a solar cell provided by another embodiment of the present application;

[0025] Figure 12 Schematic cross-sectional view of a solar cell provided by yet another embodiment of the present application;

[0026] Figure 13 Schematic cross-sectional view of a back-contact solar cell provided by an embodiment of the present application; and

[0027] Figure 14 Top view schematic of the first surface of a back-contact solar cell provided by an embodiment of the present application.

[0028] Explanation of reference numerals:

[0029] 1 - Semiconductor substrate;

[0030] A - First surface;

[0031] B - Second surface;

[0032] C - First side;

[0033] C1 - First region;

[0034] C2 - Second region;

[0035] C3 - Third region;

[0036] 11 - First semiconductor substrate bottom;

[0037] 12 - Second semiconductor substrate bottom;

[0038] 13 - Third semiconductor substrate bottom;

[0039] d1 - Protrusion height of the first region;

[0040] d2 - Protrusion height of the third region;

[0041] 2 - Interface passivation layer;

[0042] 3 - First doped semiconductor layer;

[0043] 31 - Third doped semiconductor layer;

[0044] 32 - Fourth doped semiconductor layer;

[0045] 4 - First passivation and antireflection layer;

[0046] 5 - Second doped semiconductor layer;

[0047] 6 - Second passivation and antireflection layer;

[0048] 10 - First electrode;

[0049] 20 - Second electrode;

[0050] 111 - Heavily doped semiconductor substrate layer;

[0051] 100 - Minority carrier region;

[0052] 200 - Majority carrier region;

[0053] 300 - Isolation region. Detailed implementation manners

[0054] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the following further elaborates on the present application in detail with reference to specific embodiments and the accompanying drawings. However, the present application can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the application thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0055] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0056] In related technologies, for example, the patent CN202410605390.9 provides a TOPCon cell that improves the leakage risk of bifacial cells. A doped silicon layer with plating retention is provided on the side of the cell substrate. The surface of the area exposed outside the doped silicon layer in the side of the silicon substrate is etched by an etching solution to prevent the doped silicon layer from remaining on the surface of the area near the doped silicon layer in the side of the silicon substrate and prevent short circuits. In the side of the silicon substrate, the surface of the area not corresponding to the doped silicon layer can be lower than the surface of the area corresponding to the doped silicon layer to further reduce the leakage risk of doped silicon layers of different doping types.

[0057] Similar to the patent CN202410605390.9, such as Figures 1-2 , the solar cell includes: a semiconductor substrate 1 having opposite first surface A and second surface B, and a first side C; an interface passivation layer 2 and a first doped semiconductor layer 3 located on the first surface A of the semiconductor substrate 1; and a first passivation and antireflection layer 4; wherein, in the direction from the first surface A to the second surface B, the first side C of the semiconductor substrate includes adjacent first region C1 and second region C2, and the first region C1 protrudes in the direction away from the first side C compared to the second region C2.

[0058] Refer to Figure 2 As shown, the first doped semiconductor layer 3 extends from the first surface A of the semiconductor substrate 1 and entirely covers the first region C1. Although the above method suppresses the leakage to a certain extent, the height of the protrusion of the first region C1 relative to the second region C2 is limited, and if there is also a plating retention area of the doped silicon layer formed on the second surface B of the solar cell on the first side C, the leakage risk is still very high.

[0059] In view of this, it is necessary to provide a solar cell and a photovoltaic module to address the technical problems in related technologies, such as the leakage risk between the front and back sides of the solar cell, the side edges being easily contaminated by metal paste or scratched during handling, resulting in a reduction in cell performance.

[0060] Figure 3 It is a top view schematic diagram of the semiconductor substrate provided by an embodiment of the present application.

[0061] Figure 4 It is a cross-sectional schematic diagram of the solar cell provided by an embodiment of the present application.

[0062] According to an exemplary embodiment of the present application, the present application provides a solar cell. Refer to Figure 3 , Figure 4 As shown, it includes:

[0063] A semiconductor substrate 1 having opposite first and second surfaces A and B, and a plurality of first side surfaces C adjacent between the first surface A and the second surface B;

[0064] A passivation contact structure disposed at least on a portion of the first surface A of the semiconductor substrate 1, the passivation contact structure including an interface passivation layer 2 and a first doped semiconductor layer 3 stacked in sequence;

[0065] Wherein, in the direction from the first surface A to the second surface B, the first side surface C includes a first region C1 and a second region C2 adjacent in sequence, and the first region C1 protrudes in a direction away from the first side surface C compared to the second region C2; the first doped semiconductor layer 3 is also disposed on a portion of the surface of the first region C1, and the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; a portion of the surface of the first region C1 adjacent to the second region C2 is not covered with the first doped semiconductor layer 3.

[0066] That is to say, in the direction from the first surface A to the second surface B, the semiconductor substrate 1 includes a first semiconductor base portion 11 and a second semiconductor base portion 12 integrally formed with the first semiconductor base portion 11; the first side surface C includes a first region C1 on the side of the first semiconductor base portion 11 and a second region C2 on the side of the second semiconductor base portion 12, and the first region C1 of at least one first side surface C protrudes in a direction away from the first side surface C compared to the second region C2.

[0067] According to an embodiment of the present application, in a cross-section parallel to the first surface A, the area of the first semiconductor base portion 11 is larger than the area of the second semiconductor base portion 12.

[0068] According to an embodiment of the present application, the protrusion height d1 of the first region C1 compared to the second region C2 is 0.5 μm to 5 μm, and for example, it can be 0.5 μm, 1 μm, 2 μm, 5 μm, but is not limited to the recited values.

[0069] According to an embodiment of the present application, the semiconductor substrate 1 can be a silicon substrate. Alternatively, the above semiconductor substrate 1 can also be a substrate of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. In addition, the above semiconductor substrate 1 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The semiconductor substrate 1 can be single crystal or polycrystalline.

[0070] According to an embodiment of the present application, the shape of the semiconductor substrate 1 is rectangular, and there is a chamfer between adjacent sides of the rectangle. Refer to Figure 3 As shown, the semiconductor substrate 1 includes, for example, 8 first side surfaces C.

[0071] According to an embodiment of the present application, the passivated contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of a first region C1 of at least one first side surface C. The passivated contact structure does not completely cover the first region C1, which can reduce the short - circuit risk brought by the passivated contact structure. In addition, there is a step structure between the first region C1 and the second region C2. On the side wall of the step structure, that is, on the connecting side wall between the first region C1 and the second region C2, there may be a doped region of the substrate. The first doped semiconductor layer 3 is likely to contact the doped region on the step side wall, resulting in direct contact between the first doped semiconductor layer 3 and the semiconductor substrate 1, causing defects in the battery. Therefore, setting the first doped semiconductor layer 3 away from this side wall can avoid the occurrence of the above - mentioned situation.

[0072] According to an embodiment of the present application, in the direction from the first surface A to the second surface B, the distance between the first doped semiconductor layer 3 on the surface of the first region C1 and the second region C2 is greater than or equal to 1 μm.

[0073] According to an embodiment of the present application, in the direction perpendicular to the first surface A, the distribution width of the first doped semiconductor layer 3 in the first region A is less than 80% of the width of the first region A.

[0074] According to an embodiment of the present application, the ratio range of the width of the first region C1 in the direction perpendicular to the first surface A to the thickness of the semiconductor substrate 1 is 1% - 20%. For example, it can be 1%, 5%, 10%, 15%, 20%, but is not limited to the listed values. If the ratio range is too small, it is difficult to achieve the technical effects of increasing the area of the passivated contact structure and improving the carrier collection efficiency; if the ratio range is too large, there is a risk of leakage between the first surface A and the second surface B.

[0075] According to an embodiment of the present application, the thickness range of the first semiconductor base portion 11 in the direction perpendicular to the first surface A is 0.5 μm - 20 μm. For example, it can be 0.5 μm, 1 μm, 5 μm, 10 μm, 20 μm, but is not limited to the listed values; the thickness of the first semiconductor base portion 11 in the direction perpendicular to the first surface A is the width of the first region C1 in the direction from the first surface A to the second surface B.

[0076] According to an embodiment of the present application, in the direction parallel to the first surface A, the first region C1 of at least one first side surface C protrudes in the direction away from the first side surface C compared with the second region C2, which is beneficial to increasing the effective area of the passivated contact structure on the first surface A, improving the passivated contact performance of the first surface A, enhancing the carrier collection efficiency, and further improving the efficiency of the solar cell.

[0077] According to an embodiment of the present application, in a direction parallel to the first surface A, a first region C1 of at least one first side surface C protrudes in a direction away from the first side surface C compared to a second region C2. Since the surface of the protruding portion of the first region has a certain distance from the surface of the second region C2, the electrical isolation between the front and back surfaces of the battery can be enhanced, and the risk of leakage between the front and back surfaces can be reduced. At the same time, during the process of preparing the electrode, it can also effectively prevent the slurry used for preparing the electrode from leaking and spreading over a larger range on the side surface of the battery, causing serious loss to the electrical performance of the battery. Moreover, due to the protrusion of the first region C1, the damage to the performance of the solar cell caused by scratching of the solar cell can be reduced.

[0078] Since the doping concentration of the doped semiconductor layer is usually relatively high, leakage of the solar cell usually occurs between doped semiconductor layers of different doping types. When the width of the first region C1 in a direction perpendicular to the first surface A is very large, the first doped semiconductor layer 3 covering the first region C1 is likely to have leakage with the second doped semiconductor layer 5 located on the second surface B.

[0079] By setting the width of the first region C1 to 1% - 20% of the thickness of the semiconductor substrate, and the first doped semiconductor layer 3 is located on a partial surface of the first region C1, the risk of leakage between the first doped semiconductor layer 3 and the second surface B is reduced.

[0080] According to the solar cell provided by the above embodiment of the present application, the first doped semiconductor layer is located on a partial surface of the first region. While reducing the leakage risk, it can increase the effective area of the passivation contact structure and improve the collection efficiency of carriers.

[0081] According to an embodiment of the present application, the solar cell can be a bifacial solar cell, such as a tunneling oxide passivated contact solar cell (TOPCon), a heterojunction solar cell (HJT).

[0082] According to an embodiment of the present application, the interface passivation layer 2 includes one of an intrinsic amorphous silicon layer, a low-doped intrinsic amorphous silicon layer (with a doping concentration lower than that of the first doped semiconductor layer), and a dielectric layer. The dielectric layer includes, but is not limited to, silicon oxide, aluminum oxide, doped aluminum oxide, silicon nitride, and silicon carbonitride. The first doped semiconductor layer 3 is at least one of a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped amorphous silicon layer.

[0083] According to an embodiment of the present application, the interface passivation layer 2 is, for example, tunneling silicon oxide, and the first doped semiconductor layer 3 is, for example, doped polycrystalline silicon.

[0084] According to an embodiment of the present application, the interface passivation layer 2 is, for example, intrinsic amorphous silicon, and the first doped semiconductor layer 3 is, for example, doped amorphous silicon.

[0085] According to an embodiment of the present application, the TOPCon solar cell further includes: a second doped semiconductor layer 5, at least located within the second surface B of the semiconductor substrate 1, serving as the emitter region of the TOPCon solar cell; one of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is N-type, and the other of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is P-type.

[0086] According to an embodiment of the present application, the TOPCon solar cell further includes a second passivation and antireflection layer 6, at least located on the surface of the second doped semiconductor layer 5 away from the semiconductor substrate 1. The second passivation and antireflection layer 6 is used to achieve the passivation and antireflection functions of the second surface B of the semiconductor substrate 1.

[0087] Figure 5 It is a partial cross-sectional schematic diagram of the solar cell provided by the embodiment of the present application.

[0088] According to an embodiment of the present application, referring to Figure 5 As shown, a heavily doped semiconductor base layer 111 is formed on the first surface A of the semiconductor substrate 1 and the surface of the first region C1. Here, the heavily doped semiconductor base layer 111 can be understood as having a doping concentration greater than that of the semiconductor substrate 1 itself. Specifically, since doping elements need to be added during the formation of the first doped semiconductor layer 3, some doping elements will diffuse into the semiconductor substrate 1, making the doping element concentration in some regions of the semiconductor substrate 1 near the first surface A and the first region C1 greater than the doping concentration of the semiconductor substrate 1. Optionally, the heavily doped semiconductor base layer 111 can be located on a partial surface of the first region C1 or on the entire surface of the first region C1.

[0089] Figure 6 It is a cross-sectional schematic diagram of the solar cell provided by another embodiment of the present application.

[0090] According to an embodiment of the present application, referring to Figure 6 As shown, the first region C1 of at least one first side C is an inclined surface extending in a direction away from the semiconductor substrate 1 from the side away from the first surface A towards the side close to the first surface A. In this way, the surface area of the first surface A can be increased, the area of the passivation contact structure located on the first surface A can be increased, which is beneficial to improving the carrier collection efficiency. And it can increase the surface distance of the entire first side in the direction perpendicular to the first surface A, which is more beneficial to the isolation between the first surface A and the second surface B.

[0091] According to an embodiment of the present application, the passivated contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of the first region C1 of at least one first side surface C.

[0092] According to an embodiment of the present application, the interface passivation layer 2 and the first doped semiconductor layer 3 are also located on a partial surface of the first region C1, which can increase the surface area of the passivated contact structure composed of the interface passivation layer 2 and the first doped semiconductor layer 3, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.

[0093] According to an embodiment of the present application, the first region C1 is an inclined plane and is relatively flat, which is beneficial to depositing a first passivation and antireflection layer 4 with better film formation quality on the first side surface C and improving the passivation and antireflection effects of the first passivation and antireflection layer 4.

[0094] According to an embodiment of the present application, the passivated contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of the first region C1 of at least one first side surface C. The passivated contact structure does not completely cover the first region C1, which can reduce the short - circuit risk brought by the passivated contact structure.

[0095] Figure 7 Schematic cross - sectional view of a solar cell provided by another embodiment of the present application.

[0096] According to an embodiment of the present application, since the first region C1 of at least one first side surface C is an inclined plane extending from the side far from the first surface A to the side close to the first surface A along the direction away from the semiconductor substrate 1, there is no large step between the first region C1 and the second region C2. Therefore, it is beneficial to improve the passivation effect of the first passivation and antireflection layer. When considering a better passivation effect, the first doped semiconductor layer 3 can also cover most of the surface of the first region C1, or even completely cover the first region C1.

[0097] Figure 8 Scanning electron microscope image of the first side surface of a solar cell provided by another embodiment of the present application.

[0098] Reference Figure 8 As shown, there are multiple holes on the first region C1, and the holes are recessed into the semiconductor substrate 1 in the direction parallel to the first surface A.

[0099] According to an embodiment of the present application, the passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of at least a first region C1 of the first side surface C. The holes are recessed into the semiconductor substrate 1 through the passivation contact structure in a direction parallel to the first surface A. The first passivation antireflection layer 4 is located on the side walls and bottom surfaces of the first region C1 and the holes, so that hydrogen in the first passivation antireflection layer 4 in the holes enters the semiconductor substrate 1, improving the hydrogen passivation effect of the semiconductor substrate 1, thereby improving the efficiency of the solar cell. Generally, the first passivation antireflection layer 4 may include one or more layers of aluminum oxide, silicon nitride, silicon oxynitride, such as a stack of aluminum oxide and silicon nitride. A large amount of hydrogen is introduced during the deposition of aluminum oxide. Due to the hole structure, a large amount of hydrogen can enter the semiconductor substrate 1.

[0100] According to an embodiment of the present application, the distribution density of the holes in the region close to the first surface A is less than the distribution density in the region close to the second region C2.

[0101] According to an embodiment of the present application, the distribution density of the holes in the region close to the first surface A is low, which can reduce the recombination centers of carriers in the region close to the first surface A, reduce the recombination of carriers, and thus improve the collection efficiency of carriers.

[0102] According to an embodiment of the present application, the radial dimension of the holes gradually decreases in the direction parallel to the first surface A from the surface of the first region C1 to the semiconductor substrate 1. That is to say, the holes are in an inverted pyramid structure extending in the direction parallel to the first surface A from the surface of the first region C1 to the semiconductor substrate 1.

[0103] According to an embodiment of the present application, the radial dimension of the holes is less than 5 μm, preferably less than 2 μm, and more preferably less than 1 μm; the radial dimension of the holes can be, for example, 4 μm, 3 μm, 2 μm, 1 μm, but is not limited to the listed values.

[0104] According to an embodiment of the present application, the ratio of the projected area of the holes in the first region A to the surface area of the first region ranges from 1% to 30%, and can be, for example, 1%, 5%, 10%, 20%, 30%, but is not limited to the listed values. If the ratio range is too small, it is difficult to achieve the technical effects of improving the passivation effect of the semiconductor substrate and increasing the area of the passivation contact structure, or the effect is not obvious; if the ratio range is too large, there will be too many defects in the semiconductor substrate 1, which is not conducive to the effective collection of carriers.

[0105] According to an embodiment of the present application, both the distribution density and the radial dimension of the hole structure in the region of the first region C1 covered by the first doped semiconductor layer 3 or the passivation contact structure are less than those in the region of the first region C1 not covered by the first doped semiconductor layer 3. This can reduce the damage to the passivation contact structure.

[0106] Figure 9 Schematic partial cross-sectional view of a solar cell provided by another embodiment of the present application.

[0107] Figure 10 Scanning electron microscope image of the first side of a solar cell provided by another embodiment of the present application.

[0108] According to an embodiment of the present application, with reference to Figure 9 、 Figure 10 As shown, the first region C1 has a raised ridge, and the ridge extends in a direction substantially parallel to the first surface A.

[0109] According to an embodiment of the present application, with reference to Figure 9 As shown, the first doped semiconductor layer 3 is also located on a partial surface of the first region C1; the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; a partial surface of the first region C1 adjacent to the second region C2 is not covered with the first doped semiconductor layer 3.

[0110] According to an embodiment of the present application, the first region C1 has a raised ridge, and the first doped semiconductor layer 3 is located on a partial surface of the first region C1, which can enhance the electrical isolation between the front and back surfaces of the cell, and can increase the surface area of the first doped semiconductor layer 3 under the condition that the leakage current is controllable, which is beneficial to improving the carrier collection efficiency.

[0111] Figure 11 Schematic partial cross-sectional view of a solar cell provided by another embodiment of the present application.

[0112] According to an embodiment of the present application, with reference to Figure 11 As shown, the first region C1 has a raised ridge, and the ridge extends in a direction substantially parallel to the first surface A, which can increase the surface area of the first region C1. Under the condition that the leakage current is controllable, the first doped semiconductor layer 3 completely covers the first region C1, which can increase the surface area of the first doped semiconductor layer 3, and thus is beneficial to improving the carrier collection efficiency.

[0113] According to an embodiment of the present application, since the first region C1 of at least one first side C has a raised ridge, and the ridge extends in a direction substantially parallel to the first surface A; that is to say, a partial region of the first region C1 close to the second region C2 is an inclined surface extending from one side of the second region C2 to the side of the ridge in a direction away from the semiconductor substrate 1.

[0114] There may not be a large step between the first region C1 and the second region C2, or even no step, which is beneficial to improving the passivation effect of the passivation and antireflection layer. When considering the passivation effect, the first doped semiconductor layer can also cover most of the surface of the first region C1, or even completely cover the first region C1. According to an embodiment of the present application, the second region C2 has a tower base structure, and the width of the first region C1 in the direction perpendicular to the first surface A is smaller than the size of the tower base structure of the second region C2, where the size of the tower base structure is defined as the side length or diagonal length of the tower base structure.

[0115] According to an embodiment of the present application, the TOPcon solar cell further includes a first electrode 10, the first electrode 10 passes through the first passivation and antireflection layer 4 and is in electrical contact with the first doped semiconductor layer 3; a second electrode 20, the second electrode 20 passes through the second passivation and antireflection layer 6 and is in electrical contact with the second doped semiconductor layer 5.

[0116] According to an embodiment of the present application, the distance between the first electrode 10 and the first region C1 in the direction perpendicular to the thickness direction of the semiconductor substrate 1 (parallel to the first surface A) is greater than or equal to 300 μm. Therefore, during the preparation of the electrode, it can also effectively prevent the paste used for preparing the electrode from leaking and distributing in a larger range on the side of the battery, causing serious loss to the electrical performance of the battery.

[0117] According to an embodiment of the present application, the first doped semiconductor layer 3 is one or more of doped polysilicon, doped amorphous silicon, and doped microcrystalline silicon. The first doped semiconductor layer 3 is, for example, doped polysilicon. The thickness of the doped polysilicon is usually between 80 nm and 500 nm, and the doping concentration is usually between 1*10 17 ~1*10 21 atoms / cm 3 ..

[0118] Figure 12 This is a schematic cross-sectional view of the solar cell provided by another embodiment of the present application.

[0119] According to an embodiment of the present application, as shown in Figure 12 the first side surface C further includes a third region C3 adjacent to the second region C2, and the third region C3 is closer to the second surface B than the second region C2. That is to say, the above-mentioned solar cell further includes: a third semiconductor base 13, which is integrally formed with the second semiconductor base 12, and the third semiconductor base 13 is closer to the second surface B than the second semiconductor base 12.

[0120] According to an embodiment of the present application, the third region C3 protrudes in the direction away from the first side surface C compared with the second region C2, and the protrusion height d2 of the third region C3 is greater than the protrusion height d1 of the first region C1.

[0121] According to an embodiment of the present application, the protrusion height d2 of the third region C3 is 3 μm to 10 μm, and for example, it can be 3 μm, 5 μm, 6 μm, 8 μm, 10 μm, but is not limited to the listed values.

[0122] According to an embodiment of the present application, when forming the second doped semiconductor layer 5 on the second surface B, the second doped semiconductor layer 5 will be plated around the first side C. When using an alkaline solution to remove the second doped semiconductor layer 5 plated around the first side C, a third region C3 is formed in the region of the first side C close to the second surface B, where the third region C3 protrudes in a direction away from the first side C compared to the second region C2. On the one hand, it can increase the spatial electrical isolation distance between the first surface A and the second surface B, and can better avoid the occurrence of leakage on the first side of the solar cell; on the other hand, it can effectively block the slurry used for preparing the electrode on the second surface B from leaking to the first side, and thus can avoid damaging the performance of the battery.

[0123] In addition, the third region C3 protrudes in a direction away from the first side C compared to the second region C2, which can increase the junction area of the PN junction formed by the semiconductor substrate 1 and the second doped semiconductor layer 5, and is beneficial to improving the photocurrent of the solar cell.

[0124] According to an embodiment of the present application, the solar cell is a solar cell with a single-sided electrode, such as an Interdigitated Back Contact (IBC) cell.

[0125] Figure 13 It is a schematic cross-sectional view of the back contact solar cell provided by the embodiment of the present application.

[0126] Figure 14 It is a schematic top view of the first surface of the back contact solar cell provided by the embodiment of the present application.

[0127] According to an exemplary embodiment of the present application, referring to Figure 13 、 Figure 14 as shown, the present application provides a back contact solar cell.

[0128] According to an embodiment of the present application, an electrode collection region is provided on the first surface A of the semiconductor substrate 1, and the electrode collection region includes a plurality of minority carrier regions 100 and a plurality of majority carrier regions 200 that are alternately distributed along the second direction, and there is an isolation region 300 between adjacent minority carrier regions 100 and majority carrier regions 200.

[0129] According to an embodiment of the present application, the first doped semiconductor layer 3 includes a third doped semiconductor layer 31 and a fourth doped semiconductor layer 32; wherein, the third doped semiconductor layer 31 for collecting and exporting minority carriers is disposed in the minority carrier region 100; the fourth doped semiconductor layer 32 for collecting and exporting majority carriers is disposed in the majority carrier region 200, where the conductivity types of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 are opposite, one of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 is N-type, and the other of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 is P-type. For example, the conductivity type of the third doped semiconductor layer 31 may be N-type, and in this case, the conductivity type of the fourth doped semiconductor layer 32 is P-type; or, the conductivity type of the third doped semiconductor layer 31 may be P-type, and in this case, the conductivity type of the fourth doped semiconductor layer 32 is N-type.

[0130] According to an embodiment of the present application, referring to Figure 13 、 Figure 14 As shown, a plurality of third doped semiconductor layers 31 extend in a first direction in a first plane parallel to the first surface A.

[0131] According to an embodiment of the present application, a plurality of fourth doped semiconductor layers 32 extend in the first direction, and the plurality of third doped semiconductor layers 31 and the plurality of fourth doped semiconductor layers 32 are alternately and spaced apart in a second direction perpendicular to the first direction in the first plane on the first surface A.

[0132] According to an embodiment of the present application, the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 are also located on a partial surface of the first region C1.

[0133] According to an embodiment of the present application, the first doped semiconductor layer 3 on the minority carrier region 100 at the outermost edge of the semiconductor substrate 1 extends perpendicularly from the first plane to a partial surface of the first region C1 of the first side surface C; and / or, the second doped semiconductor layer 5 on the majority carrier region 200 at the outermost edge of the semiconductor substrate 1 extends perpendicularly from the first plane to a partial surface of the first region C1 of the first side surface C.

[0134] According to an embodiment of the present application, a first interface passivation layer is further formed between the semiconductor substrate 1 and the third doped semiconductor layer 31. A second interface passivation layer is further formed between the semiconductor substrate 1 and the fourth doped semiconductor layer 32.

[0135] According to an embodiment of the present application, the first interface passivation layer and / or the second interface passivation layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.

[0136] According to an embodiment of the present application, the first passivation and antireflection layer 4 of the back contact solar cell is located on the surfaces of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 away from the semiconductor substrate 1, and on the semiconductor substrate 1 of the isolation region 300. The material of the first passivation and antireflection layer 4 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The first passivation and antireflection layer 4 is used to achieve the surface passivation and antireflection functions of the back contact cell.

[0137] According to an embodiment of the present application, the back contact solar cell further includes: a first electrode 10, the first electrode 10 penetrates through the first passivation and antireflection layer 4 and is in electrical contact with the third doped semiconductor layer 31; a second electrode 20, the second electrode 20 penetrates through the first passivation and antireflection layer 4 and is in electrical contact with the fourth doped semiconductor layer 32.

[0138] According to an embodiment of the present application, the width of the first electrode 10 is 5 μm to 600 μm, and for example, it can be 5 μm, 10 μm, 100 μm, 500 μm, 600 μm, but is not limited to the recited values.

[0139] According to an embodiment of the present application, the width of the second electrode 20 is 5 μm to 600 μm, and for example, it can be 5 μm, 10 μm, 100 μm, 500 μm, 600 μm, but is not limited to the recited values.

[0140] According to an embodiment of the present application, the material of the first electrode 10 and / or the second electrode 20 includes, but is not limited to, one or more of metals, metal oxides, metal nitrides, metal carbides, and metal sulfides. The first electrode 10 and / or the second electrode 20 can also be other conductive connection materials such as graphene.

[0141] According to an embodiment of the present application, during the electrode preparation process, electrode paste is coated on the first passivation and antireflection layer 4 on the first surface A, and then after sintering, the electrode paste penetrates through the first passivation and antireflection layer 4 and forms contact with the doped semiconductor film layer.

[0142] According to an exemplary embodiment of the present application, the present application provides a photovoltaic module including the above-mentioned solar cell.

[0143] The ordinal numbers used in the description and claims, such as "first", "second", "third", etc., are used to modify the corresponding elements. They do not themselves imply any ordinal number of the element, nor do they represent the order of one element and another element or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish one element with a certain name from another element with the same name.

[0144] The specific embodiments described above further elaborate on the objective, technical solution, and beneficial effects of the present application. It should be understood that the above description is only for the specific embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A solar cell, characterized in that, Comprising: A semiconductor substrate (1) having opposite first (A) and second (B) surfaces, and a plurality of first side surfaces (C) adjacent between the first (A) and second (B) surfaces; A passivated contact structure disposed at least on a portion of the first surface (A) of the semiconductor substrate (1), the passivated contact structure including an interface passivation layer (2) and a first doped semiconductor layer (3) stacked in sequence; Wherein, in the direction from the first surface (A) towards the second surface (B), the first side surface (C) includes a first region (C1) and a second region (C2) adjacent in sequence, and the first region (C1) protrudes in a direction away from the first side surface (C) compared to the second region (C2); The first doped semiconductor layer (3) is also disposed on a portion of the surface of the first region (C1), and the first doped semiconductor layer (3) on the first region (C1) is integrally continuous with the first doped semiconductor layer (3) on the first surface (A); a portion of the surface of the first region (C1) adjacent to the second region (C2) is not covered by the first doped semiconductor layer (3); In the direction from the first surface (A) towards the second surface (B), the distance between the first doped semiconductor layer (3) on the surface of the first region (C1) and the second region (C2) is greater than or equal to 1 μm.

2. The solar cell according to claim 1, wherein The ratio of the width of the first region (C1) in a direction perpendicular to the first surface (A) to the thickness of the semiconductor substrate (1) ranges from 1% to 20%.

3. The solar cell according to claim 1, wherein The width of the first region (C1) in a direction perpendicular to the first surface (A) is 0.5 μm to 20 μm.

4. The solar cell according to claim 1, characterized in that, In a direction perpendicular to the first surface (A), the distribution width of the first doped semiconductor layer (3) in the first region (C1) is less than 80% of the width of the first region (C1).

5. The solar cell according to any one of claims 1 - 4, wherein The first region (C1) of at least one of the first side surfaces (C) is an inclined surface extending in a direction away from the semiconductor substrate (1) from a side away from the first surface (A) towards a side close to the first surface (A).

6. The solar cell according to any one of claims 1-4, characterized in that, The first region (C1) includes an edge extending parallel to the first surface (A).

7. The solar cell according to any one of claims 1 - 4, wherein The first region (C1) has a plurality of holes, and the holes are recessed into the semiconductor substrate (1) in a direction parallel to the first surface (A).

8. The solar cell according to claim 7, characterized in that, The distribution density of the holes in a region close to the first surface (A) is less than the distribution density in a region close to the second region (C2).

9. The solar cell according to claim 8, wherein The radial dimension of the hole gradually decreases in the direction from the surface of the first region (C1) to the semiconductor substrate (1); and / or, the radial dimension of the hole is less than 5 μm.

10. The solar cell according to any one of claims 1-4, characterized in that, It further includes: a second doped semiconductor layer (5) at least located within the second surface (B) of the semiconductor substrate (1); and a second passivation and antireflection layer (6) at least located on the surface of the second doped semiconductor layer (5) away from the semiconductor substrate (1).

11. The solar cell according to any one of claims 1-4, characterized in that, The solar cell is a back-contact solar cell, the first doped semiconductor layer (3) includes a plurality of third doped semiconductor layers (31) and a plurality of fourth doped semiconductor layers (32), and the plurality of third doped semiconductor layers (31) and the plurality of fourth doped semiconductor layers (32) are alternately and spacedly distributed on the first surface (A); wherein, one of the third doped semiconductor layer (31) and the fourth doped semiconductor layer (32) is N-type, and the other of the third doped semiconductor layer and the fourth doped semiconductor layer is P-type.

12. The solar cell according to any one of claims 1-4, characterized in that, It further includes: a first passivation and antireflection layer (4) at least located on the surface of the passivation contact structure away from the semiconductor substrate (1); a first electrode (10), the first electrode (10) penetrates through the first passivation and antireflection layer (4) and contacts the first doped semiconductor layer (3); wherein, the distance between the first electrode (10) and the first region (C1) in the direction parallel to the first surface (A) is greater than or equal to 300 μm.

13. The solar cell according to any one of claims 1-4, characterized in that, The first side surface (C) further includes a third region (C3) adjacent to the second region (C2), and the third region (C3) is closer to the second surface (B) than the second region (C2); the third region (C3) protrudes in the direction away from the first side surface (C) compared to the second region (C2), and the protrusion height of the third region (C3) is greater than the protrusion height of the first region (C1).

14. A photovoltaic module, characterized in that, It includes the solar cell according to any one of claims 1 to 13.

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