Display apparatus and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes: a first sub-pixel electrode and a second sub-pixel electrode spaced apart from each other; a sub-pixel defining layer covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode; a first stack including a first emission layer and a first opposing electrode, on the sub-pixel defining layer, and overlapping the first sub-pixel electrode; a second stack including a second emission layer and a second opposing electrode, on the sub-pixel defining layer, and overlapping the second sub-pixel electrode; a first encapsulation layer covering each of an edge of the first stack and an edge of the second stack, and including a first opening overlapping each of the first stack and the second stack and a second opening between the first stack and the second stack; and a common electrode on the first encapsulation layer and electrically connected to a first opposing electrode of the first stack and a second opposing electrode of the second stack.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0094655 filed in the Korean Intellectual Property Office on July 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of one or more embodiments are directed to a display device including a light emitting diode and a method of manufacturing the display device. Background Art

[0004] The display device visually displays data. The display device may display images using light emitting diodes. The purpose and structure of the display device have changed over time, and a structure that can be bent to a preset angle relative to a flat state may be required.

[0005] The display device may include a plurality of sub-pixels in a pattern to display an image. In order to realize the plurality of sub-pixels, a plurality of light-emitting diodes each including a sub-pixel electrode, an emission layer, and a counter electrode may be arranged on the substrate. The plurality of light-emitting diodes may be arranged or formed simultaneously (or synchronously) or individually arranged or formed in sequence.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] When a light emitting diode is formed in a pattern on a substrate, a portion of each of the layers forming the light emitting diode may be exposed. When each layer is exposed, there is a risk of moisture or contaminant penetration and / or oxidation in each layer (particularly oxidation of metal-containing layers). This may result in degradation of the image quality and reliability of the display device. Aspects of one or more embodiments include a display device and a method for manufacturing a display device in which the exposure of each layer can be reduced while forming a light emitting diode.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to one or more embodiments, a display device includes: a first subpixel electrode and a second subpixel electrode separated from each other; a subpixel defining layer covering an edge of the first subpixel electrode and an edge of the second subpixel electrode; a first stack including a first emission layer and a first relative electrode on the subpixel defining layer and overlapping with the first subpixel electrode; a second stack including a second emission layer and a second relative electrode on the subpixel defining layer and overlapping with the second subpixel electrode; a first encapsulation layer covering each of an edge of the first stack and an edge of the second stack and including a first opening overlapping with each of the first stack and the second stack and a second opening between the first stack and the second stack; and a common electrode on the first encapsulation layer and electrically connected to the first relative electrode of the first stack and the second relative electrode of the second stack.

[0010] According to some embodiments, the first encapsulation layer may overlap a portion of an upper surface and a side surface of the first stack and a portion of an upper surface and a side surface of the second stack.

[0011] According to some embodiments, the display device may further include a first auxiliary layer between the first opposing electrode and the common electrode and between the second opposing electrode and the common electrode, respectively.

[0012] According to some embodiments, the display device may further include a second auxiliary layer between the second subpixel electrode and the second emission layer, wherein a central portion of the second auxiliary layer may be in direct contact with the second subpixel electrode and an outer portion of the second auxiliary layer may be separated from the second subpixel electrode by a subpixel defining layer.

[0013] According to some embodiments, the number of layers between the first subpixel electrode and the first opposing electrode may be different from the number of layers between the second subpixel electrode and the second opposing electrode.

[0014] According to some embodiments, the display device may further include a second encapsulation layer on the common electrode and extending to overlap the first stack and the second stack.

[0015] According to some embodiments, in a plan view, the second openings of the first encapsulation layer may have a mesh structure surrounding each of the first openings.

[0016] According to one or more embodiments, a display device includes: first to third subpixel electrodes separated from each other; a subpixel defining layer covering an edge of each of the first to third subpixel electrodes and including an opening overlapping a central portion of each of the first to third subpixel electrodes; first to third emission layers, respectively on the first to third subpixel electrodes; first to third relative electrodes, respectively on the first to third emission layers; a 1-1 encapsulation layer covering at least a portion of the first relative electrode and at least a portion of the first emission layer, and including an opening overlapping a central portion of the first relative electrode; a 1-2 encapsulation layer covering at least a portion of the second relative electrode and at least a portion of the second emission layer, and including an opening overlapping a central portion of the second relative electrode; a 1-3 encapsulation layer covering at least a portion of the third relative electrode and at least a portion of the third emission layer, and including an opening overlapping a central portion of the third relative electrode; and a common electrode, on the first to third relative electrodes, and electrically connected to the first to third relative electrodes, wherein the 1-1 to 1-3 encapsulation layers have isolated shapes and are separated from each other.

[0017] According to some embodiments, the common electrode may contact an upper surface of the sub-pixel defining layer in a space between adjacent encapsulation layers among the 1-1 to 1-3 encapsulation layers.

[0018] According to some embodiments, the display device may further include a 1-1 auxiliary layer between the first opposing electrode and the common electrode, a 1-2 auxiliary layer between the second opposing electrode and the common electrode, and a 1-3 auxiliary layer between the third opposing electrode and the common electrode.

[0019] According to some embodiments, the 1-1 encapsulation layer may directly contact a portion of an upper surface and a side surface of the 1-1 auxiliary layer, a side surface of the first opposite electrode, and a side surface of the first emission layer.

[0020] According to some embodiments, the display device may further include a 2-2 auxiliary layer between the second sub-pixel electrode and the second emission layer, wherein the first sub-pixel electrode is in direct contact with the first emission layer.

[0021] According to some embodiments, the display device may further include a second encapsulation layer on the common electrode.

[0022] According to some embodiments, in a plan view, each of the 1-1 to 1-3 encapsulation layers may surround an edge of the first opposing electrode, an edge of the second opposing electrode, and an edge of the third opposing electrode.

[0023] According to one or more embodiments, a method for manufacturing a display device includes: forming a first sub-pixel electrode and a second sub-pixel electrode separated from each other; forming a first stack layer on the first sub-pixel electrode and the second sub-pixel electrode, wherein the first stack layer includes a first light-emitting material layer and a first opposing electrode layer; forming a 1-1 auxiliary material layer on the first stack layer; forming a first stack and a 1-1 auxiliary layer overlapping the first stack by etching a portion of the 1-1 auxiliary material layer and a portion of the first stack layer, wherein the first stack overlaps the first sub-pixel electrode and includes a first emission layer and a first opposing electrode; forming a 1-1 encapsulation material layer to cover the first stack and the 1-1 auxiliary layer; forming a 1-1 encapsulation layer by etching a portion of the 1-1 encapsulation material layer, wherein the 1-1 encapsulation layer is adjacent to an upper surface of the first stack and the 1-1 auxiliary layer. 1-2 auxiliary layer is completely overlapped with the upper surface of the 1-1 encapsulation layer and the second sub-pixel electrode; a second stacking layer is formed on the 1-1 encapsulation layer and the second sub-pixel electrode, wherein the second stacking layer includes a second light-emitting material layer and a second relative electrode layer; a 1-2 auxiliary material layer is formed on the second stacking layer; a second stack and a 1-2 auxiliary layer overlapping with the second stack are formed by etching a portion of the 1-2 auxiliary material layer and a portion of the second stacking layer, wherein the second stack overlaps with the second sub-pixel electrode and includes a second emission layer and a second relative electrode; a 1-2 encapsulation material layer is formed to cover the second stack and the 1-2 auxiliary layer; and a 1-2 encapsulation layer is formed by etching a portion of the 1-2 encapsulation material layer, wherein the 1-2 encapsulation layer completely overlaps with the upper surface of the second stack and the upper surface of the 1-2 auxiliary layer, wherein the 1-1 encapsulation layer and the 1-2 encapsulation layer are separated from each other.

[0024] According to some embodiments, the method may further include forming a first opening in each of the 1-1 encapsulation layer and the 1-2 encapsulation layer.

[0025] According to some embodiments, the 1-1 encapsulation layer may be in direct contact with a portion of the upper surface and side surface of the 1-1 auxiliary layer and the side surface of the first stack, and the 1-2 encapsulation layer may be in direct contact with a portion of the upper surface and side surface of the 1-2 auxiliary layer and the side surface of the second stack.

[0026] According to some embodiments, the method may further include forming a second auxiliary material layer under the second stack layer, wherein forming the second stack may include forming the second auxiliary layer by etching a portion of the second auxiliary material layer, and the second auxiliary layer is in direct contact with the upper surface of the second subpixel electrode.

[0027] According to some embodiments, the method may further include forming a common electrode layer (also referred to as a “common electrode”) overlapping the first opening of the 1-1 encapsulation layer and the first opening of the 1-2 encapsulation layer.

[0028] According to some embodiments, the method may further include forming a sub-pixel defining layer covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode, wherein the common electrode layer may be in direct contact with an upper surface of the sub-pixel defining layer in a separation area between the 1-1 encapsulation layer and the 1-2 encapsulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and characteristics of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic perspective view of a display device according to some embodiments;

[0031] Figure 2 is a schematic cross-sectional view of a portion of a display device according to some embodiments;

[0032] Figure 3 is a schematic equivalent circuit diagram of a sub-pixel of a display device according to some embodiments;

[0033] Figure 4 is a schematic cross-sectional view of a portion of a display device according to some embodiments;

[0034] Figure 5 is a schematic cross-sectional view of a portion of a display device according to some embodiments;

[0035] Figure 6 is a schematic enlarged plan view of a portion of a display device according to some embodiments; and

[0036] FIG. 7A to FIG. 7P is a schematic cross-sectional view illustrating a state corresponding to a process of manufacturing a display device according to some embodiments. DETAILED DESCRIPTION

[0037] Now will be referred to in detail embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain the various aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the statement "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c and / or any combination of a, b, and c.

[0038] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of the present disclosure and methods for achieving them will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0039] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout and repeated descriptions thereof will be omitted.

[0040] Although terms such as "first" and "second" may be used to describe various elements, these elements are not necessarily limited to the above terms. The above terms are used to distinguish one element from another.

[0041] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] It will be understood that as used herein, the terms “comprises,” “comprising,” “includes,” and / or “comprising” specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0043] It will also be understood that when a layer, region or element is referred to as being "on" another layer, region or element, it can be directly or indirectly on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0044] For convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. As an example, the size and thickness of each element shown in the drawings are arbitrarily represented for convenience of description, and therefore, the present disclosure is not necessarily limited thereto.

[0045] Where a certain embodiment may be implemented differently, a specific process sequence may be performed in a different order than that described. As an example, two processes described in succession may be performed substantially simultaneously or in a reverse order.

[0046] In the present specification, “A and / or B” means A or B, or A and B. In the present specification, “at least one of A and B” means A or B, or A and B, or any combination of A and B.

[0047] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, it may be "directly connected" to the other layer, region, or element, or it may be "indirectly connected" to the other layer, region, or element with another layer, region, or element interposed therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be "directly electrically connected" to the other layer, region, or element, or it may be "indirectly electrically connected" to the other layer, region, or element with another layer, region, or element interposed therebetween.

[0048] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different orientations that are not perpendicular to each other.

[0049] Figure 1 is a schematic perspective view of a display device 1 according to some embodiments.

[0050] refer to Figure 1 , the display device 1 may include a display area DA and a non-display area NDA outside the display area DA. The display area DA may be configured to display an image by means of sub-pixels P arranged in the display area DA. The non-display area NDA is arranged outside the display area DA and does not display an image. The non-display area NDA may completely surround the display area DA. A driver or the like configured to provide an electrical signal or power to the display area DA may be arranged in the non-display area NDA. A pad may be arranged in the non-display area NDA, wherein the pad is an area to which an electronic component or a printed circuit board may be electrically connected.

[0051] According to some embodiments, although Figure 1 The display area DA is shown to be a polygon (e.g., a quadrilateral) in which its length in the x direction is smaller than its length in the y direction, but according to some embodiments, the display area DA may be a polygon (e.g., a quadrilateral) in which its length in the y direction is smaller than its length in the x direction. Figure 1 The display area DA is shown to be approximately a quadrilateral, but the embodiments of the present disclosure are not limited thereto. According to some embodiments, the display area DA may have various shapes such as an N-gon (where N is a natural number of 3 or more), a circle, or an ellipse. Figure 1 , the display area DA is shown to have a shape in which corners of the display area DA include vertices at which straight lines intersect with the straight lines, but according to some embodiments, the display area DA may have a polygon in which the corners are curved.

[0052] Hereinafter, for the convenience of description, although the case where the display device 1 is a smart phone is described, the display device 1 according to some embodiments is not limited thereto. The display device 1 can be applied to various products including televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). In addition, the display device 1 according to some embodiments can be applied to wearable devices including smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, according to some embodiments, the display device 1 can be applied to a display screen in an instrument panel for a car, a central panel for a car, or a central information display (CID) arranged on a dashboard, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system for rear seat passengers arranged on the back side of a front seat in a car.

[0053] Figure 2 is a schematic cross-sectional view of a portion of a display device according to some embodiments.

[0054] refer to Figure 2 , a plurality of sub-pixels may be arranged in the display area DA over the substrate 100. As an example, a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 may be positioned over the substrate 100.

[0055] The substrate 100 may include a polymer resin of glass or a plastic material. The substrate 100 may have a structure in which a base layer including a polymer resin and an inorganic barrier layer including an inorganic insulating material are stacked. The polymer resin includes polyethersulfone (PES), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), etc. According to some embodiments, in the case where the substrate 100 includes a plastic material or a metal material, the flexibility can be improved compared to the case where the substrate 100 includes a glass material.

[0056] The display elements DPE corresponding to the first sub-pixel P1 , the second sub-pixel P2 , and the third sub-pixel P3 , respectively, may be electrically connected to the first thin film transistor TFT1 , the second thin film transistor TFT2 , and the third thin film transistor TFT3 , respectively.

[0057] As an example, a first subpixel electrode 1210 of a display element DPE corresponding to a first subpixel P1 may be electrically connected to a first thin film transistor TFT1. The first thin film transistor TFT1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1, wherein the first gate electrode G1 overlaps a portion of the first active layer A1, and each of the first source electrode S1 and the first drain electrode D1 directly contacts a portion of the first active layer A1.

[0058] The second subpixel electrode 2210 of the display element DPE corresponding to the second subpixel P2 may be electrically connected to the second thin film transistor TFT2. The second thin film transistor TFT2 may include a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2, wherein the second gate electrode G2 overlaps a portion of the second active layer A2, and each of the second source electrode S2 and the second drain electrode D2 directly contacts a portion of the second active layer A2.

[0059] The third subpixel electrode 3210 of the display element DPE corresponding to the third subpixel P3 may be electrically connected to the third thin film transistor TFT3. The third thin film transistor TFT3 may include a third active layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3, wherein the third gate electrode G3 overlaps a portion of the third active layer A3, and each of the third source electrode S3 and the third drain electrode D3 directly contacts a portion of the third active layer A3.

[0060] The first gate electrode G1, the second gate electrode G2 and the third gate electrode G3 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and include a single layer or a multilayer containing the above materials.

[0061] The buffer layer 101 may be located between the first active layer A1, the second active layer A2, and the third active layer A3 and the substrate 100, wherein the buffer layer 101 is configured to prevent impurities from penetrating. The gate insulating layer 103 may be located between the first active layer A1, the second active layer A2, and the third active layer A3 and the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3. The interlayer insulating layer 105 may be located on the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3. Each of the buffer layer 101, the gate insulating layer 103, and the interlayer insulating layer 105 may include a material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AlO x) and aluminum nitride (AlN x ), titanium oxide (TiO x ) or titanium nitride (TiN x ) of inorganic insulating materials.

[0062] The first source electrode S1, the second source electrode S2, and the third source electrode S3 may be located on the interlayer insulating layer 105, and respectively connected to the first active layer A1, the second active layer A2, and the third active layer A3 through contact holes formed in the interlayer insulating layer 105 and the gate insulating layer 103. The first source electrode S1, the second source electrode S2, and the third source electrode S3 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), and include a single layer or a multilayer including the above materials.

[0063] The first drain electrode D1, the second drain electrode D2, and the third drain electrode D3 may be located on the interlayer insulating layer 105, and connected to the first active layer A1, the second active layer A2, and the third active layer A3, respectively, through contact holes formed in the interlayer insulating layer 105 and the gate insulating layer 103. The first drain electrode D1, the second drain electrode D2, and the third drain electrode D3 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), and include a single layer or a multilayer including the above materials. According to some embodiments, the first source electrode S1, the second source electrode S2, and the third source electrode S3 and the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3 may include the same material.

[0064] The first organic insulating layer 107 may be located on the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3. As an example, the first organic insulating layer 107 may be arranged to cover the first source electrode S1, the second source electrode S2, and the third source electrode S3 and the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3. The first organic insulating layer 107 may include an organic insulating material such as acrylic resin, benzocyclobutene (BCB), polyimide (PI), or hexamethyldisiloxane (HMDSO). The first organic insulating layer 107 may include a plurality of contact holes. As an example, the first organic insulating layer 107 may include a plurality of contact holes overlapping the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3, respectively.

[0065] The connection metal CM may be located on the first organic insulating layer 107. The connection metal CM may include aluminum (Al), copper (Cu) and / or titanium (Ti), and include a single layer or multiple layers including the above materials. The connection metal CM may be provided in plurality, and the plurality of connection metals CM may be arranged to overlap the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3, respectively. A portion of each of the connection metals CM may be located in a contact hole formed in the first organic insulating layer 107. As an example, the connection metal CM may be directly in contact with the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3, respectively, through the contact holes formed in the first organic insulating layer 107.

[0066] The second organic insulating layer 109 may be located between the connection metal CM and the sub-pixel electrode 210. The second organic insulating layer 109 may include an organic insulating material such as acrylic resin, benzocyclobutene (BCB), polyimide (PI), or hexamethyldisiloxane (HMDSO). The second organic insulating layer 109 may include contact holes respectively overlapping the connection metal CM.

[0067] The sub-pixel electrode 210 may include a first sub-pixel electrode 1210, a second sub-pixel electrode 2210, and a third sub-pixel electrode 3210. The first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may be located on the second organic insulating layer 109. The first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may be formed as a reflective electrode. As an example, the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In addition, the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210 may include a layer formed on the reflective layer, wherein the layer includes an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) inorganic material. According to some embodiments, the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked. However, the embodiment is not limited thereto, and the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 may include various materials, and their structures may include a single layer or multiple layers, and various modifications may be made.

[0068] The first subpixel electrode 1210 , the second subpixel electrode 2210 , and the third subpixel electrode 3210 may be electrically connected to the overlapping connection metal CM through contact holes formed in the second organic insulating layer 109 , respectively.

[0069] According to the reference Figure 2 In some embodiments described, although the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 are electrically connected to and respectively connected to the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 through the connection metal CM, the embodiments according to the present disclosure are not limited thereto. According to some embodiments, the connection metal CM may be omitted, and one organic insulating layer may be located between the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 and the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. Alternatively, at least three organic insulating layers may be located between the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 and the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 are electrically connected to and respectively connected to the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 through a plurality of connection metals CM.

[0070] The sub-pixel defining layer 111 may cover the edge region (or edge) of the first sub-pixel electrode 1210, the edge region (or edge) of the second sub-pixel electrode 2210, and the edge region (or edge) of the third sub-pixel electrode 3210. In other words, the sub-pixel defining layer 111 may include a plurality of openings that expose the central portion of the first sub-pixel electrode 1210, the central portion of the second sub-pixel electrode 2210, and the central portion of the third sub-pixel electrode 3210, respectively. As an example, the sub-pixel defining layer 111 may include a 3-1 opening 111-OP1 overlapping the first sub-pixel electrode 1210. The sub-pixel defining layer 111 may include a 3-2 opening 111-OP2 overlapping the second sub-pixel electrode 2210. The sub-pixel defining layer 111 may include a 3-3 opening 111-OP3 overlapping the third sub-pixel electrode 3210.

[0071] The openings of the sub-pixel defining layer 111 may respectively define the emission region of the first sub-pixel P1, the emission region of the second sub-pixel P2, and the emission region of the third sub-pixel P3. As an example, the 3-1 opening 111-OP1 may define the emission region of the first sub-pixel P1. The 3-2 opening 111-OP2 may define the emission region of the second sub-pixel P2. The 3-3 opening 111-OP3 may define the emission region of the third sub-pixel P3.

[0072] Figure 3 is a schematic equivalent circuit diagram of a sub-pixel P of a display device according to some embodiments.

[0073] Figure 3 The sub-pixel P is, for example, Figure 2 Each of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 shown in FIG.

[0074] The sub-pixel P may include a sub-pixel circuit PC and a display element DPE connected to the sub-pixel circuit PC. The sub-pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The sub-pixel P may be configured to emit light of a specific color from the display element DPE. As an example, the sub-pixel P may be configured to emit, for example, red light, green light, or blue light by using the display element DPE, or to emit red light, green light, blue light, or white light.

[0075] The switching thin film transistor T2 is connected to the scan line SL and the data line DL and is configured to transfer a data voltage or data signal Dm input from the data line DL to the driving thin film transistor T1 according to a scan voltage or scan signal Sn input from the scan line SL.

[0076] The storage capacitor Cst may be connected to the switching thin film transistor T2 and the driving voltage line PL, and configured to store a voltage corresponding to a difference between a voltage transferred from the switching thin film transistor T2 and a first power source voltage ELVDD supplied to the driving voltage line PL.

[0077] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and is configured to control a driving current according to a voltage stored in the storage capacitor Cst, and the driving current flows from the driving voltage line PL to the display element DPE. The display element DPE may be configured to emit light with a preset brightness based on the driving current. An opposite electrode (e.g., a cathode) of the display element DPE may be configured to receive a second power supply voltage ELVSS.

[0078] Although in Figure 32 shows that the sub-pixel circuit PC includes two thin film transistors and one storage capacitor, but the embodiment according to the present disclosure is not limited thereto, and the sub-pixel circuit PC may include three or more thin film transistors.

[0079] Figure 4 is a schematic cross-sectional view of a portion of a display device according to some embodiments.

[0080] Figure 4 According to some embodiments of the present invention, the above reference Figure 2 1. A cross-sectional view of a display element DPE is described. The display element DPE corresponding to the first subpixel P1 may include a first subpixel electrode 1210 and a first stack 1220 on the first subpixel electrode 1210. The display element DPE corresponding to the second subpixel P2 may include a second subpixel electrode 2210 and a second stack 2220 on the second subpixel electrode 2210. The display element DPE corresponding to the third subpixel P3 may include a third subpixel electrode 3210 and a third stack 3220 on the third subpixel electrode 3210.

[0081] refer to Figure 4 , the first sub-pixel electrode 1210 , the second sub-pixel electrode 2210 , and the third sub-pixel electrode 3210 of the display element DPE may be arranged to be spaced apart from each other on the second organic insulating layer 109 .

[0082] The subpixel defining layer 111 may be arranged to cover edges of the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210. In other words, the subpixel defining layer 111 may include a plurality of openings that expose central portions of the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210, respectively.

[0083] The first stack 1220, the second stack 2220, and the third stack 3220 may be separated from each other and respectively located on the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210. As an example, the first stack 1220 may be located on the first sub-pixel electrode 1210. The second stack 2220 may be located on the second sub-pixel electrode 2210. The third stack 3220 may be located on the third sub-pixel electrode 3210.

[0084] The first stack 1220 may include a first emission layer 1221 and a first opposing electrode 1222 on the first emission layer 1221. The second stack 2220 may include a second emission layer 2221 and a second opposing electrode 2222 on the second emission layer 2221. The third stack 3220 may include a third emission layer 3221 and a third opposing electrode 3222 on the third emission layer 3221.

[0085] The first emission layer 1221 , the second emission layer 2221 , and the third emission layer 3221 may be located on the first sub-pixel electrode 1210 , the second sub-pixel electrode 2210 , and the third sub-pixel electrode 3210 , respectively.

[0086] As an example, the first emission layer 1221 may be located on the first sub-pixel electrode 1210. The second emission layer 2221 may be located on the second sub-pixel electrode 2210. The third emission layer 3221 may be located on the third sub-pixel electrode 3210.

[0087] Portions of the first emission layer 1221 , the second emission layer 2221 , and the third emission layer 3221 may be located in the 3-1 opening 111 - OP1 , the 3-2 opening 111 - OP2 , and the 3-3 opening 111 - OP3 of the subpixel defining layer 111 , respectively.

[0088] As an example, a portion of the first emission layer 1221 may be located in the 3-1 opening 111-OP1 of the sub-pixel defining layer 111. Another portion of the first emission layer 1221 may overlap with the edge region (or edge) of the first sub-pixel electrode 1210 and be located on the sub-pixel defining layer 111. A portion of the second emission layer 2221 may be located in the 3-2 opening 111-OP2 of the sub-pixel defining layer 111. Another portion of the second emission layer 2221 may overlap with the edge region (or edge) of the second sub-pixel electrode 2210 and be located on the sub-pixel defining layer 111. A portion of the third emission layer 3221 may be located in the 3-3 opening 111-OP3 of the sub-pixel defining layer 111. Another portion of the third emission layer 3221 may overlap with the edge region (or edge) of the third sub-pixel electrode 3210 and be located on the sub-pixel defining layer 111.

[0089] The first emission layer 1221, the second emission layer 2221, and the third emission layer 3221 may include an organic material configured to emit light of a preset color. According to some embodiments, the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221 may include an inorganic material.

[0090] The first emission layer 1221, the second emission layer 2221, and the third emission layer 3221 may include materials configured to emit light of different colors. According to some embodiments, the first emission layer 1221 may include a material configured to emit red light, the second emission layer 2221 may include a material configured to emit green light, and the third emission layer 3221 may include a material configured to emit blue light.

[0091] According to some embodiments, a common layer may be additionally located on and / or below the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221, wherein the common layer includes a hole injection layer, a hole transport layer, an electron transport layer, and / or an electron injection layer. According to some embodiments, a common layer including a hole injection layer and / or a hole transport layer may be located below each of the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221. According to some embodiments, a common layer including an electron transport layer and / or an electron injection layer may be located on each of the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221. According to some embodiments, a first common layer including a hole injection layer and / or a hole transport layer may be located below each of the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221, and a second common layer including an electron transport layer and / or an electron injection layer may be located on each of the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221.

[0092] The first opposing electrode 1222, the second opposing electrode 2222, and the third opposing electrode 3222 may be located on the first emission layer 1221, the second emission layer 2221, and the third emission layer 3221. As an example, the first opposing electrode 1222 may be located on the first emission layer 1221. The second opposing electrode 2222 may be located on the second emission layer 2221. The third opposing electrode 3222 may be located on the third emission layer 3221.

[0093] The first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222 may include a conductive material having a small work function. As an example, the first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222 may also include a (semi) transparent layer containing ITO, IZO, ZnO, or In on the (semi) transparent layer containing the above materials. 2 O 3 layer.

[0094] Although in Figure 4 1 and 2 show that the first stack 1220, the second stack 2220, and the third stack 3220 include tapered side surfaces relative to the upper surface of the sub-pixel defining layer 111, but embodiments of the present disclosure are not limited thereto. According to some embodiments, the first stack 1220, the second stack 2220, and the third stack 3220 include side surfaces that form a right angle with respect to the upper surface of the sub-pixel defining layer 111.

[0095] The 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may be located on the first stack 1220, the second stack 2220, and the third stack 3220. As an example, the 1-1 auxiliary layer 1230 may be located on the first stack 1220. The 1-2 auxiliary layer 2230 may be located on the second stack 2220. The 1-3 auxiliary layer 3230 may be located on the third stack 3220.

[0096] The 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may be in direct contact with the first opposing electrode 1222, the second opposing electrode 2222, and the third opposing electrode 3222. As an example, the 1-1 auxiliary layer 1230 may be located on the first opposing electrode 1222 and in direct contact with the first opposing electrode 1222. The 1-2 auxiliary layer 2230 may be located on the second opposing electrode 2222 and in direct contact with the second opposing electrode 2222. The 1-3 auxiliary layer 3230 may be located on the third opposing electrode 3222 and in direct contact with the third opposing electrode 3222.

[0097] The 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may have light transmittance and conductivity. As an example, the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may include a transparent conductive oxide. According to some embodiments, the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may include a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0098] The first encapsulation layer 310 may be located on the subpixel defining layer 111. The first encapsulation layer 310 may include a 1-1 encapsulation layer 1310, a 1-2 encapsulation layer 2310, and a 1-3 encapsulation layer 3310 partially overlapping the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210, respectively.

[0099] As an example, the 1-1 encapsulation layer 1310 may partially overlap the first subpixel electrode 1210 and be located on the subpixel defining layer 111. The 1-2 encapsulation layer 2310 may partially overlap the second subpixel electrode 2210 and be located on the subpixel defining layer 111. The 1-3 encapsulation layer 3310 may partially overlap the third subpixel electrode 3210 and be located on the subpixel defining layer 111.

[0100] The first encapsulation layer 310 may include first openings 310-OP1 respectively overlapping the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210. The first openings 310-OP1 may include a 1-1 opening 1310-OP, a 1-2 opening 2310-OP, and a 1-3 opening 3310-OP.

[0101] As an example, the 1-1 opening 1310-OP may be formed in the 1-1 encapsulation layer 1310 to overlap the first sub-pixel electrode 1210. The 1-2 opening 2310-OP may be formed in the 1-2 encapsulation layer 2310 to overlap the second sub-pixel electrode 2210. The 1-3 opening 3310-OP may be formed in the 1-3 encapsulation layer 3310 to overlap the third sub-pixel electrode 3210.

[0102] The 1-1 opening 1310-OP, the 1-2 opening 2310-OP, and the 1-3 opening 3310-OP may be penetration holes penetrating the first encapsulation layer 310. The 1-1 opening 1310-OP, the 1-2 opening 2310-OP, and the 1-3 opening 3310-OP may expose a portion of the upper surface of the 1-1 auxiliary layer 1230, a portion of the upper surface of the 1-2 auxiliary layer 2230, and a portion of the upper surface of the 1-3 auxiliary layer 3230. As an example, the 1-1 opening 1310-OP may expose a central portion of the upper surface of the 1-1 auxiliary layer 1230. The 1-2 opening 2310-OP may expose a central portion of the upper surface of the 1-2 auxiliary layer 2230. The 1-3 opening 3310-OP may expose a central portion of the upper surface of the 1-3 auxiliary layer 3230.

[0103] The 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may cover at least a portion of the first stack 1220, at least a portion of the second stack 2220, and at least a portion of the third stack 3220 and cover at least a portion of the 1-1 auxiliary layer 1230, at least a portion of the 1-2 auxiliary layer 2230, and at least a portion of the 1-3 auxiliary layer 3230.

[0104] As an example, the upper surface of the first stack 1220 may be covered by the 1-1 auxiliary layer 1230. Each side surface of the first stack 1220 may be covered by the 1-1 encapsulation layer 1310. Each side surface of the 1-1 auxiliary layer 1230 may be covered by the 1-1 encapsulation layer 1310. An edge region (or edge) of the upper surface of the 1-1 auxiliary layer 1230 may be covered by the 1-1 encapsulation layer 1310. An area (e.g., a central area) of the upper surface of the 1-1 auxiliary layer 1230 that is not covered by the 1-1 encapsulation layer 1310 may overlap with the 1-1 opening 1310-OP. The 1-1 encapsulation layer 1310 may be in direct contact with the first stack 1220 and the 1-1 auxiliary layer 1230.

[0105] The 1-1 auxiliary layer 1230 and the 1-1 encapsulation layer 1310 may be configured to prevent the first stack 1220 from being exposed to the outside air. In particular, the 1-1 auxiliary layer 1230 and the 1-1 encapsulation layer 1310 may be configured to prevent moisture from being transmitted to the first opposing electrode 1222, thereby preventing oxidation of a metal material included in the first opposing electrode 1222.

[0106] The upper surface of the second stack 2220 may be covered by the 1-2 auxiliary layer 2230. Each side surface of the second stack 2220 may be covered by the 1-2 encapsulation layer 2310. Each side surface of the 1-2 auxiliary layer 2230 may be covered by the 1-2 encapsulation layer 2310. An edge region (or edge) of the upper surface of the 1-2 auxiliary layer 2230 may be covered by the 1-2 encapsulation layer 2310. An area (e.g., a central area) of the upper surface of the 1-2 auxiliary layer 2230 that is not covered by the 1-2 encapsulation layer 2310 may overlap with the 1-2 opening 2310-OP. The 1-2 encapsulation layer 2310 may be in direct contact with the second stack 2220 and the 1-2 auxiliary layer 2230.

[0107] The 1-2 auxiliary layer 2230 and the 1-2 encapsulation layer 2310 may be configured to prevent the second stack 2220 from being exposed to the outside air. In particular, the 1-2 auxiliary layer 2230 and the 1-2 encapsulation layer 2310 may be configured to prevent moisture from being transmitted to the second opposing electrode 2222, thereby preventing oxidation of a metal material included in the second opposing electrode 2222.

[0108] The upper surface of the third stack 3220 may be covered by the 1-3 auxiliary layer 3230. Each side surface of the third stack 3220 may be covered by the 1-3 encapsulation layer 3310. Each side surface of the 1-3 auxiliary layer 3230 may be covered by the 1-3 encapsulation layer 3310. The edge region (or edge) of the upper surface of the 1-3 auxiliary layer 3230 may be covered by the 1-3 encapsulation layer 3310. The region (e.g., the central region) of the upper surface of the 1-3 auxiliary layer 3230 that is not covered by the 1-3 encapsulation layer 3310 may overlap with the 1-3 opening 3310-OP. The 1-3 encapsulation layer 3310 may be in direct contact with the third stack 3220 and the 1-3 auxiliary layer 3230.

[0109] The 1-3 auxiliary layer 3230 and the 1-3 encapsulation layer 3310 may be configured to prevent the third stack 3220 from being exposed to the outside air. In particular, the 1-3 auxiliary layer 3230 and the 1-3 encapsulation layer 3310 may be configured to prevent moisture from being transmitted to the third opposing electrode 3222, thereby preventing oxidation of the metal material included in the third opposing electrode 3222.

[0110] The first encapsulation layer 310 may include a second opening 310 - OP2 between adjacent two of the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 .

[0111] As an example, the second opening 310 - OP2 may be located between the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310 and between the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310 .

[0112] The second opening 310-OP2 may be a penetration hole penetrating the first encapsulation layer 310. Thus, a portion of the sub-pixel defining layer 111 may be exposed through the second opening 310-OP2. As an example, a portion of the sub-pixel defining layer 111 may be exposed in a region between the first sub-pixel electrode 1210 and the second sub-pixel electrode 2210 through the second opening 310-OP2 located between the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310. A portion of the sub-pixel defining layer 111 may be exposed in a region between the second sub-pixel electrode 2210 and the third sub-pixel electrode 3210 through the second opening 310-OP2 located between the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310.

[0113] In other words, the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may be separated from each other. As an example, the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310 may be separated from each other and located on the sub-pixel defining layer 111, and the second opening 310-OP2 is between the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310. The 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310 may be separated from each other and located on the sub-pixel defining layer 111, and the second opening 310-OP2 is between the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310.

[0114] The first encapsulation layer 310 may include an inorganic insulating material. As an example, the first encapsulation layer 310 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ) and / or inorganic insulating materials of silicon oxynitride (SiON).

[0115] The 2-2 auxiliary layer 2240 and the 2-3 auxiliary layer 3240 may be respectively located on the second sub-pixel electrode 2210 and the third sub-pixel electrode 3210. As an example, the 2-2 auxiliary layer 2240 may be located between the second sub-pixel electrode 2210 and the second stack 2220 (or the second emission layer 2221). The 2-3 auxiliary layer 3240 may be located between the third sub-pixel electrode 3210 and the third stack 3220 (or the third emission layer 3221).

[0116] A portion of the 2-2 auxiliary layer 2240 may overlap the second sub-pixel electrode 2210. As an example, a central area of ​​the 2-2 auxiliary layer 2240 may be located in the 3-2 opening 111-OP2 of the sub-pixel defining layer 111 and may overlap the central area of ​​the second sub-pixel electrode 2210. In this case, the 2-2 auxiliary layer 2240 may be in direct contact with the second sub-pixel electrode 2210.

[0117] The edge region (or edge) of the 2-2 auxiliary layer 2240 may overlap the edge region (or edge) of the second sub-pixel electrode 2210 and be located on the sub-pixel defining layer 111. That is, the edge region (or edge) of the 2-2 auxiliary layer 2240 may be located on the upper surface of the sub-pixel defining layer 111 covering the edge region (or edge) of the second sub-pixel electrode 2210. In other words, a portion of the sub-pixel defining layer 111 may be arranged between the edge region (or edge) of the 2-2 auxiliary layer 2240 and the edge region (or edge) of the second sub-pixel electrode 2210.

[0118] A portion of the 2-3 auxiliary layer 3240 may overlap the third sub-pixel electrode 3210. As an example, a central area of ​​the 2-3 auxiliary layer 3240 may be located in the 3-3 opening 111-OP3 of the sub-pixel defining layer 111 and may overlap the central area of ​​the third sub-pixel electrode 3210. In this case, the 2-3 auxiliary layer 3240 may be in direct contact with the third sub-pixel electrode 3210.

[0119] The edge region (or edge) of the 2-3 auxiliary layer 3240 may overlap the edge region (or edge) of the third sub-pixel electrode 3210 and be located on the sub-pixel defining layer 111. That is, the edge region (or edge) of the 2-3 auxiliary layer 3240 may be located on the upper surface of the sub-pixel defining layer 111 covering the edge region (or edge) of the third sub-pixel electrode 3210. In other words, a portion of the sub-pixel defining layer 111 may be arranged between the edge region (or edge) of the 2-3 auxiliary layer 3240 and the edge region (or edge) of the third sub-pixel electrode 3210.

[0120] The auxiliary layer may not be located between the first stack 1220 (or the first emission layer 1221) and the first sub-pixel electrode 1210. That is, the first emission layer 1221 may be in direct contact with the first sub-pixel electrode 1210.

[0121] In other words, the number of layers between the first subpixel electrode 1210 and the first opposing electrode 1222 may be different from the number of layers between the second subpixel electrode 2210 and the second opposing electrode 2222. According to some embodiments, because a portion of the subpixel defining layer 111 and the first emission layer 1221 may be located between the first subpixel electrode 1210 and the first opposing electrode 1222, two layers may be located between the first subpixel electrode 1210 and the first opposing electrode 1222. Because a portion of the subpixel defining layer 111, the second emission layer 2221, and the 2-2 auxiliary layer 2240 may be located between the second subpixel electrode 2210 and the second opposing electrode 2222, three layers may be located between the second subpixel electrode 2210 and the second opposing electrode 2222.

[0122] Side surfaces of the 2-2 auxiliary layer 2240 and side surfaces of the 2-3 auxiliary layer 3240 may be covered by the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310 .

[0123] As an example, the upper surface of the 2-2 auxiliary layer 2240 may be covered by the second emission layer 2221. Each side surface of the 2-2 auxiliary layer 2240 may be covered by the 1-2 encapsulation layer 2310. In this case, the 2-2 auxiliary layer 2240 may be in direct contact with the second emission layer 2221 and the 1-2 encapsulation layer 2310.

[0124] The upper surface of the 2-3 auxiliary layer 3240 may be covered by the third emission layer 3221. Each side surface of the 2-3 auxiliary layer 3240 may be covered by the 1-3 encapsulation layer 3310. In this case, the 2-3 auxiliary layer 3240 may be in direct contact with the third emission layer 3221 and the 1-3 encapsulation layer 3310.

[0125] The 2-2 auxiliary layer 2240 and the 2-3 auxiliary layer 3240 may include a metal material. As an example, the 2-2 auxiliary layer 2240 and the 2-3 auxiliary layer 3240 may include a metal oxide. According to some embodiments, the 2-2 auxiliary layer 2240 and the 2-3 auxiliary layer 3240 may include a metal material such as aluminum oxide (AlO x ), molybdenum oxide (MoO x ) and / or tungsten oxide (WO x ) of metal oxides.

[0126] The common electrode 250 may be located on the first encapsulation layer 310. As an example, the common electrode 250 may be arranged to cover the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310. In this case, the common electrode 250 may be in direct contact with the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310.

[0127] The common electrode 250 may be integrally formed while completely covering the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 .

[0128] As an example, a portion of the common electrode 250 may be located in the 1-1 opening 1310-OP, the 1-2 opening 2310-OP, and the 1-3 opening 3310-OP. The portion of the common electrode 250 located in the 1-1 opening 1310-OP, the 1-2 opening 2310-OP, and the 1-3 opening 3310-OP may be in direct contact with the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230.

[0129] In other words, the 1-1 auxiliary layer 1230 , the 1-2 auxiliary layer 2230 , and the 1-3 auxiliary layer 3230 may be located between the first stack 1220 , the second stack 2220 , and the third stack 3220 and the common electrode 250 , respectively.

[0130] As an example, the 1-1 auxiliary layer 1230 may be located between the first stack 1220 and the common electrode 250. The 1-2 auxiliary layer 2230 may be located between the second stack 2220 and the common electrode 250. The 1-3 auxiliary layer 3230 may be located between the third stack 3220 and the common electrode 250.

[0131] A portion of the common electrode 250 may be located in the second opening 310-OP2. As an example, a portion of the common electrode 250 may be located in the second opening 310-OP2 formed between the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310. A portion of the common electrode 250 may be located in the second opening 310-OP2 formed between the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310. In this case, the common electrode 250 may be in direct contact with the sub-pixel defining layer 111.

[0132] The common electrode 250 may have light transmittance and conductivity. As an example, the common electrode 250 may include a transparent conductive oxide. According to some embodiments, the common electrode 250 may include a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0133] The common electrode 250 may have conductivity and be integrally formed. The common electrode 250 may be in direct contact with the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230, and the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230 may be in direct contact with the first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222. Therefore, the first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222 may be electrically connected to each other through the common electrode 250 and the 1-1 auxiliary layer 1230, the 1-2 auxiliary layer 2230, and the 1-3 auxiliary layer 3230. In this way, the same voltage may be applied to the first relative electrode 1222, the second relative electrode 2222, and the third relative electrode 3222.

[0134] Figure 5 is a schematic cross-sectional view of a portion of a display device according to some embodiments.

[0135] refer to Figure 5 , you can also find Figure 4 In the illustrated embodiment, a second encapsulation layer 320 is employed.

[0136] The second encapsulation layer 320 may cover the common electrode 250. In this case, the second encapsulation layer 320 may be in direct contact with the common electrode 250.

[0137] A portion of the second encapsulation layer 320 may be located in the 1-1 opening 1310-OP, the 1-2 opening 2310-OP, and the 1-3 opening 3310-OP. The second encapsulation layer 320 may fill at least a portion of the 1-1 opening 1310-OP, at least a portion of the 1-2 opening 2310-OP, and at least a portion of the 1-3 opening 3310-OP.

[0138] According to some embodiments, second encapsulation layer 320 may fill at least a portion (e.g., all) of 1-1 opening 1 310-OP. Second encapsulation layer 320 may fill at least a portion (e.g., all) of 1-2 opening 2 310-OP. Second encapsulation layer 320 may fill at least a portion (e.g., all) of 1-3 opening 3 310-OP.

[0139] A portion of the second encapsulation layer 320 may be located in the second opening 310 - OP2 . The second encapsulation layer 320 may fill at least a portion (eg, the entirety) of the second opening 310 - OP2 .

[0140] As an example, a portion of the second encapsulation layer 320 may be located in the space between the 1-1 encapsulation layer 1310 and the 1-2 encapsulation layer 2310 and may fill at least a portion (e.g., all) of the second opening 310-OP2. A portion of the second encapsulation layer 320 may be located in the space between the 1-2 encapsulation layer 2310 and the 1-3 encapsulation layer 3310 and may fill at least a portion (e.g., all) of the second opening 310-OP2.

[0141] The second encapsulation layer 320 may include an inorganic insulating material. As an example, the second encapsulation layer 320 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ) and / or an inorganic insulating material of silicon oxynitride (SiON). According to some embodiments, the second encapsulation layer 320 may include the same material as the first encapsulation layer 310. According to some embodiments, the second encapsulation layer 320 may include a different material from the first encapsulation layer 310.

[0142] Figure 6 is a schematic enlarged plan view of a display device according to some embodiments.

[0143] The first subpixel P1, the second subpixel P2, and the third subpixel P3, each including a display element and a first encapsulation layer 310, may be arranged in the display area DA.

[0144] The first subpixel P1, the second subpixel P2, and the third subpixel P3 may respectively include a first stack 1220, a second stack 2220, and a third stack 3220 each including an emission layer.

[0145] The first subpixel P1 may include a first stack 1220 including an emission layer. The second subpixel P2 may include a second stack 2220 including an emission layer. The third subpixel P3 may include a third stack 3220 including an emission layer.

[0146] The first subpixel P1 , the second subpixel P2 , and the third subpixel P3 may be configured to emit light of different colors, respectively.

[0147] According to some embodiments, the first stack 1220 may include a material configured to emit red light, and the first subpixel P1 may be configured to emit red light. The second stack 2220 may include a material configured to emit green light, and the second subpixel P2 may be configured to emit green light. The third stack 3220 may include a material configured to emit blue light, and the third subpixel P3 may be configured to emit blue light.

[0148] The first encapsulation layer 310 may include a 1-1 encapsulation layer 1310 , a 1-2 encapsulation layer 2310 , and a 1-3 encapsulation layer 3310 surrounding the first stack 1220 , the second stack 2220 , and the third stack 3220 , respectively.

[0149] The 1-1 encapsulation layer 1310 may have a shape surrounding the first stack 1220. The 1-2 encapsulation layer 2310 may have a shape surrounding the second stack 2220. The 1-3 encapsulation layer 3310 may have a shape surrounding the third stack 3220. As an example, the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may each have a frame shape in a plan view.

[0150] The 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 may include 1-1 openings 1310 -OP, 1-2 openings 2310 -OP, and 1-3 openings 3310 -OP respectively exposing portions of the first stack 1220 , the second stack 2220 , and the third stack 3220 .

[0151] As an example, the 1-1 encapsulation layer 1310 may include a 1-1 opening 1310-OP overlapping a central portion of the first stack 1220. The 1-2 encapsulation layer 2310 may include a 1-2 opening 2310-OP overlapping a central portion of the second stack 2220. The 1-3 encapsulation layer 3310 may include a 1-3 opening 3310-OP overlapping a central portion of the third stack 3220.

[0152] Portions of the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 may overlap portions of the first stack 1220 , the second stack 2220 , and the third stack 3220 , respectively.

[0153] As an example, an edge region (or edge) of the first stack 1220 may overlap with an inner edge region (or edge) of the 1-1 encapsulation layer 1310 adjacent to the 1-1 opening 1310-OP. An edge region (or edge) of the second stack 2220 may overlap with an inner edge region (or edge) of the 1-2 encapsulation layer 2310 adjacent to the 1-2 opening 2310-OP. An edge region (or edge) of the third stack 3220 may overlap with an inner edge region (or edge) of the 1-3 encapsulation layer 3310 adjacent to the 1-3 opening 3310-OP.

[0154] The 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may be separated from each other. In other words, the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may each have an isolated shape or an island shape.

[0155] The first encapsulation layer 310 may include a second opening 310 - OP2 between adjacent two of the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 .

[0156] In a plan view, the second opening 310-OP2 may have a mesh (or mesh) structure. As an example, the second opening 310-OP2 may have a mesh (or mesh) structure surrounding a corresponding portion of the first encapsulation layer 310 (e.g., 1-1 encapsulation layer 1310, 1-2 encapsulation layer 2310, and 1-3 encapsulation layer 3310). Alternatively, the second opening 310-OP2 has a mesh (or mesh) structure, and a corresponding portion of the first encapsulation layer 310 (e.g., 1-1 encapsulation layer 1310, 1-2 encapsulation layer 2310, and 1-3 encapsulation layer 3310) may be located in a corresponding hole of the mesh (or mesh) structure of the second opening 310-OP2.

[0157] According to some embodiments, a portion of the second opening 310-OP2 may be located in a space between the adjacent 1-1 encapsulation layer 1310 and 1-2 encapsulation layer 2310. A portion of the second opening 310-OP2 may be located in a space between the adjacent 1-2 encapsulation layer 2310 and 1-3 encapsulation layer 3310.

[0158] like Figure 6As shown in , the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may each be provided in plurality, and the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 surrounding the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, respectively, may be provided in plurality. In this case, the second opening 310-OP2 may be located between the first encapsulation layers 310 adjacent to each other. As an example, a portion of the second opening 310-OP2 may be located between a portion of the first encapsulation layer 310 surrounding the first sub-pixel P1 (e.g., the 1-1 encapsulation layer 1310) and a portion of the first encapsulation layer 310 surrounding another sub-pixel arranged in the -y direction of the first sub-pixel P1 (e.g., the 1-1 encapsulation layer 1310).

[0159] A portion of the sub-pixel defining layer 111 may be exposed through a separation space or a second opening 310 - OP2 between the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , and the 1-3 encapsulation layer 3310 .

[0160] Although in Figure 6 , the shapes of the first subpixel P1, the second subpixel P2, and the third subpixel P3, as well as the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 are shown as approximately quadrilateral shapes with angled corners, but are not limited thereto according to the embodiments of the present disclosure. According to some embodiments, the first subpixel P1, the second subpixel P2, and the third subpixel P3, as well as the 1-1 encapsulation layer 1310, the 1-2 encapsulation layer 2310, and the 1-3 encapsulation layer 3310 may each have a shape such as an N-gon (N is a natural number of 3 or greater) shape or an elliptical shape, or a shape with rounded corners. However, the shapes may be variously modified.

[0161] FIG. 7A to FIG. 7P is a schematic cross-sectional view illustrating a state corresponding to a process of manufacturing a display device according to some embodiments.

[0162] refer to Fig. 7A , the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210 may be arranged to be spaced apart from each other on the second organic insulating layer 109. The subpixel defining layer 111 may include an opening overlapping with a central portion of each of the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210 and located on the second organic insulating layer 109. Alternatively, the subpixel defining layer 111 may cover an edge region (or edge) of the first subpixel electrode 1210, the second subpixel electrode 2210, and the third subpixel electrode 3210 and be located on the second organic insulating layer 109.

[0163] The first subpixel electrode 1210 , the second subpixel electrode 2210 , and the third subpixel electrode 3210 may be arranged to be separated from each other. A portion of the subpixel defining layer 111 may be located between separation spaces between the first subpixel electrode 1210 , the second subpixel electrode 2210 , and the third subpixel electrode 3210 .

[0164] The first stacked layer 1220' may be arranged to cover the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210 and the sub-pixel defining layer 111. The first stacked layer 1220' may include a first light emitting material layer 1221' and a first opposing electrode layer 1222' on the first light emitting material layer 1221', wherein the first light emitting material layer 1221' is in direct contact with the first sub-pixel electrode 1210, the second sub-pixel electrode 2210, and the third sub-pixel electrode 3210.

[0165] The 1-1 auxiliary material layer 1230' may be positioned on the first stacked layer 1220'. As an example, the 1-1 auxiliary material layer 1230' may be positioned on the first opposing electrode layer 1222'. The first photoresist PR1 may be positioned on the 1-1 auxiliary material layer 1230' to overlap with the first sub-pixel electrode 1210.

[0166] The first light emitting material layer 1221' may include the first emission layer 1221 (see Figure 4 ) The first relative electrode layer 1222' may include the same material as the first relative electrode 1222 (see Figure 4 ) The 1-1 auxiliary material layer 1230' may include the same material as the 1-1 auxiliary layer 1230 (see Figure 4 )same materials.

[0167] refer to Figure 7B , a first stack 1220 and a 1-1 auxiliary layer 1230 may be formed. The first stack layer 1220′ may be etched using the first photoresist PR1 as a mask (see Fig. 7A ) and a portion of 1-1 auxiliary material layer 1230' (see Fig. 7A ). The etching process may include dry etching.

[0168] The first stack 1220 and the 1-1 auxiliary layer 1230 may be remaining portions after the etching process.

[0169] As an example, the first stack 1220 may be formed by etching the first stack layer 1220′ (see Fig. 7A ) is a portion of the remaining portion after etching. The 1-1 auxiliary layer 1230 may be a portion of the remaining portion after etching the 1-1 auxiliary material layer 1230' (see Fig. 7A ) after the remainder.

[0170] In other words, the first stacked layer 1220′ may be patterned by using the first photoresist PR1 as a mask (see Fig. 7A ) and 1-1 auxiliary material layer 1230' (see Fig. 7A ) to form a first stack 1220 and a 1-1 auxiliary layer 1230.

[0171] refer to Figure 7C , the first photoresist PR1 can be removed (see Figure 7B ). Remove the first photoresist PR1 (see Figure 7B ) may include an ashing process (eg, a dry ashing process).

[0172] exist Figure 7C In the process shown in , the side surface of the first stack 1220 and the upper surface and side surface of the 1-1 auxiliary layer 1230 may be exposed. In this case, when the first stack 1220 and the 1-1 auxiliary layer 1230 are exposed to the outside air, there may be a risk of moisture transmission and / or oxidation. As an example, there may be a risk of oxidation of the side surface of the first relative electrode 1222. Therefore, in order to prevent the first stack 1220 and the 1-1 auxiliary layer 1230 from being exposed to the outside air, according to some embodiments, from the present process to Fig.7D The process shown in can maintain the vacuum state.

[0173] refer to Fig.7D , you can Figure 7C In the embodiment shown in FIG. 1 , a 1-1 encapsulation material layer 1310 ′ is used. The 1-1 encapsulation material layer 1310 ′ may cover the 1-1 auxiliary layer 1230 , the sub-pixel defining layer 111 , the second sub-pixel electrode 2210 , and the third sub-pixel electrode 3210 .

[0174] The second photoresist PR2 may be positioned on the 1-1 encapsulation material layer 1310 ′ to overlap the first sub-pixel electrode 1210 .

[0175] refer to Fig. 7E , a 1-1 encapsulation layer 1310 can be formed. A second photoresist PR2 (see Fig.7D ) as a mask to etch the 1-1 packaging material layer 1310' (see Fig.7D ). The etching process may include dry etching.

[0176] The 1-1 encapsulation layer 1310 may be a portion remaining after the etching process. As an example, the 1-1 encapsulation layer 1310 may be a portion remaining after the etching process. Fig.7D ) after a part of it.

[0177] In other words, by using the second photoresist PR2 (see Fig.7D ) as a mask to pattern the 1-1 packaging material layer 1310 ′ (see Fig.7D ) to form a 1-1 encapsulation layer 1310.

[0178] After forming the 1-1 encapsulation layer 1310, the second photoresist PR2 may be removed (see Fig.7D ).

[0179] refer to Figure 7F , you can find it in About Fig. 7E In the illustrated embodiment, a 2-2 auxiliary material layer 2240' is used.

[0180] The 2-2 auxiliary material layer 2240 ′ may cover the 1-1 encapsulation layer 1310 , the sub-pixel defining layer 111 , the second sub-pixel electrode 2210 , and the third sub-pixel electrode 3210 .

[0181] refer to Figure 7G , you can find it in About Figure 7F The illustrated embodiment employs a second stacked layer 2220' and 1-2 auxiliary material layers 2230'.

[0182] As an example, the second stacked layer 2220' may be positioned on the 2-2 auxiliary material layer 2240'. The second stacked layer 2220' may include a second light emitting material layer 2221' and a second opposing electrode layer 2222'. The second opposing electrode layer 2222' may be positioned on the second light emitting material layer 2221'.

[0183] The 1-2 auxiliary material layer 2230' may be positioned on the second stacked layer 2220'. As an example, the 1-2 auxiliary material layer 2230' may be positioned on the second opposing electrode layer 2222'. The third photoresist PR3 may be positioned on the 1-2 auxiliary material layer 2230' to overlap with the second sub-pixel electrode 2210.

[0184] The second light emitting material layer 2221' may include the second emission layer 2221 (see Figure 4 ) The second relative electrode layer 2222' may include the same material as the second relative electrode 2222 (see Figure 4 ) The 1-2 auxiliary material layer 2230' may include the same material as the 1-2 auxiliary layer 2230 (see Figure 4 )same materials.

[0185] refer to Figure 7H , a second stack 2220, a 1-2 auxiliary layer 2230, and a 2-2 auxiliary layer 2240 may be formed. A third photoresist PR3 (see Figure 7G ) as a mask to etch the second stacked layer 2220' (see Figure 7G ) part, 1-2 auxiliary material layer 2230 '(see Figure 7G ) and 2-2 auxiliary material layer 2240 '(see Figure 7G ) portion. The etching process may include dry etching.

[0186] The second stack 2220 , the 1-2 auxiliary layer 2230 , and the 2-2 auxiliary layer 2240 may be portions remaining after an etching process, respectively.

[0187] As an example, the second stack 2220 may be formed by etching the second stack layer 2220′ (see Figure 7G ) The remaining portion after etching. The 1-2 auxiliary layer 2230 may be the portion remaining after etching the 1-2 auxiliary material layer 2230' (see Figure 7G ) The remaining portion after etching. 2-2 auxiliary layer 2240 may be the auxiliary material layer 2240' (see Figure 7G ) after the remainder.

[0188] In other words, by using the third photoresist PR3 (see Figure 7G ) as a mask to pattern the second stacked layer 2220' (see Figure 7G )、1-2 auxiliary material layer 2230 '(see Figure 7G ) and 2-2 auxiliary material layer 2240' (see Figure 7G ) to form a second stack 2220, a 1-2 auxiliary layer 2230 and a 2-2 auxiliary layer 2240.

[0189] After forming the second stack 2220, the 1-2 auxiliary layer 2230, and the 2-2 auxiliary layer 2240, the third photoresist PR3 may be removed (see Figure 7G ). Remove the third photoresist PR3 (see Figure 7G ) may include an ashing process (eg, a dry ashing process).

[0190] exist Figure 7H In the process shown in , the side surface of the second stack 2220 and the upper surface and side surface of the 1-2 auxiliary layer 2230 may be exposed. In this case, when the second stack 2220 and the 1-2 auxiliary layer 2230 are exposed to the outside air, there may be a risk of moisture transmission and / or oxidation. As an example, there may be a risk of oxidation of the side surface of the second relative electrode 2222. Therefore, in order to prevent the second stack 2220 and the 1-2 auxiliary layer 2230 from being exposed to the outside air, according to some embodiments, from the present process to Fig.7I The process shown in can maintain the vacuum state.

[0191] refer to Fig.7I , you can find it in About Figure 7HThe 1-2 encapsulation material layer 2310 ′ is used in the illustrated embodiment and may cover the 1-1 encapsulation layer 1310 , the second stack 2220 , the 1-2 auxiliary layer 2230 , the 2-2 auxiliary layer 2240 , the sub-pixel defining layer 111 and the third sub-pixel electrode 3210 .

[0192] The fourth photoresist PR4 may be positioned on the 1-2 encapsulation material layer 2310 ′ to overlap the second sub-pixel electrode 2210 .

[0193] refer to Figure 7J , a 1-2 encapsulation layer 2310 can be formed. A fourth photoresist PR4 (see Fig.7I ) as a mask to etch the 1-2 packaging material layer 2310' (see Fig.7I ). The etching process may include dry etching.

[0194] The 1-2 encapsulation layer 2310 may be a portion remaining after the etching process. As an example, the 1-2 encapsulation layer 2310 may be a portion remaining after the etching process. Fig.7I ) after a part of it.

[0195] In other words, by using the fourth photoresist PR4 (see Fig.7I ) as a mask to pattern the 1-2 packaging material layer 2310' (see Fig.7I ) to form a 1-2 encapsulation layer 2310.

[0196] After forming the 1-2 encapsulation layer 2310, the fourth photoresist PR4 may be removed (see Fig.7I ).

[0197] refer to Figure 7K , you can find it in About Figure 7J In the illustrated embodiment, 2-3 auxiliary material layers 3240' are used.

[0198] The 2-3 auxiliary material layer 3240 ′ may cover the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , the sub-pixel defining layer 111 , and the third sub-pixel electrode 3210 .

[0199] refer to Figure 7L , you can find it in About Figure 7K In the illustrated embodiment, a third stacked layer 3220' and 1-3 auxiliary material layers 3230' are used.

[0200] As an example, the third stacked layer 3220' may be positioned on the 2-3 auxiliary material layer 3240'. The third stacked layer 3220' may include a third light emitting material layer 3221' and a third opposing electrode layer 3222'. The third opposing electrode layer 3222' may be positioned on the third light emitting material layer 3221'.

[0201] The 1-3 auxiliary material layer 3230' may be positioned on the third stacked layer 3220'. As an example, the 1-3 auxiliary material layer 3230' may be positioned on the third opposing electrode layer 3222'. The fifth photoresist PR5 may be positioned on the 1-3 auxiliary material layer 3230' to overlap with the third sub-pixel electrode 3210.

[0202] The third light emitting material layer 3221′ may include the third emission layer 3221 (see Figure 4 ) The third relative electrode layer 3222' may include the same material as the third relative electrode 3222 (see Figure 4 ) The 1-3 auxiliary material layer 3230' may include the same material as the 1-3 auxiliary layer 3230 (see Figure 4 )same materials.

[0203] refer to Figure 7M , a third stack 3220, a 1-3 auxiliary layer 3230, and a 2-3 auxiliary layer 3240 may be formed. A fifth photoresist PR5 (see Figure 7L ) as a mask to etch the third stacked layer 3220′ (see Figure 7L ) part, 1-3 auxiliary material layer 3230 '(see Figure 7L ) and 2-3 auxiliary material layers 3240' (see Figure 7L ) portion. The etching process may include dry etching.

[0204] The third stack 3220 , the 1-3 auxiliary layer 3230 , and the 2-3 auxiliary layer 3240 may be portions remaining after the etching process, respectively.

[0205] As an example, the third stack 3220 may be formed by etching the third stack layer 3220′ (see Figure 7L ) The remaining portion after etching. The 1-3 auxiliary layer 3230 may be the portion remaining after etching the 1-3 auxiliary material layer 3230' (see Figure 7L ) The remaining portion after etching. The 2-3 auxiliary layer 3240 may be the auxiliary material layer 3240′ (see Figure 7L ) after the remainder.

[0206] In other words, by using the fifth photoresist PR5 (see Figure 7L ) as a mask to pattern the third stacked layer 3220' (see Figure 7L )、1-3 auxiliary material layer 3230 '(see Figure 7L ) and 2-3 auxiliary material layers 3240' (see Figure 7L ) to form a third stack 3220, a 1-3 auxiliary layer 3230 and a 2-3 auxiliary layer 3240.

[0207] After forming the third stack 3220, the 1-3 auxiliary layer 3230, and the 2-3 auxiliary layer 3240, the fifth photoresist PR5 may be removed (see Figure 7L ). Remove the fifth photoresist PR5 (see Figure 7L ) may include an ashing process (eg, a dry ashing process).

[0208] exist Figure 7M In the process shown in , the side surface of the third stack 3220 and the upper surface and side surface of the 1-3 auxiliary layer 3230 may be exposed. In this case, when the third stack 3220 and the 1-3 auxiliary layer 3230 are exposed to the outside air, there may be a risk of moisture transmission and / or oxidation. As an example, there may be a risk of oxidation of the side surface of the third relative electrode 3222. Therefore, in order to prevent the third stack 3220 and the 1-3 auxiliary layer 3230 from being exposed to the outside air, according to some embodiments, from the present process to Figure 7N The process shown in can maintain the vacuum state.

[0209] refer to Figure 7N , you can find it in About Figure 7M The illustrated embodiment uses a 1-3 encapsulation material layer 3310 ′, which may cover the 1-1 encapsulation layer 1310 , the 1-2 encapsulation layer 2310 , the third stack 3220 , the 1-3 auxiliary layer 3230 , the 2-3 auxiliary layer 3240 , and the sub-pixel defining layer 111 .

[0210] The sixth photoresist PR6 may be positioned on the 1-3 encapsulation material layer 3310 ′ to overlap the third sub-pixel electrode 3210 .

[0211] refer to Fig.7O , 1-3 encapsulation layers 3310 can be formed. The sixth photoresist PR6 (see Figure 7N ) as a mask to etch 1-3 packaging material layer 3310' (see Figure 7N ). The etching process may include dry etching.

[0212] 1-3 packaging layer 3310 may be a portion remaining after the etching process. As an example, 1-3 packaging layer 3310 may be a portion remaining after etching 1-3 packaging material layer 3310' (see Figure 7N ) after a part of it.

[0213] In other words, by using the sixth photoresist PR6 (see Figure 7N ) as a mask to pattern the 1-3 packaging material layer 3310 '(see Figure 7N ) to form a 1-3 encapsulation layer 3310.

[0214] After forming the 1-3 encapsulation layer 3310, the sixth photoresist PR6 may be removed (see Figure 7N ).

[0215] refer to Figure 7P , a 1-1 opening 1 310 -OP, a 1-2 opening 2 310 -OP and a 1-3 opening 3 310 -OP may be formed.

[0216] The 1-1 opening 1310 -OP may be formed by etching a portion of the 1-1 encapsulation layer 1310 . As an example, the 1-1 opening 1310 -OP may be formed by etching a portion of the upper surface of the 1-1 encapsulation layer 1310 in a region overlapping the 1-1 auxiliary layer 1230 .

[0217] A portion of the upper surface of the 1-1 auxiliary layer 1230 may be exposed through the 1-1 opening 1310-OP. As an example, a central portion of the upper surface of the 1-1 auxiliary layer 1230 may be exposed through the 1-1 opening 1310-OP. In other words, the 1-1 opening 1310-OP may pass through the 1-1 encapsulation layer 1310.

[0218] The 1-2 opening 2310-OP may be formed by etching a portion of the 1-2 encapsulation layer 2310. As an example, the 1-2 opening 2310-OP may be formed by etching a portion of the upper surface of the 1-2 encapsulation layer 2310 in a region overlapping the 1-2 auxiliary layer 2230.

[0219] A portion of the upper surface of the 1-2 auxiliary layer 2230 may be exposed through the 1-2 opening 2310-OP. As an example, a central portion of the upper surface of the 1-2 auxiliary layer 2230 may be exposed through the 1-2 opening 2310-OP. In other words, the 1-2 opening 2310-OP may pass through the 1-2 encapsulation layer 2310.

[0220] The 1-3 opening 3310-OP may be formed by etching a portion of the 1-3 encapsulation layer 3310. As an example, the 1-3 opening 3310-OP may be formed by etching a portion of the upper surface of the 1-3 encapsulation layer 3310 in a region overlapping the 1-3 auxiliary layer 3230.

[0221] A portion of the upper surface of the 1-3 auxiliary layer 3230 may be exposed through the 1-3 opening 3310-OP. As an example, a central portion of the upper surface of the 1-3 auxiliary layer 3230 may be exposed through the 1-3 opening 3310-OP. In other words, the 1-3 opening 3310-OP may pass through the 1-3 encapsulation layer 3310.

[0222] The processes of forming the 1-1 opening 1 310 -OP, the 1-2 opening 2 310 -OP, and the 1-3 opening 3 310 -OP may be performed simultaneously or individually.

[0223] When about Figure 7P In the embodiment shown, a common electrode 250 is used (see Figure 4 ), you can achieve Figure 4 The embodiment shown. Figure 7P In the embodiment shown, a common electrode 250 is used (see Figure 5 ) and a second encapsulation layer 320 (see Figure 5 ), you can achieve Figure 5 The embodiment shown in .

[0224] According to some embodiments having the above configuration, in a display device including a light emitting diode, since the upper surface of the opposing electrode is covered by the first auxiliary layer and the side surface of the opposing electrode is covered by the first encapsulation layer, the opposing electrode may not be exposed and oxidized during the deposition process. In addition, the opposing electrodes formed to be separated from each other may be electrically connected to each other through a common electrode. However, the scope of the embodiments according to the present disclosure is not limited by these characteristics.

[0225] It should be understood that the embodiments described herein should be considered to be merely illustrative and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. Display equipment, including: A first sub-pixel electrode and a second sub-pixel electrode spaced apart from each other; a sub-pixel defining layer, covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode; a first stack, including a first emitting layer and a first opposing electrode, on the subpixel defining layer and overlapping the first subpixel electrode; a second stack, including a second emitting layer and a second opposing electrode, on the subpixel defining layer and overlapping the second subpixel electrode; a first encapsulation layer covering each of an edge of the first stack and an edge of the second stack and comprising a first opening overlapping each of the first stack and the second stack and a second opening between the first stack and the second stack; as well as A common electrode is on the first encapsulation layer and is electrically connected to the first opposing electrode of the first stack and the second opposing electrode of the second stack.

2. The display device according to claim 1, wherein: The first encapsulation layer overlaps a portion of an upper surface and a side surface of the first stack and a portion of an upper surface and a side surface of the second stack. 3 . The display device according to claim 1 , further comprising a first auxiliary layer between the first opposing electrode and the common electrode and between the second opposing electrode and the common electrode, respectively.

4. The display device according to claim 1, further comprising a second auxiliary layer between the second subpixel electrode and the second emission layer, in, A central portion of the second auxiliary layer directly contacts the second sub-pixel electrode, and an outer portion of the second auxiliary layer is spaced apart from the second sub-pixel electrode by the sub-pixel defining layer.

5. The display device according to claim 1, wherein: The number of layers between the first subpixel electrode and the first opposing electrode is different from the number of layers between the second subpixel electrode and the second opposing electrode. 6 . The display device of claim 1 , further comprising a second encapsulation layer on the common electrode and extending to overlap the first stack and the second stack.

7. The display device according to claim 1, wherein: In a plan view, the second openings of the first encapsulation layer have a mesh structure surrounding each of the first openings.

8. Display equipment, including: A first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode spaced apart from each other; a subpixel defining layer covering an edge of each of the first subpixel electrode, the second subpixel electrode, and the third subpixel electrode and including an opening overlapping a central portion of each of the first subpixel electrode, the second subpixel electrode, and the third subpixel electrode; A first emission layer, a second emission layer and a third emission layer are respectively on the first sub-pixel electrode, the second sub-pixel electrode and the third sub-pixel electrode; A first relative electrode, a second relative electrode and a third relative electrode are respectively on the first emission layer, the second emission layer and the third emission layer; 1-1 an encapsulation layer, covering at least a portion of the first opposing electrode and at least a portion of the first emission layer, and including an opening overlapping a central portion of the first opposing electrode; 1-2 an encapsulation layer, covering at least a portion of the second opposing electrode and at least a portion of the second emission layer, and including an opening overlapping a central portion of the second opposing electrode; 1-3 an encapsulation layer, covering at least a portion of the third opposing electrode and at least a portion of the third emission layer, and comprising an opening overlapping a central portion of the third opposing electrode; as well as a common electrode on the first relative electrode, the second relative electrode and the third relative electrode and electrically connected to the first relative electrode, the second relative electrode and the third relative electrode, The 1-1 encapsulation layer, the 1-2 encapsulation layer and the 1-3 encapsulation layer have isolated shapes and are spaced apart from each other.

9. The display device according to claim 8, wherein: The common electrode contacts an upper surface of the sub-pixel defining layer in a space between adjacent encapsulation layers among the 1-1 encapsulation layer, the 1-2 encapsulation layer, and the 1-3 encapsulation layer.

10. The display device according to claim 8, further comprising: 1-1 auxiliary layer, between the first relative electrode and the common electrode; 1-2 auxiliary layer, between the second relative electrode and the common electrode; as well as 1-3 auxiliary layer, between the third relative electrode and the common electrode.

11. The display device according to claim 10, wherein: The 1-1 encapsulation layer directly contacts a portion of an upper surface and a side surface of the 1-1 auxiliary layer, a side surface of the first opposing electrode, and a side surface of the first emission layer.

12. The display device according to claim 8, further comprising a 2-2 auxiliary layer between the second sub-pixel electrode and the second emission layer, in, The first sub-pixel electrode directly contacts the first emission layer.

13. The display device of claim 8, further comprising a second encapsulation layer on the common electrode.

14. The display device according to claim 8, wherein: In a plan view, each of the 1-1 encapsulation layer, the 1-2 encapsulation layer, and the 1-3 encapsulation layer surrounds an edge of the first opposing electrode, an edge of the second opposing electrode, and an edge of the third opposing electrode.

15. A method for manufacturing a display device, the method comprising: forming a first sub-pixel electrode and a second sub-pixel electrode spaced apart from each other; forming a first stacked layer on the first sub-pixel electrode and the second sub-pixel electrode, wherein the first stacked layer includes a first light-emitting material layer and a first opposite electrode layer; forming a 1-1 auxiliary material layer on the first stacked layer; forming a first stack and a 1-1 auxiliary layer overlapping the first stack by etching a portion of the 1-1 auxiliary material layer and a portion of the first stack layer, wherein the first stack overlaps the first sub-pixel electrode and includes a first emission layer and a first opposing electrode; forming a 1-1 packaging material layer to cover the first stack and the 1-1 auxiliary layer; forming a 1-1 encapsulation layer by etching a portion of the 1-1 encapsulation material layer, wherein the 1-1 encapsulation layer completely overlaps an upper surface of the first stack and an upper surface of the 1-1 auxiliary layer; forming a second stacked layer on the 1-1 encapsulation layer and the second sub-pixel electrode, wherein the second stacked layer includes a second light-emitting material layer and a second relative electrode layer; forming 1-2 auxiliary material layers on the second stacked layer; Forming a second stack and a 1-2 auxiliary layer overlapping the second stack by etching a portion of the 1-2 auxiliary material layer and a portion of the second stack layer, wherein the second stack overlaps the second sub-pixel electrode and includes a second emission layer and a second opposing electrode; forming a 1-2 packaging material layer to cover the second stack and the 1-2 auxiliary layer; and forming a 1-2 encapsulation layer by etching a portion of the 1-2 encapsulation material layer, wherein the 1-2 encapsulation layer completely overlaps an upper surface of the second stack and an upper surface of the 1-2 auxiliary layer, Wherein, the 1-1 encapsulation layer and the 1-2 encapsulation layer are spaced apart from each other. 16 . The method of claim 15 , further comprising forming a first opening in each of the 1-1 encapsulation layer and the 1-2 encapsulation layer.

17. The method according to claim 16, wherein: The 1-1 encapsulation layer is in direct contact with a portion of the upper surface and side surface of the 1-1 auxiliary layer and a side surface of the first stack, and the 1-2 encapsulation layer is in direct contact with a portion of the upper surface and side surface of the 1-2 auxiliary layer and a side surface of the second stack.

18. The method according to claim 15, further comprising forming a second auxiliary material layer below the second stacked layer, in, Forming the second stack includes forming a second auxiliary layer by etching a portion of the second auxiliary material layer, the second auxiliary layer directly contacting an upper surface of the second sub-pixel electrode. 19 . The method of claim 16 , further comprising forming a common electrode layer overlapping the first opening of the 1-1 encapsulation layer and the first opening of the 1-2 encapsulation layer.

20. The method according to claim 19, further comprising forming a sub-pixel defining layer covering an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode, in, The common electrode layer directly contacts an upper surface of the sub-pixel defining layer in a separation region between the 1-1 encapsulation layer and the 1-2 encapsulation layer.

Images