Sensor and display device

Abstract

The invention discloses a sensor and a display device. The sensor includes: a light sensing element connected between a sensing node and a driving voltage line; a first transistor connected between the reset voltage line and the sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the sensing node; and a third transistor connected between the intermediate node and the readout line and including a gate electrode connected to the scan line. A voltage level of a reset voltage supplied to the reset voltage line varies according to a voltage level of a driving voltage supplied to the driving voltage line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0101286 filed in the Korean Intellectual Property Office on August 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device including a sensor. Background Art

[0004] Multimedia electronic devices such as televisions (TVs), mobile phones, tablet computers, navigation systems, or game consoles include display devices for displaying images. In addition to general input devices such as buttons, keyboards, or mice, electronic devices may also include display devices that can provide a touch-based input solution that allows users to easily and intuitively input information or commands.

[0005] The display panel of the display device may include a sensor that enables a touch-based input scheme to operate. The sensor may receive a reset voltage through a reset line and receive a drive voltage through a voltage line. However, the level of the reset voltage may vary depending on the position of the reset line and based on whether the level of the drive voltage changes, thereby reducing the performance of the sensor. Summary of the invention

[0006] At least one embodiment of the present disclosure provides a display device capable of maintaining the performance of a sensor even if a voltage level of a driving voltage supplied to a pixel and a sensor is changed.

[0007] According to an embodiment, the sensor includes a light sensing element, a first transistor, a second transistor, and a third transistor. The light sensing element is connected between a sensing node and a driving voltage line. The first transistor is connected between a reset voltage line and a sensing node. The second transistor is connected between a sensor driving voltage line and an intermediate node, and includes a gate electrode connected to the sensing node. The third transistor is connected between the intermediate node and a readout line, and includes a gate electrode connected to a scan line. The voltage level of the reset voltage supplied to the reset voltage line changes according to the voltage level of the driving voltage supplied to the driving voltage line. For example, the driving controller may determine the voltage level of the driving voltage, and change the reset voltage based on the determined voltage level of the driving voltage.

[0008] In an embodiment, the first transistor may be a transistor of a first type, and each of the second transistor and the third transistor may be a transistor of a second type different from the first type.

[0009] In an embodiment, the first transistor may include a gate electrode receiving a reset signal, and a voltage level of the reset signal may be changed according to a voltage level of the driving voltage.

[0010] In an embodiment, the light sensing element may include an anode connected to the sensing node and a cathode connected to the driving voltage line.

[0011] According to an embodiment, a display device includes a pixel, a sensor, a drive controller, and a voltage generator. The pixel includes a light-emitting element connected to a drive voltage line for transmitting a drive voltage. The sensor includes a light-sensing element connected to the drive voltage line and a reset voltage line for receiving a reset voltage. The drive controller receives an image signal and a control signal. The voltage generator generates a drive voltage and a reset voltage in response to the voltage control signal. The drive controller determines a voltage level of the drive voltage based on the image signal and the control signal, determines a voltage level of the reset voltage based on the determined voltage level of the drive voltage, and outputs a voltage control signal corresponding to the voltage level of the drive voltage and the voltage level of the reset voltage.

[0012] In an embodiment, the sensor may include: a light sensing element connected between a sensing node and a driving voltage line; a first transistor connected between a reset voltage line and the sensing node; a second transistor connected between the sensor driving voltage line and an intermediate node and including a gate electrode connected to the sensing node; and a third transistor connected between the intermediate node and a readout line and including a gate electrode connected to a scan line.

[0013] In an embodiment, the first transistor may be a transistor of a first type, and the second transistor and the third transistor may be transistors of a second type different from the first type.

[0014] In an embodiment, the light sensing element may include a cathode connected to the driving voltage line and an anode connected to the sensing node, and the light emitting element may include an anode and a cathode connected to the driving voltage line.

[0015] In an embodiment, the drive controller may include: a memory storing a voltage data signal, the voltage data signal including information about a voltage distribution of a driving voltage provided to a display panel; and a controller receiving the voltage data signal from the memory, determining a voltage level of a reset control voltage based on the voltage data signal, and outputting a voltage control signal corresponding to the voltage level of the reset control voltage.

[0016] In an embodiment, the voltage generator may further generate a reset control voltage in response to the voltage control signal.

[0017] In an embodiment, the display device may further include: a sensor driver outputting a scan signal for driving the pixel, and outputting a reset signal for driving the sensor.

[0018] In an embodiment, the sensor driver may output a reset signal corresponding to a voltage level of the reset control voltage.

[0019] In an embodiment, the first transistor may include a gate electrode receiving a reset signal.

[0020] According to an embodiment, a display device may include a display panel, a drive controller and a voltage generator. The display panel includes pixels and sensors. The drive controller receives an image signal and a control signal. The voltage generator generates a drive voltage and a reset voltage in response to the voltage control signal. Each of the sensors includes a light sensing element connected to a drive voltage line receiving a drive voltage and a reset voltage line receiving a reset voltage. The drive controller determines a voltage level of the drive voltage based on the image signal and the control signal, determines a voltage level of the reset voltage based on the determined voltage level of the drive voltage, and outputs a voltage control signal corresponding to the voltage level of the drive voltage and the voltage level of the reset voltage.

[0021] In an embodiment, the display device may further include: a sensor driver outputting a scan signal for driving the pixel, and outputting a reset signal for driving the sensor.

[0022] In an embodiment, the voltage generator may further generate a reset control voltage in response to the voltage control signal, and the sensor driver may output a reset signal corresponding to a voltage level of the reset control voltage.

[0023] In an embodiment, the display panel may include a first region and a second region, and the sensor may include a first sensor disposed in the first region and a second sensor disposed in the second region.

[0024] In an embodiment, the reset signal may include a first reset signal to be provided to the first sensor and a second reset signal to be provided to the second sensor, and a voltage level of the first reset signal and a voltage level of the second reset signal may be different from each other.

[0025] In an embodiment, the first sensor may include a first light sensing element connected between a first sensing node and a driving voltage line, and a first transistor connected between a reset voltage line and the first sensing node and including a gate electrode receiving a first reset signal. The second sensor may include a second light sensing element connected between a second sensing node and a driving voltage line, and a second transistor connected between the reset voltage line and the second sensing node and including a gate electrode receiving a second reset signal.

[0026] In an embodiment, the display panel may further include: a base layer; a circuit layer disposed on the base layer, the first transistor and the second transistor being disposed in the circuit layer; and an element layer disposed on the circuit layer and including the first light sensing element and the second light sensing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0029] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 4 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0031] Figure 5 is a circuit diagram of a pixel and a sensor according to an embodiment of the present disclosure.

[0032] Figure 6 yes Figure 5 A timing diagram of the operation of a pixel is shown in FIG.

[0033] Figure 7 yes Figure 5 0047] A timing diagram of the operation of the sensor is shown in FIG.

[0034] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0035] Fig. 9A and Fig. 9B is a diagram illustrating voltage distribution of a second driving voltage in a display panel.

[0036] Fig.10 is a graph illustrating changes in current density of a light sensing element.

[0037] Fig.11 is a block diagram of a drive controller according to an embodiment of the present disclosure.

[0038] Fig.12 is a diagram illustrating pixels and sensors provided in a display panel.

[0039] Fig.13A , Fig. 13B and Fig. 13C The diagram is provided to Fig.12 FIG. 4 is a diagram of a reset signal for a reset line illustrated in FIG. DETAILED DESCRIPTION

[0040] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals may represent the same components.

[0041] In the specification, the statement that a first component (or region, layer, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or coupled to the second component, or that a third component is interposed therebetween.

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view illustrating a display device DD according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0044] refer to Figure 1 and Figure 2 , the display device DD may be a device that is activated according to an electrical signal. For example, the display device DD may be a mobile phone, a tablet computer, a car navigation system, a game console, or a wearable device, but the present disclosure is not limited thereto. Figure 1 An example in which the display device DD is a smartphone is illustrated in FIG.

[0045] Despite Figure 1 A bar-shaped rigid display device DD is illustrated in FIG. 1 as an example, but the present disclosure is not limited thereto. For example, the display device DD may be a foldable, rollable, or slidable display device DD.

[0046] The upper surface of the display device DD may be defined as a display surface IS, and may have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD may be provided to a user through the display surface IS. Below, a normal direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the specification, the expression "when viewed from above the plane" may mean "when viewed in the third direction DR3". That is, the plane may be parallel to the surface defined by the first direction DR1 and the second direction DR2.

[0047] The display surface IS may be divided into a transparent area TA and a border area BZA. The transparent area TA may be an area in which the image IM is displayed. The user visually perceives the image IM through the transparent area TA. In an embodiment, the transparent area TA is illustrated as a quadrilateral shape whose vertices are rounded. However, this is illustrated as an example. The transparent area TA may have various shapes and is not limited to any particular shape.

[0048] The border area BZA is adjacent to the transparent area TA. The border area BZA may have a given color. The border area BZA may surround the transparent area TA. Therefore, the shape of the transparent area TA may be substantially defined by the border area BZA. However, this is illustrated as an example. The border area BZA may be disposed adjacent to only one side of the transparent area TA, or may be omitted.

[0049] The display device DD can sense external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, in addition to contact with a part of the body (such as the user's hand US_F), the external input may also include an external input (e.g., hovering) in which the user's hand US_F approaches the display device DD or is adjacent to the display device DD within a given distance. In addition, the external input may have various types such as a force type, a pressure type, a temperature type, and a light type. The external input may also be provided by a separate device such as an active pen or a digitizer pen. In addition, the display device DD can sense biometric information of the user applied from the outside.

[0050] The appearance of the display device DD may be realized by the window WM and the housing EDC. For example, the window WM and the housing EDC may be combined with each other, and the remaining components of the display device DD such as the display module DM may be accommodated in a space formed by the window WM and the housing EDC thus combined.

[0051] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other by an adhesive, or may have a glass substrate and a plastic film bonded to each other by an adhesive.

[0052] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components of the display device DD housed in the internal space from external impacts. A battery module for supplying power required for the overall operation of the display device DD may be interposed between the display module DM and the housing EDC.

[0053] The display module DM may include a display panel DP and an anti-reflection layer CFL.

[0054] The display panel DP may be a component that generates an image. The display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel. Below, a description will be given assuming that the display panel DP is an organic light-emitting display panel.

[0055] The display panel DP includes a base layer BL, a pixel layer PXL and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel or a rigid display panel folded around a folding axis.

[0056] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0057] The pixel layer PXL is disposed on the base layer BL. The pixel layer PXL may include a circuit layer DP_CL and a device layer DP_ED. The circuit layer DP_CL is interposed between the base layer BL and the device layer DP_ED.

[0058] In an embodiment, the circuit layer DP_CL includes at least one insulating layer and a circuit element. Below, the insulating layer included in the circuit layer DP_CL is referred to as an "intermediate insulating layer". In an embodiment, the intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The circuit layer DP_CL may further include a signal line connected to the pixel circuit and / or the sensor driving circuit.

[0059] As an example of the present disclosure, each of the multiple sensors may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, and the like. In addition, each of the multiple sensors may include an optical sensor that optically recognizes biometric information. According to an embodiment of the present disclosure, multiple sensors may be used to sense external inputs (e.g., a user's touch) as well as biometric information such as fingerprints. Accordingly, the display device DD does not need to include a separate input sensing layer for sensing external inputs. In this case, the thickness of the display device DD can become thinner, and thus the flexibility can be improved. This may make it possible to realize various types of display devices DD, such as the above-mentioned foldable, rollable, or slidable display device DD.

[0060] The element layer DP_ED may include a light emitting element included in each of the pixels and a light sensing element included in each of the sensors. As an example of the present disclosure, the light sensing element may be a photodiode. The light sensing element may be a sensor that senses light reflected by a user's fingerprint or reacts to light. Figure 8 The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0061] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0062] The anti-reflection layer CFL may be provided on the display panel DP. The anti-reflection layer CFL may reduce the reflectivity of external light incident from the outside of the display device DD. The anti-reflection layer CFL may be formed on the display panel DP by a continuous process, but the present disclosure is not limited thereto. For example, the anti-reflection layer CFL may include a color filter, a black matrix, and a planarization layer. The color filter may have a given arrangement. For example, the color filter may be arranged in consideration of the color of light emitted from the pixels included in the display panel DP. In an embodiment, the anti-reflection layer CFL includes a black matrix and a reflection control layer. The reflection control layer may selectively absorb light belonging to a partial band among light reflected from the inside of the display panel DP and / or the electronic device and / or light incident from the outside of the display panel DP and / or the electronic device. In an embodiment, the anti-reflection layer CFL may be a polarizing film.

[0063] The display device DD according to an embodiment of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the anti-reflection layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0064] Figure 3 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0065] refer to Figure 3 The display device DD includes a display panel DP, a driving controller 100 (e.g., a controller circuit), a data driver 200 (e.g., a data driving circuit), a scan and sensor driver 300 (e.g., a first driver circuit), an emission driver 400 (e.g., a second driver circuit), a voltage generator 500, and a readout circuit 600.

[0066] The drive controller 100 allows an image to be displayed on the display panel DP. The drive controller 100 receives an input image signal RGB and a control signal CTRL. The drive controller 100 generates an output image signal DATA by converting the data format of the input image signal RGB so as to be suitable for the data driver 200 and the display panel DP. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, an emission control signal ECS, a readout control signal RCS, and a voltage control signal VCS.

[0067] The data driver 200 receives the data control signal DCS and the output image signal DATA from the driving controller 100. The data driver 200 converts the output image signal DATA into a data signal and then outputs the data signal to a plurality of data lines DL1 to DLm. The data signal may be an analog voltage corresponding to the grayscale of the output image signal DATA.

[0068] The voltage generator 500 generates a voltage for operation of the display panel DP in response to a voltage control signal VCS from the driving controller 100. In an embodiment, the voltage generator 500 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, a reset voltage VRST, a sensor driving voltage VCOM, and a reset control voltage VGR. In an embodiment, the first driving voltage ELVDD is greater than the second driving voltage ELVSS. In an embodiment, the second driving voltage ELVSS is a ground voltage.

[0069] In an embodiment, the voltage generator 500 changes or sets a voltage level of the reset voltage VRST and a voltage level of the reset control voltage VGR in response to the voltage control signal VCS.

[0070] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, a reset line GRL1, emission lines EML1 to EMLn, data lines DL1 to DLm, readout lines RL1 to RLk, pixels PX, and sensors SX. Figure 3 A single reset line GRL1 is illustrated in FIG. 2 , but the display panel DP may include a plurality of reset lines.

[0071] The display panel DP may include a transparent area TA (refer to Figure 1 ) corresponding to the display area DA and the frame area BZA (reference Figure 1 ) corresponds to the non-display area NDA. The pixels PX and the sensors SX may be disposed in the display area DA.

[0072] The scan and sensor driver 300 and the emission driver 400 may be disposed in the non-display area NDA of the display panel DP.

[0073] In an embodiment, the scan and sensor driver 300 is disposed adjacent to a first side of the display area DA in the display panel DP. The scan and sensor driver 300 receives a scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan and sensor driver 300 may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn, and may reset the reset signal GR1 (reference signal GR2). Figure 5 The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn and the reset line GRL1 may extend from the scan and sensor driver 300 in the first direction DR1.

[0074] In an embodiment, the scan and sensor driver 300 determines the reset signal GR1 (refer to the reset signal GR2) to be supplied to the reset line GRL1 based on the reset control voltage VGR received from the voltage generator 500. Figure 5 ) voltage level.

[0075] The emission driver 400 is disposed adjacent to the second side of the display area DA in the display panel DP. The emission driver 400 receives an emission control signal ECS from the drive controller 100. The emission driver 400 may output emission signals to the emission lines EML1 to EMLn in response to the emission control signal ECS. The emission lines EML1 to EMLn may extend from the emission driver 400 in a direction away from the first direction DR1.

[0076] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, the reset line GRL1, and the emission lines EML1 to EMLn may be arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm may extend from the data driver 200 in a direction away from the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1.

[0077] The plurality of pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, the emission lines EML1 to EMLn and the data lines DL1 to DLm. In an embodiment, each of the plurality of pixels PX is electrically connected to four scan lines and a single emission line. For example, Figure 3As shown, the pixels PX belonging to the first row can be connected to the scan lines GIL1, GCL1, GWL1, and GBL1 and the emission line EML1. In addition, the pixels PX belonging to the second row can be connected to the scan lines GIL2, GCL2, GWL2, and GBL2 and the emission line EML2. In an embodiment, each of the plurality of pixels PX is electrically connected to a single data line. For example, as Figure 3 shown, the pixels PX belonging to the first column can be connected to the data line DL1. In addition, the pixels PX belonging to the second column can be connected to the data line DL2.

[0078] Each of the plurality of pixels PX includes a light-emitting element ED (refer to Figure 5 ) and a pixel circuit PXC (refer to Figure 5 ) for controlling the emission of the light-emitting element ED. The pixel circuit PXC may include one or more transistors and one or more capacitors. The scan and sensor driver 300 and the emission driver 400 may include transistors formed by the same process as the transistors of the pixel circuit PXC.

[0079] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2 from a voltage generator 500.

[0080] Each of the sensors SX includes a photosensing element OPD (refer to Figure 5 ) and a sensor driving circuit SDC (refer to Figure 5 ). The sensor driving circuit SDC may include transistors formed by the same process as the transistors of the pixel circuit PXC.

[0081] Each of the sensors SX can be connected to a corresponding one of the scan lines GWL1 to GWLn among the scan lines and a corresponding one of the readout lines RL1 to RLk among the readout lines. The sensor SX can be connected to the reset line GRL1. In an embodiment, when the number of the reset lines GRL1 is plural, the sensor SX can be connected to a corresponding one of the plural reset lines.

[0082] In an embodiment, the number of the sensors SX is less than the number of the pixels PX. However, the present disclosure is not limited thereto. In an embodiment, the number of the sensors SX provided in the display panel DP is greater than or equal to the number of the pixels PX. In an embodiment, the number of the readout lines RL1 to RLk is less than the number of the data lines DL1 to DLm. That is, k < m. However, the present disclosure is not limited thereto. In an embodiment, the number of the readout lines RL1 to RLk provided in the display panel DP is greater than or equal to the number of the data lines DL1 to DLm.

[0083] The readout circuit 600 may receive the sensing signals from the readout lines RL1 to RLk in response to the readout control signal RCS to output the readout signal RS to the driving controller 100 .

[0084] In an embodiment, the sensor SX and the readout circuit 600 may operate in a biometric sensing mode and a touch sensing mode. In an embodiment, the sensor SX and the readout circuit 600 may sense information about the user's blood pressure and fingerprint in the biometric sensing mode. In an embodiment, the sensor SX and the readout circuit 600 may sense a position touched by the user in the touch sensing mode.

[0085] exist Figure 3 In the example illustrated in FIG. 1 , the scanning and sensor driver 300 is arranged to face the emission driver 400 with the pixel PX interposed therebetween, but the present disclosure is not limited thereto. For example, the scanning and sensor driver 300 and the emission driver 400 may be arranged side by side in the display panel DP at a position adjacent to one of the first side and the second side of the display area DA. In an embodiment, the scanning and sensor driver 300 and the emission driver 400 are implemented using a single circuit.

[0086] Figure 4 According to the embodiment of the present disclosure Figure 3 FIG. 1 is an enlarged plan view of a partial area of ​​the display panel DP.

[0087] refer to Figure 4 , pixels PXR, pixels PXG, and pixels PXB are arranged in the display panel DP. The pixels PXR, PXG, and PXB may be respectively Figure 3 Each of the pixels PXR, PXG, and PXB includes a light emitting element (one of ED_R, ED_G, and ED_B) and a pixel circuit PXC. Figure 3 Each of the pixels PX shown in FIG. Figure 4 Each of the sensors SX includes a light sensing element OPD and a sensor driving circuit SDC.

[0088] refer to Figure 4 , pixels PXR and PXB and sensor SX are arranged at odd rows (ie, the first row and the third row). In an embodiment, for each of the first row and the third row, pixels PXR and PXB and sensor SX are alternately arranged in the first direction DR1. Only pixel PXG is arranged in each of the second row and the fourth row.

[0089] In an embodiment, the pixel PXR may include a light emitting element ED_R that outputs light of a first color (e.g., red). The pixel PXG may include a light emitting element ED_G that outputs light of a second color (e.g., green). The pixel PXB may include a light emitting element ED_B that outputs light of a third color (e.g., blue).

[0090] like Figure 4 As shown in , the pixels PXR and PXB may be alternately and repeatedly arranged not only in the first direction DR1 but also in the second direction DR2. Each of the pixels PXG may be arranged between two light sensing elements OPD arranged in the second direction DR2.

[0091] Although pixels PXR, PXG, PXB and sensors SX Figure 4 The illustrative embodiment is illustrated as having a specific arrangement, but the arrangement may be variously changed or modified.

[0092] In an embodiment, the size of the light emitting element ED_R is larger than the size of the light emitting element ED_G. In addition, the size of the light emitting element ED_B may be larger than or equal to the size of the light emitting element ED_R. The size of each of the light emitting elements ED_R, ED_G, and ED_B is not limited thereto, and various changes and applications may be made. For example, in an embodiment of the present disclosure, the light emitting elements ED_R, ED_G, and ED_B have the same size.

[0093] In addition, each of the light emitting elements ED_R, ED_G, and ED_B may be implemented in a variety of shapes such as a polygon, a circle, or an ellipse. In an embodiment, the light emitting elements ED_R, ED_G, and ED_B are implemented to have different shapes. For example, the light emitting element ED_G may have a circular shape, and the light emitting elements ED_R and ED_B may have a quadrilateral shape.

[0094] In an embodiment, the area occupied by the sensor driving circuit SDC is different from the area occupied by the pixel circuit PXC. For example, the area of ​​the sensor driving circuit SDC may be smaller than the area of ​​the pixel circuit PXC.

[0095] Figure 5 is a circuit diagram of a pixel PX and a sensor SX according to an embodiment of the present disclosure.

[0096] Figure 5 Shows Figure 3 One pixel PX among the plurality of pixels PX shown in FIG. Figure 3 One sensor SX among the multiple sensors SX shown in the figure. Figure 3 Each of the pixels PX shown in FIG. Figure 5 The pixel PX shown in FIG. has the same circuit configuration. Figure 3 Each of the plurality of sensors SX shown in FIG. Figure 5 The sensor SX illustrated in FIG. 1 has the same circuit configuration.

[0097] refer to Figure 5 , the pixel PX includes a pixel circuit PXC and at least one light emitting element ED. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element LD may be an organic light emitting diode including an organic emission layer. The pixel circuit PXC according to the embodiment includes first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst.

[0098] The third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 may be N-type transistors using an oxide semiconductor as a semiconductor layer, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all of the first transistor T1 to the seventh transistor T7 are P-type transistors. In an embodiment, all of the first transistor T1 to the seventh transistor T7 are N-type transistors. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 is an N-type transistor, and the other transistors of the first transistor T1 to the seventh transistor T7 are P-type transistors. The construction of the pixel circuit PXC according to the present disclosure is not limited to Figure 5 The embodiment shown in FIG. Figure 5 The pixel circuit PXC illustrated in FIG. 1 is merely an example, and the configuration of the pixel circuit PXC may be variously modified and implemented.

[0099] The pixel PX is electrically connected to the scan lines GILi, GCLi, GWLi and GBLi, the emission lines EMLi and the data lines DLj. The scan lines GILi, GCLi, GWLi and GBLi can transmit scan signals GIi, GCi, GWi and GBi, respectively, and the emission lines EMLi can transmit emission control signals EMi. The data lines DLj transmit data signals Dj. The data signals Dj can have the same value as that input to the display device DD (reference Figure 3 ) The first to fourth driving voltage lines VL1, VL2, VL3 and VL4 may transmit a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1 and a second initialization voltage VINT2, respectively.

[0100] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to the first end of the capacitor Cst. The first transistor T1 can receive the data signal Dj transmitted through the data line DLj according to the switching operation of the second transistor T2, and can supply the driving current Id to the light emitting element ED.

[0101] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 can be turned on according to the scan signal GWi transmitted through the scan line GWLi, and can transmit the data signal Dj from the data line DLj to the first electrode of the first transistor T1. For example, the gate electrode of the second transistor T2 can receive the scan signal GWi.

[0102] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 can be turned on according to the scan signal GCi transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first transistor T1 can be connected to each other, that is, the first transistor T1 can be diode-connected. For example, the gate electrode of the third transistor T3 can receive the scan signal GCi.

[0103] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the fourth driving voltage line VL4 transmitting the second initialization voltage VINT2, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on according to the scan signal GIi transmitted through the scan line GILi, and therefore, the second initialization voltage VINT2 can be transmitted to the gate electrode of the first transistor T1. For example, the gate electrode of the fourth transistor T4 can receive the scan signal GIi. Therefore, the voltage of the gate electrode of the first transistor T1 can be initialized. This operation can be referred to as an "initialization operation".

[0104] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission line EMLi.

[0105] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission line EMLi.

[0106] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the emission control signal EMi transmitted through the emission line EMLi, and thus the first driving voltage ELVDD may be compensated by the diode-connected transistor T1 so as to be supplied to the light emitting element ED. For example, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may receive the emission control signal EMi.

[0107] The seventh transistor T7 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the third driving voltage line VL3, and a gate electrode connected to the scan line GBLi. The seventh transistor T7 can be turned on according to the scan signal GBi transmitted through the scan line GBLi, and can electrically connect the anode of the light emitting element ED to the third driving voltage line VL3. For example, the gate electrode of the seventh transistor T7 can receive the scan signal GBi.

[0108] A first end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and a second end of the capacitor Cst is connected to the first driving voltage line VL1. A cathode of the light emitting element ED may be connected to a second driving voltage line VL2 receiving a second driving voltage ELVSS. The structure of the pixel PX according to the embodiment is not limited to Figure 5 For example, in one pixel PX, the number of transistors, the number of capacitors, and their connection relationship may be variously changed or modified.

[0109] The sensor SX is electrically connected to the scanning line GWLi, the reset line GRL1, and the readout line RLw.

[0110] The sensor SX includes a light sensing element OPD and a sensor driving circuit SDC. The light sensing element OPD may be a photodiode. As an example of the present disclosure, the light sensing element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The light sensing anode O_AE of the light sensing element OPD may be connected to a sensing node SN, and its cathode may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS.

[0111] The sensor driving circuit SDC includes transistors ST1, ST2 and ST3. The transistors ST1, ST2 and ST3 may be a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3, respectively. The transistors ST1, ST2 and ST3 may also be referred to as a "first transistor ST1", a "second transistor ST2" and a "third transistor ST3", respectively.

[0112] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the others of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be N-type transistors. Figure 5 The third transistor T3 of the pixel PX shown in FIG. 1 is the same as an N-type transistor, and the amplifying transistor ST2 and the output transistor ST3 are the same as Figure 5 The first transistor T1 and the second transistor T2 of the pixel PX illustrated in the figure are the same P-type transistors. However, the present disclosure is not limited thereto. In an embodiment, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 are P-type transistors. In an embodiment, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 are N-type transistors.

[0113] The reset transistor ST1 includes a first electrode connected to a reset voltage line VL5 receiving a reset voltage VRST, a second electrode connected to a sensing node SN, and a gate electrode connected to a reset line GRL1 receiving a reset signal GR1. The reset transistor ST1 can reset the potential of the sensing node SN to the reset voltage VRST in response to the reset signal GR1.

[0114] The amplifying transistor ST2 includes a first electrode connected to a sensor driving voltage line VL6 receiving a sensor driving voltage VCOM, a second electrode connected to an intermediate node IN, and a gate electrode connected to a sensing node SN. In an embodiment, the voltage level of the sensor driving voltage VCOM is equal to the voltage level provided to the sensor driving voltage VCOM. Figure 5 The amplifying transistor ST2 may provide a current corresponding to the potential of the sensing node SN to the intermediate node IN.

[0115] The output transistor ST3 includes a first electrode connected to the intermediate node IN, a second electrode connected to the readout line RLw, and a gate electrode connected to the scan line GWLi receiving the scan signal GWi. The output transistor ST3 may transmit the sensing signal FSw to the readout line RLw in response to the scan signal GWi.

[0116] The circuit configuration of the sensor drive circuit SDC according to the present disclosure is not limited to Figure 5 . Figure 5 The sensor driving circuit SDC illustrated in FIG. 1 is provided only as an example, and the configuration of the sensor driving circuit SDC may be variously modified and implemented.

[0117] Figure 6 yes Figure 50 is a timing diagram of the operation of the pixel PX illustrated in FIG.

[0118] refer to Figure 5 and Figure 6 , one frame Fs (or one frame period) may include an emission period EP and a non-emission period NEP. The emission period EP may correspond to a low level period (i.e., an effective period) of the emission control signal EMi, and the non-emission period NEP may correspond to a high level period (i.e., an invalid period) of the emission control signal EMi.

[0119] The non-emission period NEP may include an initialization period and a data programming and compensation period.

[0120] When a high-level scan signal GIi is provided through the scan line GILi during the initialization period, the fourth transistor T4 is turned on. The second initialization voltage VINT2 is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, and thus, the first transistor T1 is initialized.

[0121] Next, when a high-level scan signal GCi is supplied through the scan line GCLi during the data programming and compensation period, the third transistor T3 is turned on. In this case, the first transistor T1 is diode-connected by the third transistor T3 thus turned on, and is forward biased. Thereafter, when a low-level scan signal GWi is supplied through the scan line GWLi, the second transistor T2 is turned on. According to the above-mentioned bias condition, a compensation voltage obtained by subtracting a threshold voltage of the first transistor T1 from a voltage of a data signal Dj supplied from a data line DLj is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 may be a compensation voltage.

[0122] When the first driving voltage ELVDD and the compensation voltage are respectively applied to opposite ends of the capacitor Cst, charges of an amount corresponding to a difference between the first driving voltage ELVDD and the compensation voltage may be stored in the capacitor Cst.

[0123] At the same time, the seventh transistor T7 is turned on in response to the low-level scan signal GBi transmitted through the scan line GBLi. When the seventh transistor T7 is turned on, the anode of the light emitting element ED is electrically connected to the third driving voltage line VL3. Accordingly, the anode of the light emitting element ED can be initialized with the first initialization voltage VINT1.

[0124] Thereafter, during the emission period EP, the emission control signal EMi supplied from the emission line EMLi is changed from a high level to a low level. During the emission period EP, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level emission control signal EMi. In this case, the driving current Id is generated according to the difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD, and is supplied to the light emitting element ED through the sixth transistor T6. That is, the driving current Id flows through the light emitting element ED. The light emitting element ED can emit light having a brightness corresponding to the driving current Id.

[0125] Figure 7 yes Figure 5 0047 is a timing diagram of the operation of the sensor SX illustrated in FIG.

[0126] refer to Figure 5 and Figure 7 When the reset signal GR1 turns to a high level, the reset transistor ST1 is turned on. When the reset transistor ST1 is turned on, the sensing node SN may be initialized with the reset voltage VRST.

[0127] After the reset signal GR1 turns to a low level, the sensor SX is exposed to light during the light exposure period LE. When the user's hand touches the display surface, the light sensing element OPD may generate photoelectrons whose number corresponds to the light reflected by the user's hand, and the generated photoelectrons may be accumulated at the sensing node SN.

[0128] The amplification transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the number of photoelectrons (or charges) of the sensing node SN that are input to the gate electrode of the amplification transistor ST2 .

[0129] When the scanning signal GWi is at an invalid level, that is, at a high level, the output transistor ST3 is maintained in a cut-off state. When the scanning signal GWi is changed to an effective level (that is, a low level), the output transistor ST3 is turned on. When the output transistor ST3 is turned on, a sensing signal FSw corresponding to the current flowing through the amplifier transistor ST2 can be output to the readout line RLw. That is, a sensing signal FSw corresponding to the amount of light sensed by the light sensing element OPD can be output to the readout line RLw.

[0130] In an embodiment, Figure 7 The scanning signal GWi and Figure 5 and Figure 6 The scanning signal GWi shown in FIG is the same. That is, Figure 3 The pixels PX and the sensors SX disposed at the i-th row illustrated in FIG. 4 may receive the same scanning signal GWi.

[0131] In an embodiment, in the biometric sensing mode, the optical sensing element OPD may generate photoelectrons whose number corresponds to light reflected by the ridges or valleys between the ridges of the fingerprint. The sensing signal FSw output from the sensor SX in the biometric sensing mode may be a signal corresponding to the fingerprint of the user.

[0132] In an embodiment, in the biometric sensing mode, the optical sensing element OPD may generate photoelectrons whose number corresponds to light reflected from blood vessels located below the dermis layer of the user's skin. During systole, blood moves toward the periphery, increasing arterial blood volume; during diastole, blood volume decreases. This change in blood volume changes the reflected light. The sensing signal FSw output from the sensor SX in the biometric sensing mode may be a signal corresponding to the user's blood pressure.

[0133] In an embodiment, in the touch sensing mode, the light sensing element OPD may generate photoelectrons whose number corresponds to light reflected by a user's touch. The sensing signal FSw output from the sensor SX in the touch sensing mode may be a signal indicating whether a user has made a touch.

[0134] Figure 8 is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 8 The middle part shows Figure 5 The first transistor T1 and the third transistor T3 and the reset transistor ST1.

[0135] refer to Figure 8 , the display panel DP may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, a device layer DP_ED, and an encapsulation layer TFE.

[0136] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin material. Although the synthetic resin layer may be a polyimide resin layer, the present disclosure is not limited thereto. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0137] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers. The plurality of inorganic layers may constitute barrier layers BR1 and BR2 and / or a buffer layer BFL to be described later. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively provided.

[0138] The barrier layers BR1 and BR2 prevent foreign matter from being introduced from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and the plurality of silicon oxide layers and the plurality of silicon nitride layers may be alternately stacked.

[0139] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. The first bottom metal layer BMC1 may be interposed between the first barrier layer BR1 and the second barrier layer BR2. In an embodiment of the present disclosure, the first bottom metal layer BMC1 may be omitted.

[0140] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0141] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0142] Figure 8 Only a portion of the first semiconductor pattern disposed on the buffer layer BFL is shown, and the first semiconductor pattern may be further disposed in any other region. The first semiconductor pattern may be arranged across pixels according to a specific rule. The electrical characteristics of the first semiconductor pattern may vary depending on whether it is doped. The first semiconductor pattern may include a first region having a high electrical conductivity and a second region having a low electrical conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped with a concentration lower than that of the first region.

[0143] The conductivity of the first region may be higher than that of the second region, and the first region may substantially serve as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the first semiconductor pattern may be an active region of a transistor, another portion of the first semiconductor pattern may be a source region or a drain region of the transistor, and the other portion of the first semiconductor pattern may be a connection electrode or a connection signal line.

[0144] The first electrode SE1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed of the first semiconductor pattern. The first electrode SE1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in directions away from each other.

[0145] exist Figure 8 FIG. 4 illustrates a portion of a connection signal line CSL formed by a first semiconductor pattern. The connection signal line CSL may be electrically connected to a sixth transistor T6 (refer to FIG. 4 ). Figure 5 )'s second electrode.

[0146] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 is a single silicon oxide layer. In addition to the first insulating layer 10, other insulating layers of the circuit layer DP_CL may also be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the present disclosure is not limited thereto.

[0147] The gate electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate electrode G1 may be a part of the metal pattern. The gate electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1. In the process of doping the first semiconductor pattern, the gate electrode G1 of the first transistor T1 may serve as a mask. The gate electrode G1 may include titanium (Ti), silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN x ), tungsten (W), tungsten nitride (WN x ), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but the present disclosure is not limited thereto.

[0148] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0149] The upper electrode UE and the second bottom metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the gate electrode G1 and the upper electrode UE overlapping the portion of the gate electrode G1 may define a capacitor Cst (refer to Figure 5). According to an embodiment of the present disclosure, the second insulating layer 20 may be replaced by an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and in the process of forming the insulating pattern by the second insulating layer 20, the upper electrode UE may serve as a mask.

[0150] The second bottom metal layer BMC2 may be disposed to correspond to a lower portion of the oxide thin film transistor (eg, the third transistor T3). The second bottom metal layer BMC2 may be supplied with a constant voltage or signal. For example, the constant voltage may be a direct current (DC) voltage.

[0151] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second bottom metal layer BMC2. The third insulating layer 30 may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0152] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished from each other according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter, referred to as the "reduction region") has a conductivity greater than that in which the metal oxide is not reduced (hereinafter, referred to as the "non-reduction region"). The reduction region may substantially serve as a source or drain or a signal line of a transistor. The non-reduction region substantially corresponds to an active region (or semiconductor region or channel region) of a transistor. In other words, a portion of the second semiconductor pattern may be an active region of a transistor, another portion thereof may be a source region or a drain region of a transistor, and the other portion thereof may be a connecting electrode or a connecting signal line.

[0153] The first electrode SE3, the channel portion A3 and the second electrode D3 of the third transistor T3 are formed by the second semiconductor pattern. The first electrode SE3 and the second electrode D3 include metal reduced from a metal oxide semiconductor. In a cross-sectional view, the first electrode SE3 and the second electrode D3 may extend from the channel portion A3 in directions away from each other.

[0154] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap the plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0155] The gate electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The gate electrode G3 may be a part of the metal pattern. The gate electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. In the process of doping the second semiconductor pattern, the gate electrode G3 may serve as a mask. According to an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0156] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the gate electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0157] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first to fifth insulating layers 10, 20, 30, 40, and 50.

[0158] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include: a polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS); a polymer derivative having a phenol group; an acrylic polymer; an imide polymer; an aryl ether polymer; an amide polymer; a fluorine polymer; a paraxylene polymer; a vinyl alcohol polymer; or a mixture thereof.

[0159] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0160] The first electrode layer is disposed on the circuit layer DP_CL. The pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a first anode R_AE and a light sensing anode O_AE. In an embodiment, the first anode R_AE and the light sensing anode O_AE are disposed on the seventh insulating layer 70. The first anode R_AE may be connected to the second connection electrode CNE20 through a third contact hole CH3 penetrating the seventh insulating layer 70. Figure 8 Only the first anode R_AE corresponding to red light is shown in FIG. 1 , but the first electrode layer may further include a second anode corresponding to green light and a third anode corresponding to blue light.

[0161] A first film opening PDL-OP1 and a second film opening PDL-OP2 may be provided in the pixel defining layer PDL. The first film opening PDL-OP1 exposes at least a portion of the first anode R_AE. The second film opening PDL-OP2 exposes at least a portion of the light sensing anode O_AE.

[0162] In an embodiment of the present disclosure, the pixel defining layer PDL further includes a black material. The pixel defining layer PDL may further include a black organic dye / pigment such as carbon black or aniline black. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repellent organic material.

[0163] like Figure 8 As shown in , the display panel DP may include an emission region PXA-R and a non-emission region NPXA-R adjacent to the emission region PXA-R. The non-emission region NPXA-R may surround the emission region PXA-R. In an embodiment, the emission region PXA-R is defined to correspond to a partial area of ​​the first anode R_AE exposed by the first film opening PDL-OP1.

[0164] The emission layer may be disposed on the first electrode layer. The emission layer may include a red emission layer, a green emission layer, and a blue emission layer. The red emission layer, the green emission layer, and the blue emission layer may be disposed in corresponding regions of the first film opening PDL-OP1, respectively. The red emission layer, the green emission layer, and the blue emission layer may be independently formed in Figure 4 In the red pixel PXR, green pixel PXG and blue pixel PXB shown in FIG. Each of the red emission layer, the green emission layer and the blue emission layer may include an organic material and / or an inorganic material. The red emission layer, the green emission layer and the blue emission layer may respectively generate light of a given color. For example, the emission layer R_EL may generate red light. Figure 8 An example in which the emission layer R_EL is provided in a region corresponding to the first film opening PDL-OP1 is illustrated in FIG.

[0165] In the embodiment, the patterned red emission layer, green emission layer and blue emission layer are described as examples, but one emission layer can be commonly arranged in multiple emission areas. In this case, the emission layer can generate white light or blue light. In addition, the emission layer can have a multilayer structure called "series".

[0166] The emission layer R_EL may include a low molecular weight organic material or a high molecular weight organic material as a light emitting material. The cathode CE is disposed on the emission layer R_EL. As an example of the present disclosure, the cathode CE may be commonly disposed in the emission region PXA-R, the non-emission region NPXA-R, and the non-pixel region NPA.

[0167] The circuit layer DP_CL may further include a sensor driving circuit SDC (refer to Figure 5 ). For ease of description, a reset transistor ST1 included in the sensor driving circuit SDC is illustrated. A first electrode STS1, a channel portion STA1, and a second electrode STD1 of the reset transistor ST1 are formed by a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. A fourth insulating layer 40 is provided to cover the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. A gate electrode STG1 of the reset transistor ST1 is provided on the fourth insulating layer 40. In an embodiment, the gate electrode STG1 may be a part of the metal pattern. The gate electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1.

[0168] In an embodiment of the present disclosure, the reset transistor ST1 is disposed at the same layer as the third transistor T3. That is, the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by the same process as the first electrode SE3, the channel portion A3, and the second electrode D3 of the third transistor T3. The gate electrode STG1 of the reset transistor ST1 and the gate electrode G3 of the third transistor T3 may be formed simultaneously by the same process. The first electrode and the second electrode of each of the amplifying transistor ST2 and the output transistor ST3 of the sensor driving circuit SDC may be formed by the same process as the first electrode SE1 and the second electrode D1 of the first transistor T1. When the reset transistor ST1 and the third transistor T3 are formed at the same layer by the same process, the process of forming the reset transistor ST1 is not additionally required, and therefore, the process efficiency may be improved and the cost may be reduced.

[0169] The device layer DP_ED may further include a light sensing device OPD (refer to Figure 5 ).exist Figure 8 The light sensing element OPD is illustrated only as an example.

[0170] The light sensing element OPD may include a light sensing anode O_AE, a photoelectric conversion layer O_RL, and a photocathode O_CE. The light sensing anode O_AE may be disposed on the same layer as the first electrode layer. That is, the light sensing anode O_AE may be disposed on the circuit layer DP_CL, and the light sensing anode O_AE and the first anode R_AE may be formed simultaneously by the same process. The display panel DP may include a sensing area SA and a non-sensing area NSA adjacent to the sensing area SA. The non-sensing area NSA may surround the sensing area SA. In an embodiment, the sensing area SA is defined as corresponding to a partial area of ​​the light sensing anode O_AE exposed by the second film opening PDL-OP2.

[0171] The second film opening PDL-OP2 of the pixel defining layer PDL exposes at least a portion of the light sensing anode O_AE. The photoelectric conversion layer O_RL is disposed on the portion of the light sensing anode O_AE exposed by the second film opening PDL-OP2. The photoelectric conversion layer O_RL may include an organic photoelectric sensing material. The photocathode O_CE may be disposed on the photoelectric conversion layer O_RL. The photocathode O_CE and the cathode CE may be formed simultaneously by the same process. As an example of the present disclosure, the photocathode O_CE may be formed integrally with the cathode CE. For example, a single layer may be used to form the photocathode O_CE and the cathode CE.

[0172] Each of the light sensing anode O_AE and the photocathode O_CE can receive an electrical signal. The photocathode O_CE and the light sensing anode O_AE can receive different signals. Accordingly, a given electric field can be formed between the light sensing anode O_AE and the photocathode O_CE. The photoelectric conversion layer O_RL generates an electrical signal corresponding to the light incident on the sensor. The photoelectric conversion layer O_RL can generate charges by absorbing the energy of the incident light. For example, the photoelectric conversion layer O_RL may include a photosensitive semiconductor material.

[0173] The charges generated by the photoelectric conversion layer O_RL change the electric field between the light sensing anode O_AE and the photocathode O_CE. The amount of charges generated by the photoelectric conversion layer O_RL may vary depending on whether light is incident on the light sensing element OPD, the amount of light incident on the light sensing element OPD, and the intensity of light incident on the light sensing element OPD. Therefore, the electric field formed between the light sensing anode O_AE and the photocathode O_CE may vary. The light sensing element OPD according to the present disclosure may obtain information about at least one of the user's fingerprint, blood pressure, and touch by the change of the electric field between the light sensing anode O_AE and the photocathode O_CE.

[0174] However, this is provided as an example, and the light sensing element OPD may also include a phototransistor in which the photoelectric conversion layer O_RL is used as an active layer. In this case, the light sensing element OPD can obtain fingerprint information by sensing the amount of current flowing through the phototransistor. The light sensing element OPD according to an embodiment of the present disclosure may include various photoelectric conversion elements each capable of generating an electrical signal in response to a change in the amount of light, but the present disclosure is not limited to one embodiment.

[0175] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. According to an embodiment of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer between the two inorganic layers. According to an embodiment of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0176] The inorganic layer of the encapsulation layer TFE protects the light emitting element ED_R and the light sensing element OPD from moisture / oxygen, and the organic layer of the encapsulation layer TFE protects the light emitting element ED_R and the light sensing element OPD from foreign matter such as dust particles. The inorganic layer of the encapsulation layer TFE may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but the present disclosure is not particularly limited thereto. The organic layer of the encapsulation layer TFE may include an acrylic organic layer, but the present disclosure is not limited thereto.

[0177] Fig. 9A and Fig. 9B is a diagram illustrating voltage distribution of the second driving voltage ELVSS in the display panel DP.

[0178] refer to Figure 3 , Fig. 9A and Fig. 9B , even if the voltage generator 500 generates the second driving voltage ELVSS at a uniform voltage level, the voltage level of the second driving voltage ELVSS may vary according to the image displayed on the display panel DP or the surrounding environment (e.g., the surrounding temperature). Specifically, the second driving voltage ELVSS may vary according to the position of the display panel DP. For example, the voltage level of the second driving voltage ELVSS in the center portion CP of the display panel DP (e.g., -2V) and the voltage level of the second driving voltage ELVSS in the edge portion EGP of the display panel DP (e.g., -6V) may be different from each other. The reason is as follows. When the second driving voltage ELVSS is supplied from the edge portion EGP of the display panel DP, the voltage level of the second driving voltage ELVSS may change in the center portion CP of the display panel DP due to a current-resistance (IR) drop phenomenon.

[0179] Fig. 9A and Fig. 9B The voltage distribution of the second driving voltage ELVSS illustrated in FIG. 1 is provided only as an example, and the present disclosure is not limited thereto.

[0180] At the same time, in order to reduce the power consumption of the pixels PX in the display panel DP, the driving controller 100 may change the voltage level of the second driving voltage ELVSS. That is, the driving controller 100 may change the voltage level of the second driving voltage ELVSS according to the brightness (or brightness level) or emission amount of the image to be displayed on the display panel DP.

[0181] like Figure 5As shown in FIG, the cathode of the light emitting element ED and the cathode of the light sensing element OPD are commonly connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. That is, when the voltage level of the second driving voltage ELVSS supplied to the pixel PX changes, the voltage level of the second driving voltage ELVSS supplied to the sensor SX also changes.

[0182] When the voltage level of the second driving voltage ELVSS changes, the difference between the reset voltage VRST and the second driving voltage ELVSS (i.e., the potential difference between the reset voltage line VL5 and the second driving voltage line VL2) changes. The difference or potential difference between the reset voltage VRST and the second driving voltage ELVSS may cause a change in the voltage level of the sensing node SN. Therefore, the amount of current of the intermediate node IN determined by the reset transistor ST1 and the amplifying transistor ST2 may change. In this case, the characteristics of the sensor SX may change, thereby reducing the readout circuit 600 (reference Figure 3 )’s sensing sensitivity.

[0183] Fig.10 : is a graph showing a change in the current density of the light sensing element OPD.

[0184] exist Fig.10 , the horizontal axis represents the difference between the reset voltage VRST and the second driving voltage ELVSS, and the vertical axis represents the current density.

[0185] refer to Fig.10 , the curve Jdark shows the change in the current density of the light sensing element OPD due to the difference between the reset voltage VRST and the second driving voltage ELVSS when there is no external light. The curve Jlight shows the change in the current density of the light sensing element OPD due to the difference between the reset voltage VRST and the second driving voltage ELVSS when there is external light.

[0186] Comparing the curve Jdark and the curve Jlight, as the difference between the reset voltage VRST and the second driving voltage ELVSS increases from 0V to -3V, a change in the current density of the curve Jlight becomes greater than a change in the current density of the curve Jdark.

[0187] The current flowing through the light sensing element OPD varies according to the difference between the reset voltage VRST and the second driving voltage ELVSS, which means that the light sensing characteristic of the sensor SX changes.

[0188] Fig.11 is a block diagram illustrating a driving controller 100 according to an embodiment of the present disclosure.

[0189] exist Fig.11Only the components in the drive controller 100 that are associated with the aspect of generating the voltage control signal VCS are illustrated. Fig.11 In addition to the components illustrated in the figure, the driving controller 100 may further include various components.

[0190] refer to Fig.11 , the driving controller 100 includes a memory 110 and a controller 120 (eg, a control circuit).

[0191] The controller 120 may determine the voltage level of the second driving voltage ELVSS based on the input image signal RGB and the control signal CTRL. In addition, the controller 120 may determine the voltage level of the reset voltage VRST corresponding to the voltage level of the second driving voltage ELVSS determined in this way. That is, when the voltage level of the reset voltage VRST changes, the voltage level of the second driving voltage ELVSS may also change. If the voltage level of the second driving voltage ELVSS does not change based on the input image signal RGB and the control signal CTRL, the voltage level of the reset voltage VRST may be maintained.

[0192] In an embodiment, the memory 110 stores a voltage distribution (refer to Fig. 9B ) (ie, the voltage data signal VSS_DATA). For example, the memory 110 may include an entry of each portion (or block) of an image to be displayed on the display panel DP and a value of the second driving voltage ELVSS of the corresponding portion.

[0193] The controller 120 reads a voltage data signal VSS_DATA associated with the second driving voltage ELVSS from the memory 110. For example, the voltage data signal VSS_DATA may indicate a voltage level of the second driving voltage ELVSS of the corresponding portion of the image to be displayed. The voltage level of the reset voltage VRST of the corresponding portion may be determined according to the voltage data signal VSS_DATA. The controller 120 may determine a voltage level of a reset control voltage VGR based on the voltage data signal VSS_DATA. The voltage level of the reset control voltage VGR may be used to operate a specific portion of the display panel DP that will display the corresponding portion of the image.

[0194] The controller 120 may output a voltage control signal VCS corresponding to the determined voltage level of the second driving voltage ELVSS, the determined voltage level of the reset voltage VRST, and the determined voltage level of the reset control voltage VGR.

[0195] Figure 3The voltage generator 500 illustrated in FIG. 5 may change voltage levels of the second driving voltage ELVSS, the reset voltage VRST, and the reset control voltage VGR in response to the voltage control signal VCS.

[0196] Fig.12 is a diagram illustrating pixels and sensors provided in the display panel DP.

[0197] refer to Fig.12 , the display panel DP may include a first area AA1, a second area AA2, and a third area AA3. Fig.12 An example in which the display panel DP includes three areas AA1, AA2, and AA3 is illustrated in FIG, but the present disclosure is not limited thereto.

[0198] The first area AA1 includes pixels PX11, PX12, PX13, PX14, PXa1, PXa2, PXa3, and PXa4 and sensors SX11, SX12, SX13, SX14, SXa1, SXa2, SXa3, and SXa4.

[0199] The second area AA2 includes pixels PXb1, PXb2, PXb3, PXb4, PXc1, PXc2, PXc3, and PXc4 and sensors SXb1, SXb2, SXb3, SXb4, SXc1, SXc2, SXc3, and SXc4.

[0200] The third area AA3 includes pixels PXd1, PXd2, PXd3, PXd4, PXe1, PXe2, PXe3, and PXe4 and sensors SXd1, SXd2, SXd3, SXd4, SXe1, SXe2, SXe3, and SXe4.

[0201] The reset line GRL1 is connected to the sensors SX11, SX12, SX13, and SX14 of the first area AA1. The reset line GRLa is connected to the sensors SXa1, SXa2, SXa3, and SXa4 of the first area AA1.

[0202] The reset line GRLb is connected to the sensors SXb1, SXb2, SXb3, and SXb4 of the second area AA2. The reset line GRLc is connected to the sensors SXc1, SXc2, SXc3, and SXc4 of the second area AA2.

[0203] The reset line GRLd is connected to the sensors SXd1, SXd2, SXd3, and SXd4 of the third area AA3. The reset line GRLe is connected to the sensors SXe1, SXe2, SXe3, and SXe4 of the third area AA3.

[0204] The reset lines GRL1, GRLa, GRLb, GRLc, GRLd and GRLe can be respectively Figure 3 The reset signals GR1, GRa, GRb, GRc, GRd, and GRe provided by the scanning and sensor driver 300 illustrated in FIG. 1 are transmitted to the sensors connected thereto.

[0205] Fig.13A , Fig. 13B and Fig. 13C The diagram is provided to Fig.12 FIG. 4 is a diagram of a reset signal for a reset line illustrated in FIG.

[0206] refer to Fig.11 , Fig.13A , Fig. 13B and Fig. 13C The memory 110 may store a voltage distribution (reference Fig. 9B ) and may provide a voltage data signal VSS_DATA to the controller 120. The voltage data signal VSS_DATA may be determined according to the information about the voltage distribution.

[0207] The controller 120 may determine a voltage level of the reset control voltage VGR based on the voltage data signal VSS_DATA.

[0208] For example, the controller 120 may determine the voltage level VGRa of the reset control voltage VGR corresponding to the first area AA1 based on the voltage distribution of the second driving voltage ELVSS corresponding to the first area AA1 of the display panel DP.

[0209] The controller 120 may determine a voltage level VGRb of the reset control voltage VGR corresponding to the second area AA2 based on the voltage distribution of the second driving voltage ELVSS corresponding to the second area AA2 of the display panel DP.

[0210] The controller 120 may determine a voltage level VGRc of the reset control voltage VGR corresponding to the third area AA3 based on the voltage distribution of the second driving voltage ELVSS corresponding to the third area AA3 of the display panel DP.

[0211] In an embodiment, when the voltage distribution of the second driving voltage ELVSS supplied to the display panel DP is uniform, voltage levels VGRa, VGRb and VGRc of the reset control voltage VGR respectively corresponding to the first, second and third areas AA1, AA2 and AA3 are the same.

[0212] In an embodiment, when the voltage distribution of the second driving voltage ELVSS supplied to the display panel DP is uneven, some of the voltage levels VGRa, VGRb and VGRc of the reset control voltage VGR corresponding to the first area AA1, the second area AA2 and the third area AA3, respectively, may be the same, and other voltage levels thereof may be different.

[0213] The controller 120 may determine voltage levels VGRa, VGRb, and VGRc of the reset control voltage VGR corresponding to the first, second, and third areas AA1, AA2, and AA3, respectively, and may output a voltage control signal VCS corresponding to the determined voltage levels.

[0214] Figure 3 The voltage generator 500 illustrated in FIG. 5 may change the voltage level of the reset control voltage VGR in response to the voltage control signal VCS. Specifically, the voltage generator 500 may differently set the voltage level of the reset control voltage VGR depending on the first, second, and third areas AA1, AA2, and AA3.

[0215] exist Fig.13A , Fig. 13B and Fig. 13C In the example illustrated in , reset signals GR1 and GRa corresponding to the first area AA1 may be identical to each other, reset signals GRb and GRc corresponding to the second area AA2 may be identical to each other, and reset signals GRd and GRe corresponding to the third area AA3 may be identical to each other.

[0216] When each of the reset signals GR1, GRa, GRb, GRc, GRd, and GRe turns to a high level, the sensor SX (reference Figure 5 )'s reset transistor ST1 can be turned on.

[0217] exist Fig.13A , Fig. 13B and Fig. 13C In the example illustrated in , the high levels of the reset control voltage VGR corresponding to the first area AA1 , the second area AA2 , and the third area AA3 , respectively, correspond to voltage levels VGRa, VGRb, and VGRc of the reset control voltage VGR, respectively.

[0218] exist Fig.13AIn the example illustrated in FIG, the high levels of the reset signals GR1 and GRa corresponding to the first area AA1 and the high levels of the reset signals GRd and GRe corresponding to the third area AA3 are the same as each other. That is, the voltage levels VGRa and VGRc are the same as each other. In addition, the high levels of the reset signals GR1 and GRa corresponding to the first area AA1 and the high levels of the reset signals GRb and GRc corresponding to the second area AA2 are different from each other. That is, the voltage level VGRa is higher than the voltage level VGRb.

[0219] exist Fig. 13B In the example illustrated in FIG, the high levels of the reset signals GR1 and GRa corresponding to the first area AA1 and the high levels of the reset signals GRb and GRc corresponding to the second area AA2 are the same as each other. That is, the voltage levels VGRa and VGRb are the same as each other. In addition, the high levels of the reset signals GR1 and GRa corresponding to the first area AA1 and the high levels of the reset signals GRd and GRe corresponding to the third area AA3 are different from each other. That is, the voltage level VGRa is higher than the voltage level VGRc.

[0220] exist Fig. 13C In the example illustrated in FIG, the high levels of the reset signals GR1 and GRa corresponding to the first area AA1, the high levels of the reset signals GRb and GRc corresponding to the second area AA2, and the high levels of the reset signals GRd and GRe corresponding to the third area AA3 are different from each other. For example, the voltage level VGRa is higher than the voltage level VGRb, and the voltage level VGRb is higher than the voltage level VGRc.

[0221] exist Fig. 9A and Fig. 9B In the example illustrated in FIG. 1 , the voltage level of the second driving voltage ELVSS at the center portion CP of the display panel DP is higher than the voltage level of the second driving voltage ELVSS at the edge portion EGP of the display panel DP. As the voltage level of the second driving voltage ELVSS increases, the difference between the reset voltage VRST and the second driving voltage ELVSS may become larger and larger; in this case, as Fig.13A As shown in FIG. 1 , the high levels of the reset signals GRb and GRc corresponding to the second area AA2 are adjusted (or controlled) to be lower than the voltage levels VGRa and VGRc.

[0222] In this case, since the reset transistor ST1 (refer to Figure 5 ) is weakly turned on, so the current of the sensing node SN can be adjusted. That is, the characteristics of the sensor SX disposed in the second area AA2 may be similar to the characteristics of the sensor SX disposed in the first area AA1 and the third area AA3.

[0223] In an embodiment, the controller 120 determines a voltage level associated with the second driving voltage ELVSS at a specific position of the display panel based on the voltage distribution of the second driving voltage ELVSS, and determines a difference between the voltage level and the current voltage level of the reset voltage at the specific position. In a first embodiment, when the difference does not exceed a threshold value (e.g., see Fig.13A When the difference exceeds a threshold (e.g., VGRa or VGRc), the reset voltage of the sensor at that particular position is maintained, and when the difference exceeds a threshold (e.g., see Fig.13A In a second embodiment, when the difference does not exceed a first threshold value (e.g., see Fig. 13C When the difference exceeds the first threshold but does not exceed the second threshold greater than the first threshold (for example, see Fig. 13C When the difference exceeds a second threshold (e.g., VGRb in FIG. 1 ), the reset voltage of the sensor at the specific position is reduced by a first amount, and when the difference exceeds a second threshold (e.g., see Fig. 13C When the VGRc in the specific position is lowered, the reset voltage of the sensor at the specific position is reduced by a second amount greater than the first amount. Therefore, the current level of the reset voltage at the specific position can be dynamically adjusted to a new level based on the difference between the current level and the value associated with the second drive voltage ELVSS at the specific position.

[0224] The characteristic variation of the sensor SX according to the voltage distribution of the second driving voltage ELVSS supplied to the display panel DP may be compensated by adjusting the voltage levels VGRa, VGRb, and VGRc of the reset signals GR1, GRa, GRb, GRc, GRd, and GRe of the respective regions of the display panel DP.

[0225] According to the sensor having the above configuration, when the voltage level of the second driving voltage changes, the voltage level of the reset voltage changes. Accordingly, it is possible to prevent the characteristics of the sensor from changing according to the change of the second driving voltage.

[0226] In addition, the voltage level of the reset signal supplied to the reset line may vary according to the position of the reset line. That is, the characteristic variation of the sensor may be compensated by setting the voltage level of the reset signal according to the voltage distribution of the second driving voltage.

[0227] Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A sensor, comprising: A light sensing element connected between the sensing node and the driving voltage line; A first transistor connected between a reset voltage line and the sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the sensing node; as well as a third transistor connected between the intermediate node and the readout line and including a gate electrode connected to the scan line, The voltage level of the reset voltage supplied to the reset voltage line changes according to the voltage level of the driving voltage supplied to the driving voltage line.

2. The sensor according to claim 1, wherein: The first transistor is a transistor of a first type, and Each of the second transistor and the third transistor is a transistor of a second type different from the first type.

3. The sensor according to claim 1, wherein: The first transistor includes a gate electrode receiving a reset signal, and a voltage level of the reset signal changes according to the voltage level of the driving voltage.

4. The sensor according to any one of claims 1 to 3, wherein: The light sensing element includes an anode connected to the sensing node and a cathode connected to the driving voltage line.

5. A display device, comprising: A pixel including a light emitting element connected to a driving voltage line for transmitting a driving voltage; a sensor including a light sensing element connected to the driving voltage line and a reset voltage line receiving a reset voltage; A driving controller configured to receive an image signal and a control signal; as well as a voltage generator configured to generate the driving voltage and the reset voltage in response to a voltage control signal, Wherein, the drive controller is configured as: determining a voltage level of the driving voltage based on the image signal and the control signal; determining a voltage level of the reset voltage based on the determined voltage level of the drive voltage; and The voltage control signal corresponding to the voltage level of the driving voltage and the voltage level of the reset voltage is output.

6. The display device according to claim 5, wherein: The light sensing element is connected between the sensing node and the driving voltage line, and Wherein, the sensor further comprises: a first transistor connected between the reset voltage line and the sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the sensing node; and A third transistor is connected between the intermediate node and the readout line and includes a gate electrode connected to the scan line.

7. The display device according to claim 6, wherein: The first transistor is a transistor of a first type, and The second transistor and the third transistor are transistors of a second type different from the first type.

8. The display device according to claim 6, wherein: The light sensing element includes a cathode connected to the driving voltage line and an anode connected to the sensing node, and The light emitting element includes an anode and a cathode connected to the driving voltage line.

9. The display device according to claim 6, wherein: The drive controller comprises: a memory configured to store a voltage data signal including information on a voltage distribution of the driving voltage supplied to a display panel; and A controller is configured to receive the voltage data signal from the memory, determine a voltage level of a reset control voltage based on the voltage data signal, and output the voltage control signal corresponding to the voltage level of the reset control voltage.

10. The display device according to claim 9, wherein: The voltage generator further generates the reset control voltage in response to the voltage control signal.

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