Processing systems and electronics

Abstract

An embodiment of the present application provides a processing system and an electronic device, wherein the processing system includes: a system-level chip and a memory chip; the system-level chip includes multiple control units and multiple processing units; the memory chip includes multiple groups of memory banks; the processing unit is connected to at least two of the control units; the control unit is connected to at least one group of the memory banks, and the control unit is connected to at least two of the processing units; wherein the control unit is used to allocate the connected memory banks to one or more of the processing units.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a processing system and an electronic device. Background Art

[0002] With the development of artificial intelligence (AI) technology, the number of parameters in AI models is growing exponentially, and AI applications are placing increasingly higher performance requirements on processors and memory, as well as higher requirements on the matching between processors and storage systems.

[0003] Dynamic random access memory (DRAM) chips have evolved from two-dimensional to three-dimensional. Increasing the capacity of DRAM chips themselves is becoming increasingly difficult. Improving performance at the storage module or system architecture level has become a new research direction. Summary of the Invention

[0004] In view of this, embodiments of the present application hope to provide a processing system and an electronic device.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present application is implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a processing system, including: a system-level chip and a memory chip;

[0007] The system-on-chip includes multiple control units and multiple processing units;

[0008] The memory chip includes multiple groups of memory banks;

[0009] The processing unit is connected to at least two of the control units;

[0010] The control unit is connected to at least one group of the storage bodies, and the control unit is connected to at least two of the processing units; wherein the control unit is used to allocate the connected storage bodies to one or more of the processing units.

[0011] In some embodiments, the storage bank includes an available storage bank and a faulty storage bank; the storage space capacity of the faulty storage bank is smaller than the storage space capacity of the available storage bank;

[0012] The control unit is configured to allocate the connected available storage banks to one or more of the processing units.

[0013] In some embodiments, a difference between the quantities of the available memory banks allocated to at least some of the processing units is less than or equal to 1.

[0014] In some embodiments, the memory chip further includes a redundant memory bank;

[0015] The control unit is configured to allocate the connected redundant memory banks to one or more of the processing units.

[0016] In some embodiments, the control unit is configured to determine the number of the memory banks allocated to the connected processing unit according to the credit value of the processing unit and the total amount of the memory banks;

[0017] The credit value is used to indicate the bandwidth requirement of the processing unit.

[0018] In some embodiments, at least part of the control units in the system-on-chip are connected to at least two of the processing units.

[0019] In some embodiments, some of the control units are connected to one processing unit;

[0020] Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1;

[0021] The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

[0022] In some embodiments, each of the control units is connected to at least two of the processing units;

[0023] Each of the processing units is connected to N control units; wherein N is an integer greater than 1;

[0024] The total number of the control units is N / 2 times the total number of the processing units.

[0025] In some embodiments, a plurality of the memory chips are stacked in sequence in a direction perpendicular to the plane where the system-on-chip is located.

[0026] On the other hand, an embodiment of the present application further provides an electronic device, including:

[0027] A processing system as described above;

[0028] A peripheral interface is connected to the processing system.

[0029] In the processing system provided by the embodiments of the present application, since at least one control unit on a system-level chip is connected to multiple processing units, the control unit can allocate part or all of the multiple storage banks connected to and controlled by it to each processing unit based on the storage space capacity of each storage bank, so that the number of storage banks obtained by each processing unit is equal or substantially equal, and the storage space capacity of the storage banks obtained by each processing unit is equal or substantially equal. This achieves dynamic allocation of storage space capacity and dynamic allocation of bandwidth within the processing system, improves capacity consistency and bandwidth consistency between processing units, and prevents certain storage banks from becoming performance bottlenecks for a particular processing unit due to their low storage space capacity, nor does it reduce the available storage space capacity and bandwidth of the entire processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1A to 1C A schematic diagram of the storage space capacity of a storage block provided in an embodiment of the present application;

[0031] Figure 2 Schematic diagram 1 of the architecture of a processing system provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 2 ;

[0033] Figure 4 A partial schematic diagram of the architecture of a processing system provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 3 ;

[0035] Figure 6 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 4 ;

[0036] Figure 7 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 5 ;

[0037] Figure 8 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 6 ;

[0038] Figure 9 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 7 ;

[0039] Figure 10 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 8 ;

[0040] Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the embodiments of this application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0045] AI chips support complex model training and real-time data processing, placing significant demands on the storage capacity of memory chips and the data transmission speed between the memory chips and the system-on-chip. To meet the high-performance computing needs of AI chips, the processing system must provide stable and reliable storage performance, and the memory chip must provide consistent capacity and bandwidth for each processing element (PE). PE bandwidth refers to the amount of data that PE can receive or send per unit time.

[0046] However, due to the yield problem of memory chips, especially after multi-layer memory chips are stacked, the yield is low and the yield distribution is irregular. This makes it difficult to ensure that the storage space capacity provided to each PE is equal. Specifically, Figure 1A As shown in the figure, a storage group includes four storage blocks. Due to yield issues, the available capacity of each storage block (the size of the available capacity is represented by the size of the rectangle) is not consistent. If the available capacity of the storage blocks is inconsistent, it may cause it to become a performance bottleneck and reduce the bandwidth of the entire PE. In order to ensure that the capacity and bandwidth provided by each storage group are consistent, it is necessary to adjust the capacity of the storage blocks in the storage group to a uniform level, or adjust the capacity of all storage blocks on the storage chip to a uniform level. This process is called "alignment". Specifically, as Figure 1B As shown, taking the storage block BK1 with the lowest capacity as the reference, by giving up part of the available capacity of other storage blocks, the available capacity of each storage block is adjusted to be equal to the available capacity of storage block BK1. Of course, if the available capacity of a storage block is particularly low, it may seriously affect the performance of the storage group. Figure 1C As shown, to ensure the reliability of the entire memory chip or memory module, the entire memory group (i.e., memory blocks BK4 to BK7) can be discarded and the entire memory chip can be downgraded. Obviously, no matter which of the above methods is used, a large amount of memory chip resources will be wasted.

[0047] AI chips generally use a network on chip (NOC) architecture to organize different processing units and memories located on the same chip. In the NOC architecture, each processing unit is connected to an internal network, and data is transmitted between nodes through routers. Each router is a network node that uses routers to connect the various processing units in the system on chip (SoC) by simulating a network. In order to provide consistent capacity and bandwidth for each processing unit, factors such as routing algorithms, flow control, and network topology need to be considered, making the design of the NoC communication architecture much more complex than traditional bus design.

[0048] In view of this, the embodiment of the present application provides a processing system, such as Figure 2 As shown, the processing system includes: a system-level chip 201 and a memory chip 202;

[0049] The system-on-chip 201 includes multiple control units 203 and multiple processing units 204;

[0050] The memory chip 202 includes multiple groups of memory banks 205;

[0051] The processing unit 204 is connected to at least two of the control units 203;

[0052] The control unit 203 is connected to at least one group of the storage bodies 205 , and the control unit 203 is connected to at least two of the processing units 204 ; wherein the control unit 203 is configured to allocate the connected storage bodies 205 to one or more of the processing units 204 .

[0053] The memory chip 202 is used to store data, which can be organized into multiple groups of memory banks 205, wherein each memory bank 205 can include multiple memory arrays or multiple memory cells. Each memory bank 205 can independently perform read or write operations. For example, a DRAM chip that uses the amount of charge stored in a capacitor to store data includes multiple memory banks, and each memory bank has a certain amount of storage space. Specifically, each memory bank can include multiple memory arrays, and each memory array can include multiple memory cells (for example, a memory cell with a 1T1C structure, including a transistor and a capacitor). In addition, each memory bank has an independent row decoder (Row Decoder), column decoder (Column Decoder) and buffer (Row Buffer), which can independently perform operations such as activation (Activate), reading (Read), writing (Write) and precharge (Precharge).

[0054] The control unit 203, also known as the memory controller (MC), is connected to the memory chip 202 via a specific interface. The system-on-chip 201 includes multiple control units 203, each of which is used to manage and control data transmission between the processing unit 204 and multiple memory banks 205, thereby implementing data read and write operations on these memory banks 205. Specifically, the control unit 203 can translate the logical address of data sent by the processing unit 204 into a physical address and generate access commands such as read, write, and refresh based on the processing unit 204's request.

[0055] The processing unit 204 is the smallest hardware unit in the system-on-chip 201 that can execute instructions. Exemplarily, the processing unit 204 can be a core in a central processing unit (CPU), a stream processor in a graphics processing unit (GPU), or a tensor core in a tensor processing unit (TPU). Multiple processing units 204 can be configured to process data in parallel to increase the processing speed of the entire processing system. It should be noted that the multiple processing units in the processing system provided in the embodiment of the present application can be the same core or different cores.

[0056] The processing unit 204 can access multiple storage bodies 205 through one or more control units 203. These storage bodies 205 can be considered a group of storage bodies 205 corresponding to the processing unit 204. Because at least one control unit 203 on the system-on-chip 201 is connected to multiple processing units 204, part or all of the multiple storage bodies 205 connected to and controlled by it can be allocated to the corresponding processing units 204 based on the storage space capacity of each storage body, so that the number of storage bodies 205 obtained by each processing unit 204 is equal or substantially equal, and the storage space capacity of the storage bodies 205 obtained is equal or substantially equal. The low storage space capacity of some storage bodies 205 will not cause them to become performance bottlenecks, thereby reducing the bandwidth of the entire processing unit 204. The bandwidth of a processing unit 204 refers to the amount of data that the processing unit 204 can receive or send per unit time.

[0057] In a specific embodiment, if Figure 3As shown, the system-on-chip 201 includes three control units 203 (control unit MC1, control unit MC2 and control unit MC3) and two processing units 204 (processing unit PE0 and processing unit PE1). Each control unit 203 is connected to and controls four storage bodies 205. Control unit MC0 is connected to processing unit PE0, control unit MC1 is connected to processing unit PE0 and processing unit PE1, and control unit MC2 is connected to processing unit PE1. Since control unit MC1 is connected to two processing units 204, control unit MC1 can distribute storage bodies 205 (storage bodies B04 to storage bodies B07) to processing unit PE0 and processing unit PE1 according to the storage space capacity of each storage body 205, so that the number of storage bodies and storage space capacity allocated to processing unit PE0 and processing unit PE1 are the same or substantially the same, thereby improving the consistency between processing unit PE0 and processing unit PE1. Since each processing unit 204 can obtain sufficient storage space, the data processing requirements of each processing unit 204 can be met.

[0058] In addition, it should be noted that, for multiple storage banks 205 connected to the same control unit 203, they can be configured into several storage bank groups. Figure 3 , memory banks B00 and B01 can be configured as memory bank set BG0, and memory banks B02 and B03 can be configured as memory bank set BG1. Control unit MC0 can operate memory bank set BG0 and memory bank set BG1 at the rising edge and falling edge of a clock respectively to improve bandwidth.

[0059] In the processing system provided by the application embodiment, since at least one control unit on a system-on-chip is connected to multiple processing units, the control unit can allocate some or all of the multiple memory banks connected to and controlled by it to each processing unit based on the storage space capacity of each memory bank, so that each processing unit obtains an equal or substantially equal number of memory banks and an equal or substantially equal storage space capacity of each memory bank. This achieves dynamic allocation of storage space capacity and bandwidth within the processing system, improving capacity and bandwidth consistency between processing units. The low storage space capacity of certain memory banks will not cause them to become performance bottlenecks for a particular processing unit, nor will it reduce the available storage space capacity and bandwidth of the entire processing unit.

[0060] In some embodiments, as Figure 4 As shown, the storage body 205 includes an available storage body 215 and a faulty storage body 225; the storage space capacity of the faulty storage body 225 is smaller than the storage space capacity of the available storage body 215;

[0061] The control unit 203 is configured to allocate the connected available storage 215 to one or more of the processing units 204 .

[0062] During the manufacturing process of the memory chip 202, due to process and other reasons, the yield of different memory banks 205 is different, that is, the amount of storage space that can be normally used in different memory banks 205 is different. If the amount of storage space that can be normally used in a certain memory bank 205 is particularly low, if the other memory banks in a group of memory banks are all lowered to the same level in order to align the memory bank, a large amount of storage space will be wasted. Figure 4 The area of ​​a memory bank represents the amount of storage space available for normal use. Among them, memory bank B04 has the smallest amount of available storage space. If the available space in memory bank B04 is retained, most of the available storage space in memory banks B05 to B07 will need to be discarded to ensure consistency, resulting in a significant waste of storage space.

[0063] Continue to refer Figure 4 By abandoning the faulty storage body B04, the control unit 203 allocates other available storage bodies (storage bodies B05 to storage bodies B07) to the processing unit PE0 and / or the processing unit PE1, so that the number of storage bodies and the storage space capacity allocated to the processing unit PE0 and the processing unit PE1 are the same or basically the same. On the basis of ensuring the consistency between the processing unit PE0 and the processing unit PE1, the storage space of the system is increased and the utilization rate of the memory chip 202 is improved.

[0064] In some embodiments, the difference between the quantities of the available memory banks 215 allocated to at least some of the processing units 204 is less than or equal to 1.

[0065] Based on the connection status of the available storage 215 and the faulty storage 225 , the connection relationship between the processing unit 204 and the available storage 215 can be dynamically adjusted so that the available storage 215 can be evenly distributed to each processing unit 204 .

[0066] like Figure 5 As shown, the four memory banks connected to control unit MC1 include one faulty memory bank (memory bank B04) and three available memory banks (memory banks B04 to B07); the four memory banks connected to control unit MC2 include one faulty memory bank (memory bank B10) and three available memory banks (memory banks B08, B09, and B11). Control unit MC1 can allocate available memory bank B05 to processing unit PE0 and available memory banks B06 and B07 to processing unit PE1, so that the number of available memory banks obtained by processing unit PE0 is 5, which is equal to the number of available memory banks obtained by processing unit PE1.

[0067] In some embodiments, the number of available storage banks may not be evenly distributed. The available storage banks 215 may be allocated according to the needs of each processing unit 204, so that the number of available storage banks 215 allocated to each processing unit 204 is not equal. However, in order to control the performance differences of each processing unit 204, the difference in number should not be too large. For example, the difference in the number of available storage banks 215 allocated to each processing unit 204 may be 1. Figure 6 As shown, the four memory banks connected to the control unit MC1 include one faulty memory bank (memory bank B04) and three available memory banks (memory banks B04 to B07). The control unit MC1 can allocate available memory banks B05 and B06 to the processing unit PE0, and allocate available memory bank B07 to the processing unit PE1, so that the number of available memory banks obtained by the processing unit PE0 is 5, and the number of available memory banks obtained by the processing unit PE1 is 6.

[0068] In some embodiments, the memory chip 202 further includes a redundant memory bank 235;

[0069] The control unit 203 is configured to allocate the connected redundant storage bank 235 to one or more of the processing units 204 .

[0070] Due to the complexity of memory chip manufacturing processes, some memory cells may be defective during production. To improve the yield and reliability of memory chips, additional storage space resources are typically configured within the memory chip. This allows for the subsequent use of redundant repair technologies to detect defective memory cells during production and replace defective rows / columns with redundant rows / columns. Specifically, address mapping can be altered so that addresses originally accessing defective memory cells are mapped to redundant rows / columns, thereby ensuring that the memory chip can provide the expected storage capacity and performance. Typically, the activation and mapping of redundant rows / columns requires precise control at the physical level of the memory chip. For example, in DRAM chips, address decoding and mapping are performed by specialized logic circuits that map logical addresses to physical addresses. This built-in logic control within the memory chip can reduce the design complexity of the system-on-chip (SoC). However, for memory chips with relatively few defective memory cells, the number of defective rows / columns that require repair may be minimal, or even unnecessary redundant row / column resources. This results in unused available storage space in the redundant rows / columns, resulting in wasted resources. Furthermore, for memory chips with a large number of defective memory cells, there may be a shortage of redundant row / column resources. Even if they are repaired using redundant rows / columns, the available storage space capacity of the repaired memory bank will not meet the target requirements. In particular, for stacked multi-layer memory chips, the yield of each layer of chips has no regular distribution pattern. Moreover, the yield of each layer can vary greatly. This results in some layers of memory chips having too many defective memory cells and insufficient capacity after repair, resulting in wasted memory bank resources. Other layers of memory chips have too few defective memory cells and cannot utilize redundant resources, resulting in wasted resources. This significantly reduces the resource utilization of multi-layer memory chips.

[0071] Direct management of redundant memory banks 235 (i.e., redundant rows and columns) by control unit 203 in SoC 201 effectively shifts memory chip repair work from within the memory chip to the system. All redundant rows and columns can be made available to SoC 201, fully utilizing the storage space resources within the redundant memory banks. This eliminates the waste of storage space caused by redundant rows and columns remaining unavailable to the system after a memory chip repair.

[0072] In some embodiments, the control unit 203 is configured to determine the number of the memory banks allocated to the connected processing unit according to the credit value of the processing unit 204 and the total amount of the memory banks 205;

[0073] The credit value is used to indicate the bandwidth requirement of the processing unit.

[0074] In the control unit 203, different bandwidths can be allocated to the processing units 204 through a credit mechanism. For example, when a processing unit 204 requests the control unit 203 to perform a read or write operation, the control unit 203 indicates the number of requests that the control unit 203 can process for each processing unit 204, that is, the amount of available storage 215 that can be allocated to each processing unit 204, based on the credit value of the processing unit 204 connected to the control unit 203 and the storage space capacity of the storage 205 connected to the control unit 203 (for example, the total amount of available storage 215).

[0075] Continue to refer Figure 5 , both processing unit PE0 and processing unit PE1 can access control unit MC1. Based on the bandwidth requirements of processing unit PE0 and processing unit PE1, control unit MC1 can allocate one of the three available memory banks to processing unit PE0 and the other two available memory banks to processing unit PE1 by configuring credit_PE0=1 and credit_PE1=2.

[0076] In some embodiments, at least part of the control units 203 in the system-on-chip 201 are connected to at least two of the processing units 204 .

[0077] In some embodiments, some control units 203 in the system-on-chip 201 are connected to two or more processing units 204. The memory banks 205 accessible to these processing units 204 are organized into a memory pool. This control unit 203 dynamically adjusts the accessible memory space of each processing unit based on available memory banks and faulty memory banks within the memory pool, enabling unified management of the memory space within the memory pool. Even if a faulty memory bank occurs, it does not affect the use of other available memory banks within the connected control units.

[0078] It should be noted that, according to the connection relationship between the processing unit and the control unit, the memory chip 202 can be divided into one or more memory pools, each memory pool includes memory banks corresponding to multiple processing units, and each memory pool is independent of each other. Figure 7 As shown, the memory banks corresponding to the processing units PE0 and PE1 (including memory banks B00 to B11) can be divided into one memory pool, and the memory banks corresponding to the processing units PE2 and PE3 (including memory banks B12 to B23) can be divided into another memory pool.

[0079] In some embodiments, all control units 203 in the system-on-chip 201 are connected to two or more processing units 204. In this case, all memory banks on the memory chip 202 can be regarded as a large memory pool. Each control unit 203 can adjust the number of memory banks allocated to the processing unit 204 to which it is connected based on the bandwidth requirements of the processing unit 204, further increasing the flexibility of memory bank allocation within the processing system. It is understandable that, based on the connection relationship between the processing unit and the control unit, the memory chip 202 can also be divided into one or more smaller memory pools, each small memory pool including memory banks corresponding to multiple processing units, and the small memory pools are independent of each other.

[0080] In some embodiments, some of the control units are connected to one processing unit;

[0081] Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1;

[0082] The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

[0083] In a resource pool consisting of m processing units and n control units, if each processing unit is connected to N control units, N of the n control units are connected to one processing unit, and the other control units are connected to two control units, then the total number of processing units m and the total number of control units n satisfy the following formula (1):

[0084]

[0085] Continue to refer Figure 5 In system-on-chip 201, control unit MC0 is connected only to processing unit PE0; control unit MC2 is connected only to processing unit PE1; and control unit MC1 is connected to both processing units PE0 and PE1. The multiple memory banks connected to these three control units form a memory pool. Even if a faulty memory bank (e.g., memory banks B04 and B10) occurs within the memory pool, the system can evenly distribute the remaining available memory banks 215 between processing units PE0 and PE1 by dynamically adjusting the available memory banks allocated to them by connecting control unit MC1 to both.

[0086] In some embodiments, each of the control units 203 is connected to two of the processing units 204;

[0087] Each of the processing units 204 is connected to N of the control units; wherein N is an integer greater than 1;

[0088] The total number of the control units 203 is N / 2 times the total number of the processing units 204 .

[0089] In a resource pool consisting of m processing units and n control units, if each control unit 203 is connected to two processing units 204, and each processing unit is connected to N control units, then the total number of processing units m and the total number of control units n satisfy the following formula (2):

[0090]

[0091] like Figure 8 As shown in Figure 1, the SoC includes three processing units (PE0, PE1, and PE2) and three control units (MC0, MC1, and MC2). Each processing unit can access the memory chip through two control units. Each control unit can adjust the number of memory banks allocated to its connected processing units based on their bandwidth requirements, increasing the system's flexibility.

[0092] It should be noted that, continue to refer to Figure 8 If the three processing units are arranged linearly on the SoC 201, the connection circuit between the processing unit PE2 and the control unit MC0 may be too long, resulting in signal delays or inconsistent performance between the processing units. Therefore, in other embodiments, the processing units 204 and the control units 203 may be arranged in a ring shape on the SoC 201.

[0093] In some embodiments, a plurality of the memory chips are stacked in sequence in a direction perpendicular to the plane where the system-on-chip is located.

[0094] Higher storage density and performance can be achieved by stacking multiple layers of memory chips in the vertical direction. For example, a 3D DRAM chip is obtained by stacking multiple DRAM layers in the vertical direction. By directly stacking the 3D DRAM chip with the SOC chip and connecting them through high-density through silicon vias (TSV), the data transmission path can be greatly shortened, thereby reducing signal delay and significantly improving data transmission bandwidth. It should be noted that the 3D DRAM chip and the SOC chip can also be laid on the same horizontal plane. As long as they are integrated in the same package, the operating efficiency within the system can be effectively improved.

[0095] This application also provides a comparative example and a specific example:

[0096] Figure 9 A processing system in a comparative embodiment is shown. Figure 9As shown, the system-on-chip 201 includes four processing units and eight control units, and each processing unit is connected to two control units. Each processing unit can independently access the eight corresponding memory banks. Since there are two faulty memory banks (memory bank B24 and memory bank B25) among the four memory banks connected to the control unit MC5, in order to ensure that the storage space capacity of each processing unit is the same, one method is to configure the available memory banks in all control units to two, so that the storage space of the entire memory chip 202 is halved. Alternatively, all the memory banks in the control unit MC6 (including available memory bank B26 and available memory bank B27) are discarded. Although only two available memory banks are reduced, it will cause bandwidth loss of the control unit MC6.

[0097] like Figure 10 As shown, the memory chip 202 is a 3D DRAM chip, which includes multiple memory banks. The system-on-chip 201 includes three processing units and eight control units. Each processing unit is connected to four control units, and the control unit is connected to one or two processing units. The 32 memory banks connected by the three processing units through the eight control units form a resource pool. This connection architecture can be called a "Butterfly" resource pool architecture. When some of the memory banks in the resource pool are faulty memory banks, the control unit can distribute all available memory banks evenly to each processing unit based on the distribution of the faulty memory banks and available memory banks. Among them, processing units and memory banks with the same background can be regarded as a group, and the software can control each processing unit to access the memory banks in its corresponding group. For example, the processing unit PE0 can access the memory banks B00, B01 and B02 through the control unit MC0; and access the memory bank B04 through the control unit MC1.

[0098] The "Butterfly" resource pool architecture enables dynamic allocation of storage space. Specifically, since the control unit MC1 is connected to two different processing units, it can be accessed by both the processing unit PE0 and the processing unit PE1. The storage bodies connected to the control unit MC1 can be proportionally allocated to the processing unit PE0 and the processing unit PE1 as needed. Similarly, the storage bodies corresponding to the control units MC2, MC5, and MC6 connected to the two processing units are proportionally allocated to each processing unit to achieve unified management of the resource pool. Even if a certain storage body is a faulty storage body, it will not affect the normal use of other available storage bodies in the group or other available storage bodies on the memory chip.

[0099] In some extreme cases, for example, if the eight memory banks corresponding to the control unit MC1 and the control unit MC5 are all faulty memory banks, the memory banks in the resource pool may not be evenly distributed. However, it is understandable that the probability of such an extreme case is extremely small and can generally be ignored. In addition, it should be noted that in Figure 8In the ring connection architecture shown, even if the above extreme situation occurs, it will not affect the even distribution of available memory banks in the system.

[0100] The "Butterfly" resource pool architecture enables dynamic bandwidth allocation. Specifically, in control unit MC1 or control unit MC5, dynamic bandwidth allocation can be achieved by configuring credit_PE0 and credit_PE1, ensuring that processing unit PE0 and processing unit PE1 have the same storage capacity and bandwidth to meet the requirements of each processing unit in AI multi-core applications.

[0101] The "Butterfly" resource pool architecture can improve the yield rate in 3D DRAM applications. Assuming that the yield rate of a memory bank or memory macro (DRAM Macro) including multiple memory cells is 90%, there are 640 memory banks or memory macros in the multi-layer stacked memory chip, and each control unit can control 10 memory banks or memory macros. The total available capacity of the 3D DRAM chip is greater than or equal to 80%, and it is considered that the 3D DRAM chip meets the target requirements. Figure 9 In the processing system connection architecture shown, each control unit is considered a bank, and all 64 control units within the system must meet the 80% yield requirement. When calculating yield using a Poisson distribution, the yield rate of 3D DRAM chips meeting the target requirement is 0.47%. If a "Butterfly" resource pool architecture is adopted, assuming that the memory banks or memory macros corresponding to eight control units form one resource pool, only the 80% yield requirement needs to be met within each of the eight control units. Calculations show that the probability of all eight resource pools achieving the 80% yield requirement is 97%, meaning that 97% of the memory chips will meet the target requirement. Compared to the previous 0.47%, the "Butterfly" resource pool architecture can significantly improve the yield rate of memory chips.

[0102] In addition, compared with the solution of using the NOC bus to connect the system-level chip and the storage chip, the "Butterfly" resource pool architecture does not increase latency because the processing unit and the control unit are connected via a point-to-point bus.

[0103] In addition, the redundant memory banks in the memory chip 202 can be opened to the system-level chip 201, that is, the system-level chip 201 can access the redundant memory banks, and thus can make full use of this part of the storage space, reduce the waste of storage space, and improve the utilization rate of the storage space in the memory chip 202. Specifically, before bonding the system-level chip 201 and the memory chip 202, there is no need to use the redundant memory banks to repair the memory chip 202. The repair work of the memory chip 202 is transferred to the system-level chip 201 side. The system selects some or all of the faulty memory banks for repair based on the distribution of the faulty memory banks in the entire memory chip. Even if the extreme situation discussed above occurs, the system may still achieve an even distribution of the available memory banks to each processing unit after repairing some of the memory banks corresponding to the control unit MC1 or the control unit MC5. In addition, the system-level chip 201 can also access the redundant memory banks remaining after the repair, which greatly increases the accessible storage space capacity of the system.

[0104] Based on the same inventive concept, the embodiment of the present application further provides an electronic device 300, such as Figure 11 The present invention includes: a processing system 200 as described above;

[0105] The peripheral interface 301 is connected to the processing system 200 .

[0106] Since the system-level chip and the memory chip in the electronic device are connected to form the above-mentioned processing system 200, which has the same or similar beneficial effects as the above-mentioned processing system 200, the beneficial effects of the electronic device are not repeated here.

[0107] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0108] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A processing system, characterized in that: include: System-on-chip and memory chips; The system-on-chip includes multiple control units and multiple processing units; The memory chip includes multiple groups of memory banks; The processing unit is connected to at least two of the control units; The control unit is connected to at least one group of the storage bodies, and the control unit is connected to at least two of the processing units; wherein, the control unit is used to allocate part or all of the connected storage bodies to one or more of the processing units according to the storage space capacity of each of the storage bodies, so that the storage space capacity of the storage bodies obtained by each processing unit is equal or substantially equal.

2. The processing system according to claim 1, wherein: The storage body includes an available storage body and a faulty storage body; the storage space capacity of the faulty storage body is smaller than the storage space capacity of the available storage body; The control unit is configured to allocate the connected available memory banks to one or more of the processing units.

3. The processing system according to claim 2, characterized in that A difference between the quantities of the available memory banks allocated to at least some of the processing units is less than or equal to 1.

4. The processing system according to claim 1, wherein: The memory chip also includes redundant memory banks; The control unit is configured to allocate the connected redundant memory banks to one or more of the processing units.

5. The processing system according to claim 1, wherein: The control unit is configured to determine the number of the memory banks allocated to the connected processing unit according to the credit value of the processing unit and the total amount of the memory banks; The credit value is used to indicate the bandwidth requirement of the processing unit.

6. The processing system according to any one of claims 1 to 5, characterized in that: At least part of the control units in the system-on-chip are connected to at least two of the processing units.

7. The processing system according to claim 6, characterized in that Some of the control units in the control unit are connected to one of the processing units; Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1; The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

8. The processing system according to claim 6, characterized in that Each of the control units is connected to two of the processing units; Each of the processing units is connected to N control units; wherein N is an integer greater than 1; The total number of the control units is N / 2 times the total number of the processing units.

9. The processing system according to any one of claims 1 to 5, characterized in that: In a direction perpendicular to the plane where the system-on-chip is located, a plurality of the memory chips are stacked in sequence.

10. An electronic device, characterized in that: include: The processing system according to any one of claims 1 to 9; A peripheral interface is connected to the processing system.

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