Method and storage system for managing shared buffer data based on type tracking

Abstract

The present invention provides a method for managing data in a shared buffer based on type tracking and a storage system. The method includes: configuring a shared buffer in the memory of a host system, and a storage device is used to perform a preset operation based on data cached in the shared buffer; tracking the type of at least one mapping entry cached in the shared buffer to obtain a tracking result; determining the priority of a target mapping entry in the at least one mapping entry according to the tracking result; and retaining the target mapping entry in the shared buffer or removing the target mapping entry from the shared buffer according to the priority. Thereby, the performance of the storage device or the entire storage system can be effectively improved on the premise of not affecting the operation efficiency of the host system itself as much as possible.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and in particular, to a method for managing data in a shared buffer based on type tracking and a storage system. Background Art

[0002] NAND flash is a non-volatile memory technology that is widely used in various storage devices. It stores charge by using floating-gate transistors, and each transistor represents a storage cell. NAND flash cells usually organize data in the form of pages, each page contains multiple bytes, and multiple pages form a block. Data is read and programmed in units of pages, while the erase operation is performed in units of blocks. This organization makes NAND flash very suitable for large-capacity storage and has a relatively high write speed.

[0003] However, as the storage capacity of storage devices continues to increase, the amount of management data used to manage the storage devices also continues to increase, resulting in insufficient use of the small-capacity memory of the storage devices themselves. Summary of the Invention

[0004] The present invention provides a method for managing data in a shared buffer based on type tracking and a storage system, which can effectively improve the performance of a storage device or the entire storage system on the premise of minimizing the impact on the operating efficiency of the host system.

[0005] An embodiment of the present invention provides a method for managing data in a shared buffer based on type tracking, which is used for a storage system. The storage system includes a host system and a storage device. The host system is connected to the storage device, and the method for managing data in the shared buffer based on type tracking includes: configuring a shared buffer in the memory of the host system, where the storage device is used to perform a preset operation based on the data cached in the shared buffer; tracking the type of at least one mapping table entry cached in the shared buffer to obtain a tracking result; determining the priority of a target mapping table entry in the at least one mapping table entry according to the tracking result; and retaining the target mapping table entry in the shared buffer or removing the target mapping table entry from the shared buffer according to the priority.

[0006] An embodiment of the present invention further provides a storage system, which includes a host system and a storage device. The storage device is connected to the host system. The host system is configured to: configure a shared buffer in the memory of the host system, wherein the storage device is configured to perform a preset operation based on the data cached in the shared buffer; track the type of at least one mapping entry cached in the shared buffer to obtain a tracking result; determine the priority of a target mapping entry in the at least one mapping entry according to the tracking result; and retain the target mapping entry in the shared buffer or remove the target mapping entry from the shared buffer according to the priority.

[0007] Based on the above, a shared buffer can be configured in the memory of the host system, and the storage device can perform a preset operation based on the data cached in the shared buffer. When the storage system operates, the type of at least one mapping entry cached in the shared buffer can be tracked to obtain a tracking result. According to the tracking result, the priority of the target mapping entry in the shared buffer can be determined. Then, according to the priority, the target mapping entry can be retained in the shared buffer or removed from the shared buffer. Thus, the performance of the storage device or the entire storage system can be effectively improved on the premise of minimizing the impact on the operation performance of the host system itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a storage system shown according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0011] Figure 4 is a flowchart of a method for managing shared buffer data based on type tracking shown according to an embodiment of the present invention;

[0012] Figure 5 is a flowchart of a method for managing shared buffer data based on type tracking shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a schematic diagram of a storage system shown according to an embodiment of the present invention. Please refer toFigure 1 , a storage system (also known as a data storage system) 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and is used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The host system 11 includes a processor 111 and a memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 can include a Central Processing Unit (CPU), a Graphical Processing Unit (GPU), or other programmable general-purpose or special-purpose microprocessors, a Digital Signal Processor (DSP), a programmable controller, an Application Specific Integrated Circuits (ASIC), a Programmable Logic Device (PLD), or other similar devices or a combination of these devices.

[0016] The memory 112 is connected to the processor 111 and is used to cache data. For example, the memory 112 can include a Random Access Memory (RAM) or a similar volatile storage device. It should be noted that the memory 112 is installed in the host system 11 (such as installed on the motherboard of the host system 11 or directly installed in the processor 111), rather than installed in the storage device 12.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as the threshold voltage). For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other programmable general-purpose or special-purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 can send an instruction sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0021] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0025] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to non-volatilely store data.

[0026] In one embodiment, a physical unit may include one or more physical erasure units. In addition, a physical unit may include a plurality of sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0027] In one embodiment, an entity programming unit may include a plurality of entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, both the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit may be adjusted according to practical requirements, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be regarded as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited to this.

[0028] In one embodiment, an entity programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on an entity programming unit to write data into this entity programming unit, multiple memory cells in this entity programming unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programming unit, a write voltage may be applied to this entity programming unit to change the threshold voltage of at least some of the memory cells in this entity programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in this memory cell.

[0029] In one embodiment, an entity erasure unit may include a plurality of entity programming units. The plurality of entity programming units in an entity erasure unit may be synchronously erased. For example, when performing an erase operation on an entity erasure unit, an erase voltage may be applied to the plurality of entity programming units in this entity erasure unit to change the threshold voltage of at least some of the memory cells in these entity programming units. By performing an erase operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0030] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0031] In one embodiment, if a certain physical unit does not store valid data, this physical unit can be associated with the idle area 32. In addition, the physical units in the idle area 32 can be erased to clear the data in this physical unit. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as the free pool.

[0032] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After the data is stored in this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be alternately used between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1) to 302(C) to map the physical units in the data area 31 (i.e., physical units 301(1) to 301(A)). For example, one logical unit can correspond to one logical block address (Logical Block Address, LBA) or other logical management units. One logical unit can be mapped to one or more physical units.

[0034] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform operations such as data reading, writing, or erasing according to the information in this management table (i.e., the logical-to-physical mapping table).

[0036] In one embodiment, the processor 111 may configure a shared buffer 101 in the memory 112. By leveraging the memory resources of the host system 11 (such as the shared buffer 101), the processor 111 provides an efficient temporary data exchange space for the storage device 12, which not only reduces the latency caused by frequent access to the flash memory but also significantly improves the performance of random read and write operations. Specifically, based on the data in the shared buffer 101, the storage device 12 can perform preset operations related to the memory module 122, such as at least one of the following operations: ① Command scheduling optimization: Allows the memory control circuit 23 to temporarily store multiple I / O requests from the host system 11 in the shared buffer 101 in advance, thereby optimizing the execution order of these requests, reducing unnecessary addressing time and page switching, and improving the overall response speed. ② Address mapping management: The shared buffer 101 can be used to store and update the logical-to-physical address mapping table (L2P Mapping Table), accelerating the process of finding the data location, especially for random read operations, and greatly improving the efficiency. And perform sorting operations on multiple mapping table entries cached in the shared buffer 101 according to a sorting algorithm to obtain a sorted queue and other operations. ③ Data caching: When reading data from the memory module 122, if the data has been loaded into the shared buffer 101, it can be directly obtained from it, avoiding accessing the slower memory module 122 again, thereby accelerating the data reading speed. Similarly, when writing new data, the data can be temporarily stored in the shared buffer 101 first, and then it is decided when and how to persist it to the memory module 122 according to the background optimization strategy. ④ Metadata processing: In addition to user data, it can also be used to cache key metadata such as the file allocation table (FAT), wear leveling information, etc., to ensure efficient data management and access patterns even under high load conditions.

[0037] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12. For example, the memory control circuit 23 may perform a handshake operation with the host system 11. The handshake operation is used to exchange information related to the establishment of the connection between the host system 11 and the storage device 12, such as clock information and / or voltage information, etc.

[0038] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12 according to the execution result of the handshake operation. Thereafter, the memory control circuit 23 may access (also referred to as access) the shared buffer 101 through the connection.

[0039] In one embodiment, the memory control circuit 23 may store management data in the shared buffer 101. During the access to the memory module 122, the memory control circuit 23 may query or update (i.e., modify) the management data correspondingly in the shared buffer 101. For example, the management data may include partial data (also referred to as mapping table entries) in the logical-to-physical mapping table. The mapping table entries may carry mapping information (such as logical-to-physical mapping information). The mapping information may reflect the mapping relationship between at least one logical unit and at least one physical unit.

[0040] In one embodiment, when the host system 11 desires to read data belonging to a certain logical unit (also referred to as the first logical unit) from the storage device 12, the processor 111 may store the read information corresponding to the first logical unit in the shared buffer 101. For example, the read information may include a read instruction indicating to read data belonging to the first logical unit. For example, the read instruction may include a random read instruction and / or a sequential read instruction. The random read instruction is used to indicate reading data from a single logical unit or multiple discontinuous logical units. The sequential read instruction is used to indicate reading data from multiple consecutive logical units. The memory control circuit 23 may access the shared buffer 101 to obtain the read information.

[0041] After obtaining the read information, the memory control circuit 23 may confirm whether the mapping table entry related to the first logical unit has been cached in the shared buffer 101. If the mapping table entry related to the first logical unit is not cached in the shared buffer 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 into the shared buffer 101.

[0042] If the mapping table entry related to the first logical unit has been cached in the shared buffer 101 (or after loading the mapping table entry from the memory module 122 into the shared buffer 101), the memory control circuit 23 may query the mapping table entry in the shared buffer 101 to obtain the mapping relationship between the first logical unit and the physical unit (also referred to as the first physical unit) in the memory module 122. Then, the memory control circuit 23 may read data (also referred to as the first data) from the first physical unit in the memory module 122 according to this mapping relationship. Then, the memory control circuit 23 may return the read first data to the host system 11 to respond to the read information.

[0043] In one embodiment, when the host system 11 desires to store data (also referred to as second data) belonging to a certain logical unit (also referred to as the second logical unit) in the storage device 12, the processor 111 may store the write information corresponding to the second logical unit in the shared buffer 101. For example, the write information may include a write instruction indicating an update to the data belonging to the second logical unit. For example, the write instruction may include a random write instruction and / or a sequential write instruction. The random write instruction is used to indicate an update to the data belonging to a single logical unit or multiple discontinuous logical units. The sequential write instruction is used to indicate an update to the data belonging to multiple consecutive logical units. The memory control circuit 23 may access the shared buffer 101 to obtain the write information.

[0044] After obtaining the write information, the memory control circuit 23 may store the second data in a physical unit (also referred to as the second physical unit) in the memory module 122 according to the write information. On the other hand, the memory control circuit 23 may confirm whether the mapping table entry related to the second logical unit has been cached in the shared buffer 101. If the mapping table entry related to the second logical unit is not cached in the shared buffer 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 into the shared buffer 101. If the mapping table entry related to the second logical unit has been cached in the shared buffer 101 (or after loading the mapping table entry from the memory module 122 into the shared buffer 101), the memory control circuit 23 may update the mapping table entry in the shared buffer 101 to establish a mapping relationship between the second logical unit and the second physical unit. Then, the memory control circuit 23 may notify the host system 11 to complete the write operation in response to the write information.

[0045] In one embodiment, the memory control circuit 23 may also store other types of management data in the shared buffer 101 (e.g., loaded from the memory module 122 into the shared buffer 101). For example, the management data may include valid count management data, wear leveling management data, or bad block management data, etc., which are not limited in the present invention. The valid count management data is used to manage the valid data storage status of at least some physical units in the memory module 122. For example, the valid count management data may include valid counts corresponding to at least one physical unit in the memory module 122. The wear leveling management data is used to manage the wear status of at least some physical units in the memory module 122. For example, the wear leveling management data may include read counts, write counts, and / or erase counts corresponding to at least one physical unit in the memory module 122. The bad block management data is used to manage the damaged physical units (also referred to as bad blocks) in the memory module 122. For example, the bad block management data can be used to mark at least one physical unit in the memory module 122 as a bad block. Thereafter, the memory control circuit 23 can access or manage the memory module 122 according to the management data in the shared buffer 101.

[0046] It should be noted that the shared buffer 101 provided in the memory 112 occupies a part of the storage space of the memory 112, resulting in a reduction in the capacity of the memory 112 available for the host system 11 itself. For example, after the shared buffer 101 is provided, the remaining capacity of the memory 112 after deducting the shared buffer 101 is the memory space available for the host system 11 itself. Therefore, if the capacity of the shared buffer 101 is larger, it may cause a reduction in the operating efficiency of the host system 11 itself (due to the reduction in the memory space available for the host system 11 itself). However, if the capacity of the shared buffer 101 is too small, it may reduce the performance of the storage device 12 (due to the reduction in the memory space available for the storage device 12).

[0047] According to the technical solution provided by the embodiment of the present invention, it is possible to achieve fine management of the mapping table entries resident in the shared buffer 101, including but not limited to operations such as sorting, adding, and removing, while maintaining a small capacity configuration of the shared buffer 101 (including but not limited to reducing its capacity requirements). In this way, on the basis of ensuring that the operating efficiency of the host system 11 is not disturbed, the performance of the storage device 12 and even the entire storage system 10 is further enhanced, achieving the best balance between the processing ability of the host system 11 and the response speed of the storage device 12, and ensuring that both can operate in an ideal state without affecting each other.

[0048] In particular, this solution is especially applicable to scenarios where random read and write performance needs to be improved. Traditionally, in order to maximize the efficiency of random read and write, in theory, all mapping table entries should be loaded into the cache memory 24. However, under the limitations of current product designs - for example, the cache memory 24 usually has a fixed capacity of 256 KB, while the data volume of the mapping table entries may reach 1 GB or more (taking a 1 TB capacity as an example), which makes it impossible to load all mapping table entries at once, resulting in the need to frequently load mapping table entries in batches, thereby increasing latency and affecting the read speed of the storage device 12. By adopting the shared buffer 101 to efficiently manage these mapping table entries, not only is this challenge solved, but also independent and non-interfering optimization of the performance of the host system 11 and the storage device 12 is achieved.

[0049] Specifically, this solution allows the storage system 10 to maintain high-speed data access speed and low-latency characteristics when processing a large number of mapping table entries, thus ensuring the performance metrics of random read and write. At the same time, it also avoids the cost increase caused by adding additional hardware resources, as well as problems such as increased system complexity and decreased stability that may be caused. In short, this innovative technical solution provides a feasible and efficient way to solve the challenges of high-performance storage systems.

[0050] However, through the technical solution proposed in the embodiments of the present invention, the mapping table entries cached in the shared buffer 101 can be properly managed (such as sorting, adding, and / or removing) when the capacity of the shared buffer 101 is not large (and even the capacity of the shared buffer 101 can be reduced). Thus, the efficiency of the storage device 12 or the entire storage system 10 can be effectively improved on the premise of minimizing the impact on the operation efficiency of the host system 11 itself.

[0051] In one embodiment, one or more mapping table entries can be cached in the shared buffer 101. After the memory control circuit 23 caches at least one mapping table entry in the shared buffer 101, the processor 111 can track the type of at least one mapping table entry cached in the shared buffer 101 to obtain a tracking result. In other words, the tracking result can reflect the type of the at least one mapping table entry currently cached in the shared buffer 101.

[0052] In one embodiment, the processor 111 may determine the priority of a certain mapping table entry (also referred to as the target mapping table entry) in the at least one mapping table entry according to the tracking result. For example, the priority may affect the order in which the target mapping table entry is retained in or removed from the shared buffer 101 when the memory 112 and / or the shared buffer 101 is about to be full or has already been full. Then, the processor 111 may retain the target mapping table entry in the shared buffer 101 or remove the target mapping table entry from the shared buffer 101 according to the priority.

[0053] In one embodiment, the processor 111 may obtain the identification information corresponding to the target mapping table entry. The identification information may reflect the type of the target mapping table entry. Then, the processor 111 may determine the type of the target mapping table entry according to the identification information.

[0054] In one embodiment, when the target mapping table entry is cached in the shared buffer 101, an identification information may be associated with the target mapping table entry according to the application to which the target mapping table entry belongs. For example, assume that the application to which the target mapping table entry belongs is Application A, then the identification information A corresponding to Application A may be associated with the target mapping table entry. Or, assume that the application to which the target mapping table entry belongs is Application B, then the identification information B corresponding to Application B may be associated with the target mapping table entry.

[0055] In one embodiment, the processor 111 may query the management table according to the identification information corresponding to the target mapping table entry to obtain a query result. The management table may record multiple types (also referred to as candidate types) respectively corresponding to multiple identification information (also referred to as candidate identification information). Then, the processor 111 may determine the type of the target mapping table entry from the multiple candidate types according to the query result. For example, according to the query result, the processor 111 may determine the candidate type matching the identification information in the management table as the type of the target mapping table entry.

[0056] In one embodiment, after determining the type of the target mapping table entry, the processor 111 may determine the priority of the target mapping table entry according to the type of the target mapping table entry. For example, mapping table entries of different types may have different priorities. For example, if the type of the target mapping table entry is a certain type (also referred to as the first type), the processor 111 may determine the priority of the target mapping table entry as a certain priority (also referred to as the first type priority). If the type of the target mapping table entry is another type (also referred to as the second type), the processor 111 may determine the priority of the target mapping table entry as another priority (also referred to as the second type priority). The first type priority may be different from the second type priority.

[0057] In one embodiment, assume that the target mapping table entry includes a first mapping table entry and a second mapping table entry. Both the first mapping table entry and the second mapping table entry are cached in the shared buffer 101. Assume that the type of the first mapping table entry is the first type, and the type of the second mapping table entry is the second type. In one embodiment, compared with the first mapping table entry (belonging to the first type) with the first type of priority, the processor 111 may preferentially remove the second mapping table entry (belonging to the second type) with the second type of priority from the shared buffer 101.

[0058] In one embodiment, the type of a mapping table entry may reflect that this mapping table entry belongs to at least one of an active foreground application, an inactive foreground application, and a background application. In one embodiment, assume that the current processor 111 is running application programs A and B. Among them, application program A is running in the foreground of the operating system (OS), and application program B is running in the background of the operating system. At this time, the processor 111 may classify application program A as an active foreground application and classify application program B as a background application. It should be noted that those skilled in the art should know how the processor runs different application programs in the foreground and background of the operating system, and will not elaborate here.

[0059] In one embodiment, assume that another application program C is switched to run in the foreground of the operating system. In response to application program C being switched to run in the foreground of the operating system, the processor 111 may classify application program C as an active foreground application. At the same time, the processor 111 may re-classify (for example, downgrade) the original active foreground application program A as an inactive foreground application and maintain application program B as a background application.

[0060] In one embodiment, the identification information corresponding to the target mapping table entry may reflect that the target mapping table entry belongs to an active foreground application, an inactive foreground application, or a background application. In addition, when the type of the target mapping table entry changes, the processor 111 may correspondingly update the identification information of the target mapping table entry. The updated identification information may reflect the current type of the target mapping table entry. For example, when the target mapping table entry changes from originally belonging to an inactive foreground application to belonging to an active foreground application, the processor 111 may correspondingly update the identification information of the target mapping table entry so that the updated identification information reflects that the target mapping table entry currently belongs to an active foreground application.

[0061] In one embodiment, if the type of the target mapping entry reflects that the target mapping entry belongs to an active foreground application (i.e., the target mapping entry is for data access of the active foreground application), the processor 111 may determine that the priority of the target mapping entry is a certain priority (also referred to as the first priority). Alternatively, if the type of the target mapping entry reflects that the target mapping entry belongs to a non-active foreground application (i.e., the target mapping entry is for data access of the non-active foreground application), the processor 111 may determine that the priority of the target mapping entry is another priority (also referred to as the second priority). Alternatively, if the type of the target mapping entry reflects that the target mapping entry belongs to a background application (i.e., the target mapping entry is for data access of the background application), the processor 111 may determine that the priority of the target mapping entry is yet another priority (also referred to as the third priority).

[0062] In one embodiment, when the processor 111 desires to remove data from the shared buffer 101 to free up new memory storage space, the mapping entries with the third priority may be removed from the shared buffer 101 prior to the mapping entries with the second priority, and the mapping entries with the second priority may be removed from the shared buffer 101 prior to the mapping entries with the first priority. In one embodiment, the mapping entries with the first priority in the shared buffer 101 may also be set to non-removable until this mapping entry no longer belongs to the active foreground application.

[0063] In one embodiment, the processor 111 may preferably retain the mapping entries related to the foreground application (such as the active foreground application and / or the non-active foreground application) in the shared buffer 101 as much as possible, and / or preferably remove the mapping entries unrelated to the foreground application (such as the active foreground application and / or the non-active foreground application) from the shared buffer 101. Thus, even if the capacity of the shared buffer 101 is limited (or even reduced), the performance of the host system 11 and the storage device 12 when executing the foreground application can still be maintained (or even improved).

[0064] In one embodiment, the processor 111 may also configure multiple regions in the shared buffer 101 to classify and store different types of mapping entries. Thus, the performance of the host system 11 and the storage device 12 can be effectively improved.

[0065] In one embodiment, the processor 111 may detect the data storage amount of at least one of the memory 112 and the shared buffer 101. For example, this data storage amount may reflect how much data has been stored in at least one of the current memory 112 and the shared buffer 101. In one embodiment, the processor 111 may detect whether the data storage amount reaches a critical value. When the data storage amount reaches the critical value, the processor 111 may, according to the priority, retain the target mapping table entry in the shared buffer 101 or remove the target mapping table entry from the shared buffer 101. However, if the data storage amount does not reach the critical value, the processor 111 may not perform the foregoing operation of removing the mapping table entry from the shared buffer 101 for the time being.

[0066] In one embodiment, when the data storage amount of at least one of the memory 112 and the shared buffer 101 is relatively large (e.g., reaches the critical value), by preferentially removing the data that has little impact on the operating efficiency of the host system 11 and the storage device 12 according to the priority, additional memory space can be released for the host system 11 (and the storage device 12) to use. Thereby, the efficiency of the host system 11 and the storage device 12 can be improved.

[0067] It should be noted that, in one embodiment, the type of at least one mapping table entry cached in the shared buffer 101 can also be configured or adjusted according to practical requirements, and is not limited to the above-mentioned active foreground applications, inactive foreground applications, and / or background applications. In addition, in one embodiment, the priorities set for different types of mapping table entries and their sorting methods can also be adjusted according to practical requirements, and the present invention does not impose any limitations.

[0068] In one embodiment, when it is desired to remove multiple mapping table entries of the same type and / or with the same priority from the shared buffer 101, the processor 111 may randomly remove at least one of the multiple mapping table entries from the shared buffer 101. In one embodiment, by preferentially removing the mapping table entries belonging to a specific type and / or having a specific priority, the efficiency of the host system 11 and the storage device 12 can still be maintained or even improved.

[0069] In one embodiment, when multiple mapping entries of the same type and / or with the same priority in the shared buffer 101 are to be removed, the processor 111 can also determine which one of the multiple mapping entries to remove from the shared buffer 101 first according to the frequencies, times, or time points at which the multiple mapping entries are respectively accessed (such as accessed, queried, or used). For example, the processor 111 can compare the frequencies, times, or time points at which the multiple mapping entries are respectively accessed (such as accessed, queried, or used) to obtain a comparison result. Then, the processor 111 can determine which one of the multiple mapping entries to remove from the shared buffer 101 first according to this comparison result. For example, the processor 111 can first remove from the shared buffer 101 the mapping entry that shows a relatively higher access frequency, a relatively larger number of access times, and / or a time point of access relatively closer to the current system time as presented by the comparison result. One or at least multiple of these evaluation factors can be incorporated as considerations for selecting the mapping entry to be removed first. Thus, it can be ensured as much as possible that after some mapping entries are removed from the shared buffer 101, the performance of the host system 11 and the storage device 12 can still be maintained or even improved. In one embodiment, the processor 111 can also select one or more mapping entries that need to be removed first from multiple mapping entries of the same type and / or with the same priority through other sorting algorithms, depending on practical requirements.

[0070] Figure 4 is a flowchart of a method for managing data in a shared buffer based on type tracking according to an embodiment of the present invention. Please refer to Figure 4 , in step S401, a shared buffer is configured in the memory of the host system, where the storage device is used to perform a preset operation based on the data cached in the shared buffer. In step S402, the type of at least one mapping entry cached in the shared buffer is tracked to obtain a tracking result. In step S403, according to the tracking result, the priority of the target mapping entry among the at least one mapping entry is determined. In step S404, according to the priority, the target mapping entry is retained in the shared buffer or removed from the shared buffer.

[0071] Figure 5 is a flowchart of a method for managing data in a shared buffer based on type tracking according to an embodiment of the present invention. Please refer to Figure 5, in step S501, determine the type of the target mapping entry currently cached in the shared buffer. In step S502, determine whether the target mapping entry belongs to an active foreground application. If the target mapping entry belongs to an active foreground application, in step S503, determine that the priority of the target mapping entry is the first priority. If the target mapping entry does not belong to an active foreground application, in step S504, determine whether the target mapping entry belongs to an inactive foreground application. If the target mapping entry belongs to an inactive foreground application, in step S505, determine that the priority of the target mapping entry is the second priority. Additionally, if the target mapping entry does not belong to an inactive foreground application, in step S506, determine that the priority of the target mapping entry is the third priority.

[0072] However, Figure 4 with Figure 5 the steps in it have been described in detail above and will not be elaborated here. It should be noted that, Figure 4 with Figure 5 the steps in it can be implemented as multiple pieces of code or circuits, which are not limited in the present invention. Additionally, Figure 4 with Figure 5 the method of can be used in conjunction with the above exemplary embodiments or used alone, which are not limited in the present invention.

[0073] In summary, the method and storage system for managing data in a shared buffer based on type tracking proposed in the embodiments of the present invention can properly manage (such as sorting, adding, and / or removing) the mapping entries cached in the shared buffer when the capacity of the shared buffer available for use by the storage device within the host system is small (or even the capacity of the shared buffer can be reduced). Thus, the performance of the storage device or the entire storage system can be effectively improved on the premise of not affecting the operation performance of the host system itself as much as possible.

[0074] In one embodiment, the aforementioned management and / or sorting mechanism for mapping entries can also be used to manage and / or sort other types of data. For example, in one embodiment, the aforementioned mapping entries can be replaced by various instructions, valid count management data, wear leveling management data, bad block management data, or other types of custom data, which will not be repeated here.

[0075] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shared cache data management method based on type tracking, characterized in that: Used in a storage system, the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache area data management method based on type tracking includes: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Tracking the type of at least one mapping table entry cached in the shared cache area to obtain a tracking result; Determining the priority of a target mapping table entry in the at least one mapping table entry according to the tracking result; and According to the priority, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area, The step of tracking the type of the at least one mapping table entry cached in the shared cache area comprises: Determining that the target mapping table entry belongs to an active foreground application, an inactive foreground application, or a background application, wherein if the application to which the target mapping table entry belongs is running in the foreground of an operating system, the target mapping table entry is determined to belong to the active foreground application, if the application is running in the background of the operating system, the target mapping table entry is determined to belong to the background application, and if another application replaces the application to run in the foreground of the operating system, the target mapping table entry is determined to belong to the inactive foreground application; and determining the type of the target mapping table entry according to whether the target mapping table entry belongs to the active foreground application, the inactive foreground application, or the background application, The step of determining the priority of the target mapping table entry in the at least one mapping table entry according to the tracking result includes: If the type of the target mapping table entry reflects that the target mapping table entry belongs to the active foreground application, determining that the priority of the target mapping table entry is a first priority; If the type of the target mapping table entry reflects that the target mapping table entry belongs to the inactive foreground application, determining that the priority of the target mapping table entry is a second priority; and If the type of the target mapping table entry reflects that the target mapping table entry belongs to the background application, determining that the priority of the target mapping table entry is the third priority, When data is to be removed from the shared cache area, the mapping table entry with the third priority is removed from the shared cache area before the mapping table entry with the second priority, and the mapping table entry with the second priority is removed from the shared cache area before the mapping table entry with the first priority.

2. The shared cache data management method based on type tracking according to claim 1, wherein the step of tracking the type of the at least one mapping table entry cached in the shared cache comprises: Obtaining identification information corresponding to the target mapping table entry; as well as The type of the target mapping table entry is determined according to the identification information.

3. The shared cache data management method based on type tracking according to claim 2, wherein the step of determining the type of the target mapping table entry according to the identification information comprises: According to the identification information, querying a management table to obtain a query result, wherein the management table records a plurality of candidate types corresponding to a plurality of candidate identification information respectively; as well as According to the query result, the type of the target mapping table entry is determined from the multiple candidate types.

4. The shared cache data management method based on type tracking according to claim 1, wherein the step of determining the priority of the target mapping table entry in the at least one mapping table entry according to the tracking result comprises: If the type of the target mapping table entry is the first type, determining that the priority of the target mapping table entry is a first priority; If the type of the target mapping table entry is the second type, the priority of the target mapping table entry is determined to be a second type of priority, wherein the first type of priority is different from the second type of priority.

5. The method for managing shared cache data based on type tracking according to claim 4, wherein the target mapping table entry comprises a first mapping table entry and a second mapping table entry, the type of the first mapping table entry is the first type, the type of the second mapping table entry is the second type, and according to the priority, the step of retaining the target mapping table entry in the shared cache or removing the target mapping table entry from the shared cache comprises: Compared with the first mapping table entry with the first priority, the second mapping table entry with the second priority is preferentially removed from the shared cache area.

6. According to the type tracking-based shared cache data management method according to claim 1, wherein the type of the at least one mapping table entry reflects that the at least one mapping table entry belongs to at least one of the active foreground application, the inactive foreground application and the background application.

7. The method for managing shared cache data based on type tracking according to claim 1, wherein the step of retaining the target mapping table entry in the shared cache or removing the target mapping table entry from the shared cache according to the priority comprises: Detecting a data storage amount of at least one of the memory and the shared cache area; as well as When the data storage amount reaches a critical value, the target mapping table entry is retained in the shared cache area or removed from the shared cache area according to the priority.

8. A storage system, characterized in that: include: Host system; as well as a storage device, connected to the host system, The host system is used to: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Tracking the type of at least one mapping table entry cached in the shared cache area to obtain a tracking result; Determining the priority of a target mapping table entry in the at least one mapping table entry according to the tracking result; as well as According to the priority, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area, The operation of tracking the type of the at least one mapping table entry cached in the shared cache area includes: Determining that the target mapping table entry belongs to an active foreground application, an inactive foreground application, or a background application, wherein if the application to which the target mapping table entry belongs is running in the foreground of an operating system, the target mapping table entry is determined to belong to the active foreground application, if the application is running in the background of the operating system, the target mapping table entry is determined to belong to the background application, and if another application replaces the application to run in the foreground of the operating system, the target mapping table entry is determined to belong to the inactive foreground application; and determining the type of the target mapping table entry according to whether the target mapping table entry belongs to the active foreground application, the inactive foreground application, or the background application, The operation of determining the priority of the target mapping table entry in the at least one mapping table entry according to the tracking result includes: If the type of the target mapping table entry reflects that the target mapping table entry belongs to the active foreground application, determining that the priority of the target mapping table entry is a first priority; If the type of the target mapping table entry reflects that the target mapping table entry belongs to the inactive foreground application, determining that the priority of the target mapping table entry is a second priority; and If the type of the target mapping table entry reflects that the target mapping table entry belongs to the background application, determining that the priority of the target mapping table entry is the third priority, When data is to be removed from the shared cache area, the mapping table entry with the third priority is removed from the shared cache area before the mapping table entry with the second priority, and the mapping table entry with the second priority is removed from the shared cache area before the mapping table entry with the first priority.

9. The storage system according to claim 8, wherein the operation of tracking the type of the at least one mapping table entry cached in the shared cache area comprises: Obtaining identification information corresponding to the target mapping table entry; as well as The type of the target mapping table entry is determined according to the identification information.

10. The storage system according to claim 9, wherein the operation of determining the type of the target mapping table entry according to the identification information comprises: According to the identification information, querying a management table to obtain a query result, wherein the management table records a plurality of candidate types corresponding to a plurality of candidate identification information respectively; as well as According to the query result, the type of the target mapping table entry is determined from the multiple candidate types.

11. The storage system according to claim 8, wherein the operation of determining the priority of the target mapping table entry in the at least one mapping table entry according to the tracking result comprises: If the type of the target mapping table entry is the first type, determining that the priority of the target mapping table entry is a first priority; If the type of the target mapping table entry is the second type, the priority of the target mapping table entry is determined to be a second type of priority, wherein the first type of priority is different from the second type of priority.

12. The storage system according to claim 11, wherein the target mapping table entry comprises a first mapping table entry and a second mapping table entry, the type of the first mapping table entry is the first type, the type of the second mapping table entry is the second type, and according to the priority, the operation of retaining the target mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area comprises: When data is to be removed from the shared cache area, the second mapping table entry with the second priority is removed from the shared cache area in preference to the first mapping table entry with the first priority. 13 . The storage system according to claim 8 , wherein the type of the at least one mapping table entry reflects that the at least one mapping table entry belongs to at least one of the active foreground application, the inactive foreground application, and the background application.

14. The storage system according to claim 8, wherein according to the priority, the operation of retaining the target mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area comprises: Detecting a data storage amount of at least one of the memory and the shared cache area; as well as When the data storage amount reaches a critical value, the target mapping table entry is retained in the shared cache area or removed from the shared cache area according to the priority.

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