Data processing system

Abstract

The invention relates to a data processing system. When rendering is performed in a tile-based graphics processor including a plurality of rendering processors, different regions of rendering output are allocated to different ones of the rendering processors for processing. The processing of the rendered output is tracked to determine when a portion of the rendered output that is still to be allocated to the rendering processor for processing falls below a threshold, and when it is determined that the portion of the rendered output that is still to be allocated to the rendering processor for processing falls below the threshold, the rendered output is output to the rendering processor. A smaller cell of the rendered output is then allocated to the rendering processor for processing.

Description

[0001] The present invention relates to data processing systems, and in particular to allocating processing tasks to processing resources of a data processing system, such as allocating regions of rendered output to be generated to a rendering processor of a tile-based graphics processing system for processing.

[0002] Many data processing systems include multiple processing resources (e.g., processing cores) that can each process different processing tasks in parallel with each other. This allows a larger processing task (processing job) to be divided into smaller processing tasks that are submitted to different ones of the processing resources for processing, thereby completing the larger processing task (processing job).

[0003] The present invention will be described with particular reference to "tile-based" graphics processing performed by a graphics processor having multiple rendering processors, although aspects of the invention are more generally applicable to data processing systems that issue data processing tasks to be completed (e.g., to process data arrays) in parallel to multiple processing resources.

[0004] In tile-based graphics processing, the (two-dimensional) output array ("render target" / "render output") of a rendering process (e.g., typically, a frame / image to be displayed to show the scene being rendered) is subdivided (partitioned) into multiple smaller regions (typically called "tiles") for the rendering process. Each tile is rendered separately. The rendered tiles are then reassembled to provide a complete output array (frame) (render target), e.g., for display.

[0005] Thus, a tile can be considered a region of the render target area (output frame) on which the rendering process operates. In such an arrangement, the render target area (output frame) is typically divided into tiles of regular size and shape (they are typically, for example, square or rectangular), but this is not required.

[0006] Other terms commonly used for "tiling" and "tile-based" rendering include "tiling" (sub-regions are called "chunks") and "bucket" rendering. This article will use the terms "tile" and "tiling" for convenience, but it should be understood that these terms are intended to cover all alternative and equivalent terms and techniques.

[0007] In a graphics processing system that includes multiple separate rendering processors (processing cores), different tiles of a render target may be processed (rendered) in parallel by different rendering processors, thereby potentially reducing the time it takes to process (render) the render target. To control the rendering of different tiles by different rendering processors, tiles may be assigned to specific respective rendering processors for processing, and the rendering processors may render their assigned tiles in succession until all of the required tiles of the render target have been rendered.

[0008] Applicants believe that there remains scope for improvement in tile-based graphics processing systems.

[0009] According to a first aspect of the present invention, there is provided a method of operating a tile-based graphics processor, the tile-based graphics processor comprising a plurality of rendering processors, each rendering processor being operable to render rendering tiles into which a rendering output is divided for rendering purposes, the method comprising:

[0010] When rendering the render output:

[0011] assigning different regions of the rendering output to different ones of the rendering processors for processing; and

[0012] Each rendering processor processes the one or more regions assigned thereto to generate rendered data for the one or more regions;

[0013] The method further comprises:

[0014] tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold; and

[0015] When it is determined that the portion of the rendering output that remains to be assigned to the rendering processor for processing falls below the threshold:

[0016] Smaller regions of the rendered output are then assigned to the rendering processor for processing.

[0017] According to a second aspect of the present invention, there is provided a tile-based graphics processor, the tile-based graphics processor comprising:

[0018] a plurality of rendering processors, each rendering processor operable to render rendering tiles into which the rendering output is divided for rendering purposes; and

[0019] a region allocation circuit configured to allocate regions of the rendered output to be processed to the rendering processor for processing;

[0020] wherein the rendering processors are configured to process the regions of rendering output allocated to them by the region allocation circuitry to generate rendered data for the regions;

[0021] and wherein the zone allocation circuit is configured to:

[0022] tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold; and

[0023] When it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing has fallen below the threshold, a smaller region of the rendering output is thereafter allocated to the rendering processor for processing.

[0024] The present invention relates to a tile-based graphics processor comprising a plurality of rendering processors. When processing a rendering output, a corresponding region of the rendering output is assigned to a corresponding one of the rendering processors for processing.

[0025] The processing (eg, rasterization and shading processes) performed by the rendering processors for respective regions of the rendering output may be used to collectively render the rendering output, such as for display.

[0026] In the present invention, the processing of the rendering output is tracked to determine when the portion of the rendering output that is still to be allocated to the rendering processor for processing falls below a threshold. When it is determined that the portion of the rendering output that is still to be allocated to the rendering processor for processing falls below the threshold, a smaller region of the rendering output is thereafter allocated to the rendering processor for processing.

[0027] As will be discussed further below, applicants have recognized that processing of rendered output may be made more efficient by reducing the size of the region allocated to a rendering processor for processing when the amount of rendered output still to be allocated for processing drops below a threshold.

[0028] Specifically, applicants have recognized that initially allocating larger regions of a rendered output to rendering processors can be beneficial, for example in terms of the overhead of the allocation process (because fewer regions may be allocated to rendering processors for the rendered output than if smaller regions were allocated for the entire rendered output), but near the end of the rendered output, there may not be enough large regions still allocated to the rendering processors, such that some rendering processors may become idle while other processors process any remaining larger regions of the rendered output.

[0029] Reducing the size of the region allocated for processing once the remaining portion of the rendering output to be allocated falls below a threshold may allow the remaining portion of the rendering output to be more evenly distributed among the different available rendering processors compared to allocating a larger region for the entire rendering output.

[0030] Specifically, this may more fully utilize the rendering processor to process the rendering output until processing of the rendering output has been completed. This may allow the rendering processor to complete processing of the rendering output more efficiently (and therefore may allow the rendering output to be made available, e.g., for display, more quickly than if a larger region of the rendering output were assigned to the rendering processor for processing for the entire rendering output).

[0031] Therefore, in the present invention, a determination is performed as to whether the portion of the rendering output that is still to be allocated to the rendering processor for processing has fallen below a threshold, and in response to determining that the portion of the rendering output that is still to be allocated to the rendering processor for processing is below the threshold, a smaller area of ​​the rendering output is allocated to the rendering processor for processing.

[0032] These aspects of the invention relate to tile-based graphics processing, i.e. where a rendered output (such as, for example, a frame to be displayed) is divided into a plurality of rendered tiles for rendering purposes. Each rendered tile should and preferably comprises a (corresponding) region (area) of the rendered output.

[0033] The tiles into which the rendering output is divided for rendering purposes may be any suitable and desired such tiles. The size and shape of the rendering tiles may be determined by the tile configuration that the graphics processor is configured to use and process.

[0034] Preferably, the rendering tiles are all the same size and shape (i.e., tiles of a regular size and shape are preferably used), although this is not required. The tiles are preferably rectangular, and preferably square. The size and number of tiles can be selected as desired. Each tile may correspond to an array of consecutive sampling positions, for example, each tile is sized 16×16 or 32×32 or 64×64 sampling positions. For the size and shape of the rendering output being used, the rendering output can be divided into as many such tiles as are required to span the rendering output.

[0035] In the present invention, any suitable division of the rendering output into regions for allocation to the rendering processors for processing may be used.

[0036] However, preferably, the division of the rendering output into regions for allocation to a rendering processor for processing is based on the tiles into which the rendering output is divided for rendering purposes.

[0037] The region of rendered output assigned to a rendering processor for processing may correspond to a tile, may correspond to an integer number of tiles (e.g., an array or line of consecutive tiles), or may correspond to a portion of a tile (sub-tile) or portions of different tiles (sub-tiles).

[0038] When the portion of the rendering output that is still to be allocated to the rendering processor for processing is above a threshold, larger regions of the same size (e.g., predetermined) are preferably allocated to the rendering processor for processing. The larger regions preferably correspond to one or more tiles, and a predetermined number and arrangement of tiles are preferably used. For example, the larger regions allocated when the portion of the rendering output is above a threshold may each correspond to an array of (whole) tiles, such as 2×2 tiles. In a particularly preferred embodiment, each (larger) region corresponds to a single (whole) tile, so that when the portion of the rendering output that is still to be allocated to the rendering processor is above a threshold, regions of the rendering output are allocated to the rendering processor on a tile-by-tile basis.

[0039] Once the portion of the rendering output that is still to be allocated to the rendering processor for processing has fallen below a threshold, the allocated smaller regions of the rendering output are preferably (also) of the same (e.g. predetermined) size as one another. Preferably, when the portion of the rendering output that is still to be allocated to the rendering processor for processing falls below a threshold, a smaller region is selected for allocation to the rendering processor by subdividing each unfinished (still to be allocated) larger region into smaller regions. Thus, each smaller region may correspond to a sub-region of a larger region. Preferably, there is a predetermined number and / or arrangement of sub-regions into which each larger region may be subdivided. For example, and preferably, when the portion of the rendering output falls below a threshold, each unfinished (larger) region may be divided into four equally sized sub-regions for allocation purposes.

[0040] The smaller regions preferably each correspond to a portion (sub-tile region) of a rendered tile. Thus, when the portion of the rendered output that is still to be allocated to the rendering processor falls below a threshold, portions (sub-tile regions) of the tile (and preferably for each tile that is still to be allocated) are preferably allocated to the rendering processor for processing separately from each other.

[0041] Therefore, according to a preferred embodiment, allocating smaller areas of the rendering output to the rendering processor for processing includes subdividing one or more of the tiles of the rendering output into multiple sub-tile areas, and allocating the sub-tile areas separately from each other to the rendering processor for processing.

[0042] In a particularly preferred embodiment, regions of rendered output are assigned to a rendering processor for processing in the following manner:

[0043] (The region allocation circuit) initially allocates (entire) tiles of the rendered output to different ones of the rendering processors for processing; and

[0044] When it is determined that the portion of the rendering output that remains to be assigned to the rendering processor for processing falls below a threshold:

[0045] Any tiles still to be assigned to a rendering processor are thereafter subdivided into a plurality of sub-tile areas, and the sub-tile areas are assigned separately from one another to the rendering processor for processing (and the rendering processor processes the sub-tile areas assigned thereto to generate rendered data for the sub-tile areas).

[0046] Therefore, the region allocation circuit is preferably operable to allocate regions corresponding to one or more (entire) tiles to the rendering processor for processing, and is also operable to allocate regions corresponding to (only) a portion of a tile (sub-tile) to the rendering processor for processing.

[0047] The region allocation circuitry may be operable to divide the tile into a fixed number of sub-tiles for allocation to the rendering processors, or may be capable of selecting a different number / size of sub-tiles to divide the tile into for allocation to the rendering processors, e.g., to allocate larger regions as larger sub-tiles and smaller regions as smaller sub-tiles.

[0048] The region allocation circuitry may allocate regions of the rendering output to the rendering processor for processing by indicating to the rendering processor the regions that the rendering processor is allocated to process in any suitable manner.

[0049] Preferably, the zone allocation circuitry may allocate a zone to a rendering processor for processing by issuing a rendering task to the rendering processor, wherein the rendering task includes a set of commands and / or data that the rendering processor may use to process the zone to which the rendering task corresponds. Preferably, the graphics processor may generate such rendering tasks independently of when the rendering processor is available to process the zone to which the rendering task corresponds. The zone may then be allocated to the rendering processor by issuing a rendering task corresponding to the zone to the rendering processor when appropriate.

[0050] In a preferred embodiment, a rendering task is issued to a rendering processor for processing when the rendering processor has availability for processing the rendering task (e.g., once it has finished processing another rendering task). Issuing rendering tasks in response to the availability of a rendering processor can allow for efficient division of processing without having to know in advance how long a particular rendering task will take to process relative to other rendering tasks. However, in another preferred embodiment, when a rendering processor has availability for processing a rendering task, a rendering task is issued in advance to the corresponding rendering processor, and the rendering processor can then process the rendering task that has been issued to it (when it has availability to do so). This can still provide an appropriate division of processing between rendering processors while allowing allocation to occur in advance when there is availability to process a rendering task.

[0051] The order in which rendering tasks for a rendering output are issued to a rendering processor for processing may be based on any suitable order of assignment. For example, the order in which rendering tasks are issued may be based on the order in which the rendering tasks are generated, may be based on the location of the regions within the rendering output to which the rendering tasks correspond, and / or may be based on some determination of the order in which the rendering tasks in question may be most efficiently processed.

[0052] The graphics processor preferably comprises a rendering task generation circuit for generating rendering tasks and providing these rendering tasks to the zone allocation circuit. The job controller of the graphics processor preferably comprises the rendering task generation circuit. Thus, the graphics processor preferably comprises a job controller which can generate a set of rendering tasks for a rendering output to be processed by the graphics processor, wherein different rendering tasks correspond to different zones of the rendering output. The zone allocation circuit preferably also forms part of the job controller.

[0053] The graphics processor is preferably operable so that the regions into which the rendering output is divided for allocation to the rendering processor need not directly correspond to the region of the rendering output to which the rendering task for the rendering output corresponds. Specifically, the region allocation circuitry may preferably (when appropriate) allocate only a portion (sub-region) of the region to which the rendering task corresponds to the rendering processor for processing.

[0054] Therefore, in a preferred embodiment, regions of rendered output are assigned to rendering processors for processing in the following manner:

[0055] (rendering task generation circuit) generates a rendering task set for processing a rendering output,

[0056] wherein different rendering tasks in the rendering task set correspond to different regions of the rendering output, and wherein the rendering processor is operable to process the corresponding rendering tasks corresponding to the corresponding regions.

[0057] A rendering task is used to process the rendering output area;

[0058] (the region allocation circuit) allocates different regions of the rendering output to different ones of the rendering processors for processing by issuing different rendering tasks to different ones of the rendering processors for processing; and

[0059] When it is determined that the portion of the rendering output that is still to be assigned to the rendering processor for processing has fallen below the threshold;

[0060] The region to which the rendering tasks in the rendering task set correspond and which is still to be assigned to the rendering processor for processing is subdivided into a plurality of sub-regions, and the sub-regions are separately assigned to the rendering processor for processing.

[0061] The rendering processors are preferably each controllable to process a particular sub-region of the region to which the rendering task issued to the rendering processor corresponds. Preferably, this is achieved by the region allocation circuit being operable to issue a sub-region indication to the rendering processor together with the rendering task, and the rendering processor being configured to respond to the sub-region indication by processing the sub-region indicated as being to be processed by the sub-region indication.

[0062] Thus, in a preferred embodiment, sub-regions of the rendered output are allocated to a rendering processor for processing (by the region allocation circuitry) by issuing to the rendering processor:

[0063] The rendering task corresponding to the region including the sub-region; and

[0064] a sub-area indication indicating the sub-area within the area;

[0065] And the rendering processor processes the sub-region by controlling the processing it performs when processing the rendering task based on the sub-region indication.

[0066] When sub-regions of the region to which the rendering task corresponds are to be allocated separately from each other, the rendering task may be issued multiple times through different sub-region indications.

[0067] In a particularly preferred embodiment, the region allocation circuit is configured to issue a sub-region indication for each rendering task to the rendering processor, wherein the sub-region indication controls which sub-region(s) of the region to which the rendering task corresponds to which the rendering processor will process in response to issuing the rendering task to the rendering processor. When the entire region to which the rendering task corresponds is allocated to the rendering processor for processing, this may be appropriately indicated by the sub-region indication (and only the rendering task needs to be issued to the rendering processor once). This may allow the same data format to be used when issuing rendering tasks to the rendering processor, regardless of whether the entire region or sub-region to which the rendering task corresponds is being allocated.

[0068] Thus, in a preferred embodiment, the method comprises issuing a subregion indication with each rendering task issued to a rendering processor;

[0069] When the entire region corresponding to the rendering task is assigned to the rendering processor for processing, the sub-region indication issued together with the rendering task indicates that the rendering processor is assigned to process the entire region corresponding to the rendering task when processing the rendering task.

[0070] The sub-region indications used in the present invention may take any suitable and desired form. For example, they may be in the form of a bit mask with entries for each different sub-region, or indicate one of a set of multiple values, each value indicating a corresponding sub-region.

[0071] Although in the present invention, the size of the region allocated to the rendering processor for processing is controlled based on the tracking of the processing of the rendering output, the size of the allocated region does not need to directly correspond to the size of the region to which the rendering task corresponds, and the rendering task for processing the rendering output can be and preferably is generated independently of the tracking.

[0072] In a preferred embodiment, rendering tasks are generated for a rendering output, each rendering task corresponding to a region of the rendering output of the same size as one another, and preferably corresponding to the same number of tiles as one another.

[0073] Preferably, the larger regions of the rendering output that are allocated when the portion of the rendering output that remains to be allocated to the rendering processor is above a threshold value each correspond to a single entire rendering task. These larger regions can then be allocated to the corresponding rendering processors by issuing (single) rendering tasks corresponding to the larger regions to the rendering processors for processing. This can reduce the number of rendering tasks that need to be generated (and issued) compared to the case where the rendering tasks each correspond to a smaller region.

[0074] As discussed above, in the present invention, the size of the region allocated to the rendering processor for processing is controlled based on whether the portion of the rendering output that remains to be allocated to the rendering processor for processing is below a threshold.

[0075] The threshold value may be based on, and determined and evaluated relative to, any suitable measure of the size of the portion of the rendering output that remains to be allocated to the rendering processor for processing. For example, this may be in terms of a rendering output area, a rendering tile, a rendering task, or some other measure such as the number of (graphics) primitives.

[0076] In a preferred embodiment, the threshold is based on the number of rendering processors (that can process the corresponding regions of the rendered output in parallel). For example, the threshold number of regions (or rendering tiles or rendering tasks) for the rendered output can be set equal to the number of rendering processors (that can process the corresponding regions in parallel), so that when the number of regions (or rendering tiles or rendering tasks) to be allocated is kept equal to or drops below the number of rendering processors, then smaller regions are allocated to the rendering processors for processing.

[0077] Accordingly, the processing of the rendered output may be tracked in any suitable manner to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold.

[0078] For example, the processing of the rendered output may be tracked by tracking how much processing of the rendered output has been allocated / performed and / or by tracking how much processing of the rendered output remains to be allocated / performed. For the threshold being used, it is possible and preferred to appropriately "measure" the "amount" of processing that has / remains to be allocated.

[0079] In a preferred embodiment, the allocation itself is tracked to determine when the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below a threshold.

[0080] Thus, in one embodiment, the size of the portion of the rendering output that remains to be allocated to the rendering processor for processing is determined by determining (tracking) the size of the portion of the rendering output that has already been allocated to the rendering processor for processing (e.g., by region, tile, rendering task, or primitive) and preferably comparing the size of the portion of the rendering output that has already been allocated to the rendering processor to the total size of the rendering output (e.g., by region, tile, rendering task, or primitive, as appropriate).

[0081] In this case, in response to determining that the portion of the rendering output that has been allocated to the rendering processor for processing exceeds a certain size (which can be set based on the total size of the rendering output), it is preferably determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing is below a threshold.

[0082] In a particularly preferred embodiment, the tracking of processing of the rendering output in relation to the threshold is based on (and uses) the number of rendering tasks and / or the number of rendering tiles for the rendering output that remain to be assigned to the rendering processor for processing.

[0083] Thus, in a preferred embodiment, tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold comprises:

[0084] Tracking when the number of tiles of the render output that remain to be assigned to the render processor for processing drops below a threshold number of tiles.

[0085] In another preferred embodiment, tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold comprises:

[0086] The issuance of the rendering tasks to the rendering processor is tracked to determine when a number of rendering tasks in the set of rendering tasks for the rendering output and still to be assigned to the rendering processor for processing falls below a threshold number of rendering tasks.

[0087] As discussed above, the threshold (and the tracking of processing) may additionally or alternatively be based on other measures of the size of the portion of the rendering output that will still be allocated to the rendering processor for processing. For example, the threshold may be based on (and the tracking of processing may be based on) how many primitives there are for the portion of the rendering output that will still be allocated to the rendering processor for processing (e.g., as a proportion of the number of primitives of the (entire) rendering output).

[0088] In a particularly preferred embodiment, the region allocation circuit counts the number of rendering tasks (or tiles) of the rendering output that it allocates to the rendering processor for processing, and compares the number of rendering tasks (or tiles) that have been allocated to the rendering processor with the total number of rendering tasks (or tiles) of the rendering output, thereby determining the number of rendering tasks (or tiles) that remain to be allocated for the rendering output. This determination may be performed any suitable number of times when processing the rendering output, for example, the comparison may be performed periodically or each time a region of the rendering output is to be allocated to the rendering processor.

[0089] As discussed above, the region allocation circuitry is operable to issue the same rendering task multiple times (with different sub-region indications). When this occurs, for the purpose of tracking the processing of the rendering output, the rendering task may be counted as allocated or not allocated according to any suitable condition, such as counting the rendering task as allocated when the rendering task is first issued, or counting the rendering task as allocated when the rendering task is last issued. However, in a preferred embodiment, the rendering tasks are each issued at least once until the size of the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below a threshold, so that multiple issuances of rendering tasks do not need to be taken into account when determining whether the portion of the rendering output that remains to be allocated to the rendering processor is below the threshold.

[0090] A single threshold may be used or multiple consecutive thresholds may be used, wherein each time the portion of the rendering output still to be allocated to the rendering processor for processing falls below a (corresponding) threshold, the size of the allocated region is reduced.

[0091] Therefore, in a preferred embodiment, the method may include reducing the size of the region of the rendering output allocated to the rendering processor for processing each time the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below one of a plurality of consecutive thresholds.

[0092] To improve processing efficiency, any number of thresholds may be used appropriately. For example, 1 to 5 thresholds may be used.

[0093] In a preferred embodiment, a region of a first size is initially allocated to a corresponding rendering processor for processing, and the processing of the rendering output is tracked to determine when the portion of the rendering output that is still to be allocated to the rendering processor falls below a threshold. When it is determined that the portion of the rendering output that is still to be allocated to the rendering processor falls below the first threshold, a region of a second size that is smaller than the first size is allocated to the corresponding rendering processor for processing. The processing of the rendering output is further tracked to determine when the portion of the rendering output that is still to be allocated to the rendering processor falls below a second threshold (which corresponds to the presence of a portion of the rendering output that is still to be allocated to the rendering processor that is smaller than the portion corresponding to the first threshold). When it is determined that the portion of the rendering output that is still to be allocated to the rendering processor for processing falls below the second threshold, a region of a third size that is smaller than the second size is allocated to the corresponding rendering processor for processing. For example, the regions of the first size may each correspond to multiple tiles, the regions of the second size may each correspond to a single tile, and the regions of the third size may each correspond to (only) a portion of a tile (a sub-tile).

[0094] Although assigning a region of rendered output to a rendering processor for processing will determine which rendering processor will process the region (by processing the tile or portion thereof of the rendered output to which the region corresponds), the rendering processor is preferably operable such that the region to which it is assigned for processing may still (where appropriate) be divided into smaller sub-regions for processing by the rendering processor, preferably based on the tile to which the assigned region corresponds.

[0095] Therefore, in a preferred embodiment, when a region corresponding to more than one tile is assigned to a rendering processor for processing, the rendering processor divides the processing it performs to process the region based on the tile to which the region corresponds. Preferably, when a rendering processor is assigned a region of rendering output for processing, the rendering processor will identify each tile to which the region corresponds, and is preferably configured to determine, for each tile to which the region corresponds, whether the region assigned to the rendering processor corresponds to the entire tile or only a portion of the tile (a sub-tile). The rendering processor can then process the region by processing each tile (or sub-tile) to which the region corresponds. For example, the rendering processor may process each tile (or sub-tile thereof) to which the region corresponds one by one, or may process different tiles in parallel with each other (e.g., by processing different tiles or sub-tiles by different sets of resources of the rendering processor).

[0096] The rendering processor (and each rendering processor) may process its assigned regions and sub-regions (tiles or sub-tiles of) in any appropriate and desired manner and undergo any operations required for the purposes of the invention, preferably doing so in the normal manner for the graphics processor and graphics processing system in question.

[0097] Therefore, in a preferred embodiment, a tile of rendered output is processed by determining primitives to be processed for the tile and rasterizing the primitives for the tile to generate graphics fragments for shading (and then shading (rendering) the graphics fragments). Therefore, the rendering processor preferably includes: a rasterization stage (rasterization circuit) that operates and is configured to rasterize primitives into graphics fragments for processing; and a fragment processing (shading) stage that processes the graphics fragments.

[0098] The primitives that need to be processed for a tile are preferably determined (identified) based on a primitive list into which primitives for rendered output are sorted and which indicates which primitives should be rendered for the corresponding region of rendered output being generated to which the primitive list relates.

[0099] Therefore, the graphics processor preferably includes an appropriate stitcher (splicing unit / circuitry / stage) that sorts the primitives into corresponding primitive lists. A primitive list corresponding to each rendering tile may be prepared, and / or a primitive list corresponding to a set of a plurality of rendering tiles may be prepared.

[0100] Once the tiling stage (tiling circuitry) has finished preparing the primitive list, each tile can be processed (rasterized and rendered).

[0101] The rasterization stage (rasterization circuit) preferably determines which sampling positions of the rendered output fall within (are covered by) the primitives, and generates graphics fragments with appropriate positions (representing appropriate sampling positions) for rendering the primitives accordingly. Each graphics fragment may correspond to a single sampling position or a set of multiple sampling positions (e.g., 2×2 sampling positions) as desired.

[0102] The rendering stage (rendering circuitry) should and preferably renders the fragments generated by the rasterization stage / rasterization circuitry to generate rendered (fragment) data.

[0103] The rendering process performed by the rendering stages (rendering circuitry) may include one or more fixed-function rendering stages, such as a texture mapper, a blender, a fog unit, and the like.

[0104] Preferably, the rendering process performs one or more fragment shading operations on the fragment to derive rendered data, such as color values ​​(e.g., red, green, and blue (RGB) color values) and "alpha" (transparency) values, for shading each covered sampling position in the rendering output corresponding to the fragment. The fragment shading operation may involve any suitable process for shading the fragment, such as executing one or more fragment shading programs on the fragment, applying a texture to the fragment, etc.

[0105] Therefore, in a preferred embodiment, the rendering stage (rendering circuit) includes a fragment shader (shader pipeline) (i.e., a programmable pipeline stage that is operable and programmable to execute a fragment shading program on a fragment in order to render it). If desired, the rendering process may also or alternatively include (perform) ray tracing.

[0106] When the entire tile is to be processed by the rendering processor, the rendering processor may process the tile in a "normal" manner. However, when only a portion of a tile, rather than the entire region (i.e., a sub-tile of the tile), is to be processed, the operation of the rendering processor is preferably configured and adjusted to take this into account. This may be done in any suitable and desired manner.

[0107] In a preferred embodiment, when a sub-tile of a tile is to be processed by a rendering processor, the rendering processor preferably operates to determine the primitives to be processed for the sub-tile, and (only) provide the rasterization stage (rasterization circuitry) with the primitives to be processed for the sub-tile (rather than having to provide all primitives to be processed for the entire tile).

[0108] Therefore, in a preferred embodiment, when a sub-tile region of a tile is assigned to a rendering processor for processing, the rendering processor:

[0109] Determine a primitive set for the tile;

[0110] Determine whether a primitive in the primitive set of the image block falls within the sub-image block area;

[0111] generating graphics fragments for the sub-tile region by rasterizing primitives determined to fall within the sub-tile region; and

[0112] The graphics fragment generated for the sub-tile region is processed to generate rendered data for the sub-tile region.

[0113] The primitives of a tile may be determined by reading one or more primitive lists for the tile by a primitive list reader of a rendering processor or by any other suitable means. However, even when used to determine the primitives of a tile, it is preferably not required that the primitive list reader use the primitive lists to distinguish which primitives are associated with a sub-tile. This may avoid the need to prepare primitive lists for regions smaller than a single tile.

[0114] Preferably, the primitives to be processed for a sub-tile of the tile are determined based on edge information representing edges of the primitives and information representing boundaries of the sub-tile in question. When regions are allocated by issuing rendering tasks, boundaries of the sub-tiles to be processed are preferably determined based on the rendering tasks and, if provided, sub-region indications of the rendering tasks.

[0115] Therefore, in a particularly preferred embodiment, the primitives to be processed for the sub-tile of the tile are determined by using edge information of (e.g., all) primitives of the tile and information representing the boundaries of the sub-tile to determine which primitives of the tile may fall within the boundaries of the sub-tile.

[0116] The information representing the boundaries of the sub-tile is preferably actually used as (and used to set) a "cropping box" that will control which primitives to be processed for the (entire) tile are to be processed for the sub-tile in question. When processing a sub-tile, primitives that are not processed for the sub-tile are preferably culled (based on the cropping box) to prevent primitives that are not processed for the sub-tile from being provided to the rasterizer stage (rasterizer circuitry) to process the sub-tile.

[0117] Therefore, a rendering processor to which a processing area to be processed (only) comprising a sub-tile of a tile is assigned preferably comprises a culling unit which can, in particular, determine primitives to be processed for the sub-tile (e.g. based on primitives to be processed for the tile provided by a primitive list reader) and provide the primitives to be processed for the sub-tile to a rasterization stage (rasterization circuit) for rasterization.

[0118] In a preferred embodiment, when processing regions smaller than a tile (sub-tiles), the writing of rendered fragment data to and from the tile buffer is also or alternatively (and preferably also) modified.

[0119] (In this regard, the rendering processor should, and preferably does (variously) include a tile buffer for storing rendered fragment data, such as color and depth values ​​associated with (the sampling positions of) the fragments. When appropriate to do so (e.g., once all of the rendered data for a tile (or portion thereof) has been generated), the rendered data is written out from the tile buffer to, for example, a frame buffer or "main" memory.)

[0120] When it is required to generate rendered data for (only) a sub-tile to render a region (or sub-region) assigned to a rendering processor, the graphics processor is preferably operable so that the rendered data for the sub-tile can be written to and from the tile buffer, without requiring data for the entire tile to be written to and from the tile buffer.

[0121] For example, rendered data for a sub-tile may be generated and written to a tile buffer by selectively rasterizing only primitives of the tile that fall within a sub-tile in the manner discussed above. To selectively write out rendered data for a sub-tile, the graphics processor is preferably operable to determine which data locations within the tile buffer correspond to locations in the rendering output that fall within a region or sub-region being processed by the associated rendering processor, and select which data locations to write out based on the determination.

[0122] Thus, in one embodiment, the graphics processor is operable to generate rendered data for a sub-tile and store the rendered data in a tile buffer, and write out the rendered data for the sub-tile from the tile buffer by the following steps:

[0123] determining which data locations within the tile buffer are associated with the sub-tile; and

[0124] The rendered data is written out for the data location of the tile buffer determined to be associated with the sub-tile.

[0125] The graphics processor may determine which data locations within the tile buffer are associated with a sub-tile in any suitable manner. However, this is preferably based on whether the data locations in the tile buffer correspond to locations in the rendered output that fall within the sub-tile. When rendering a sub-tile in response to determining that a region or sub-region assigned to a rendering processor includes the sub-tile (rather than including the entire corresponding tile), determining whether a location in the rendered output falls within the sub-tile may be determined by determining whether the location falls within the region or sub-region assigned to the rendering processor.

[0126] The above describes specific elements of a graphics processor involved in the operation performed in the manner of the present invention. As will be appreciated by those skilled in the art, the graphics processor may additionally include and preferably does include and execute any or one or more and preferably all of the other processing circuits / stages that a graphics processor may (usually) include.

[0127] Thus, for example, the graphics processor preferably also includes one or more of the following, and preferably a plurality of the following, and preferably all of the following: one or more shader stages / circuits (such as one or more vertex shaders); one or more (early and / or late) culling (e.g., depth and / or stencil) testers (culling (e.g., depth and / or stencil) test stages), blenders (blending stages), etc.

[0128] The writing out of rendered data from the tile buffer to the output buffer (in memory) may also include, for example, downsampling and / or compressing the data from the tile buffer as it is written out.

[0129] Of course, other arrangements of graphics processing performed would be possible.

[0130] The rendered output to be generated may include any rendered output that can and is to be generated by the graphics processor and processing pipeline, such as frames for display, render-to-texture output, etc. In a preferred embodiment, the rendered output is an output frame, and preferably an image.

[0131] In a particularly preferred embodiment, the various functions of the present invention are performed on a single graphics processing platform that generates and outputs (rendered) data, which is written, for example, to a frame buffer for a display device.

[0132] The graphics processor may also communicate with a host microprocessor, and / or with a display for displaying images based on the output of the graphics processor.

[0133] While aspects of the invention described above relate to tile-based graphics processing, it is believed that allocating different regions of a data array to different processing circuits for processing in the manner described above for processing rendered output may itself be novel and inventive.

[0134] Thus, according to a third aspect of the present invention there is provided a method of operating a data processor comprising a plurality of processing circuits, each processing circuit being operable to process regions into which a data array is partitioned for processing purposes, the method comprising:

[0135] When processing arrays of data:

[0136] assigning different regions of the data array to different ones of the processing circuits for processing; and

[0137] Each processing circuit processes the one or more zones assigned to it;

[0138] The method further comprises:

[0139] tracking the processing of the data array to determine when a portion of the data array that remains to be allocated to the processing circuitry falls below a threshold; and

[0140] When determining that the portion of the data array that is still to be allocated to the processing circuitry falls to a low

[0141] At this threshold:

[0142] Smaller regions of the data array are thereafter allocated to the processing circuitry for processing.

[0143] According to a fourth aspect of the present invention, there is provided a data processor, the data processor comprising:

[0144] a plurality of processing circuits, each processing circuit being operable to process the regions into which the data array is partitioned for processing purposes; and

[0145] a region allocation circuit configured to allocate regions of the data array to be processed to the processing circuits for processing;

[0146] wherein the processing circuitry is configured to process regions of the data array allocated to them by the region allocation circuitry;

[0147] and wherein the zone allocation circuit is configured to:

[0148] tracking the processing of the data array to determine when a portion of the data array that remains to be allocated to the processing circuitry for processing falls below a threshold; and

[0149] When it is determined that the portion of the data array that is still to be allocated to the processing circuit for processing has fallen below the threshold, a smaller region of the data array is thereafter allocated to the processing circuit for processing.

[0150] The third and fourth aspects of the invention may include, where appropriate, any of the preferred and optional features described above in relation to the first and second aspects.

[0151] For example, smaller regions of a data array may be provided by subdividing larger regions of an initially prepared set of regions of the data array for allocation to processing circuits.

[0152] The method preferably comprises (processing task generation circuitry of the data processor) generating a set of processing tasks for processing the data array, wherein different processing tasks in the set of processing tasks correspond to different regions of the data array, and wherein the processing circuitry is operable to process a region of the data array by processing the respective processing tasks corresponding to the respective regions;

[0153] (the region allocation circuit) allocates different regions of the data array to different ones of the processing circuits for processing by issuing different processing tasks to different ones of the rendering processors for processing; and

[0154] When it is determined that the data array still needs to be assigned to the processing circuit for processing

[0155] When the portion falls below this threshold:

[0156] The area to which the processing tasks in the processing task set correspond and which is still to be allocated to the processing circuit for processing is subdivided into a plurality of sub-areas, and the sub-areas are allocated separately from one another to the processing circuit for processing.

[0157] Preferably, a sub-region is allocated to a processing circuit for processing by issuing to the processing circuit:

[0158] The processing task corresponding to the region including the sub-region; and

[0159] a sub-area indication indicating the sub-area within the area;

[0160] And the processing circuit preferentially processes the sub-region by controlling the processing it performs when processing the processing task based on the sub-region indication.

[0161] In a preferred embodiment, the region allocation circuit is configured to issue a sub-region indication with each processing task issued to the processing circuit;

[0162] The zone allocation circuit is configured to allocate the entire zone corresponding to the processing task to the processing circuit for processing by issuing the processing task and a sub-zone indication, wherein the sub-zone indication indicates that the processing circuit is allocated to process the entire zone corresponding to the processing task when processing the processing task.

[0163] When a sub-region is assigned to a processing circuit for processing, the processing circuit preferably controls the processing it performs to process the sub-region so as to process the sub-region without performing all processing required to process the (entire) region including the sub-region.

[0164] The data processor preferably includes a respective data buffer for respective ones of the processing circuits, wherein the processing circuits are each configured to store processed data of a region of the data array in the respective data buffer for the processing circuit. When a sub-region is processed by the processing circuit, the processing circuit is preferably configured to determine which data locations in the data buffer store the processed data of the sub-region, and write out the processed data of the sub-region from the data locations determined to store the processed data of the sub-region (without writing out the data from all data locations in the data buffer).

[0165] In a preferred embodiment, the region allocation circuit reduces the size of the region of the data array allocated to the processing circuit for processing each time the portion of the data array still to be allocated to the processing circuit for processing falls below one of a plurality of consecutive thresholds.

[0166] The present invention may be implemented in any suitable system such as a suitably configured microprocessor-based system. In some embodiments, the present invention is implemented in a computer and / or microprocessor-based system.

[0167] In preferred embodiments, the graphics processor or data processor includes and / or communicates with one or more memories and / or memory devices that store the data described herein and / or store software for performing the processes described herein.

[0168] The various functions of the present invention can be performed in any desired and suitable manner. For example, unless otherwise specified, the functions of the present invention can be implemented as needed in hardware or software herein. Therefore, for example, unless otherwise specified, the various functional elements, levels and "devices" of the present invention may include suitable one or more processors, one or more controllers, functional units, circuit systems, circuits, processing logic components, microprocessor arrangements, etc., which may be configured to perform various functions, etc., such as appropriate dedicated hardware elements (processing circuits / circuitry) and / or programmable hardware elements (processing circuits / circuitry), which may be programmed to operate in a desired manner.

[0169] It should also be noted here that, as will be appreciated by those skilled in the art, the various functions of the present invention may be repeated and / or performed in parallel on a given processor, etc. Likewise, the various processing stages may share processing circuitry / circuits, etc., if desired.

[0170] Furthermore, unless otherwise indicated, any one or more or all of the processing stages of the present invention may be embodied as, for example, processing stage circuits in the form of one or more fixed function units (hardware) (processing circuits) and / or in the form of programmable processing circuits that can be programmed to perform desired operations. Likewise, any one or more of the processing stages and processing stage circuits of the present invention may be provided as independent circuit elements to any one or more of the other processing stages or processing stage circuits, and / or any one or more or all of the processing stages and processing stage circuits may be formed at least in part by shared processing circuits.

[0171] The graphics processor and / or data processor may additionally include any one or more or all of the usual functional units included in a graphics processor and / or data processor, etc., subject to any hardware required to perform the specific functions discussed above.

[0172] It will also be understood by those skilled in the art that all of the described embodiments of the present invention may optionally include any one, more, or all of the features described herein in one embodiment.

[0173] The method according to the present invention can be implemented at least in part using software such as a computer program. Therefore, it can be seen that embodiments of the present invention may provide computer software herein, which is particularly suitable for performing the methods described herein when installed on a data processor; a computer program element, which includes a computer software code portion for performing the methods described herein when the program element is run on a data processor; and a computer program, which includes a code suitable for performing all steps of one or more methods described herein when the program is run on a data processing system. The data processor may be a microprocessor system, a programmable FPGA (field programmable gate array), etc.

[0174] The invention also extends to a computer software carrier comprising such software for use in operating a display controller or a microprocessor system comprising a data processor, in conjunction with the data processor, the controller or the system to perform the steps of the method of the invention. Such a computer software carrier may be a physical storage medium such as a ROM chip, CD ROM, RAM, flash memory or a disk, or may be a signal such as an electronic signal through a wire, an optical signal or a radio signal such as a signal to a satellite, etc.

[0175] It will also be appreciated that not all steps of the method of the present invention need be performed by computer software, and therefore according to a broader embodiment, the present invention provides computer software and such software installed on a computer software carrier for performing at least one of the steps of the method set out herein.

[0176] The present invention may therefore be suitably embodied as a computer program product for use with a computer system. Such a specific implementation may include a series of computer-readable instructions fixed on a tangible non-transitory medium, such as a computer-readable medium, for example a disk, CDROM, ROM, RAM, flash memory or hard disk. It may also include a series of computer-readable instructions that can be transmitted to a computer system via a modem or other interface device through a tangible medium (including but not limited to optical communication lines or analog communication lines) or passively using wireless technology (including but not limited to microwave, infrared or other transmission technology). The series of computer-readable instructions embodies all or part of the functions previously described herein.

[0177] Those skilled in the art will appreciate that such computer readable instructions may be written in a variety of programming languages ​​for use with many computer architectures or operating systems. In addition, such instructions may be stored using any current or future memory technology (including but not limited to semiconductor, magnetic, or optical technology), or transmitted using any current or future communication technology (including but not limited to optical, infrared, or microwave technology). It is contemplated that such computer program products may be distributed as removable media with accompanying printed or electronic documentation (e.g., shrink-wrapped software), may be preloaded with a computer system, such as on a system ROM or fixed disk, or may be distributed via a network (e.g., the Internet or the World Wide Web) from a server or electronic bulletin board.

[0178] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0179] Figure 1 An exemplary computer graphics processing system is schematically illustrated.

[0180] Figure 2 A graphics processor according to an embodiment of the present invention is schematically shown.

[0181] Figure 3 A graphics processing pipeline executed by a graphics processor according to an embodiment of the present invention is schematically shown.

[0182] Figure 4 A method of allocating regions of rendering output to a rendering processor for processing according to an embodiment of the present invention is schematically illustrated.

[0183] Figure 5 The allocation of regions of rendered output to rendering processors for processing is schematically illustrated according to an embodiment of the present invention.

[0184] Figure 6 Schematically illustrates rendering tasks and sub-region indications for allocating regions to rendering processors for processing according to an embodiment of the present invention.

[0185] Figure 7 A method of issuing rendering tasks to process rendering output according to an embodiment of the present invention is schematically illustrated.

[0186] Figure 8 A method for issuing rendering tiles to process rendering tasks according to an embodiment of the present invention is schematically illustrated.

[0187] Fig. 9 A method of selectively processing primitives of a sub-region of a tile according to an embodiment of the present invention is schematically illustrated.

[0188] Fig.10 A method of selectively writing out rendered data of a sub-region of a tile from a tile buffer according to an embodiment of the present invention is schematically illustrated.

[0189] Embodiments of the present invention relate to computer graphics processing.

[0190] Figure 1 A typical computer graphics processing system is shown.

[0191] An application 2 (such as a game) executing on a host processor (CPU) 1 will require graphics processing operations to be performed by an associated graphics processor (graphics processing unit (GPU)) 3, which implements the graphics processing pipeline. To do this, the application will generate API (application programming interface) calls, which are interpreted by a driver 4 for the graphics processor 3 running on the host processor 1, generating appropriate commands for the graphics processor 3 to generate the graphics output required by the application 2. To facilitate this, a collection of "commands" will be provided to the graphics processor 3 in response to commands from the application 2 running on the host system 1 for graphics output (e.g., to generate a frame to be displayed).

[0192] like Figure 1 As shown, the graphics processing system will also include a suitable memory system 5 for use by the host CPU 1 and the graphics processor 3.

[0193] When a computer graphics image is to be displayed, it is usually first defined as a series of primitives (polygons), which are then divided (rasterized) into graphics fragments and then used for graphics rendering. During normal graphics rendering operations, the renderer will modify (for example) color (red, green and blue, RGB) and transparency (α, a) data associated with each fragment so that the fragment can be displayed correctly. Once these fragments have completely traversed the renderer, their associated data values ​​are stored in memory ready for output, such as for display.

[0194] In embodiments of the present invention, graphics processing is performed in a pipelined fashion, where one or more pipeline stages operate on data to generate a final output (eg, a displayed frame).

[0195] Embodiments of the present invention relate to tile-based graphics processing, wherein tiles into which a rendering output is divided for rendering purposes may be processed by a rendering processor executing a graphics processing pipeline to process and output tiles (or portions thereof) separately from the processing or output of other tiles (or portions thereof).

[0196] Figure 2 A graphics processor 3 in a preferred embodiment is schematically shown. The graphics processor 3 is a tile-based graphics processor and includes a geometry processor 11 and a plurality of rendering processors (renderer / shader cores) 12, 13, 14, 15, all of which have access to a memory 16 of a memory system 5. The memory 16 may be local to the geometry processor 11 and the renderers 12, 13, 14, 15 (e.g., "on chip" with them), or may be an external memory (e.g., "main" memory) accessible by the geometry processor 11 and the rendering processors 12, 13, 14, 15.

[0197] Figure 2 A graphics processor 3 having four rendering processors is shown, but other configurations of multiple rendering processors may be used if desired.

[0198] Especially and if Figure 2 As shown, the memory 16 stores a collection of original geometry data 17 (for example, provided by a graphics processor driver 4 or an API 2 running on a host system (microprocessor) 1 of the graphics processor 3), a collection of transformed geometry data 18 (which is the result of various transformations and processing operations performed on the original geometry data 17), and a collection of primitive lists 19.

[0199] Primitive lists 19 may each correspond to a respective tile into which a rendered output (such as a frame to be displayed) generated by graphics processor 3 is divided for rendering purposes, and contain data, commands, etc. for a respective primitive to be processed for the respective tile to which the list corresponds.

[0200] The transformed geometric data 18 includes, for example, transformed vertices (vertex data) and the like.

[0201] In response to the graphics processor 3 receiving a command to perform a rendering job 20 from, for example, the graphics processor driver 4, the geometry processor 11 takes as its input raw geometry data 17 stored in the memory 16 and processes the data to provide transformed geometry data 18 (which is then stored in the memory 16), including geometry data in a form ready for placement in a rendered output (e.g., a frame to be displayed).

[0202] Geometry processor 11 and the processes it performs may take any suitable form and be any suitable and desired such processes.For example, geometry processor 11 may include a programmable vertex shader that performs vertex shading operations to generate desired transformed geometry data 18 .

[0203] like Figure 2 As shown, the geometry processor 11 also includes a stitching unit 21. The stitching unit 21 performs the process of assigning primitives to primitive lists, which are then used to identify primitives that should be rendered for each tile to be rendered to generate a rendered output (in this embodiment, it is a frame to be rendered for display). To do this, the stitching unit 21 takes as input the transformed and processed vertex data 18 (i.e. the positions of the primitives in the rendered output), uses this data to build primitive lists, and stores those primitive lists as primitive lists 19 in the memory 16.

[0204] To prepare the primitive list, the tiling unit 21 takes each transformed primitive in turn, determines the position of the primitive, compares the position of the primitive with the position of the corresponding region (the covered rendering output area) for which the primitive list is to be prepared, and then includes the primitive in the corresponding primitive list 19 for the region determined to potentially fall within (intersect with) the primitive in question. This can be performed, for example, by a bounding box binning technique or by an exact binning technique.

[0205] In an embodiment of the present invention, the region sets for which primitive lists are prepared are arranged in a hierarchy of region sets, wherein each region set corresponds to a layer in the hierarchy of region sets, and wherein the regions for which primitive lists are prepared become progressively larger in progressively higher layers of the hierarchy. Each region for which a primitive list may be prepared in the lowest layer of the hierarchy corresponds to a single tile of the rendered output. However, other configurations of primitive lists are also possible.

[0206] In an embodiment of the present invention, to process a tile or portion thereof, a rendering processor takes the transformed primitives read from the primitive list applied to the tile and the rasterizer, and renders those primitives appropriately to generate rendered graphics data in the form of output fragments (sampling points) for each corresponding sampling position within the tile or portion thereof it is processing. To this end, each rendering processor includes a corresponding rasterization unit, a rendering unit, and a collection of one or more tile buffers 22 that store the rendering data generated by the rendering processor. Once a rendering processor has completed its processing of a given tile or portion of a tile, the stored rendered data for that tile or portion of a tile is output from the tile buffer 22 to an output rendering target, which in this embodiment is a frame buffer 23 for a display.

[0207] As discussed above, embodiments of the present invention relate to a tile-based graphics processor 3, which includes a plurality of rendering processors 12, 13, 14, and 15, wherein rendering output (e.g., a frame to be rendered) is rendered as a plurality of separate rendering zones that each correspond to one or more tiles or portions thereof. Thus, a respective rendering processor may render a zone of rendering output to which it has been assigned by rendering a tile or portion thereof corresponding to the assigned zone, and when the rendering processor has processed a tile or portion thereof within the zone it is processing, the rendered data of the tile or portion thereof is written to the frame buffer 23. When one tile or portion thereof within the zone assigned to the rendering processor has been processed, another tile or portion thereof within the zone (when present) may be processed by the rendering processor, and the rendered data of the tile or portion thereof may be written to the frame buffer 23. When a rendering processor has finished processing one zone, another zone of rendering output that has not yet been processed may be assigned to the rendering processor for processing. In this way, each tile will be processed and output separately from other tiles, but the respective tiles themselves may be output together or as separate portions (sub-tiles).

[0208] Therefore, the corresponding regions of the rendering output are allocated as rendering tasks to the corresponding rendering processors 12, 13, 14, and 15 for processing. This operation is performed by the region allocator (region allocation circuit) 24.

[0209] In an embodiment of the present invention, the zone allocator is part of the job controller 25 of the graphics processor 3. The job controller 25 will, among other things, issue commands and data to the zone allocator 24 for the zone allocator 24 to then schedule appropriate rendering tasks for and onto the graphics processing pipeline 100 of the rendering processor. The generation of rendering output by the execution of the rendering job 20 is performed by the processing of the rendering tasks. Thus, the zone allocator 24 operates to allocate rendering tasks to the rendering processors 12, 13, 14, and 15 to process the rendering job 20 to be executed by the graphics processor 3.

[0210] When a rendering processor 12, 13, 14, 15 is assigned a rendering task corresponding to a region to be processed for rendered output, the rendering processor processes the region by executing a graphics processing pipeline for the tile or portion thereof to which the region corresponds. This operation of the rendering processor will now be described in more detail.

[0211] Figure 3 An exemplary graphics processing pipeline 100 is shown as being executed by a rendering processor (shader core) 12 of a graphics processor in an embodiment of the present invention. The other rendering processors 13, 14, 15 also execute the graphics processing pipeline in the same manner.

[0212] Figure 31 shows the main elements and pipeline stages of a graphics processing pipeline 100 according to an embodiment of the present invention. As will be appreciated by those skilled in the art, there may be multiple stages in the graphics processing pipeline. Figure 3 Other components not shown in FIG. It should also be noted here that Figure 3 are schematic only, and in practice, for example, even if the functional units and pipeline stages shown are Figure 3 are schematically shown as individual stages, but they may also share important hardware circuits. Likewise, there is no need to provide Figure 3 Some of the elements depicted in Figure 3 Only one example of a graphics processing pipeline 100 is shown. It should also be understood that Figure 3 Each of the illustrated stages, elements, units, etc. of the graphics processing pipeline may be implemented as desired and will accordingly include, for example, appropriate circuitry and / or processing logic components, etc. for performing the desired operations and functions.

[0213] Figure 3 The graphics processing pipeline shown will be executed on and implemented by (each) rendering processor (shader core) 12 of a graphics processor (graphics processing unit (GPU)) 3, which graphics processor will accordingly include necessary functional units, processing circuits, etc. that are operable to execute the graphics processing pipeline stages.

[0214] Figure 3 There is shown a job controller 25 and the stages of the graphics processing pipeline performed by the rendering processor 12. The stages performed by the rendering processor 12 are performed after the tiling unit 21 of the graphics processor 3 has prepared the required primitive lists.

[0215] Once the tiling unit 21 has completed the preparation of the primitive list (the list of primitives to be processed for each region of the rendering output), the tile of the rendering output may be rendered with reference to its associated primitive list.

[0216] To do this, the corresponding tiles are Figure 3 The respective tiles may be processed as a single (whole) tile or as a plurality of sub-tiles that are each processed separately by the graphics processing pipeline stages and then combined.

[0217] A region allocator (or “fragment task iterator”) 24 allocates regions to rendering processors 12 for processing by graphics processing pipeline 100 .

[0218] The region allocator 24 may therefore schedule the rendering processors 12, 13, 14, 15 to process tiles through the graphics processing pipeline stages of the rendering processors 12, 13, 14, 15 to generate a rendered output, which may be, for example, a frame to be displayed.

[0219] When the rendering processor 12 is assigned a region to process, the fragment shader endpoint 110 of the rendering processor 12 identifies one or more tiles to which the region corresponds (eg, at least partially intersects or is covered by).

[0220] For a given tile that is to be processed in whole or in part, a primitive list reader ("polygon list reader") 120 identifies a set of primitives to be processed for the tile based on a primitive list (e.g., based on the primitives listed in a primitive list for the tile), and then issues the set of primitives for the tile into the graphics processing pipeline 100 for processing.

[0221] The vertex loader 130 then loads the vertices of the primitives, which are then passed into a primitive setup unit (or "triangle setup unit") 140, which operates, among other things, to determine edge information representing the edges of the primitives from the vertices of the primitives.

[0222] When it is determined that only a portion (a sub-tile) of a tile is to be processed (as opposed to the entire tile), primitives that will not contribute to (e.g., do not fall within) the sub-tile in question are preferably discarded (culled) before passing the primitives to the rasterizer 150. Primitives that do not contribute to the sub-tile may thereby be prevented from being passed to the rasterizer for rasterization.

[0223] The primitives to be rasterized are then passed to the rasterizer 150 which rasterizes the primitives into corresponding sets of one or more sampling points and generates, for the primitives, separate graphics fragments with appropriate locations (representing appropriate sampling locations) for rendering the primitives.

[0224] The fragments generated by the rasterizer 150 are then sent forward to the rest of the pipeline for processing.

[0225] For example, in an embodiment of the present invention, fragments generated by the rasterizer 150 are subjected to an (early) depth (Z) / stencil test 160 to see if any fragments can be discarded (culled) at this stage. To this end, the Z / stencil test stage 160 compares the depth values ​​of the fragments (associated with it) issued from the rasterizer 150 with the depth values ​​of the already rendered fragments (these depth values ​​are stored in the depth (Z) buffer that is part of the tile buffer 22) to determine if the new fragment will be blocked by the already rendered fragments. At the same time, an early stencil test is performed.

[0226] Fragments that pass the fragment early Z and stencil test stage 160 may then be passed to a fragment shading stage in the form of a shader (execution / processing) core 170 for rendering.

[0227] The fragment shading stage 170 performs appropriate fragment processing operations on fragments that pass the early Z and stencil tests in order to process the fragments to generate appropriate rendered data.

[0228] The fragment processing may include any suitable and desired fragment shading process, such as executing a fragment shader program for the fragment, applying a texture to the fragment, applying fog or other operations to the fragment, etc., to generate appropriate rendered data.

[0229] In an embodiment of the present invention, the fragment shading stage is in the form of a shader pipeline (programmable fragment shader) and is therefore implemented by an appropriate shader (execution / processing) core 170 .

[0230] Thus, in an embodiment of the present invention, the fragment shading stage (execution core) 170 includes a programmable execution unit (engine) operable to execute a fragment shader program for a corresponding execution thread (where each thread corresponds to a work item for the output being generated, such as a separate fragment) in order to perform the required fragment shading operations, thereby generating rendered data. In this regard, the execution unit may operate in any suitable and desired manner and include any suitable and desired processing circuitry, etc.

[0231] Once fragment shading is complete, the output rendered (shaded) fragment data is written to a tile buffer 22 from which it is written out 180 to, for example, a frame buffer 23 (e.g., in memory 16) for display. The depth value of the output fragment is also suitably written to a Z-buffer within the tile buffer 22. (The tile buffer stores a color buffer and a depth buffer, each of which stores an appropriate color, etc., or Z-value for each sample point represented by the buffer (essentially for each sample point of the rendered tile being processed).) These buffers store arrays of fragment data representing portions of the overall output (e.g., an image to be displayed), with respective sets of sample values ​​in the buffer corresponding to respective pixels of the overall output (e.g., each 2×2 set of sample values ​​may correspond to an output pixel where 4× multisampling is used).

[0232] When the region assigned to the rendering processor 12 corresponds to all or part of more than one tile, then the next tile of the region is identified by the fragment shader endpoint 110 and processed in the manner described above, and so on until processing of the region assigned to the rendering processor has been completed.

[0233] Once enough tiles have been processed to generate an entire rendered output (eg, a frame (image) to be displayed), the process may be repeated for the next rendered output (eg, frame), and so on.

[0234] For the rendered output generated by the graphics processor 3, according to aspects of the present invention, the graphics processor will track the processing performed to generate the rendered output. This tracking is used to control the allocation of zones of the rendered output by the zone allocator 24, so that the allocation of zones to the rendering processors 12, 13, 14, 15 can make the processing to be performed to generate the rendered output more evenly distributed between the respective rendering processors 12, 13, 14, 15. This operation of the graphics processor 3 will now be described in more detail.

[0235] Figure 4 The relevant operation of the graphics processor 3 when allocating regions of rendering output for processing according to a preferred embodiment of the present invention is shown.

[0236] When you want to allocate a region for a new render output, Figure 4 The operation shown begins (step 201). Initially, the region allocator 24 of the graphics processor 3 allocates respective larger regions of the rendering output to respective ones of the rendering processors 12, 13, 14 and 15 for processing (step 202). The processing of the rendering output is tracked, and it is determined when the portion of the rendering output that remains to be allocated to the rendering processors for processing falls below a threshold (step 203). In this regard, as more larger regions are allocated to the rendering processors, the portion of the rendering output that remains to be allocated to the rendering processors will decrease, and by tracking the processing of the rendering output (e.g., based on tracking the allocations themselves), the rendering processor 3 is configured to determine when the portion of the rendering output that remains to be allocated to the rendering processors for processing falls below a threshold.

[0237] When it is determined that the portion of the rendering output that is still to be allocated to the rendering processors 12, 13, 14, and 15 for processing has fallen below the threshold, in order to allocate the regions of the remaining portion of the rendering output that is still to be allocated, the region allocator thereafter allocates smaller regions of the rendering output (relatively smaller regions compared to the larger regions of the rendering output that were previously allocated) to the rendering processors 12, 13, 14, and 15 for processing (step 204). Once the regions for the entire rendering output have been allocated, the allocation of the rendering output is completed (step 205).

[0238] Figure 5 An example of a rendering output 300 according to an embodiment of the present invention is shown, in which a larger area 301 and a smaller area 302 are assigned to rendering processors 12, 13, 14 and 15 of a graphics processor 3 for processing.

[0239] like Figure 5As shown, region 301a is assigned to rendering processor 12, region 301b is assigned to rendering processor 13, region 301c is assigned to rendering processor 14, and region 301d is assigned to rendering processor 15. Regions 301 of rendered output then continue to be assigned to rendering processors 12, 13, 14, and 15 for processing in raster path 303, with the next region to be assigned being assigned to the appropriate rendering processor (e.g., the next rendering processor that becomes available once the previous region of rendered output 300 has finished processing). However, when the number of remaining (larger) regions 301 to be assigned to rendering processors 12, 13, 14, and 15 drops below a threshold value (in an embodiment of the present invention, the threshold value corresponds to a threshold size of four larger regions 301), smaller regions 302 of rendered output are thereafter assigned to rendering processors 12, 13, 14, and 15 for processing.

[0240] In an embodiment of the present invention, this is performed by assigning smaller region 302d to rendering processor 14, smaller region 302b to rendering processor 15, smaller region 302a to rendering processor 12, and smaller region 302c to rendering processor 13. Smaller regions 302 may then continue to be assigned to rendering processors 12, 13, 14, and 15 for processing as and when rendering processors become available until all regions of the rendered output have been assigned to rendering processors 12, 13, 14, and 15 for processing.

[0241] Although in embodiments of the present invention, one exemplary raster path (sequence) is used for allocation, it should be understood that any other ordering of the allocated regions 301 and 302 may be used. It will also be understood that although in embodiments of the present invention, consecutive regions 302a-302d are each processed by a different rendering processor, a rendering processor may process consecutive allocated regions (whether they are larger regions 301 or smaller regions 302) when appropriate, even though the regions are allocated separately from each other. This may occur, for example, if the last rendering processor to be allocated a region becomes the next rendering processor available to process another region.

[0242] As mentioned above Figure 2 As discussed, the graphics processor 3 may allocate regions of rendering output by issuing rendering tasks to the rendering processors 12, 13, 14, and 15 for processing via the region distributor 24.

[0243] In an embodiment of the present invention, the rendering output 300 is processed by dividing the entire rendering output 300 into larger regions 301 and generating a rendering task for each larger region 301. When a smaller region 302 of the rendering output is to be allocated, this is performed by dividing the appropriate larger region 301 into a plurality of sub-regions that are allocated separately from each other, so that the allocated smaller region 302 is a sub-region of the larger region 301.

[0244] The larger region 301 may be divided into any suitable number of sub-regions. However, in an embodiment of the present invention, the smaller region 301 is allocated by dividing the larger region 302 into four equally sized (2×2) sub-regions that are allocated separately from each other. For example, continuing to refer to Figure 5 , the smaller regions 302a-302d are sub-regions of the larger region 301x. In a particularly preferred embodiment, each larger region may correspond to 64×64 pixels, and each sub-region may correspond to 32×32 pixels. However, other arrangements and configurations of the regions are of course possible.

[0245] The graphics processor 3 preferably allocates regions 301 and 302 by issuing a rendering task to a rendering processor together with a sub-region indication indicating which sub-region 302 of region 301 the rendering task that the rendering processor is assigned to process corresponds to. This will refer to Figure 7 and Figure 8 Let's discuss further.

[0246] Figure 6 It is shown how the sub-region indication according to the preferred embodiment can indicate which sub-region(s) 302 of the region 301 the rendering processor is assigned to process when a rendering task corresponding to the region 301 is issued to the rendering processor.

[0247] When the region allocator 24 issues a rendering task to a corresponding rendering processor for processing, the region allocator 24 additionally issues a sub-region indication to the rendering processor. The sub-region indication indicates which sub-region 302 of the region 301 the rendering processor is to process when processing a rendering task corresponding to the region 301.

[0248] exist Figure 6 In the illustrated embodiment, the sub-region indication includes first a "full" (or "valid") flag, which can be set to indicate that the entire (larger) region 301 is to be processed by the rendering processor; and an appropriate two-bit code, which can be set to appropriate values ​​to indicate different specific sub-regions to be processed that would be used and interpreted when the "full" indicator is not set.

[0249] If desired, other arrangements may be used instead, such as using a bit mask having an entry for each respective sub-region, which entry may be set accordingly to indicate whether the sub-region is to be rendered.

[0250] In this way, when the entire (larger) area 301 is to be assigned to a rendering processor, the corresponding rendering task for the area 301 only needs to be issued once. However, when the area 301 is to be assigned to multiple sub-areas 302, the same corresponding rendering task for the area 301 can be issued multiple times through different sub-areas instructions.

[0251] Figure 7 Operation of region allocator 24 for issuing rendering tasks to process rendering output 300 is shown in accordance with an embodiment of the present invention.

[0252] like Figure 7 As shown, when the rendering output 300 is to be generated (step 401), the rendering task corresponding to the area 301 of the rendering output 300 is selected to be assigned (issued) to the rendering processor (step 402). To this end, a list of rendering tasks corresponding to the corresponding area 301 of the rendering output 300 is prepared by the job controller 25, and the next rendering task to be assigned by the task assignor 24 is selected based on the assignment order of the rendering tasks.

[0253] The allocation of rendering tasks is controlled based on whether the portion of the rendering output 300 that is still to be allocated to the rendering processors has fallen below a threshold value. In an embodiment of the present invention, this is performed by determining whether the number of rendering tasks for the zone 301 of the rendering output 300 that is still to be allocated to the rendering processors 12, 13, 14, and 15 has fallen below a threshold number of rendering tasks (corresponding to the threshold number of zone 301) (step 403). To this end, the zone allocator 24 counts the number of rendering tasks in the rendering task list for the rendering output 300 and the number of rendering tasks that it has (already) allocated to the rendering processors 12, 13, 14, and 15 for processing. The number of rendering tasks that are still to be allocated can then be determined based on the difference between the number of rendering tasks for the rendering output 300 and the number of rendering tasks that have been allocated to the rendering processors 12, 13, 14, and 15 for processing. When the same rendering task is assigned to the rendering processors 12 , 13 , 14 and 15 multiple times for different sub-areas 302 , for tracking purposes, once the rendering task has been issued for all its sub-areas 302 , the rendering task is counted as one assigned rendering task.

[0254] In order to control whether the rendering processor processes the (entire) region 301 or a specific sub-region 302 when processing a rendering task, the region allocator 24 issues a corresponding sub-region indication for the corresponding rendering task allocated thereto.

[0255] When it is determined that the number of rendering tasks still to be assigned to rendering processors 12, 13, 14 and 15 has not fallen below the threshold, the sub-region indication for the rendering task is selected to indicate that the entire region 301 corresponding to the rendering task is to be processed (step 404).

[0256] However, when it is determined that the number of rendering tasks still to be assigned to the rendering processors 12, 13, 14, and 15 has fallen below a threshold, a sub-region indication for the rendering task is selected to indicate a specific sub-region 302 to be processed that the region 301 corresponding to the rendering task is divided into for assignment to the rendering processors 12, 13, 14, and 15 (step 405). The sub-region 302 that the rendering task is selected to indicate may be based on any suitable order of assignment.

[0257] When the rendering task and sub-region indication have been issued to the rendering processor for processing (step 406), the region allocator 24 determines whether the region 301 to which the rendering task corresponds has any unfinished sub-regions 302 that are still to be allocated to the rendering processor for processing (step 407).

[0258] When there are unfinished sub-regions 302 of region 301 that still need to be allocated, the rendering task for region 301 is reissued to the rendering processor for processing, and the sub-region indication issued together with the (reissued) rendering task is selected to indicate the remaining sub-regions 302 (or multiple sub-regions) for region 301.

[0259] When there are no remaining sub-regions 302 of the region 301 that are still to be allocated (i.e., when all sub-regions 302 have been selected for processing in one or more of the issued sub-region indications of the rendering task for the region 301), the allocation of the rendering task is completed and the region allocator 24 determines whether there are any unfinished rendering tasks to be allocated for the rendering output 300 (step 408), and the process may be repeated for any unfinished rendering tasks. When there are no unfinished rendering tasks to be allocated (i.e., when all regions 301 to be processed for the rendering output 300 have been allocated in the rendering task), the allocation process for the rendering output 300 has been completed (step 409), and the region allocator may, for example, start allocating rendering tasks for the next rendering output.

[0260] Figure 8 Operation 500 of a rendering processor 12, 13, 14, 15 in issuing rendering tiles to its resources to process a rendering task is shown in accordance with an embodiment of the present invention.

[0261] When the rendering processor 12, 13, 14, 15 receives a rendering task and a sub-region indication (step 501) for processing the rendering output 300, the rendering processor 12, 13, 14, 15 uses the sub-region indication to determine which tile(s) of the rendered output 300 divided into is covered by the sub-region 302 that the sub-region indication indicates the rendering processor 12, 13, 14, 15 is to process. When a tile is covered by one or more sub-regions that the sub-region indication indicates the rendering processor is to process, the tile is issued for processing.

[0262] Therefore, the rendering processors 12, 13, 14, 15 determine which tile(s) to issue for processing by selecting the tiles into which the rendering output 300 is divided for processing (step 502) and determining whether the sub-region indicated by the sub-region indication and the associated rendering task to be processed covers the selected tile (step 503).

[0263] When it is determined that the selected tile is covered by the sub-region 302 indicated by the sub-region indication as being to be processed, the tile is issued to the processing pipeline of the rendering processor 12, 13, 14, 15 for processing (step 504). When it is determined that the selected tile is not covered by the sub-region 302 indicated by the sub-region indication as being to be processed, the selected tile is not issued for processing in order to process the received rendering task.

[0264] When it is determined that there are remaining tiles to be processed to process the received rendering task (step 505), steps 502 and 503 are repeated by selecting the next tile and determining whether the selected next tile is covered by the sub-region 302 indicated by the sub-region indication to be processed. This may be performed until the next tile is issued for processing (step 504 is repeated for the next tile), and then step 505 may be repeated for it to determine whether there are (additional) remaining tiles to be processed.

[0265] Steps 502-505 may then continue to be repeated as appropriate until it is determined that all tiles for processing the sub-region indicated as the sub-region to be processed for the rendering task have been issued for processing, at which point the operation of issuing tiles to be processed for the rendering task and sub-region indication in question is completed (step 506).

[0266] The rendering processor may then begin operation 500 appropriately for the next rendering task and subregion indication it has received.

[0267] Tiles may be selected for determining whether they are covered by a sub-region 302 in any suitable order based on, for example, some indication of which tiles have locations within the rendering output that are most likely to be covered by a particular region 301 to which the rendering task corresponds and / or a particular sub-region 302 of that region 301. In embodiments where there is a direct known correspondence between a particular tile and a sub-region, tiles known or determined to correspond to a particular sub-region may be emitted without requiring selection of other tiles for determination.

[0268] As discussed above, the sub-regions 302 into which the region 301 is divided for allocation purposes may correspond to (cover) the entire tile or may correspond to (cover) only a portion of the tile (a "sub-tile"). When the sub-region 302 corresponds only to a particular sub-tile, the sub-region may be processed by processing the entire tile including the sub-tile being processed. However, preferably, the rendering processors 12, 13, 14, and 15 are operable to process a sub-tile region without being required to perform all the processing required to process the entire tile. Fig. 9 and Fig.10 A manner of processing only a specific sub-tile according to an embodiment of the present invention is discussed.

[0269] Fig. 9 Operation 600 of the rendering processors 12, 13, 14, 15 when processing primitives of a tile issued for processing in response to a rendering task and a sub-region indication is shown according to an embodiment of the present invention.

[0270] In this operation 600 of the rendering processor, when a tile is issued for processing by the rendering processor, the rendering processor may determine which primitives of the tile are to be rasterized for processing required by the rendering task in question and the sub-region indication. This may be performed by a primitive list reader of the rendering processor reading a primitive list to determine the primitives of the tile, the primitive list reader providing the primitives of the tile to a triangle setup unit of the rendering processor, and the triangle setup unit of the rendering processor determining which primitives of the tile should be rasterized to process the sub-region indicated by the sub-region indication as being to be processed (which may only cover a specific sub-tile region of the tile).

[0271] Continue to refer Fig. 9 , when a tile is issued for processing by a rendering processor in response to a rendering task and a sub-region indication and a primitive of the issued tile is provided (step 601), and when it is to be determined whether the primitive is to be rasterized, the rendering processor determines whether the sub-region indication indicates that the entire region 301 corresponding to the rendering task is to be processed by the rendering processor (step 602).

[0272] When the sub-region indication indicates that the entire region 301 is to be processed, a cropping box (bounding box) is selected to determine whether the primitive of the tile falls within the region 301 to which the rendering task corresponds. However, when the sub-region indication indicates that one or more sub-regions 302 (rather than the entire region 301) are to be processed, a cropping box (bounding box) is selected to determine whether the primitive of the tile falls within the one or more sub-regions 302 indicated by the sub-region indication (step 603).

[0273] The clipping box is then applied (step 604) to determine whether the primitive should be rasterized for the rendering task and processing required for the subregion indication based on whether the primitive falls within the clipping box.

[0274] The primitive may then be processed according to the determination (step 605), wherein if the primitive falls within the cropping box, it is rasterized to generate fragments for rendering, and if the primitive does not fall within the cropping box, it is culled.

[0275] Processing of the primitive in question may thereby be completed (step 606 ), and operation 600 may be repeated for another primitive, and so on, until all primitives of the tile have been processed.

[0276] Fig. 9 It is shown that a determination is performed for the primitive to be processed as to whether the sub-region indication indicates that the entire region 301 corresponding to the rendering task is to be processed (step 602). However, while this may be performed individually for each primitive, it may also be performed together for a group of primitives. For example, rather than determining an appropriate cropping frame to be applied to each primitive individually, the determination may be performed for the tile being processed and then the cropping frame selected for use may be applied to all primitives of the tile.

[0277] The rendering processor is operable to selectively process any indicated sub-tile portion by selecting an appropriate cropping frame. However, in various embodiments, the region 301 and the sub-region 302 may be configured so that the tile is only operable to be divided in a predetermined manner, such as into quadrants. For example, the region 301 may be selected to include the entire tile, and the sub-regions may be selected to each include a certain number (e.g., separate) of quadrants of the tile. In this case, the cropping frame may be selected to correspond to the appropriate quadrant of the tile when the sub-region 302 is to be processed and to correspond to the entire tile when the region 301 is to be processed.

[0278] Using a cropping box to selectively rasterize specific primitives may thereby allow processing of a sub-tile area of ​​a tile (the portion of the tile covered by the cropping box) rather than processing the entire tile.

[0279] Selectively rasterizing particular ones of the primitives provided for a tile may allow sub-tiles to be selectively rendered by remaining stages of a tile-based graphics processing pipeline without necessarily requiring any of those remaining stages to be modified depending on whether an entire tile or a sub-tile is to be rendered.

[0280] When rendered data for a sub-tile is generated by rendering the fragment, the rendered data is stored in a tile buffer, which is used to store rendered data for the tile. Once the rendered data for the sub-tile is generated, the data can be output from the tile buffer by outputting all data from the tile buffer in the same manner as would be done for the entire tile. However, in various embodiments, the writing of data from the tile buffer can be controlled depending on whether the rendered data is for a tile or for a sub-tile. Reference Fig.10 Exemplary ways of controlling this are described further.

[0281] Fig.10 Operations 700 for controlling data written out of a tile buffer are shown, in accordance with an embodiment of the present invention.

[0282] In this embodiment, the tile buffer is operable to store data representing a tile of rendered output as a data array, where a position in the data array corresponds to a (sampled) position in the tile. Each position in the data array may have a one-to-one mapping to a particular pixel of the final rendered output, but this is not required, for example, when writing data out of the tile buffer, shrinking or enlarging may occur. Each position in the data array may store, for example, a rendered color and depth value based on the fragment at that position.

[0283] When data for a sub-tile (but not an entire tile) is being generated and written to the tile buffer, the rendered data for the sub-tile is stored with the location in the data array corresponding to the location occupied by the sub-tile. The remaining locations of the data array operable to store data for tile regions other than the rendered sub-tile may, for example, be "empty" or store previously generated data values ​​that are invalid for the sub-tile in question.

[0284] When a write back from the tile buffer to the memory is triggered while executing a rendering task (step 701), a location within the data array stored in the tile buffer is selected (step 702), and a determination is made as to whether the location in the data array corresponds to a location in a tile that falls within the region 301 or sub-region 302 indicated by the rendering task and associated sub-region indication as being to be processed (step 703).

[0285] When the position is outside the indicated region 301 or sub-region, another position in the data array is selected without writing out the data for the position in question. When the position in the data array corresponds to a position in the rendered output within the indicated region 301 or sub-region 302, the data for that position is written out to the memory (step 705), optionally after other processing of that data position (step 704), such as upsampling or downsampling the data.

[0286] It is then determined whether there are remaining locations of the data array to be written (step 706), and when there are remaining locations, the next location may be selected and the process repeated as appropriate until it is determined that all desired locations of the data array have been written.

[0287] When all required data locations have been written out, then the writing of the data in the tile buffer is complete (step 707), and rendered data for another tile may begin to be written to the tile buffer, for example as it is generated.

[0288] Selectively writing out data for specific locations in this manner can be used to control whether the entire tile or sub-tile is written out to memory. However, operation 700 can optionally be used to control only which locations of the sub-tile are written to memory, and when it is determined that the entire tile is to be written out, then, for example, all data locations can be written out without individually determining whether to write each location. This can be achieved by appropriately enabling or disabling operation 700 based on, for example, whether the entire tile or sub-tile is required for the rendering task and sub-area being executed.

[0289] As can be seen from the above, at least in a preferred embodiment of the present invention, the present invention can provide a more efficient distribution of processing between rendering processors when performing tile-based graphics processing. This is achieved in a preferred embodiment of the present invention at least by tracking the processing of the rendering output to determine when the portion of the rendering output that is still to be allocated to the rendering processor for processing falls below a threshold, and based on this tracking, controlling the size of the region of the rendering output allocated to the rendering processor.

[0290] Although embodiments of the present invention have been described in relation to performing graphics processing to render rendered output, the present invention is also more generally applicable to processing a data array by assigning different regions of the data array to different processing circuits for processing, wherein processing of the data array is tracked to determine when portions of the data array that remain to be assigned to the processing circuits for processing fall below a threshold, and based on the tracking the size of the regions of the data array that are assigned to the processing circuits for processing are controlled.

Claims

1. A method of operating a tile-based graphics processor, the tile-based graphics processor comprising a plurality of rendering processors, each rendering processor being operable to render rendering tiles into which a rendering output is divided for rendering purposes, the method comprising: When rendering the render output: assigning different regions of the rendering output to different ones of the rendering processors for processing; as well as Each rendering processor processes the one or more regions assigned thereto to generate rendered data for the one or more regions; The method further comprises: tracking the processing of the rendered output to determine when a portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold; as well as When it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below the threshold: Smaller regions of the rendered output are thereafter assigned to the rendering processors for processing.

2. The method of claim 1 , wherein allocating smaller regions of the rendering output to the rendering processor for processing comprises subdividing one or more of the tiles of the rendering output into a plurality of sub-tile regions, and allocating the sub-tile regions separately from one another to the rendering processor for processing.

3. The method according to claim 2, comprising: initially assigning tiles of the rendered output to different ones of the rendering processors for processing; as well as When it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below the threshold: Any tiles that are still to be assigned to a rendering processor for processing are thereafter subdivided into a plurality of sub-tile regions, and the sub-tile regions are assigned to the rendering processor for processing separately from one another.

4. The method according to claim 2 or 3, comprising: When a sub-tile area of ​​a tile is assigned to a rendering processor for processing, the rendering processor; providing a primitive set for the tile; Determining whether a primitive in the primitive set of the picture block falls within the sub-picture block area; generating graphics fragments for the sub-tile region by rasterizing primitives determined to fall within the sub-tile region; as well as The graphics fragments generated for the sub-tile region are processed to generate rendered data for the sub-tile region. 5 . The method of claim 4 , wherein the rendering processor determines whether a primitive in the primitive set of the tile falls within the sub-tile area based on edge information indicating an edge of the primitive and information indicating the boundary of the sub-tile area.

6. The method according to claim 1, 2 or 3, comprising: generating a set of rendering tasks for processing the rendering output, wherein different rendering tasks in the set of rendering tasks correspond to different regions of the rendering output, and wherein the rendering processor is operable to process a region of the rendering output by processing the respective rendering tasks corresponding to the respective regions; assigning different regions of the rendering output to different ones of the rendering processors for processing by issuing different rendering tasks to different ones of the rendering processors for processing; as well as when it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below the threshold; The region to which the rendering tasks in the rendering task set correspond and which is still to be allocated to the rendering processor for processing is subdivided into a plurality of sub-regions, and the sub-regions are allocated separately from one another to the rendering processor for processing.

7. The method according to claim 6, comprising: A subregion is assigned to a rendering processor for processing by issuing to the rendering processor: the rendering task corresponding to the region including the sub-region; and a sub-area indication indicating the sub-area within the area; And the method also includes: The rendering processor processes the sub-region by controlling the processing it performs when processing the rendering task based on the sub-region indication.

8. The method of claim 7, comprising issuing a subregion indication with each rendering task issued to a rendering processor; in, When the entire region to which a rendering task corresponds is allocated to a rendering processor for processing, the sub-region indication issued together with the rendering task indicates that the rendering processor is allocated to process the entire region to which the rendering task corresponds when processing the rendering task.

9. The method of claim 1 , 2 or 3, wherein tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold comprises: Tracking when a number of tiles of the render output that remain to be assigned to the render processor for processing drops below a threshold number of tiles.

10. The method of claim 6, wherein tracking the processing of the rendered output to determine when the portion of the rendered output that remains to be allocated to the rendering processor for processing falls below a threshold comprises: The issuing of the rendering tasks to the rendering processor is tracked to determine when a number of rendering tasks in the set of rendering tasks for the rendering output and still to be assigned to the rendering processor for processing falls below a threshold number of rendering tasks.

11. A method according to claim 1, 2 or 3, comprising reducing the size of the region of the rendering output allocated to the rendering processor for processing each time the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below one of a plurality of consecutive thresholds.

12. A tile-based graphics processor comprising: a plurality of rendering processors, each rendering processor operable to render rendering tiles into which the rendering output is divided for rendering purposes; and a region allocation circuit configured to allocate regions of the rendered output to be processed to the rendering processor for processing; wherein the rendering processors are configured to process regions of rendering output allocated to them by the region allocation circuitry to generate rendered data for the regions; and wherein the zone allocation circuit is configured to: tracking the processing of a rendering output to determine when a portion of the rendering output that remains to be allocated to the rendering processor for processing falls below a threshold; as well as When it is determined that the portion of the rendered output that remains to be allocated to the rendering processor for processing has fallen below the threshold, a smaller region of the rendered output is thereafter allocated to the rendering processor for processing.

13. A graphics processor according to claim 12, wherein the region allocation circuit is configured to allocate the smaller regions of the rendering output to the rendering processor for processing by subdividing one or more of the tiles of the rendering output into multiple sub-tile regions, and allocating the sub-tile regions separately from each other to the rendering processor for processing.

14. The graphics processor of claim 13, wherein the zone allocation circuit is configured to: initially assigning tiles of the rendered output to different ones of the rendering processors for processing; and When it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below the threshold: Any tiles that are still to be assigned to a rendering processor for processing are thereafter subdivided into a plurality of sub-tile regions, and the sub-tile regions are assigned to the rendering processor for processing separately from one another.

15. The graphics processor of claim 12 or 13, wherein the rendering processor is configured, when assigned a sub-tile region of a tile for processing, to process the sub-tile region by: providing a primitive set for the tile; Determining whether a primitive in the primitive set of the picture block falls within the sub-picture block area; generating graphics fragments for the sub-tile region by rasterizing primitives determined to fall within the sub-tile region; and The graphics fragments generated for the sub-tile region are processed to generate rendered data for the sub-tile region.

16. The graphics processor of claim 15 , wherein the rendering processor is configured to, in response to being assigned a sub-tile area of ​​a tile for processing, determine whether a primitive in the primitive set of the tile falls within the sub-tile area based on edge information representing an edge of the primitive and information representing the boundary of the sub-tile area.

17. The graphics processor of claim 12, 13 or 14, comprising: a rendering task generation circuit configured to generate a rendering task set for processing a rendering output, wherein different rendering tasks in the rendering task set correspond to different regions of the rendering output, and wherein the rendering processor is operable to process a region of the rendering output by processing the respective rendering tasks corresponding to the respective regions; Wherein the zone allocation circuit is configured to: assigning different regions of the rendering output to different ones of the rendering processors for processing by issuing different rendering tasks to different ones of the rendering processors for processing; as well as when it is determined that the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below the threshold; The region to which the rendering tasks in the rendering task set correspond and which is still to be allocated to the rendering processor for processing is subdivided into a plurality of sub-regions, and the sub-regions are allocated separately from one another to the rendering processor for processing.

18. The graphics processor of claim 17, wherein the zone allocation circuit is configured to allocate a sub-zone to a rendering processor for processing by issuing to the rendering processor: the rendering task corresponding to the region including the sub-region; and a sub-area indication indicating the sub-area within the area; And wherein the rendering processor is configured to, when assigned a sub-region for processing, process the sub-region by processing the rendering task and using the sub-region indication to control the processing performed when processing the rendering task.

19. The graphics processor of claim 18, wherein the zone allocation circuit is configured to issue a sub-zone indication with each rendering task issued to a rendering processor; The region allocation circuit is configured to allocate the entire region corresponding to the rendering task to the rendering processor for processing by issuing a rendering task and a sub-region indication, wherein the sub-region indication indicates that the rendering processor is allocated to process the entire region corresponding to the rendering task when processing the rendering task.

20. The graphics processor of claim 12, 13 or 14, wherein the zone allocation circuit is configured to track the processing of rendering output to determine when the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below a threshold by: Tracking when a number of tiles of the render output that remain to be assigned to the render processor for processing drops below a threshold number of tiles.

21. The graphics processor of claim 17, wherein the zone allocation circuit is configured to track the processing of rendering output to determine when the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below a threshold by: The issuing of the rendering tasks to the rendering processor is tracked to determine when a number of rendering tasks in the set of rendering tasks for the rendering output and still to be assigned to the rendering processor for processing falls below a threshold number of rendering tasks.

22. A graphics processor according to claim 12, 13 or 14, wherein the zone allocation circuit is configured to reduce the size of the zone of the rendering output allocated to the rendering processor for processing each time the portion of the rendering output that remains to be allocated to the rendering processor for processing falls below one of a plurality of consecutive thresholds.

23. A method of operating a data processor, the data processor comprising a plurality of processing circuits, each processing circuit being operable to process regions into which a data array is partitioned for processing purposes, the method comprising: When processing arrays of data: assigning different regions of the data array to different ones of the processing circuits for processing; as well as Each processing circuit processes the one or more zones assigned to it; The method further comprises: tracking the processing of the data array to determine when a portion of the data array that remains to be allocated to the processing circuitry falls below a threshold; as well as When it is determined that the portion of the data array still to be allocated to the processing circuitry falls below the threshold: Smaller regions of the data array are thereafter allocated to the processing circuitry for processing.

24. The method of claim 23, comprising generating a set of processing tasks for processing the data array, wherein different processing tasks in the set of processing tasks correspond to different regions of the data array, and wherein the processing circuitry is operable to process a region of the data array by processing the respective processing tasks corresponding to the respective regions; assigning different regions of the data array to different ones of the processing circuits for processing by issuing different processing tasks to different ones of the rendering processors for processing; as well as When it is determined that the portion of the data array that is still to be allocated to the processing circuitry for processing falls below the threshold: The area to which the processing tasks in the processing task set correspond and which is still to be allocated to the processing circuit for processing is subdivided into a plurality of sub-areas, and the sub-areas are allocated separately from one another to the processing circuit for processing.

25. The method according to claim 24, comprising: A sub-region is allocated to a processing circuit for processing by issuing to said processing circuit: the processing tasks corresponding to the zone including the sub-zone; and a sub-area indication indicating the sub-area within the area; And the method further comprises: The processing circuit processes the sub-region by controlling the processing it performs when processing the processing task based on the sub-region indication.

26. A data processor comprising: a plurality of processing circuits, each processing circuit being operable to process the regions into which the data array is partitioned for processing purposes; and a region allocation circuit configured to allocate regions of a data array to be processed to a processing circuit for processing; wherein the processing circuitry is configured to process regions of the data array allocated to them by the region allocation circuitry; and wherein the zone allocation circuit is configured to: tracking the processing of the data array to determine when a portion of the data array that remains to be allocated to the processing circuitry for processing falls below a threshold; as well as When it is determined that the portion of the data array that is still to be allocated to the processing circuit for processing has fallen below the threshold, a smaller region of the data array is thereafter allocated to the processing circuit for processing.

27. A computer program comprising computer software code for performing a method according to any one of claims 1, 2, 3, 23, 24 or 25 when said program is run on one or more data processors.

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