Driving circuit, driving method and display device

Abstract

The invention provides a driving circuit, a driving method and a display device. The driving circuit comprises an inverting circuit, a first output node control circuit, a second output node control circuit and an output circuit. The inverting circuit inverts the potential of the first output node in at least part of the time period of the display period to obtain the potential of the first node; the first output node control circuit controls the potential of the first output node; the second output node control circuit obtains the potential of a second output node according to the potential of the first node; and the output circuit controls the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node. The embodiment of the invention provides a novel structure of the driving circuit so as to output the driving signal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device. Background Art

[0002] In recent years, the development of displays has shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (English full name: Gate Driver on Array, Chinese full name: integrated gate drive circuit) technology. The gate drive circuit is integrated on the array substrate of the display panel using GOA technology, so that the gate drive integrated circuit part can be saved to reduce product costs in terms of material cost and manufacturing process. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit, where each shift register in the gate switch circuit is also called a GOA unit. Summary of the invention

[0003] The main purpose of the present invention is to provide a new driving circuit structure to enable driving signal output.

[0004] In one aspect, the driving circuit according to the embodiment of the present invention includes an inverting circuit, a first output node control circuit, a second output node control circuit and an output circuit;

[0005] The inverting circuit is electrically connected to the first output node and the first node respectively, and is used to invert the potential of the first output node in at least a part of the display period to obtain the potential of the first node;

[0006] The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node;

[0007] The second output node control circuit is electrically connected to the first node and the second output node respectively, and is used to obtain the potential of the second output node according to the potential of the first node;

[0008] The output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0009] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first energy storage circuit;

[0010] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

[0011] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor;

[0012] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0013] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0014] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0015] The first end of the storage capacitor is electrically connected to the first clock signal end, and the second end of the storage capacitor is electrically connected to the second node.

[0016] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0017] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0018] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0019] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0020] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0021] Optionally, the first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal or a frame reset terminal.

[0022] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and an on-off control circuit;

[0023] The on-off control circuit is electrically connected to the first output node, the first clock signal terminal and the first terminal of the second energy storage circuit respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node;

[0024] The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electric energy.

[0025] Optionally, the on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0026] The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor;

[0027] The second end of the second capacitor is electrically connected to the first output node.

[0028] Optionally, the first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

[0029] Optionally, the first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

[0030] Optionally, the driving circuit also includes a first node control circuit; the first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0031] Optionally, the second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0032] Optionally, the output circuit is also electrically connected to the first voltage terminal and the second voltage terminal respectively;

[0033] The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

[0034] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;

[0035] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0036] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node;

[0037] A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0038] Optionally, the eighth transistor is a dual-gate transistor.

[0039] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0040] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0041] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node;

[0042] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node;

[0043] A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0044] Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;

[0045] The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0046] A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0047] Optionally, the second output node control circuit includes a twelfth transistor and a thirteenth transistor;

[0048] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node;

[0049] A gate of the thirteenth transistor is electrically connected to the first output node, a first electrode of the thirteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second output node.

[0050] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0051] The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;

[0052] A gate of the fifteenth transistor is electrically connected to the second output node, a first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

[0053] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit;

[0054] The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

[0055] An embodiment of the present invention further provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0056] The inverting circuit inverts the potential of the first output node to obtain the potential of the first node;

[0057] A first output node control circuit controls the potential of the first output node;

[0058] The second output node control circuit obtains the potential of the second output node according to the potential of the first node;

[0059] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0060] An embodiment of the present invention further provides a display device, comprising the above-mentioned driving circuit.

[0061] The driving circuit described in the embodiment of the present invention adopts an inverting circuit. The inverting circuit inverts the potential of the first output node in at least a part of the display period to obtain the potential of the first node. The embodiment of the present invention provides a new driving circuit structure to enable driving signal output. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0063] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0064] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0065] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0066] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0067] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0068] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0069] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0070] Fig. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0071] Fig.10 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0072] Fig.11 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0073] Fig.12 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0074] Fig.13 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0075] Fig.14 The present invention Fig.13 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0076] Fig.15A The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the first time period;

[0077] Fig. 15B The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the second time period;

[0078] Fig. 15C The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the third time period;

[0079] Fig.15D The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the fourth time period;

[0080] Fig.15E The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the fifth time period;

[0081] Fig.15F The present invention Fig.13 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the sixth time period;

[0082] Fig.16 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0083] Fig.17 The present invention Fig.16 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0084] Fig.18 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0085] Fig.19 The present invention Fig.18 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0086] Fig. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0087] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0088] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0089] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0090] like Figure 1 As shown, the driving circuit according to the embodiment of the present invention includes an inverting circuit 11, a first output node control circuit 12, a second output node control circuit 14 and an output circuit 15;

[0091] The inverting circuit 11 is electrically connected to the first output node N1 and the first node N2 respectively, and is used to invert the potential of the first output node N1 in at least a part of the display period to obtain the potential of the first node N2;

[0092] The first output node control circuit 12 is electrically connected to the first output node N1 and is used to control the potential of the first output node N1;

[0093] The second output node control circuit 14 is electrically connected to the first node N2 and the second output node N4 respectively, and is used to obtain the potential of the second output node N4 according to the potential of the first node N2;

[0094] The output circuit 15 is electrically connected to the first output node N1, the second output node N4 and the driving output terminal O1 respectively, and is used to control the driving output terminal O1 to output a driving signal under the control of the potential of the first output node N1 and the potential of the second output node N4.

[0095] The driving circuit described in the embodiment of the present invention adopts an inverting circuit 11. The inverting circuit 11 inverts the potential of the first output node N1 in at least part of the time period of the display cycle to obtain the potential of the first node N2. The embodiment of the present invention provides a new driving circuit structure to enable driving signal output.

[0096] The driving circuit described in at least one embodiment of the present invention further includes a first energy storage circuit;

[0097] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

[0098] In a specific implementation, the driving circuit may further include a first energy storage circuit, wherein a first end of the first energy storage circuit is electrically connected to the first output node, and a second end of the first energy storage circuit is electrically connected to the driving output end.

[0099] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a first energy storage circuit 21;

[0100] A first end of the first energy storage circuit 21 is electrically connected to the first output node N1 , a second end of the first energy storage circuit 21 is electrically connected to the driving output end O1 , and the first energy storage circuit 21 is used for storing electric energy.

[0101] The present invention Figure 2 When at least one embodiment of the driving circuit shown is in operation, when the potential of the driving signal provided by the driving output terminal O1 drops from a high voltage to a low voltage, the potential of the first output node N1 drops only once through the voltage bootstrapping effect of the first energy storage circuit 21, thereby making it possible to make the falling edge of the driving signal provided by the driving output terminal O1 step-free.

[0102] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor;

[0103] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0104] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0105] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0106] The first end of the storage capacitor is electrically connected to the first clock signal end, and the second end of the storage capacitor is electrically connected to the second node.

[0107] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0108] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0109] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0110] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0111] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0112] In at least one embodiment of the present invention, the first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal or a frame reset terminal.

[0113] Optionally, the frame reset signal provided by the frame reset terminal may be inverted with respect to the start signal.

[0114] The driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and an on-off control circuit;

[0115] The on-off control circuit is electrically connected to the first output node, the first clock signal terminal and the first terminal of the second energy storage circuit respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node;

[0116] The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electric energy.

[0117] In a specific implementation, the driving circuit may further include a second energy storage circuit and an on-off control circuit. The on-off control circuit controls the connection or disconnection between the first end of the second energy storage circuit and the first clock signal end under the control of the potential of the first output node. The second end of the second energy storage circuit is electrically connected to the first output node for storing electrical energy.

[0118] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 31 and an on-off control circuit 32;

[0119] The on-off control circuit 32 is electrically connected to the first output node N1, the first clock signal terminal CKB and the first end of the second energy storage circuit 31 respectively, and is used to control the connection or disconnection between the first end of the second energy storage circuit 31 and the first clock signal terminal CKB under the control of the potential of the first output node N1;

[0120] The second end of the second energy storage circuit 31 is electrically connected to the first output node N1 , and the second energy storage circuit 31 is used for storing electric energy.

[0121] The present invention Figure 3 When at least one embodiment of the driving circuit shown is in operation, the potential of the first output node N1 can be pulled down multiple times within one frame time through the second energy storage circuit 31 and the on-off control circuit 32, thereby stabilizing the output of the transistor whose gate is electrically connected to the first output node in the output circuit, reducing the influence of the parasitic capacitance of the transistor on the voltage of the first output node N1, and effectively improving the reliability of the driving circuit.

[0122] Optionally, the on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0123] The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor;

[0124] The second end of the second capacitor is electrically connected to the first output node.

[0125] In at least one embodiment of the present invention, the first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal, the first voltage terminal and the first output node, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

[0126] Optionally, the first voltage terminal may be a high voltage terminal, but is not limited thereto.

[0127] like Figure 4 As shown, in Figure 2 On the basis of at least one embodiment of the driving circuit shown, the first output node control circuit 12 is also electrically connected to the input terminal STV, the first node N2, the first clock signal terminal CKB, the second clock signal terminal CK and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first output node N1 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the first output node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0128] like Figure 5 As shown, in Figure 3 On the basis of at least one embodiment of the driving circuit shown, the first output node control circuit 12 is also electrically connected to the input terminal STV, the first node N2, the first clock signal terminal CKB, the second clock signal terminal CK and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first output node N1 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the first output node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0129] In at least one embodiment of the present invention, the first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

[0130] like Figure 6 As shown, in Figure 3 On the basis of at least one embodiment of the driving circuit shown, the first output node control circuit 12 is also electrically connected to the third node N3, the input terminal STV, the second clock signal terminal CK, the first node N2, the first voltage terminal V1, the first clock signal terminal CKB and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the third node N3 and the input terminal I1 under the control of the second clock signal provided by the second clock signal terminal CK, control the connection or disconnection between the third node N3 and the first voltage terminal V1 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB, and control the connection or disconnection between the third node N3 and the first output node N1 under the control of the third voltage signal provided by the third voltage terminal V3.

[0131] exist Figure 6 In at least one embodiment of the driving circuit shown, the first output node control circuit 12 is directly electrically connected to the third node N3, and is used to control the connection or disconnection between the third node N3 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the third node N3 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0132] exist Figure 6 In at least one embodiment of the driving circuit shown, the first output node may be electrically connected to the third node via a normally-on transistor.

[0133] Optionally, the third voltage terminal may be the first low voltage terminal, but is not limited thereto.

[0134] In at least one embodiment of the present invention, the driving circuit further includes a first node control circuit;

[0135] The first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0136] In a specific implementation, the first node control circuit can also control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0137] Optionally, the fourth voltage terminal may be the second low voltage terminal, but is not limited thereto.

[0138] like Figure 7 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit further includes a first node control circuit 13;

[0139] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0140] like Figure 8 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit may further include a first node control circuit 13;

[0141] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0142] like Fig. 9 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit may further include a first node control circuit 13;

[0143] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0144] In at least one embodiment of the present invention, the second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0145] In a specific implementation, the second output node control circuit can also control the connection or disconnection between the first node and the second output node under the control of the first clock signal, and control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0146] In at least one embodiment of the present invention, the output circuit is also electrically connected to the first voltage terminal and the second voltage terminal respectively;

[0147] The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

[0148] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0149] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;

[0150] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0151] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node;

[0152] A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0153] Optionally, the eighth transistor is a dual-gate transistor.

[0154] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0155] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0156] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node;

[0157] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node;

[0158] A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0159] Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;

[0160] The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0161] A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0162] Optionally, the second output node control circuit includes a twelfth transistor and a thirteenth transistor;

[0163] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node;

[0164] A gate of the thirteenth transistor is electrically connected to the first output node, a first electrode of the thirteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second output node.

[0165] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0166] The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;

[0167] A gate of the fifteenth transistor is electrically connected to the second output node, a first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

[0168] The driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit;

[0169] The first end of the third energy storage circuit is electrically connected to the second output node, the third energy storage circuit is electrically connected to the first voltage end respectively, and the third energy storage circuit is used to store electric energy.

[0170] In a specific implementation, the driving circuit further includes a third energy storage circuit, and the third energy storage circuit is used to maintain the potential of the second output node.

[0171] like Fig.10 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 101;

[0172] The second output node control circuit 14 is also electrically connected to the first output node N1, the first clock signal terminal CKB and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0173] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0174] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0175] A first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , a second end of the third energy storage circuit 101 is electrically connected to the first voltage terminal V1 , and the third energy storage circuit 101 is used to store electrical energy.

[0176] like Fig.11 As shown, in Figure 8 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 101;

[0177] The second output node control circuit 14 is also electrically connected to the first output node N1, the first clock signal terminal CKB and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0178] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0179] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0180] The first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , and the third energy storage circuit 101 is electrically connected to the first voltage end V1 , respectively. The third energy storage circuit 101 is used to store electrical energy.

[0181] like Fig.12 As shown, in Fig. 9 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 101;

[0182] The second output node control circuit 14 is also electrically connected to the first output node N1, the first clock signal terminal CKB and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0183] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0184] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0185] The first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , and the third energy storage circuit 101 is electrically connected to the first voltage end V1 , respectively. The third energy storage circuit 101 is used to store electrical energy.

[0186] like Fig.13 As shown, in Fig.10 Based on at least one embodiment of the driving circuit shown,

[0187] The inverting circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C0;

[0188] The gate of the first transistor T1 is electrically connected to the first output node N1, the source of the first transistor T1 is electrically connected to the second node N7, and the drain of the first transistor T1 is electrically connected to the high voltage terminal VGH;

[0189] The gate of the second transistor T2 is electrically connected to the first output node N1, the source of the second transistor T2 is electrically connected to the first node N2, and the drain of the second transistor T2 is electrically connected to the high voltage terminal VGH;

[0190] The gate of the third transistor T3 is electrically connected to the second node N7, the source of the third transistor T3 is electrically connected to the low voltage terminal VGL, and the drain of the third transistor T3 is electrically connected to the first node N2;

[0191] The first end of the storage capacitor C0 is electrically connected to the first clock signal terminal CKB, and the second end of the storage capacitor C0 is electrically connected to the second node N7;

[0192] The first output node control circuit includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0193] The gate of the sixth transistor T6 is electrically connected to the first clock signal terminal CKB, and the source of the sixth transistor T6 is electrically connected to the high voltage terminal VGH;

[0194] The gate of the seventh transistor T7 is electrically connected to the first node N2, the source of the seventh transistor T7 is electrically connected to the drain of the sixth transistor T6, and the drain of the seventh transistor T7 is electrically connected to the first output node N1;

[0195] The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal CK, the source of the eighth transistor T8 is electrically connected to the input terminal STV, and the drain of the eighth transistor T8 is electrically connected to the first output node N1;

[0196] The first node control circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0197] The gate of the tenth transistor T10 is electrically connected to the first node N2, the source of the tenth transistor T10 is electrically connected to the second low voltage terminal VGL2, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0198] The gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal CKB, and the drain of the eleventh transistor T11 is electrically connected to the first node N2;

[0199] The second output node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13;

[0200] A gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CKB, a source of the twelfth transistor T12 is electrically connected to the first node N2, and a second electrode of the twelfth transistor T12 is electrically connected to the second output node N4;

[0201] The gate of the thirteenth transistor T13 is electrically connected to the first output node N1, the source of the thirteenth transistor T13 is electrically connected to the high voltage terminal VGH, and the drain of the thirteenth transistor T13 is electrically connected to the second output node N4;

[0202] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0203] The gate of the fourteenth transistor T14 is electrically connected to the first output node N1, the source of the fourteenth transistor T14 is electrically connected to the driving output terminal O1, and the drain of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL;

[0204] The gate of the fifteenth transistor T15 is electrically connected to the second output node N4, the source of the fifteenth transistor T15 is electrically connected to the high voltage terminal VGH, and the drain of the fifteenth transistor T15 is electrically connected to the driving output terminal O1;

[0205] The first energy storage circuit includes a first capacitor C1;

[0206] A first end of the first capacitor C1 is electrically connected to the first output node N1, and a second end of the first capacitor C1 is electrically connected to the driving output terminal O1;

[0207] The third energy storage circuit includes a third capacitor C3;

[0208] A first end of the third capacitor C3 is electrically connected to the second output node N4 , and the third capacitor C3 is electrically connected to the high voltage end VGH.

[0209] In at least one embodiment of the present invention, the voltage value of the second low voltage signal provided by VGL2 may be greater than the voltage value of the first low voltage signal provided by VGL1. For example, the voltage value of the first low voltage signal may be -7V, and the voltage value of the second low voltage signal may be -9V, but not limited thereto.

[0210] exist Fig.13 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0211] exist Fig.13 In at least one embodiment of the driving circuit shown, the fifth node N5 is a node between T6 and T7, and the sixth node N6 is a node between T10 and T11.

[0212] exist Fig.13 In at least one embodiment of the driving circuit shown, T8 may be a dual-gate transistor to reduce leakage of T8 and prevent C1 from leaking through T8.

[0213] exist Fig.13 In at least one embodiment of the driving circuit shown, in order to prevent C1 from leaking through T8, a normally-on transistor can be added, and the gate of the normally-on transistor can be electrically connected to the low voltage end. The normally-on transistor is arranged between N1 and the gate of T14, which can stabilize the potential of N1 and effectively improve the leakage of N1.

[0214] like Fig.14 As shown, the present invention Fig.13 When at least one embodiment of the driving circuit shown is in operation, the display cycle includes a first time period S1, a second time period S2, a third time period S3, a fourth time period S4, a fifth time period S5 and a sixth time period S6 which are arranged in sequence;

[0215] In the first time period S1, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, and the potential of N1 is maintained at a low voltage. Fig.15A As shown, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0216] In the second time period S2, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal. Fig. 15B As shown, T8 is turned on, the potential of N1 is a high voltage, T4 is turned off, T1, T2 and T3 are all turned off, T12 is turned off, T14 and T15 are turned off, and O1 outputs a low voltage signal;

[0217] In the third time period S3, when CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a high voltage signal. Fig. 15C As shown, since the potential of the first clock signal provided by CKB is reduced from a high voltage to a low voltage, the potential of N7 is a low voltage, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, N2 is connected to VGL2, T12 is turned on, the potential of N4 is a low voltage, T15 is turned on, O1 outputs a high voltage signal, T8 is turned off, T6 and T7 are turned on, the potential of N1 is a high voltage, and T14 is turned off;

[0218] In the fourth time period S4, when CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal. Fig.15D As shown, T8 is turned on, the potential of N1 is a high voltage, T14 is turned off, T1 and T2 are turned off, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is maintained at the first voltage, T10 is turned on, T11 is turned off, T12 is turned off, the potential of N4 is maintained at a low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0219] In the fifth time period S5, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a low voltage signal. Fig.15E As shown, T8 is turned on, the potential of N1 is a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 and T11 are turned off, T6 and T7 are turned off, T13 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0220] In the sixth time period S6, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a low voltage signal. Fig.15F As shown, T8 is turned off, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 is turned off, T11 is turned off, T12 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal.

[0221] like Fig.14 As shown, the present invention Fig.13 When at least one embodiment of the driving circuit shown is in operation, the falling edge of the driving signal output by O1 has no step.

[0222] The present invention Fig.13 At least one embodiment of the driving circuit shown in the figure is in operation.

[0223] In the first time period S1, the potential of N1 is a low voltage, the potential of N2 is a high voltage, the potential of N4 is a high voltage, the potential of N5 is a high voltage, the potential of N6 is a low voltage, and O1 outputs a low voltage signal;

[0224] In the second time period S2, the potential of N1 is a high voltage, the potential of N2 is a high voltage, the potential of N4 is a high voltage, the potential of N5 is a high voltage, the potential of N6 is a low voltage, and O1 outputs a low voltage signal;

[0225] In the third time period S3, the potential of N1 is a high voltage, the potential of N2 is a low voltage, the potential of N4 is a low voltage, the potential of N5 is a high voltage, the potential of N6 is a low voltage, and O1 outputs a high voltage signal;

[0226] In the fourth time period S4, the potential of N1 is a low voltage, the potential of N2 is a high voltage, the potential of N4 is a high voltage, the potential of N5 is a high voltage, the potential of N6 is a low voltage, and O1 outputs a low voltage signal;

[0227] In the fifth time period S5, the potential of N1 is a low voltage, the potential of N2 is a high voltage, the potential of N4 is a high voltage, the potential of N5 is a high voltage, the potential of N6 is a high voltage, and O1 outputs a low voltage signal.

[0228] The present invention Fig.16 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Fig.13 The difference of at least one embodiment of the driving circuit shown is that:

[0229] The storage capacitor C0 is not included;

[0230] The present invention Fig.16 At least one embodiment of the driving circuit shown further includes a fourth transistor T4;

[0231] The gate of the fourth transistor T4 and the source of the fourth transistor T4 are both electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the second node N7;

[0232] T4 is a p-type transistor.

[0233] exist Fig.16 In at least one embodiment of the driving circuit shown, T8 may be a dual-gate transistor to reduce leakage of T8 and prevent C1 from leaking through T8.

[0234] exist Fig.16 In at least one embodiment of the driving circuit shown, in order to prevent C1 from leaking through T8, a normally-on transistor can be added, and the gate of the normally-on transistor can be electrically connected to the low voltage end. The normally-on transistor is arranged between N1 and the gate of T14, which can stabilize the potential of N1 and effectively improve the leakage of N1.

[0235] The present invention Fig.16 When at least one embodiment of the driving circuit shown is in operation, the display cycle includes a first time period, a second time period, a third time period, a fourth time period, a fifth time period and a sixth time period which are arranged in sequence;

[0236] In the first time period, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0237] In the second time period, CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a high voltage signal, T8 is turned on, the potential of N1 is a high voltage, T4 is turned off, T1 and T2 are turned off, T12 is turned off, T14 and T15 are turned off, and O1 outputs a low voltage signal;

[0238] In the third time period S3, when CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a high voltage signal, the potential of N1 is a high voltage, T1 and T2 are turned off, T4 is turned on, the potential of N7 is a low voltage, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, T12 is turned on, the potential of N4 is a low voltage, T15 is turned on, O1 outputs a high voltage signal, T8 is turned off, and T14 is turned off;

[0239] In the third time period, when CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a high voltage signal, T8 is turned on, the potential of N1 is a high voltage, T14 is turned off, T1 and T2 are turned off, T4 is turned on, the potential of N7 is a low voltage, T3 is turned on, the potential of N2 is a low voltage, T10 is turned on, T11 is turned off, T12 is turned off, the potential of N4 is maintained at a low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0240] In the fourth time period, CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a low voltage signal, T8 is turned on, the potential of N1 is a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 and T11 are turned off, T6 and T7 are turned off, T13 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0241] In the fifth time period, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, T8 is turned off, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 is turned off, T11 is turned off, T12 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal.

[0242] Fig.17 The present invention Fig.16 FIG. 1 is a timing diagram of the operation of at least one embodiment of the driving circuit shown.

[0243] exist Fig.16 In at least one embodiment of the driving circuit shown, the gate of T4 and the source of T4 may also be electrically connected to the first clock signal terminal; or, the gate of T4 and the source of T4 may also be electrically connected to the second clock signal terminal; or, the gate of T4 and the source of T4 may also be electrically connected to the control terminal.

[0244] In at least one embodiment of the present invention, the control signal provided by the control terminal may be inversely proportional to the input signal provided by the STV.

[0245] The present invention Fig.16 When at least one embodiment of the driving circuit shown is in operation, the falling edge of the driving signal output by O1 has no step.

[0246] The present invention Fig.18 At least one embodiment of the driving circuit shown in the figure is consistent with the present invention Fig.13 The difference of at least one embodiment of the driving circuit shown is that:

[0247] The present invention Fig.18 At least one embodiment of the driving circuit shown in the figure further includes a fifth transistor T5, a second capacitor C2 and a ninth transistor T9; Fig.18 At least one embodiment of the driving circuit shown does not include C1;

[0248] The gate of the fifth transistor T5 is electrically connected to the first output node N1, the source of the fifth transistor T5 is electrically connected to the first clock signal terminal CKB, and the drain of the fifth transistor T5 is electrically connected to the first end of the second capacitor C2;

[0249] The second end of the second capacitor C2 is electrically connected to the first output node N1;

[0250] The gate of the ninth transistor T9 is electrically connected to the low voltage terminal VGL, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the first output node N1;

[0251] The drain of the seventh transistor T7 is electrically connected to the third node N3;

[0252] A drain of the eighth transistor T8 is electrically connected to the third node N3.

[0253] exist Fig.18 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0254] exist Fig.18 In at least one embodiment of the driving circuit shown, T9 may not be provided.

[0255] The present invention Fig.18 At least one embodiment of the driving circuit shown is additionally provided with T5 and C2; each time the potential of the first clock signal provided by CKB decreases from a high level to a low level, the potential of N1 will be pulled down, and the driving signal output by O1 will be more stable.

[0256] like Fig.19 As shown, the present invention Fig.18 At least one embodiment of the driving circuit shown in the figure is in operation.

[0257] In the first time period S1, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, the potential of N1 is a low voltage, T14 is turned on, and O1 outputs a low voltage signal;

[0258] In the second time period S2, STV provides a high voltage signal, CK provides a low voltage signal, CKB provides a high voltage signal, T8 is turned on, the potential of N1 is a high voltage signal, T1 and T2 are turned off, the potential of N7 is a high voltage signal, T3 is turned off, T12 is turned off, T9 is turned on, T14 and T15 are turned off, and O1 outputs a low voltage signal;

[0259] In the third time period S3, STV provides a high voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T8 is turned off, the potential of N1 is maintained as a high voltage signal, T1 and T2 are turned off, the potential of N7 is a low voltage, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, T12 is turned on, the potential of N4 is a low voltage, and O1 outputs a high voltage signal;

[0260] In the fourth time period S4, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T8 is turned off, the potential of N1 is maintained as a high voltage signal, T1 and T2 are turned off, the potential of N7 is a low voltage signal, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, T12 is turned on, the potential of N4 is a low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0261] In the fifth time period S5, STV provides a low voltage signal, CK provides a low voltage signal, CKB provides a high voltage signal, T8 is turned on, the potential of N1 is a low voltage, T14 is turned on, O1 outputs a low voltage signal; T1 and T2 are turned on, the potential of N2 is a high voltage, T12 is turned off, T13 is turned on, the potential of N4 is a high voltage, and T15 is turned on;

[0262] In the sixth time period S6, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T5 is turned on, the potential of N1 is pulled down again by C2 coupling, T14 is turned on, and O1 outputs a low voltage signal.

[0263] Fig. 20 At least one embodiment of the driving circuit shown is Fig.18 The difference of at least one embodiment of the driving circuit shown is that the tenth transistor and the eleventh transistor are not included.

[0264] In a specific implementation, since there is an inverting circuit that can control the potential of N2, without including the tenth transistor and the eleventh transistor, Fig. 20 At least one embodiment of the driving circuit can also work normally.

[0265] The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0266] The inverting circuit inverts the potential of the first output node to obtain the potential of the first node;

[0267] A first output node control circuit controls the potential of the first output node;

[0268] The second output node control circuit obtains the potential of the second output node according to the potential of the first node;

[0269] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0270] The display device described in the embodiment of the present invention includes the above-mentioned driving circuit.

[0271] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: comprising an inverting circuit, a first output node control circuit, a second output node control circuit and an output circuit; The inverting circuit is electrically connected to the first output node and the first node respectively, and is used to invert the potential of the first output node in at least a part of the display period to obtain the potential of the first node; The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node; The second output node control circuit is electrically connected to the first node and the second output node respectively, and is used to obtain the potential of the second output node according to the potential of the first node; The output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

2. The driving circuit according to claim 1, characterized in that: Also included is a first energy storage circuit; The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

3. The driving circuit according to claim 1, wherein: The inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor; The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node; The first end of the storage capacitor is electrically connected to the first clock signal end, and the second end of the storage capacitor is electrically connected to the second node.

4. The driving circuit according to claim 1, wherein: The inverter circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node; The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

5. The driving circuit according to claim 4, characterized in that: The first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal or a frame reset terminal.

6. The driving circuit according to claim 1, characterized in that: Also includes a second energy storage circuit and an on-off control circuit; The on-off control circuit is electrically connected to the first output node, the first clock signal terminal and the first terminal of the second energy storage circuit respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node; The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electric energy.

7. The driving circuit according to claim 6, characterized in that: The on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor; The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor; The second end of the second capacitor is electrically connected to the first output node.

8. The driving circuit according to any one of claims 1 to 7, characterized in that: The first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

9. The driving circuit according to any one of claims 1 to 7, characterized in that: The first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

10. The driving circuit according to any one of claims 1 to 7, characterized in that: The driving circuit also includes a first node control circuit; The first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

11. The driving circuit according to any one of claims 1 to 7, characterized in that: The second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

12. The driving circuit according to any one of claims 1 to 7, characterized in that: The output circuit is also electrically connected to the first voltage terminal and the second voltage terminal respectively; The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

13. The driving circuit according to claim 8, characterized in that: The first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor; The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node; A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

14. The driving circuit according to claim 13, characterized in that: The eighth transistor is a dual-gate transistor.

15. The driving circuit according to claim 9, characterized in that: The first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node; The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node; A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

16. The driving circuit according to claim 10, characterized in that: The first node control circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor; A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

17. The driving circuit according to claim 11, characterized in that: The second output node control circuit includes a twelfth transistor and a thirteenth transistor; The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node; A gate of the thirteenth transistor is electrically connected to the first output node, a first electrode of the thirteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second output node.

18. The driving circuit according to claim 12, wherein: The output circuit includes a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal; A gate of the fifteenth transistor is electrically connected to the second output node, a first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

19. The driving circuit according to any one of claims 1 to 6, characterized in that: Also included is a third tank circuit; The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

20. A driving method, applied to the driving circuit according to any one of claims 1 to 19, characterized in that: The driving method comprises: The inverting circuit inverts the potential of the first output node to obtain the potential of the first node; A first output node control circuit controls the potential of the first output node; The second output node control circuit obtains the potential of the second output node according to the potential of the first node; The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

21. A display device, characterized in that: The method comprises a driving circuit as claimed in any one of claims 1 to 19.

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