Pixel and display device having same

Abstract

A pixel and a display device having the same are provided. The pixel includes a light emitting element, a driving transistor, a data writing transistor, and a leakage current compensator. The drive transistor applies a drive current to the light-emitting element. The data write transistor applies a data voltage to the driving transistor in response to a first write signal, and is connected to a first electrode of the driving transistor. A leakage current compensator is connected to a second electrode of the driving transistor, and operates in response to a second write signal different from the first write signal in such a manner that an off state of the driving transistor is maintained in an emission waiting period. The leakage current compensator includes an eighth transistor, and an off state of the driving transistor is maintained in an emission waiting period by the eighth transistor connected to a second electrode of the driving transistor.

Description

Technical Field

[0001] Embodiments of the invention relate to a pixel and a display device including the same. More particularly, embodiments of the invention relate to a pixel for compensating for leakage current to enhance display quality and a display device including the same. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel typically includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, an emission driver for providing an emission signal to the emission line, and a drive controller for controlling the gate driver, the data driver, and the emission driver. Summary of the invention

[0003] In a display device, a threshold voltage of a transistor of a pixel may change due to static electricity or under high temperature conditions. When the threshold voltage of a transistor of a pixel changes, current may leak at the transistor.

[0004] Embodiments of the invention provide a pixel for enhancing display quality.

[0005] An embodiment of the invention also provides a display device including the pixel.

[0006] In an embodiment of a pixel according to the invention, the pixel includes a light emitting element, a driving transistor, a data writing transistor and a leakage current compensator. In such an embodiment, the driving transistor applies a driving current to the light emitting element. In such an embodiment, the data writing transistor applies a data voltage to the driving transistor in response to a first writing signal and is connected to a first electrode of the driving transistor. In such an embodiment, the leakage current compensator is connected to a second electrode of the driving transistor and operates in a manner such that the off state of the driving transistor is maintained during the emission waiting period in response to a second writing signal different from the first writing signal.

[0007] In an embodiment, the leakage current compensator may include an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the second electrode of the driving transistor.

[0008] In an embodiment, the voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0009] In an embodiment, the pixel may further include a storage capacitor. In such an embodiment, the storage capacitor may include a first electrode receiving the first power supply voltage and a second electrode connected to the control electrode of the drive transistor. In such an embodiment, the second write signal is the first power supply voltage.

[0010] In an embodiment, the leakage current compensator may include an eighth transistor and a first capacitor. In such an embodiment, the eighth transistor may include a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to a fifth node. In such an embodiment, the first capacitor may include a first electrode connected to the fifth node and a second electrode connected to the second electrode of the driving transistor.

[0011] In an embodiment, the voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0012] In an embodiment, the emission waiting period may be after the writing period in which the first write signal may have an active level. In such an embodiment, the first write signal and the second write signal may have an inactive level in the emission waiting period.

[0013] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving a first write signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a seventh transistor including a control electrode receiving a first write signal, a first electrode receiving an initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to the first node; and a light emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage. In such an embodiment, the driving transistor may be a first transistor. In such an embodiment, the data writing transistor may be a second transistor. In such an embodiment, the leakage current compensator may include an eighth transistor. In such an embodiment, a voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0014] In an embodiment, a frame period of a pixel may include: an initialization period, in which the emission signal may have a non-activation level, the initialization signal may have an activation level, the first write signal may have a non-activation level, and the second write signal may have a non-activation level; a write period, in which the emission signal may have a non-activation level, the initialization signal may have a non-activation level, the first write signal may have an activation level, and the second write signal may have a non-activation level; an emission waiting period, in which the emission signal may have a non-activation level, the initialization signal may have a non-activation level, the first write signal may have a non-activation level, and the second write signal may have a non-activation level; and an emission period, in which the emission signal may have an activation level, the initialization signal may have a non-activation level, the first write signal may have a non-activation level, and the second write signal may have a non-activation level.

[0015] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving a first write signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a seventh transistor including a control electrode receiving a first write signal, a first electrode receiving an initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to the fifth node; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node; a second capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to the first node; and a light emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage. In such an embodiment, the drive transistor may be a first transistor. In such an embodiment, the data write transistor may be a second transistor. In such an embodiment, the leakage current compensator may include an eighth transistor and a first capacitor. In such an embodiment, the voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0016] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving a first write signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a seventh transistor including a control electrode receiving a first write signal, a first electrode receiving a second initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to the first node; and a light emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage. In such an embodiment, the driving transistor may be a first transistor. In such an embodiment, the data writing transistor may be a second transistor. In such an embodiment, the leakage current compensator may include an eighth transistor. In such an embodiment, a voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0017] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving a first write signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a compensation signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a seventh transistor including a control electrode receiving a light emitting element initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to the first node; and a light emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage. In such an embodiment, the driving transistor may be a first transistor. In such an embodiment, the data writing transistor may be a second transistor. In such an embodiment, the leakage current compensator may include an eighth transistor. In such an embodiment, a voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0018] In an embodiment of a display device according to the invention, the display device includes a display panel, a gate driver, a data driver, and an emission driver. In such an embodiment, the display panel includes pixels. In such an embodiment, the gate driver applies a gate signal to the pixel. In such an embodiment, the data driver applies a data voltage to the pixel. In such an embodiment, the emission driver applies an emission signal to the pixel. In such an embodiment, the pixel includes: a light-emitting element; a driving transistor, applying a driving current to the light-emitting element; a data writing transistor, applying a data voltage in response to a first writing signal and connected to a first electrode of the driving transistor; and a leakage current compensator, connected to a second electrode of the driving transistor, wherein the leakage current compensator operates in response to a second writing signal different from the first writing signal in such a way that the off state of the driving transistor is maintained during the emission waiting period.

[0019] In an embodiment, the leakage current compensator may include an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the second electrode of the driving transistor.

[0020] In an embodiment, the voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0021] In an embodiment, the pixel may further include a storage capacitor. In such an embodiment, the storage capacitor may include a first electrode receiving the first power supply voltage and a second electrode connected to the control electrode of the drive transistor. In such an embodiment, the second write signal is the first power supply voltage.

[0022] In an embodiment, the leakage current compensator may include an eighth transistor and a first capacitor. In such an embodiment, the eighth transistor may include a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to a fifth node. In such an embodiment, the first capacitor may include a first electrode connected to the fifth node and a second electrode connected to the second electrode of the driving transistor.

[0023] In an embodiment, the voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0024] In an embodiment, the emission waiting period may be after the writing period in which the first write signal may have an active level. In such an embodiment, the first write signal and the second write signal may have an inactive level in the emission waiting period.

[0025] In an embodiment, a pixel may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving a first write signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a seventh transistor including a control electrode receiving a first write signal, a first electrode receiving an initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving a second write signal, a first electrode receiving a data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to the first node; and a light emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage. In such an embodiment, the driving transistor may be a first transistor. In such an embodiment, the data writing transistor may be a second transistor. In such an embodiment, the leakage current compensator may include an eighth transistor. In such an embodiment, a voltage level of the second write signal may be maintained at an inactive level during the frame period.

[0026] According to the embodiments of the pixel and the display device described herein, when the leakage current flows through the data writing transistor, the off state of the driving transistor can be maintained by making the voltage of the first electrode of the driving transistor and the voltage of the second electrode of the driving transistor equal through the leakage current compensator. Therefore, the voltage of the control electrode of the driving transistor can be maintained.

[0027] In such an embodiment, since the voltage of the control electrode of the driving transistor can be maintained, the brightness control of the pixel can be enhanced. Therefore, the display quality of the display panel can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the embodiments of the invention will become more apparent by describing in detail the embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing a display device according to an embodiment of the invention; Figure 2 It is shown Figure 1 A circuit diagram of a pixel; Figure 3is shown applied to Figure 2 A timing diagram of an input signal of a pixel; Figure 4 is a circuit diagram showing a pixel of a display device according to an embodiment of the invention; Figure 5 is a circuit diagram showing a pixel of a display device according to an embodiment of the invention; Figure 6 is a circuit diagram showing a pixel of a display device according to an embodiment of the invention; Figure 7 is a circuit diagram showing a pixel of a display device according to an embodiment of the invention; Figure 8 is shown applied to Figure 7 A timing diagram of an input signal of a pixel; Fig. 9 is shown applied to Figure 7 A timing diagram of an input signal of a pixel; Fig.10 is shown applied to Figure 7 A timing diagram of an input signal of a pixel; Fig.11 is a block diagram showing an electronic device according to an embodiment of the invention; and Fig.12 It is shown Fig.11 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0029] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals represent the same elements throughout.

[0030] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0031] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0032] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both singular and plural. Therefore, in the claim, mentioning an element ("one" element) followed by mentioning "the" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one" will not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. It will also be understood that the term "including" and / or its variants or "comprising" and / or its variants when used in this specification, illustrate the existence of the stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0033] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in one of the figures in the figure is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the figure is turned over, the element described as being "below" or "under" the other element will then be oriented as "above" the other element. Therefore, the term "below..." or "under..." can cover both upper and lower orientations.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0035] Hereinafter, embodiments of the invention will be described in more detail with reference to the accompanying drawings.

[0036] Figure 1 is a block diagram showing a display device according to an embodiment of the invention.

[0037] Reference Figure 1 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0038] The display panel 100 includes a display area configured to display an image and a peripheral area adjacent to the display area.

[0039] The display panel 100 includes gate lines GL, data lines DL, emission lines EL, and pixels 110 electrically connected to the gate lines GL, data lines DL, and emission lines EL, respectively. The gate lines GL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1. The gate lines GL include a first write gate line GWL, a second write gate line GWCL, and an initialization gate line GIL.

[0040] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device. In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. In an embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0041] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0042] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the generated first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0043] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the generated second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0044] The driving controller 200 generates a data signal DATA based on input image data IMG and outputs the data signal DATA to the data driver 500 .

[0045] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the generated third control signal CONT3 to the gamma reference voltage generator 400 .

[0046] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the generated fourth control signal CONT4 to the emission driver 600 .

[0047] The gate driver 300 generates gate signals GI, GWC, and GW for driving the gate lines GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signals GI, GWC, and GW to the gate lines GL.

[0048] In an embodiment according to the invention, the gate driver 300 may be installed in a peripheral area of ​​the display panel 100. In an embodiment, for example, the gate driver 300 may be integrated (or integrally formed) in the peripheral area of ​​the display panel 100.

[0049] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to each of the data signals DATA.

[0050] In an embodiment, for example, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0051] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into a data voltage VDATA having an analog form by using the gamma reference voltage VGREF. The data driver 500 may output the data voltage VDATA to the data line DL.

[0052] In an embodiment according to the invention, the data driver 500 may be installed in the peripheral area of ​​the display panel 100. In an embodiment, for example, the data driver 500 may be integrated (or integrally formed) in the peripheral area of ​​the display panel 100.

[0053] The emission driver 600 generates an emission signal EM for driving the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal EM to the emission line EL.

[0054] In an embodiment, for example, the emission driver 600 may be integrated (or integrally formed) in a peripheral area of ​​the display panel 100. In an embodiment, for example, the emission driver 600 may be installed in a peripheral area of ​​the display panel 100.

[0055] Although for ease of illustration and description, Figure 1 100 and the emission driver 600 are provided on a second side of the display panel 100 opposite to the first side, but the invention is not limited thereto. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be provided on the same side of the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be provided on both sides of the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be formed integrally with each other, for example, as the same integrated circuit chip.

[0056] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel 110. Figure 3 is shown applied to Figure 2 1 is a timing diagram of the input signal of the pixel 110.

[0057] In an embodiment, the pixel 110 receives the first write signal GW, the second write signal GWC, the initialization signal GI, the data voltage VDATA, the emission signal EM, and the light emitting element EE emits light based on the data voltage VDATA, and the display panel 100 displays an image.

[0058] The pixel 110 may include: a light emitting element EE; a driving transistor T1, applying a driving current to the light emitting element EE; a data writing transistor, applying a data voltage VDATA to the driving transistor T1 in response to a first writing signal GW and connected to a first electrode of the driving transistor T1; and a leakage current compensator, operating in a manner such that the off state of the driving transistor T1 is maintained during the emission waiting period. The leakage current compensator may be connected to the second electrode of the driving transistor T1. In an embodiment, the leakage current compensator may include an eighth transistor T8. For example, the eighth transistor T8 may be referred to as a leakage current compensation transistor.

[0059] In an embodiment, Figure 2 As shown in , the pixel 110 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a second capacitor C2, and a light emitting element EE.

[0060] The first transistor T1 may include a control electrode connected to the first node N1 , a first electrode connected to the second node N2 , and a second electrode connected to the third node N3 .

[0061] The second transistor T2 may include a control electrode configured to receive the first write signal GW (or connected to a line transmitting the first write signal GW), a first electrode configured to receive the data voltage VDATA, and a second electrode connected to the second node N2.

[0062] The third transistor T3 may include a control electrode configured to receive the first write signal GW, a first electrode connected to the third node N3 , and a second electrode connected to the first node N1 .

[0063] Although for ease of illustration and description, Figure 2 , an embodiment in which the third transistor T3 is a single transistor is shown, but the third transistor T3 may include or be defined by two transistors (double transistor) connected to each other in series.

[0064] The fourth transistor T4 may include a control electrode configured to receive the initialization signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the first node N1. The initialization voltage VINT may be referred to as a first initialization voltage.

[0065] Although for ease of illustration and description, Figure 2 , an embodiment in which the fourth transistor T4 is a single transistor is shown, but the fourth transistor T4 may include or be defined by two transistors (double transistor) connected to each other in series.

[0066] The fifth transistor T5 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the second node N2.

[0067] The sixth transistor T6 may include a control electrode configured to receive the emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0068] The seventh transistor T7 may include a control electrode configured to receive the first write signal GW, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the fourth node N4.

[0069] The eighth transistor T8 may include a control electrode configured to receive the second write signal GWC, a first electrode configured to receive the data voltage VDATA, and a second electrode connected to the third node N3. In an embodiment, for example, the inactive level of the second write signal GWC may be maintained, that is, the voltage level of the second write signal GWC may be maintained at the inactive level. In an embodiment, for example, the second write signal GWC may have a DC voltage. In an embodiment, for example, the eighth transistor T8 may always be turned off by the second write signal GWC.

[0070] In some embodiments, for example, the first transistor T1 to the eighth transistor T8 may be a P-type thin film transistor. The control electrode of the first transistor T1 to the eighth transistor T8 may be a gate electrode, the first electrode of the first transistor T1 to the eighth transistor T8 may be a source electrode, and the second electrode of the first transistor T1 to the eighth transistor T8 may be a drain electrode. The source electrode and the drain electrode of the first transistor T1 to the eighth transistor T8 may be referred to as opposite electrodes opposite to each other.

[0071] The second capacitor C2 may include a first electrode configured to receive the first power voltage ELVDD and a second electrode connected to the first node N1.

[0072] The light emitting element EE may include an anode connected to the fourth node N4 and a cathode configured to receive the second power voltage ELVSS. The second power voltage ELVSS may be lower than the first power voltage ELVDD.

[0073] The first transistor T1 may be referred to as a driving transistor. The second transistor T2 may be referred to as a data writing transistor. The eighth transistor T8 may be referred to as a leakage current compensation transistor. The second capacitor C2 may be referred to as a storage capacitor.

[0074] Reference Figure 3, in the first period DU1A, the first node N1 and the second capacitor C2 are initialized by the initialization signal GI. In the second period DU2A, the threshold voltage of the first transistor T1 is compensated by the first write signal GW, wherein the data voltage VDATA in which the threshold voltage of the first transistor T1 is compensated is applied to the first node N1, and the anode of the light emitting element EE is initialized by the first write signal GW. The third period DU3A may be referred to as an emission waiting period. The emission waiting period may be after the writing period in which the first write signal GW has an activation level. In an embodiment, for example, the emission waiting period may be a period in which the first write signal GW has a non-activation level after having an activation level and before the emission signal has an activation level. In the fourth period DU4A, the light emitting element EE emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0075] In the first period DU1A, the initialization signal GI may have an activation level. In an embodiment, for example, the activation level of the initialization signal GI may be a low level. When the initialization signal GI has an activation level, the fourth transistor T4 may be turned on. Therefore, the initialization voltage VINT may be applied to the first node N1. For example, the first period DU1A may be referred to as an initialization period.

[0076] In the second period DU2A, the first write signal GW may have an activation level. In an embodiment, for example, the activation level of the first write signal GW may be a low level. When the first write signal GW has an activation level, the second transistor T2 and the third transistor T3 may be turned on. In the second period DU2A, the first transistor T1 may be turned on by the initialization voltage VINT. In the second period DU2A, since the first write signal GW may have an activation level, the seventh transistor T7 may be turned on. Therefore, the initialization voltage VINT may be applied to the anode of the light emitting element EE. For example, the second period DU2A may be referred to as a write period.

[0077] In the second period DU2A, the voltage of the first node N1 may have the sum of the data voltage VDATA and the threshold voltage of the first transistor T1 through the path of the first transistor T1 , the second transistor T2 , and the third transistor T3 .

[0078] The third period DU3A may be a period for waiting for the emission signal EM. In the third period DU3A, the inactive levels of the first write signal GW and the second write signal GWC may be maintained.

[0079] In an embodiment, the threshold voltage of the transistor may change due to static electricity and high temperature conditions. In an embodiment, for example, in the case where the transistor may be a P-type thin film transistor, the threshold voltage of the P-type transistor may be positively shifted due to static electricity and high temperature conditions. Therefore, the threshold voltage of the P-type thin film transistor may have a positive value. For example, a positive value may be referred to as a positive threshold voltage. In a conventional pixel (e.g., a pixel that does not include the eighth transistor T8), when the threshold voltage of the transistor changes due to static electricity and high temperature conditions, the driving transistor T1 of the conventional pixel may be turned on. Therefore, the voltage of the control electrode of the driving transistor T1 of the conventional pixel may change, so that the brightness control of the conventional pixel may be degraded.

[0080] In an embodiment of the invention, when the leakage current flows through the second transistor T2 and the eighth transistor T8, a voltage (e.g., ΔVDATA) lower than the data voltage VDATA may be applied to the second node N2 and the third node N3. Therefore, the voltage of the first electrode of the driving transistor T1 and the voltage of the second electrode of the driving transistor T1 may be substantially the same as each other. Therefore, the driving transistor T1 may be turned off. In an embodiment, for example, the turned-off state of the driving transistor T1 may be maintained.

[0081] The first electrode (e.g., source electrode) of the third transistor T3 may have a voltage (e.g., ΔVDATA) lower than the data voltage VDATA. The voltage obtained by subtracting the voltage of the first electrode (e.g., source electrode) of the third transistor T3 from the voltage of the control electrode of the third transistor T3 may be higher than the positive threshold voltage. Therefore, the cut-off state of the third transistor T3 may be maintained. Therefore, the voltage of the control electrode of the driving transistor T1 may be maintained, so that the brightness control of the pixel 110 may be enhanced, and the display quality of the display panel 100 may be enhanced.

[0082] In an embodiment, for example, the first period DU1A, the second period DU2A, and the third period DU3A may be collectively defined as a non-transmission period.

[0083] In the fourth period DU4A, the emission signal EM may have an activation level. In an embodiment, for example, the activation level of the emission signal EM may be a low level. When the emission signal EM may have an activation level, the fifth transistor T5 and the sixth transistor T6 may be turned on. In addition, the first transistor T1 may be turned on by the data voltage VDATA. For example, the fourth period DU4A may be referred to as an emission period.

[0084] In the fourth period DU4A, a driving current may be applied to the light emitting element EE through a path of the fifth transistor T5, the first transistor T1, and the sixth transistor T6. The driving current may be determined by the data voltage VDATA. The brightness of the light emitting element EE may be determined by the driving current.

[0085] Figure 4 is a circuit diagram showing a pixel 120 of a display device according to an embodiment of the invention.

[0086] In addition to the first power supply voltage ELVDD being applied to the control electrode of the eighth transistor T8 of the pixel 120, according to Figure 4 The display device of the embodiment shown in FIG. Figures 1 to 3 The display devices of the embodiments described are substantially the same. Therefore, the same reference numerals will be used to denote the same as those in the above referenced embodiments. Figures 1 to 3 The components described are the same or similar components, and any repeated detailed description thereof will be omitted.

[0087] Reference Figure 4 In an embodiment, the pixel 120 includes an eighth transistor T8. Therefore, when the leakage current flows through the second transistor T2 and the eighth transistor T8, the voltage of the first electrode of the driving transistor T1 and the voltage of the second electrode of the driving transistor T1 may be substantially the same as each other. Therefore, the cut-off state of the driving transistor T1 may be maintained. Therefore, the voltage of the control electrode of the driving transistor T1 may be maintained, so that the brightness control of the pixel 120 may be enhanced, and the display quality of the display panel 100 may be enhanced.

[0088] In an embodiment, the second write signal GWC may be the first power supply voltage ELVDD. Therefore, the lines of the pixels 120 may be reduced, and thus the integration and reliability of the pixels 120 may be enhanced.

[0089] Figure 5 is a circuit diagram showing a pixel 130 of a display device according to an embodiment of the invention.

[0090] In addition to the second initialization voltage AINT being applied to the first electrode of the seventh transistor T7 of the pixel 130, according to Figure 5 The display device of the embodiment shown in FIG. Figures 1 to 3 The display devices of the embodiments described are substantially the same. Therefore, the same reference numerals will be used to denote the same Figures 1 to 3 The present invention relates to components that are the same as or similar to those described in the previous embodiments, and any repeated detailed description thereof will be omitted.

[0091] Reference Figure 5In an embodiment, the pixel 130 includes an eighth transistor T8. Therefore, when the leakage current flows through the second transistor T2 and the eighth transistor T8, the voltage of the first electrode of the driving transistor T1 and the voltage of the second electrode of the driving transistor T1 may be substantially the same. Therefore, the cut-off state of the driving transistor T1 may be maintained, and the voltage of the control electrode of the driving transistor T1 may be maintained, so that the brightness control of the pixel 130 may be enhanced, and the display quality of the display panel 100 may be enhanced. In such an embodiment, the second initialization voltage AINT is applied to the first electrode of the seventh transistor T7, so that the stability of the pixel 130 may be enhanced.

[0092] Figure 6 is a circuit diagram showing a pixel 140 of a display device according to an embodiment of the invention.

[0093] In addition to the pixel 140 further including the first capacitor C1, according to Figure 6 The display device of the embodiment shown in FIG. Figures 1 to 3 The display devices of the embodiments described are substantially the same. Therefore, the same reference numerals will be used to denote the same Figures 1 to 3 The present invention relates to components that are the same as or similar to those described in the previous embodiments, and any repeated detailed description thereof will be omitted.

[0094] Reference Figure 6 In an embodiment, the first capacitor C1 may include a first electrode connected to the second electrode of the eighth transistor T8 and a second electrode connected to the third node N3. In an embodiment, for example, the second electrode of the eighth transistor T8 may be connected to the first electrode of the first capacitor C1 at the fifth node N5.

[0095] In an embodiment, a parasitic capacitance may occur due to the connection between the second electrode of the second transistor T2 and the first electrode of the driving transistor T1. In such an embodiment, the leakage current compensator of the pixel 140 further includes a first capacitor C1, so that the voltage of the second electrode (e.g., the drain electrode) of the driving transistor T1 can be higher than the voltage of the first electrode (e.g., the source electrode) of the driving transistor T1 through charge sharing between the parasitic capacitance and the first capacitor C1. Therefore, the off state of the driving transistor T1 can be maintained.

[0096] Therefore, the voltage of the control electrode of the driving transistor T1 can be maintained. In such an embodiment, since the voltage of the control electrode of the driving transistor T1 is maintained, the brightness control of the pixel 140 can be enhanced, and thus the display quality of the display panel 100 can be enhanced.

[0097] Figure 7 is a circuit diagram showing a pixel 150 of a display device according to an embodiment of the invention.

[0098] Except that the control electrode of the third transistor T3 of the pixel 150 receives the compensation signal GC instead of the first write signal GW, and the control electrode of the seventh transistor T7 of the pixel 150 receives the light emitting element initialization signal GB instead of the first write signal GW, according to Figure 7 The display device of the embodiment shown in FIG. Figures 1 to 3 The display devices of the embodiments described are substantially the same. Therefore, the same reference numerals will be used to denote the same Figures 1 to 3 The present invention relates to components that are the same as or similar to those described in the previous embodiments, and any repeated detailed description thereof will be omitted.

[0099] Figure 8 is shown applied to Figure 7 Timing diagram of the pixel input signal.

[0100] Reference Figure 1 , Figure 7 and Figure 8 , in the first period DU1B, the first node N1 and the second capacitor C2 may be initialized by the initialization signal GI. In the second period DU2B, the threshold voltage of the first transistor T1 may be compensated by the first write signal GW and the compensation signal GC, and the data voltage VDATA in which the threshold voltage of the first transistor T1 is compensated may be applied to the first node N1. In the third period DU3B, the anode of the light emitting element EE may be initialized by the light emitting element initialization signal GB. The fourth period DU4B may be a light emitting waiting period for waiting for the emission signal EM. In the fourth period DU4B, the inactive level of the first write signal GW and the inactive level of the second write signal GWC may be maintained, that is, the voltage levels of the first write signal GW and the second write signal GWC may be maintained at the inactive level. In the fifth period DU5B, the light emitting element EE may emit light in response to the emission signal EM, and the display panel 100 may display an image.

[0101] In the first period DU1B, the initialization signal GI may have an activation level. In an embodiment, for example, the activation level of the initialization signal GI may be a low level. When the initialization signal GI has an activation level, the fourth transistor T4 may be turned on so that the initialization voltage VINT may be applied to the first node N1.

[0102] In the second period DU2B, the first write signal GW and the compensation signal GC may have an activation level. In an embodiment, for example, the activation level of the first write signal GW and the activation level of the compensation signal GC may be a low level. When the first write signal GW and the compensation signal GC have an activation level, the second transistor T2 and the third transistor T3 may be turned on. In addition, the first transistor T1 may be turned on by the initialization voltage VINT.

[0103] In an embodiment of the invention, the control electrode of the second transistor T2 and the control electrode of the third transistor T3 may be connected to each other.

[0104] Although an embodiment in which the first write signal GW and the compensation signal GC have activation levels at substantially the same timing is described, the invention is not limited thereto. Alternatively, the activation period of the first write signal GW and the activation period of the compensation signal GC may partially overlap each other, but the first write signal GW and the compensation signal GC may have activation levels at different timings.

[0105] In the second period DU2B, the voltage of the first node N1 may have the sum of the data voltage VDATA and the threshold voltage of the first transistor T1 through the path of the turned-on first transistor T1 , second transistor T2 , and third transistor T3 .

[0106] In the third period DU3B, the light emitting element initialization signal GB may have an activation level. In an embodiment, for example, the activation level of the light emitting element initialization signal GB may be a low level. When the light emitting element initialization signal GB has an activation level, the seventh transistor T7 may be turned on so that the initialization voltage VINT may be applied to the anode of the light emitting element EE.

[0107] In the fourth period DU4B, the initialization signal GI, the first write signal GW, the compensation signal GC, the light emitting element initialization signal GB, and the second write signal GWC may have an inactive level. For example, the fourth period DU4B may be an emission waiting period.

[0108] In the fifth period DU5B, the emission signal EM may have an activation level. In an embodiment, for example, the activation level of the emission signal EM may be a low level. When the emission signal EM may have an activation level, the fifth transistor T5 and the sixth transistor T6 may be turned on. In the fifth period DU5B, the first transistor T1 may be turned on by the data voltage VDATA.

[0109] In the fifth period DU5B, the driving current may sequentially flow through the fifth transistor T5, the first transistor T1, and the sixth transistor T6, and may drive the light emitting element EE. The intensity of the driving current may be determined by the data voltage VDATA. The brightness of the light emitting element EE may be determined by the intensity of the driving current.

[0110] Fig. 9 is shown applied to Figure 7 Timing diagram of the pixel input signal.

[0111] Reference Figure 1 , Figure 7 and Fig. 9, an embodiment of the display panel 100 includes pixels 150, and each of the pixels 150 includes a light emitting element EE.

[0112] The pixel 150 receives the first write signal GW, the second write signal GWC, the compensation signal GC, the initialization signal GI, the light emitting element initialization signal GB and the emission signal EM, the light emitting element EE emits light with brightness corresponding to the level of the data voltage VDATA, and the display panel 100 displays an image.

[0113] In an embodiment, the activation period of the initialization signal GI applied to the control electrode of the fourth transistor T4 may have a different timing from the activation period of the first write signal GW applied to the control electrode of the second transistor T2 .

[0114] The activation period of the first write signal GW may be substantially the same as the activation period of the compensation signal GC applied to the control electrode of the third transistor T3 .

[0115] The activation period of the first write signal GW may be substantially the same as the activation period of the light emitting element initialization signal GB applied to the control electrode of the seventh transistor T7.

[0116] In an embodiment, Fig. 9 As shown in, in the first period DU1C, the first node N1 and the second capacitor C2 are initialized by the initialization signal GI. In the second period DU2C, the threshold voltage of the first transistor T1 is compensated by the first write signal GW and the compensation signal GC, and the data voltage VDATA in which the threshold voltage of the first transistor T1 is compensated is applied to the first node N1. In the second period DU2C, the anode of the light emitting element EE is initialized by the light emitting element initialization signal GB. The third period DU3C may be an emission waiting period. In the third period DU3C, the inactive level of the first write signal GW and the inactive level of the second write signal GWC may be maintained, that is, the voltage levels of the first write signal GW and the second write signal GWC may be maintained at the inactive level. In the fourth period DU4C, the light emitting element EE emits light in response to the emission signal EM, and the display panel 100 displays an image.

[0117] Fig.10 is shown applied to Figure 7 A timing diagram of the input signal of pixel 150.

[0118] Reference Figure 1 , Figure 7 and Fig.10, an embodiment of the display panel 100 includes pixels 150, and each of the pixels 150 includes a light emitting element EE. The pixel 150 receives a first write signal GW, a second write signal GWC, a compensation signal GC, an initialization signal GI, a light emitting element initialization signal GB, a data voltage VDATA, and an emission signal EM, and the light emitting element EE emits light having a brightness corresponding to a level of the data voltage VDTA, and the display panel 100 displays an image.

[0119] In an embodiment, the activation period of the initialization signal GI applied to the control electrode of the fourth transistor T4 may be different from (or may not overlap) the activation period of the first write signal GW applied to the control electrode of the second transistor T2 .

[0120] The activation period of the first write signal GW may be substantially the same as the activation period of the compensation signal GC applied to the control electrode of the third transistor T3 .

[0121] The activation period of the initialization signal GI may be substantially the same as the activation period of the light emitting element initialization signal GB applied to the control electrode of the seventh transistor T7.

[0122] In an embodiment, Fig.10 As shown in, in the first period DU1D, the first node N1 and the second capacitor C2 are initialized by the initialization signal GI. In the first period DU1D, the anode of the light emitting element EE is initialized by the light emitting element initialization signal GB. In the second period DU2D, the threshold voltage of the first transistor T1 is compensated by the first write signal GW and the compensation signal GC, and the data voltage VDATA in which the threshold voltage of the first transistor T1 is compensated is applied to the first node N1. The third period DU3D may be a period for waiting for the emission signal. In the third period DU3D, the inactive level of the first write signal GW and the inactive level of the second write signal GWC may be maintained. In the fourth period DU4D, the light emitting element EE may emit light in response to the emission signal EM. In the fourth period DU4D, the display panel 100 displays an image.

[0123] Fig.11 is a block diagram showing an electronic device 1000 according to an embodiment of the invention. Fig.12 It is shown Fig.11 The electronic device 1000 is implemented as an example of a smart phone.

[0124] Reference Fig.11 and Fig.12, an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0125] According to an embodiment, Fig.12 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0126] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0127] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 A drive controller 200 is provided.

[0128] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0129] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include an input device (such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc.) and an output device (such as a printer, a speaker, etc.). In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0130] In the pixel and the display device according to the embodiment of the invention, even when leakage current flows through the data writing transistor, the off state of the driving transistor can be maintained, so that the brightness control of the pixel is enhanced and the display quality of the display panel is enhanced.

[0131] The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0132] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A pixel, comprising: Light emitting element; A driving transistor for applying a driving current to the light emitting element; a data writing transistor that applies a data voltage in response to a first writing signal and is connected to the first electrode of the driving transistor; as well as A leakage current compensator is connected to the second electrode of the driving transistor, wherein the leakage current compensator operates in response to a second write signal different from the first write signal in such a manner that an off state of the driving transistor is maintained in an emission waiting period.

2. The pixel according to claim 1, wherein: The leakage current compensator includes an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the second electrode of the driving transistor.

3. The pixel according to claim 1, wherein: The voltage level of the second write signal is maintained at an inactive level during a frame period.

4. The pixel according to claim 1, wherein: The pixel further includes a storage capacitor, wherein the storage capacitor comprises a first electrode receiving a first power supply voltage and a second electrode connected to a control electrode of the driving transistor, and Wherein, the second write signal is the first power supply voltage.

5. The pixel according to claim 1, wherein: The leakage current compensator includes an eighth transistor and a first capacitor, The eighth transistor includes a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the fifth node, and The first capacitor includes a first electrode connected to the fifth node and a second electrode connected to the second electrode of the driving transistor.

6. The pixel according to claim 5, wherein: The voltage level of the second write signal is maintained at an inactive level during a frame period.

7. The pixel according to claim 1, wherein: The emission waiting period is after a writing period in which the first writing signal has an active level, and The first write signal and the second write signal have an inactive level in the emission waiting period.

8. The pixel according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode receiving the first write signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving the first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving a transmission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving the transmission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a seventh transistor including a control electrode receiving the first write signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the first node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage, wherein the driving transistor is the first transistor, wherein the data writing transistor is the second transistor, Wherein, the leakage current compensator includes the eighth transistor, and The voltage level of the second write signal is maintained at an inactive level during a frame period.

9. The pixel according to claim 8, wherein: The frame period of the pixel includes: an initialization period in which the emission signal has an inactive level, the initialization signal has an active level, the first write signal has an inactive level, and the second write signal has an inactive level; a writing period in which the emission signal has an inactive level, the initialization signal has an inactive level, the first writing signal has an active level, and the second writing signal has an inactive level; the emission waiting period, in which the emission signal has an inactive level, the initialization signal has an inactive level, the first write signal has an inactive level, and the second write signal has an inactive level; and An emission period in which the emission signal has an active level, the initialization signal has an inactive level, the first write signal has an inactive level, and the second write signal has an inactive level.

10. The pixel according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode receiving the first write signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving the first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving a transmission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving the transmission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a seventh transistor including a control electrode receiving the first write signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to a fifth node; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node; a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the first node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage, wherein the driving transistor is the first transistor, wherein the data writing transistor is the second transistor, Wherein, the leakage current compensator includes the eighth transistor and the first capacitor, and The voltage level of the second write signal is maintained at an inactive level during a frame period.

11. The pixel according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode receiving the first write signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving the first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving a transmission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving the transmission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a seventh transistor including a control electrode receiving the first write signal, a first electrode receiving a second initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the first node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage, wherein the driving transistor is the first transistor, wherein the data writing transistor is the second transistor, Wherein, the leakage current compensator includes the eighth transistor, and The voltage level of the second write signal is maintained at an inactive level during a frame period.

12. The pixel according to claim 1, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode receiving the first write signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a compensation signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving a transmission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving the transmission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; A seventh transistor includes a control electrode receiving an initialization signal of the light emitting element, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the first node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage, wherein the driving transistor is the first transistor, wherein the data writing transistor is the second transistor, Wherein, the leakage current compensator includes the eighth transistor, and The voltage level of the second write signal is maintained at an inactive level during a frame period.

13. A display device, comprising: Display panel, including pixels; A gate driver for applying a gate signal to the pixel; a data driver for applying a data voltage to the pixel; as well as an emission driver, applying an emission signal to the pixel, The pixel includes: a light-emitting element; a driving transistor that applies a driving current to the light-emitting element; a data write transistor that applies the data voltage in response to a first write signal and is connected to a first electrode of the driving transistor; and a leakage current compensator that is connected to a second electrode of the driving transistor, and wherein the leakage current compensator operates in response to a second write signal different from the first write signal in such a way that the cut-off state of the driving transistor is maintained during an emission waiting period.

14. The display device according to claim 13, wherein: The leakage current compensator includes an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the second electrode of the driving transistor.

15. The display device according to claim 13, wherein: The voltage level of the second write signal is maintained at an inactive level during a frame period.

16. The display device according to claim 13, wherein: The pixel further includes a storage capacitor, wherein the storage capacitor comprises a first electrode receiving a first power supply voltage and a second electrode connected to a control electrode of the driving transistor, and Wherein, the second write signal is the first power supply voltage.

17. The display device according to claim 13, wherein: The leakage current compensator includes an eighth transistor and a first capacitor, The eighth transistor includes a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the fifth node, and The first capacitor includes a first electrode connected to the fifth node and a second electrode connected to the second electrode of the driving transistor.

18. The display device according to claim 17, wherein: The voltage level of the second write signal is maintained at an inactive level during a frame period.

19. The display device according to claim 13, wherein: The emission waiting period is after a writing period in which the first writing signal has an active level, and The first write signal and the second write signal have an inactive level in the emission waiting period.

20. The display device according to claim 13, wherein: The pixels include: a first transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode receiving the first write signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving the first write signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a control electrode receiving the emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor including a control electrode receiving the transmission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a seventh transistor including a control electrode receiving the first write signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode receiving the second write signal, a first electrode receiving the data voltage, and a second electrode connected to the third node; a second capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the first node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage, wherein the driving transistor is the first transistor, wherein the data writing transistor is the second transistor, Wherein, the leakage current compensator includes the eighth transistor, and The voltage level of the second write signal is maintained at an inactive level during a frame period.

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