Semiconductor device having electrical via member

Abstract

According to some embodiments, there is provided a semiconductor device including: a first semiconductor chip including a first via and a first front pad electrically connected to the first via; and a second semiconductor chip disposed under the first semiconductor chip, a semiconductor device includes a substrate, a circuit layer disposed under the substrate, a second front pad under the circuit layer, a back pad disposed on the substrate and electrically connected to a corresponding first front pad, a second via penetrating the substrate and electrically connected to the second front pad, and a back redistribution layer electrically connecting the second via and the back pad, at least one of the rear pads is spaced apart from a corresponding one of the second vias in a horizontal direction and overlaps a corresponding one of the first vias in a vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0098680 filed on July 28, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices having electrical vias. Background Art

[0004] With the recent miniaturization and realization of high performance of electronic devices, three-dimensional semiconductor devices having a plurality of semiconductor chips stacked vertically have been developed using through silicon vias (TSVs).

[0005] When constructing a three-dimensional semiconductor device by stacking heterogeneous chips, there may be design limitations in vertically aligning a TSV region of each heterogeneous chip. Summary of the invention

[0006] Some aspects of the present disclosure provide a semiconductor device having improved design freedom for a TSV region.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor chip, comprising a first through-hole member and a first front pad electrically connected to the first through-hole member; and a second semiconductor chip, which is arranged below the first semiconductor chip and comprises a substrate, a circuit layer arranged below the substrate, a second front pad below the circuit layer, a rear pad arranged on the substrate and electrically connected to the corresponding first front pad, a second through-hole member penetrating the substrate and electrically connected to the second front pad, and a rear redistribution layer for electrically connecting the second through-hole member and the rear pad, wherein at least one of the rear pads is spaced apart from a corresponding one of the second through-hole members in the horizontal direction and overlaps with a corresponding one of the first through-hole members in the vertical direction (at least partially aligned in the vertical direction).

[0008] In addition, according to another aspect of the present disclosure, a semiconductor device is provided, including: a first semiconductor chip, which includes a first through-hole member arranged in a first TSV region and a first front pad electrically connected to the first through-hole member; and a second semiconductor chip, which is disposed below the first semiconductor chip and includes a second through-hole member arranged in the second TSV region, a rear pad electrically connected to the front pad, and a rear redistribution layer for electrically connecting the second through-hole member and the rear pad, wherein at least a portion of the first TSV region deviates from the second TSV region in a horizontal direction.

[0009] In addition, according to another aspect of the present disclosure, a semiconductor device is provided, comprising: one or more semiconductor chips, which include a first power through-hole member; and a base chip, which is arranged below the one or more semiconductor chips and includes a second power through-hole member and a rear redistribution layer for electrically connecting the second power through-hole member to the first power through-hole member, wherein the first power through-hole member includes a first sub-through-hole member vertically overlapping with the second power through-hole member and a second sub-through-hole member spaced apart from the second power through-hole member in a horizontal direction.

[0010] In addition, according to another aspect of the present disclosure, a semiconductor device is provided, including: at least one semiconductor chip, which includes a first through-hole member; a base chip, which is arranged under the at least one semiconductor chip and includes a second through-hole member; and a plurality of bumps, which are arranged between the base chip and the at least one semiconductor chip and are configured to electrically connect the first through-hole member and the second through-hole member, wherein the first through-hole member includes a first sub-through-hole member arranged in a first sub-TSV region and a second sub-through-hole member arranged in a second sub-TSV region, and a separation distance between the first sub-TSV region and the second sub-TSV region is greater than a gap between adjacent first sub-through-hole members and a gap between adjacent second sub-through-hole members.

[0011] In addition, according to another aspect of the present disclosure, a semiconductor device is provided, including: a substrate; a first power supply through-hole member and a second power supply through-hole member, which penetrate the substrate; and a first power supply region and a second power supply region, wherein the first power supply through-hole member is arranged in the first power supply region and the second power supply through-hole member is arranged in the second power supply region, wherein a separation distance between the first power supply region and the second power supply region is greater than a gap between mutually adjacent first power supply through-hole members and a gap between mutually adjacent second power supply through-hole members.

[0012] According to some embodiments of the present disclosure, a post-redistribution structure for redistributing TSVs may be introduced, thereby providing a semiconductor device having improved design freedom for a TSV region.

[0013] The advantages and effects of the present application are not limited to the foregoing and may be more easily understood in the course of describing an example of an embodiment of the present disclosure, as described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0015] Figure 1A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 1B yes Figure 1AA partial enlarged view of area 'A'.

[0017] Figure 1C It is shown Figure 1A A perspective view of the connection relationship between some semiconductor chips.

[0018] FIG. 2A to FIG. 2D is a plan view of an example of a TSV region.

[0019] Figure 3A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 3B yes Figure 3A A partial enlarged view of area 'B'.

[0021] Figure 4A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 4B yes Figure 4A A partial enlarged view of area 'C'.

[0023] Figure 5A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 5B yes Figure 5A A partial enlarged view of area 'D'.

[0025] Fig. 6A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0026] Figure 6B It is shown Fig. 6A A perspective view of the connection relationship between some semiconductor chips.

[0027] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0028] Fig. 8A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0029] Figure 8B yes Fig. 8A A partial enlarged view of area 'G'.

[0030] Fig. 9A is a plan view of an example of a semiconductor package in which a semiconductor device according to some embodiments of the present disclosure is mounted.

[0031] Fig. 9B is along Fig. 9A A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Unless otherwise specified,

[0033] In the present specification, it is understood that expressions such as "on", "above", "upper", "under", "lower", "lower" and "side" relate to orientation based on the drawings and may actually vary depending on the direction in which components are arranged.

[0034] In order to distinguish various elements, steps and directions from each other, ordinal numbers such as “first”, “second”, “third”, etc. may be used as marks such as specific elements, steps and directions, and terms not described using “first”, “second”, etc. in the specification may still be referred to as “first” or “second” in the claims. In addition, a term referred to as a specific ordinal number (for example, “first” in some claims) may be described as a different ordinal number elsewhere (for example, “second” in the specification or other claims).

[0035] Figure 1A is a cross-sectional view of a semiconductor device 1000A according to some embodiments of the present disclosure, Figure 1B yes Figure 1A A partial enlarged view of area 'A', and Figure 1C It is shown Figure 1A A perspective view of the connection relationship between some semiconductor chips.

[0036] refer to Figure 1A , Figure 1B and Figure 1C , the semiconductor device 1000A of some embodiments may include a first semiconductor chip C1 and a second semiconductor chip C2 (hereinafter referred to as a "base chip"). According to some embodiments of the present disclosure, the first semiconductor chip C1 may be sequentially stacked on the second semiconductor chip C2, or may be provided in the form of a plurality of first semiconductor chips arranged in parallel. The first semiconductor chip C1 and the second semiconductor chip C2 are shown to have substantially the same size (width and area), but according to some embodiments of the present disclosure, the first semiconductor chip C1 and the second semiconductor chip C2 may have different sizes.

[0037] According to some embodiments, the second semiconductor chip C2 may include a rear redistribution structure 240 for redistributing the second via 230. Even when the horizontal / lateral position of the second via 230 is different from the horizontal / lateral positions of the first via 130 and the first front pad 104 of the first semiconductor chip C1, the rear redistribution structure 240 may redistribute electricity (e.g., signal) from the second via 230 to the first via 130 and / or the first front pad 104, so that the first semiconductor chip C1 may be designed without limitation on the TSV area.

[0038] For example, the first semiconductor chip C1 may include a first TSV region R1 in which a first via member 130 is arranged, and the second semiconductor chip C2 may include a second TSV region R2 in which a second via member 230 is arranged. In this case, at least a portion of the first TSV region R1 may be offset from the second TSV region R2 in a horizontal direction (e.g., an X direction). The rear pad 205 of the second semiconductor chip C2 may be formed to be aligned with the first via member 130 of the first semiconductor chip C1, and the rear redistribution layer 245 of the rear redistribution structure 240 may electrically connect the second via member 230 to the rear pad 205 of the second semiconductor chip C2.

[0039] The semiconductor device 1000A may further include an uppermost semiconductor chip CT. According to some embodiments of the present disclosure, two or more semiconductor chips may be stacked between the uppermost semiconductor chip CT and the base chip C2 (see FIG. 6A to FIG. 8B Although the uppermost semiconductor chip CT is illustrated as not including a via member, in some embodiments, the uppermost semiconductor chip CT may also include a via member penetrating the semiconductor substrate 410 .

[0040] The first semiconductor chip C1, the second semiconductor chip C2, and the top semiconductor chip CT may be IC chips formed with integrated circuits. The first semiconductor chip C1 and the second semiconductor chip C2 may be semiconductor chips of different types. The first semiconductor chip C1, the second semiconductor chip C2, and the top semiconductor chip CT may include, for example, logic chips (such as central processing units (CPUs), graphic processing units (GPUs), image processing units (ISPs), field programmable gate arrays (FPGAs), digital signal processors, encryption processors, microprocessors, microcontrollers, analog-to-digital converters, and application-specific ICs (ASICs)) or memory chips (including volatile memories (such as dynamic RAMs (DRAMs) and static RAMs (SRAMs)) and nonvolatile memories (such as phase change RAMs (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), and flash memories)).

[0041] Hereinafter, components of each of the first semiconductor chip C1 , the second semiconductor chip C2 , and the uppermost semiconductor chip CT will be described.

[0042] The first semiconductor chip C1 may include a first substrate 110, a first circuit layer 120, and a first via member 130. In addition, the first semiconductor chip C1 may include a first front pad 104 and a first rear pad 105.

[0043] The first substrate 110 may be a semiconductor wafer. The first substrate 110 may include, for example, semiconductor elements such as silicon and germanium or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first substrate 110 may include a conductive region 112 and an isolation region 113 formed on one surface thereof. The conductive region 112 may be, for example, a well doped with impurities or a structure doped with impurities. The isolation region 113 may be a device isolation structure having a shallow trench isolation (STI) structure, and may include silicon oxide.

[0044] The individual element ID may be electrically connected to the conductive region 112 of the first substrate 110. The individual element ID may include, for example, a FET (such as a planar FET or a FinFET), a memory device (such as a flash memory, a DRAM, a SRAM, an EEPROM, a PRAM, an MRAM, a FeRAM, and a RRAM), a logic device (such as AND, OR, and NOT), and various devices and / or passive devices (such as a system LSI, a CIS, and a MEMS). The individual element ID may include a gate structure 115. The gate structure 115 may include a gate insulating layer GI, a gate electrode GE disposed on the gate insulating layer GI, and a gate spacer GS surrounding the gate insulating layer GI and the gate electrode GE. The gate insulating layer GI may include silicon oxide or silicon nitride. The gate electrode GE may include a semiconductor material and a metal material. The gate spacer GS may be formed by a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof.

[0045] The first circuit layer 120 may be disposed on a surface of the first substrate 110 where the conductive region 112 is formed. The first circuit layer 120 may include an interlayer insulating layer 121 and a wiring structure 125. The interlayer insulating layer 121 may be formed to cover the individual element ID and the wiring structure 125, and may electrically separate the individual element ID disposed on the first substrate 110. The interlayer insulating layer 121 may be formed of a flowable oxide (FOX), Tonen Si laZen (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl (PETEOS), fluoride silicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer 121 surrounding the wiring structure 125 may be formed of a low dielectric layer. The interlayer insulating layer 121 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process.

[0046] The wiring structure 125 may be formed as a multilayer structure including a plurality of wiring patterns and a plurality of vias, and may be formed of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring pattern or / and the via and the interlayer insulating layer 121. The wiring structure 125 may be electrically connected to a separate element ID through an interconnector 123 (e.g., a contact plug).

[0047] The first via 130 may penetrate the first substrate 110 and may be electrically connected to the first front pad 104 and the first rear pad 105. The first via 130 may include at least one of a signal via, a power via, and a ground via electrically connected to the wiring structure 125. The first front pad 104 may be disposed under the first circuit layer 120.

[0048] The first through-hole member 130 may include a hole plug 135 and a side barrier film 131 surrounding the side surface of the hole plug 135. The hole plug 135 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by an electroplating process, a PVD process, or a CVD process. The side barrier film 131 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by an electroplating process, a PVD process, or a CVD process. A side insulating film including an insulating material (e.g., a high aspect ratio process (HARP) oxide) such as silicon oxide, silicon nitride, or silicon oxynitride may be formed between the side barrier film 131 and the first substrate 110. The first front pad 104 and the first rear pad 105 may include at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0049] The second semiconductor chip C2 may be disposed below the first semiconductor chip C1. The second semiconductor chip C2 may be arranged in a direction in which the second rear pad 205 faces the first front pad 104. The second semiconductor chip C2 may include a second substrate 210, a second circuit layer 220, and a second via member 230. Since the second substrate 210, the second circuit layer 220, and the second via member 230 have the same or similar features as those of the first substrate 110, the first circuit layer 120, and the first via member 130 described above, repeated description thereof is omitted.

[0050] The second semiconductor chip C2 may include a post redistribution structure 240 for redistributing the second via member 230 and connecting the second via member 230 to the first via member 130 of the first semiconductor chip C1. The post redistribution structure 240 may include a dielectric layer 241 and a post redistribution layer 245. The dielectric layer 241 may include silicon oxide, silicon nitride, or a combination thereof. The dielectric layer 241 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process.

[0051] The rear redistribution layer 245 may be formed as a multilayer structure including a plurality of wiring patterns and a plurality of vias, and may be formed of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the rear redistribution layer 245 and the dielectric layer 241. The rear redistribution layer 245 may extend in a horizontal direction and electrically connect the second via 230 and the second rear pad 205.

[0052] The second rear pads 205 may be aligned with the first vias 130 or the first front pads 104 in the vertical direction. For example, at least one of the second rear pads 205' may be spaced apart from a corresponding one of the second vias 230' in the horizontal direction (e.g., X direction), and may overlap (extend at least partially above / below) a corresponding one of the first vias 130' in the vertical direction (e.g., Z direction). One of the first front pads 104' in the first front pads 104 may overlap (extend at least partially above / below) a corresponding one of the first vias 130' in the vertical direction (Z direction). One of the first front pads 104' in the first front pads 104 may be aligned with a corresponding one of the second rear pads 205' in the vertical direction (Z direction). One of the first through-hole members 130 ′ and one of the second through-hole members 230 ′ corresponding to each other may not overlap each other in the vertical direction (Z direction).

[0053] The second semiconductor chip C2 may be the bottommost semiconductor chip in the stacked chip. A plurality of connection bumps CBP may be disposed below the second semiconductor chip C2. A plurality of connection bumps CBP may be electrically connected to the second front pad 204. A plurality of connection bumps CBP may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and / or alloys thereof. According to some embodiments of the present disclosure, a plurality of connection bumps CBP may have a combination of a metal column and a solder ball.

[0054] The top semiconductor chip CT may be disposed on the first semiconductor chip C1. The top semiconductor chip CT may be disposed on the topmost portion of the stacked chip. The top semiconductor chip CT may include a semiconductor substrate 410 and an integrated circuit layer 420. The front pad 404 may be disposed below the integrated circuit layer 420. Since the semiconductor substrate 410 and the integrated circuit layer 420 have the same or similar features as the above-mentioned first substrate 110 and the first circuit layer 120, their repeated description will be omitted. The top semiconductor chip CT may not include a through-hole member. In this case, the upper surface of the semiconductor substrate 410 may be covered with an insulating film formed by a silicon oxide film, a silicon nitride film, a polymer or a combination thereof. According to some embodiments of the present disclosure, the top semiconductor chip CT may also include a through-hole member penetrating the semiconductor substrate 410. For example, the top semiconductor chip CT may include a pixel array and a through-hole member connected to the pixel array by a plurality of row lines and a plurality of column lines.

[0055] In addition, the semiconductor device 1000A further includes a bump BP and an insulating film layer IF, which are disposed between the first semiconductor chip C1, the second semiconductor chip C2, and the uppermost semiconductor chip CT. The bump BP may be disposed between the front pads 104 and 404 and the rear pads 105 and 205. The bump BP may electrically connect the first through-hole member 130 and the second through-hole member 230.

[0056] The bump BP may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and / or alloys thereof, and according to some embodiments, the bump BP may have a form in which a metal column and a solder ball are combined. The insulating film layer IF may surround the bump BP and fix the semiconductor chips C1, C2 and CT. The insulating film layer IF may be a non-conductive film (NCF), but the present disclosure is not limited thereto, and for example, the insulating film layer IF may be formed of all types of insulating films capable of thermal compression processing.

[0057] like Figure 1C As shown, the first semiconductor chip C1 may include a first IC region IC1 and a first TSV region R1. The second semiconductor chip C2 may include a second IC region IC2 and a second TSV region R2.

[0058] Units or circuits constituting the above-mentioned logic chip or memory chip may be formed in the first IC region IC1 and the second IC region IC2. In the first TSV region R1, the first vias 130 may be disposed vertically and horizontally adjacent to each other. In the second TSV region R2, the second vias 230 may be disposed vertically and horizontally adjacent to each other.

[0059] In some embodiments, the first TSV region R1 may include two or more sub-TSV regions R1a and R1b spaced apart from each other. The first TSV region R1 may include a first sub-TSV region R1a and a second sub-TSV region R1b, each of which extends in one direction (e.g., the Y direction). On a plane, the first sub-TSV region R1a may be adjacent to a first side of the first semiconductor chip C1, and the second sub-TSV region R1b may be adjacent to a second side of the first semiconductor chip C1. The first IC region IC1 may be disposed between the first sub-TSV region R1a and the second sub-TSV region R1b.

[0060] The first via member 130 may include a first sub-via member 130a disposed in the first sub-TSV region R1a and a second sub-via member 130b disposed in the second sub-TSV region R1b. A separation distance D between the first sub-TSV region R1a and the second sub-TSV region R1b may be greater than a distance d1 between the first sub-via members 130a adjacent to each other and a distance d2 between the second sub-via members 130b adjacent to each other.

[0061] However, the shapes of the first and second TSV regions R1 and R2 may be changed to be different from those of the first and second semiconductor chips C1 and C2 according to the designs of the first and second semiconductor chips C1 and C2. Figure 1C For example, the first sub-TSV region R1a or the second sub-TSV region R1b may overlap with the second TSV region R2 (see Figure 3A and Figure 3B ).

[0062] Below, we will refer to FIG. 2A to FIG. 2D A modification example applicable to the TSV region R of the semiconductor chips C1 , C2 , and CT is described.

[0063] FIG. 2A to FIG. 2D is a plan view of a modified example of the TSV region R.

[0064] refer to Figure 2A In a modified example, the TSV region R may be provided only on one side of the IC region IC. The TSV region R may extend along the side surface of the semiconductor chip CP in a first direction (eg, a Y direction).

[0065] refer to Figure 2B In a modified example, the TSV region R may be disposed on both sides of the IC region IC. The TSV region R may include sub-TSV regions Ra, Rb, and Rc spaced apart from each other. The first sub-TSV region Ra may extend from the central portion of the semiconductor chip CP in a first direction (e.g., the Y direction). The second sub-TSV region Rb may be spaced apart from the first sub-TSV region Ra in a second direction (e.g., the X direction), and may be disposed adjacent to the first edge S1 of the semiconductor chip CP. The third sub-TSV region Rc may be spaced apart from the first sub-TSV region Ra in a second direction (e.g., the X direction), and may be disposed adjacent to the second edge S2 of the semiconductor chip CP. The third sub-TSV region Rc may be disposed opposite to the second sub-TSV region Rb.

[0066] refer to Figure 2CIn the modified example, the TSV region R may be arranged to surround the IC region IC. The TSV region R may include sub-TSV regions Ra, Rb, Rc, and Rd adjacent to respective edges of the semiconductor chip CP. For example, the TSV region R includes a first sub-TSV region Ra, a second sub-TSV region Rb, a third sub-TSV region Rc, and a fourth sub-TSV region Rd, which are respectively arranged adjacent to four surfaces of the IC region IC.

[0067] refer to Figure 2D In the modified example, the TSV region R may be disposed between the respective IC regions IC. The TSV region R may extend from a central portion of the semiconductor chip CP in a first direction (eg, a Y direction) and a second direction (eg, an X direction).

[0068] As mentioned above, Figure 1C The first TSV region R1 and the second TSV region R2 shown may be defined in various shapes and are not limited to Figure 1C and 2A to Figure 2D Shape shown.

[0069] Figure 3A is a cross-sectional view of a semiconductor device 1000B according to some embodiments of the present disclosure, and Figure 3B yes Figure 3A A partial enlarged view of area 'B'.

[0070] refer to Figure 3A and Figure 3B , some embodiments of the semiconductor device 1000B may have the same Figures 1A to 2D The features described are the same or similar features except that the semiconductor device 1000B includes a first sub via member 130 a and a second sub via member 130 b .

[0071] According to some embodiments, the first via member 130 may be arranged regardless of the arrangement of the second via member 230 disposed below the first via member 130. For example, the first via member 130 may include a first sub-via member 130a and a second sub-via member 130b. The first sub-via member 130a may overlap with the second via member 230 in the vertical direction (Z direction) (at least partially aligned with the second via member 230). The second sub-via member 130b may not overlap with the second via member 230 in the vertical direction (Z direction). At least some of the second via members 230 may be electrically redistributed to the second sub-via member 130b through the rear redistribution layer 245.

[0072] In this manner, the second via members 230 may be redistributed by the post-redistribution structure 240 of the second semiconductor chip C2 , thereby designing the semiconductor device 1000B.

[0073] Figure 4A is a cross-sectional view of a semiconductor device 1000C according to some embodiments of the present disclosure, and Figure 4B yes Figure 4A A partial enlarged view of area 'C'.

[0074] refer to Figure 4A and Figure 4B , some embodiments of the semiconductor device 1000C may have the same Figures 1A to 3B The semiconductor device 1000C may include dummy structures 104D, 205D, and DBP. The first semiconductor chip C1 may include a first dummy pad 104D adjacent to the first front pad 104. The second semiconductor chip C2 may include a second dummy pad 205D adjacent to the second rear pad 205. The first dummy pad 104D and the second dummy pad 205D may be connected via a dummy bump DBP. According to some embodiments, the first dummy pad 104D and the second dummy pad 205D may contact each other without a bump (see Figure 5A and Figure 5B The first dummy pad 104D and the second dummy pad 205D may be electrically insulated from the first via member 130 and the second via member 230. According to some embodiments, the first semiconductor chip C1 and / or the second semiconductor chip C2 may further include a dummy via member connected to the first dummy pad 104D and the second dummy pad 205D.

[0075] Figure 5A is a cross-sectional view of a semiconductor device 1000D according to some embodiments of the present disclosure, and Figure 5B yes Figure 5A A partial enlarged view of area 'D'.

[0076] refer to Figure 5A and Figure 5B , some embodiments of the semiconductor device 1000D may have the same Figure 4B The features described are the same or similar features, except that multiple semiconductor chips C1, C2 and CT are directly connected and coupled to each other without separate connecting members (e.g., metal pillars, solder bumps, adhesive films, etc.) (a construction that may be referred to as, for example, hybrid bonding and direct bonding).

[0077] The first semiconductor chip C1 may include a front insulating layer 104L surrounding the first front pad 104 and a rear insulating layer 105L surrounding the rear pad 105. The second semiconductor chip C2 may include a rear insulating layer 205L surrounding the rear pad 205. The uppermost semiconductor chip CT may include a front insulating layer 404L surrounding the front pad 404. The front insulating layers 104L and 404L and the rear insulating layers 105L and 205L may be respectively referred to as a first insulating layer, a second insulating layer, a third insulating layer, etc.

[0078] The front insulating layers 104L and 404L and the rear insulating layers 105L and 205L may include at least one of materials that can be bonded and coupled to each other (e.g., silicon oxide (SiO) and silicon carbonitride (SiCN)). The front pads 104 and 404 and the rear pads 105 and 205 adjacent to each other may include materials that can be bonded and coupled to each other, for example, one of copper (Cu), nickel (Ni), gold (Au) and silver (Ag) or an alloy thereof. A bonding surface BS formed by metal bonding of the front pads 104 and 404 with the rear pads 105 and 205 and dielectric bonding of the front insulating layers 104L and 404L with the rear insulating layers 105L and 205L may be formed between the plurality of semiconductor chips C1, C2 and CT.

[0079] Fig. 6A is a cross-sectional view of a semiconductor device 1000E according to some embodiments of the present disclosure, and Figure 6B It is shown Fig. 6A A perspective view of the connection relationship of some semiconductor chips.

[0080] refer to Fig. 6A and Figure 6B , some embodiments of the semiconductor device 1000E may have the same Figures 1A to 5B The features described are the same or similar features except that the semiconductor device 1000E further includes a third semiconductor chip C3 between the first semiconductor chip C1 and the uppermost semiconductor chip CT.

[0081] The third semiconductor chip C3 may include a third substrate 310, a third circuit layer 320, and a third through-hole member 330. In addition, the third semiconductor chip C3 may include a third front pad 304 and a third rear pad 305. Since the sub-elements of the third semiconductor chip C3 have the same or similar features as those of the sub-elements of the first semiconductor chip C1 described above, repeated description thereof will be omitted.

[0082] The first semiconductor chip C1 may include a post redistribution structure 140 for redistributing the first vias 130 and connecting the first vias 130 to the third vias 330 of the third semiconductor chip C3. The post redistribution structure 140 may have the same or similar features as the post redistribution structure 240 of the second semiconductor chip C2 described above.

[0083] The first rear pads 105 may be aligned in the vertical direction with the third vias 330 or the third front pads 304. For example, at least one of the first rear pads 105' may be spaced apart from a corresponding one of the first vias 130' in the horizontal direction (e.g., X direction), and may overlap with a corresponding one of the third vias 330' in the vertical direction (e.g., Z direction). One of the first vias 130' and one of the third vias 330' that correspond to each other may not overlap each other in the vertical direction (Z direction).

[0084] like Figure 6B As shown, the first semiconductor chip C1 may include a first IC region IC1 and a first TSV region R1. The second semiconductor chip C2 may include a second IC region IC2 and a second TSV region R2. The third semiconductor chip C3 may include a third IC region IC3 and a third TSV region R3.

[0085] Units or circuits constituting the above-mentioned logic chip or memory chip may be formed in the first IC region IC1, the second IC region IC2, and the third IC region IC3. In the first TSV region R1, the first through-hole member 130 may be disposed vertically and horizontally adjacent to each other. In the second TSV region R2, the second through-hole member 230 may be disposed vertically and horizontally adjacent to each other. In the third TSV region R3, the third through-hole member 330 may be disposed vertically and horizontally adjacent to each other.

[0086] In some embodiments, the first TSV region R1, the second TSV region R2, and the third TSV region R3 may be offset in the horizontal direction (e.g., the X direction). The offset distance of the first TSV region R1, the second TSV region R2, and the third TSV region R3 may be greater than the gap between the first via members 130 adjacent to each other, the gap between the second via members 230 adjacent to each other, and the gap between the third via members 330 adjacent to each other.

[0087] However, the shapes of the first TSV region R1, the second TSV region R2, and the third TSV region R3 may be changed to be different from the shapes of the first IC region IC1, the second IC region IC2, and the third IC region IC3 according to the design of the first IC region IC1, the second IC region IC2, and the third IC region IC3. Figure 6B Various shapes of the shapes shown.

[0088] Figure 7 is a cross-sectional view of a semiconductor device 1000F according to some embodiments of the present disclosure.

[0089] refer to Figure 7 , some embodiments of the semiconductor device 1000F may have the same Figures 1A to 6B The features described are the same or similar features except that the semiconductor device 1000F includes a plurality of first semiconductor chips C1 and a sealing layer 450 .

[0090] A plurality of first semiconductor chips C1 may be sequentially stacked on the second semiconductor chip C2. The second semiconductor chip C2 may be a buffer chip including a plurality of logic elements and / or memory elements in the circuit layer 220. Therefore, the second semiconductor chip C2 may transmit signals from the respective first semiconductor chips C1 stacked on the upper portion and the uppermost semiconductor chip CT to the outside, and may also transmit signals and power from the outside to the respective first semiconductor chips C1 and the uppermost semiconductor chip CT. The second semiconductor chip C2 may perform logic functions and memory functions through logic elements and memory elements, but according to some embodiments, the second semiconductor chip C2 may perform only logic functions by including only logic elements. The width of the second semiconductor chip C2 may be greater than the width of the first semiconductor chip C1 and the uppermost semiconductor chip CT.

[0091] The plurality of first semiconductor chips C1 and the topmost semiconductor chip CT may be IC chips of the same type. The plurality of first semiconductor chips C1 may all have the same arrangement of the first through-hole members 130. The first through-hole member 130 of each of the plurality of first semiconductor chips C1 may be aligned with the corresponding through-hole member in the vertical direction (Z direction). The plurality of first semiconductor chips C1 and the topmost semiconductor chip CT may be composed of memory chips or memory elements to store or output data based on address commands and control commands received from the second semiconductor chip C2. For example, the plurality of first semiconductor chips C1 and the topmost semiconductor chip CT may include volatile memory elements (such as DRAM or SRAM) or non-volatile memory elements (such as flash memory, PRAM, MRAM, FeRAM or RRAM).

[0092] The uppermost semiconductor chip CT does not include a through-hole member, and its upper surface may be exposed from the sealing layer 450, but the present disclosure is not limited thereto. For example, the sealing layer 450 may be formed of an insulating material such as epoxy mold compound (EMC), but the present disclosure is not particularly limited thereto.

[0093] Fig. 8A is a cross-sectional view of a semiconductor device 1000G according to some embodiments of the present disclosure, and Figure 8Byes Fig. 8A A partial enlarged view of area 'E'.

[0094] refer to Fig. 8A and Figure 8B , some embodiments of the semiconductor device 1000G may have the same Figures 1A to 7 The features described are the same or similar features, except for the arrangement of the power supply vias 130P and 230P. The first via 130 and the second via 230 may include at least one of a power supply via and a ground via. Hereinafter, 'power supply via' may be referred to as 'power supply via', which may represent at least one of a power supply via and a ground via.

[0095] In some embodiments, the first via 130 may include a first power via 130P, and the second via 230 may include a second power via 230P. The first power via 130P and the second power via 230P may be electrically connected through the rear redistribution layer 245. The first power via 130P may include a first sub-via 130a and a second sub-via 130b. The first sub-via 130a may overlap with the second power via 230P in the vertical direction (at least partially aligned with the second power via 230P). The second sub-via 130b may not overlap with the second power via 230P. The second power via 230P may be electrically connected to the first sub-via 130a and the second sub-via 130b through the rear redistribution layer 245. The second rear pad 205 may be aligned with the first sub-via 130a and the second sub-via 130b in the vertical direction.

[0096] The first semiconductor chip C1 of some embodiments may include a first power supply region and a second power supply region, wherein a first sub-via member 130a (which may be referred to as a 'first power supply via member') is disposed in the first power supply region, and a second sub-via member 130b (which may be referred to as a 'second power supply via member') is disposed in the second power supply region. Here, the first power supply region and the second power supply region may be understood as Figure 2B The sub-TSV regions Ra, Rb, and Rc shown in are similarly arranged.

[0097] The number of the first vias 130 may be greater than the number of the second vias 230. The rear redistribution layer 245 may connect one of the second vias 230 and at least two of the rear pads 205. For example, one of the second power vias 230P may be electrically connected to a corresponding one of the first sub-vias 130a and a corresponding one of the second sub-vias 130b through the rear redistribution layer 245. The number of the first sub-vias 130a may be the same as the number of the second power vias 230P, but the present disclosure is not limited thereto.

[0098] In this manner, the second power via 230P and the additional second sub-via 130 b may be connected through the rear redistribution layer 245 , thereby improving the power delivery characteristics of the semiconductor device 1000G.

[0099] Fig. 9A is a plan view of an example of a semiconductor package 10000 in which the semiconductor device 1000 according to some embodiments of the present disclosure is mounted, and Fig. 9B is along Fig. 9A A cross-sectional view taken along line II'.

[0100] refer to Fig. 9A and Fig. 9B , the semiconductor package 10000 may include a package substrate 600, an interposer substrate 700, at least one semiconductor device 1000, and a processor unit 800. The semiconductor device 1000 may have the same Figures 1A to 8B The semiconductor devices 1000A, 1000B, 1000C, 1000D, 1000E, 1000F, and 1000G are described as having the same or similar features. According to some embodiments, the semiconductor device 1000 may be mounted on the interposer substrate 700 or the package substrate 600 alone.

[0101] The package substrate 600 is a supporting substrate on which the interposer substrate 700, the processor unit 800, and the semiconductor device 1000 are mounted, and the package substrate 600 may be a board for a semiconductor package, including a printed circuit board (PCB), a ceramic board, a glass board, and a tape wiring board. Depending on the substrate type, the body of the package substrate 600 may include different materials. For example, if the package substrate 600 is a printed circuit board, the package substrate 600 may have a form in which a wiring layer is additionally stacked on a body copper foil laminate or a cross-sectional surface or both surfaces of the copper foil laminate.

[0102] The package substrate 600 may include a lower terminal 612, an upper terminal 611, and a redistribution circuit 613. The upper terminal 611, the lower terminal 612, and the redistribution circuit 613 may form an electrical path for connecting the lower surface and the upper surface of the package substrate 600. The upper terminal 611, the lower terminal 612, and the redistribution circuit 613 are metal materials, such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). At least one metal or two or more metals. The external connection terminal 620 connected to the lower terminal 612 may be provided on the lower surface of the package substrate 600. The external connection terminal 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or their alloys.

[0103] Interposer substrate 700 may include substrate 701, lower protection layer 703, upper pads 704, lower pads 705, interconnection structure 710, metal bumps 720, and vias 730. Semiconductor device 1000 and processor unit 800 may be electrically connected to each other via interposer substrate 700.

[0104] The substrate 701 may be formed of any one of, for example, a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the substrate 701 is a silicon substrate, the interposer substrate 700 may be referred to as a silicon interposer. When the substrate 701 is an organic substrate, the interposer substrate 700 may be referred to as a plate interposer.

[0105] The lower protective layer 703 may be disposed on the lower surface of the substrate 701, and the lower pad 705 may be disposed under the lower protective layer 703. The lower pad 705 may be connected to the via 730. The semiconductor device 1000 and the processor unit 800 may be electrically connected to the package substrate 600 through the metal bump 720 disposed under the lower pad 705.

[0106] The interconnect structure 710 may be disposed on the upper surface of the substrate 701, and may include an interlayer insulating layer 711 and a single-layer or multi-layer wiring structure 712. The upper pad 704 may be disposed on the upper surface of the interconnect structure 710, and may be electrically connected to the wiring structure 712. When the interconnect structure 710 has a multi-layer wiring structure 712, wiring patterns of different layers may be connected to each other through contact vias.

[0107] The via 730 may extend from the upper surface to the lower surface of the substrate 701 and may penetrate the substrate 701. In addition, the via 730 may extend to the inside of the interconnect structure 710 and may be electrically connected to the wiring of the interconnect structure 710. When the substrate 701 is silicon, the via 730 may be referred to as a TSV. According to some embodiments, the interposer substrate 700 may include only the interconnect structure therein and may not include a via.

[0108] The interposer substrate 700 may be used to convert or transmit input electrical signals between the package substrate 600 and the semiconductor device 1000 or the processor unit 800. Therefore, the interposer substrate 700 may not include devices such as active devices or passive devices. In addition, according to some embodiments, the interconnect structure 710 may be arranged below the via 730. For example, the positional relationship between the interconnect structure 710 and the via 730 may be considered to be relative.

[0109] The metal bumps 720 may electrically connect the interposer substrate 700 and the package substrate 600. The semiconductor device 1000 may be electrically connected to the metal bumps 720 through the upper pads 704, the wiring of the interconnect structure 710, and the vias 730. According to some embodiments, the lower pads 705 for power or grounding may be integrated and connected together to the metal bumps 720, so that the number of the lower pads 705 may be greater than the number of the metal bumps 720.

[0110] The processor unit 800 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an application-specific integrated circuit (ASIC).

[0111] According to some embodiments, the semiconductor package 10000 may further include an internal sealant for covering the semiconductor device 1000 and the processor unit 800 on the interposer substrate 700. In addition, the semiconductor package 10000 may further include an external sealant for covering the interposer substrate 700 and the internal sealant on the package substrate 600. The external sealant and the internal sealant may be formed together and may not be distinguished and identified. According to some embodiments, the semiconductor package 10000 may further include a heat dissipation structure for covering the semiconductor device 1000 and the processor unit 800.

[0112] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed. Certain features described in the context of each individual embodiment in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may point to a sub-combination or a variation of the sub-combination.

[0113] The scope of the present disclosure is not limited to the above examples and drawings. Therefore, those skilled in the art may make various substitutions, modifications or changes without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications or changes should be interpreted as being included within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: a first semiconductor chip including a first via member and a first front pad electrically connected to the first via member; as well as A second semiconductor chip is disposed below the first semiconductor chip, wherein the second semiconductor chip comprises: Substrate, a circuit layer disposed below the substrate, A second front pad, which is below the circuit layer, a rear pad disposed on the substrate and electrically connected to the first front pad, a second through-hole member penetrating the substrate and electrically connected to the second front pad, and a rear redistribution layer electrically connecting the second through-hole members to the rear pads, wherein at least one of the rear pads is horizontally spaced apart from a corresponding one of the second through-hole members and vertically extends at least partially below a corresponding one of the first through-hole members.

2. The semiconductor device according to claim 1, wherein One of the first front pads extends at least partially below a second corresponding one of the first via members in the vertical direction.

3. The semiconductor device according to claim 1, wherein One of the first front pads extends at least partially over a corresponding one of the rear pads in the vertical direction.

4. The semiconductor device according to claim 1, wherein The first through-hole member and the second through-hole member are spaced apart from each other in the horizontal direction.

5. The semiconductor device according to claim 1, wherein The first via and the second via each include at least one of a power via and a ground via.

6. The semiconductor device according to claim 5, wherein: The number of the first through-hole members is greater than the number of the second through-hole members.

7. The semiconductor device according to claim 5, wherein: The rear redistribution layer electrically connects one of the second vias to at least two of the rear pads.

8. The semiconductor device according to claim 1, further comprising: A bump electrically connects the first front pad to the rear pad.

9. The semiconductor device according to claim 8, wherein: The bumps include tin or a tin alloy.

10. The semiconductor device according to claim 1, wherein The first semiconductor chip further includes a first insulating layer surrounding the first front pad, and The second semiconductor chip further includes a second insulating layer surrounding the rear pad and contacting the first insulating layer.

11. The semiconductor device according to claim 10, wherein The first front pad and the rear pad contact each other.

12. The semiconductor device according to claim 10, wherein: The first insulating layer and the second insulating layer include at least one of silicon oxide, silicon nitride and silicon carbonitride, and The first front pad and the rear pad include at least one of copper, nickel, gold, silver, and alloys thereof.

13. The semiconductor device according to claim 1, wherein The circuit layer comprises: Individual circuit components, and A wiring structure electrically connects the individual circuit elements to the second front pad and the second via member.

14. The semiconductor device according to claim 1, wherein The first semiconductor chip further includes a first rear pad disposed opposite to the first front pad and a first rear redistribution layer electrically connecting the first rear pad to the first through-hole member, and Wherein, the semiconductor device further comprises: A third semiconductor chip is disposed on the first semiconductor chip, and the third semiconductor chip includes: A third front pad electrically connected to the first rear pad, and a third via member electrically connected to the third front pad.

15. The semiconductor device according to claim 14, wherein: At least one of the first rear pads is spaced apart from a second corresponding one of the first vias in the horizontal direction and extends at least partially below a corresponding one of the third vias in the vertical direction.

16. A semiconductor device comprising: a first semiconductor chip including a first via arranged in a first through silicon via region and a front pad electrically connected to the first via; as well as A second semiconductor chip is disposed below the first semiconductor chip, wherein the second semiconductor chip comprises: a second through-silicon via disposed in a second through-silicon via region, a rear pad electrically connected to the front pad, and A rear redistribution layer electrically connects the second through-via to the rear pad, wherein at least a portion of the first through-silicon via region is offset from the second through-silicon via region in a horizontal direction.

17. The semiconductor device according to claim 16, wherein: At least one of the first TSV region and the second TSV region includes two or more sub-TSV regions horizontally spaced apart from each other.

18. The semiconductor device according to claim 16, wherein: The first TSV region includes a first TSV sub-region and a second TSV sub-region. The first sub-TSV region is disposed at a central portion of the first semiconductor chip, and The second sub-TSV region is disposed adjacent to an edge of the first semiconductor chip.

19. A semiconductor device comprising: one or more semiconductor chips including a first power via; as well as A base chip, which is arranged below the one or more semiconductor chips, and the base chip comprises: a second power supply via, and a rear redistribution layer electrically connecting the second power via to the first power via, The first power supply via comprises a first sub-via extending at least partially above the second power supply via in a vertical direction, and a second sub-via spaced apart from the second power supply via in a horizontal direction.

20. The semiconductor device according to claim 19, wherein One of the second power vias is electrically connected to both a corresponding one of the first sub-vias and a corresponding one of the second sub-vias through the rear redistribution layer.

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