Equalization driving circuit of transmitter and processing method of signal to be transmitted

Abstract

The invention discloses a transmitter equalization driving circuit and a method for processing a signal to be transmitted. The circuit comprises a serialization and retiming module used for generating multiple paths of parallel data based on a signal to be transmitted; the data selector module is connected with the serialization and retiming module and used for receiving the clock signal corresponding to each path of parallel data and generating process data including front tap data, main tap data, first rear tap data and second rear tap data based on the parallel data and the clock signal; the pulse generation module is connected with the data selector module and is used for receiving the process data to generate a front tap equalization pulse and a first rear tap equalization pulse; and the hybrid equalization driving module is connected with the pulse generation module and the data selector module, and is used for receiving the front tap data, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data to generate an output signal of the signal to be transmitted. The circuit can improve the signal quality of the output signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a transmitter equalization driving circuit and a method for processing a signal to be transmitted. Background Art

[0002] With the rapid development of communication technology and the substantial increase in the amount of data transmitted between communication devices, it is becoming increasingly important to achieve fast data transmission between communication devices. However, due to the limited number of chip pins and the strict timing requirements between parallel lines, traditional parallel data transmission cannot meet the growing demand for high-speed bandwidth data transmission, making parallel data transmission face severe challenges. To address the above problems, the SerDes (serializer / deserializer) system came into being, which developed rapidly and gradually replaced parallel data transmission.

[0003] Currently, the SerDes system consists of three parts: transmitter, wired channel and receiver. Among them, due to the existence of non-ideal factors such as skin effect, dielectric loss and signal reflection in the wired channel, the signal transmission quality will be seriously affected, causing the eye diagram of the signal received by the receiver to shrink or even close. In addition, with the rapid increase in signal transmission rate, the signal quality attenuation is more serious, which in turn seriously affects the working range and signal transmission rate of the SerDes system.

[0004] To address the above problems, a feedforward equalizer (FFE), decision feedback equalizer (DFE) and continuous time linear equalizer (CTLE) are usually set in the SerDes system. However, the above solutions are still limited by the fixed compensation range and equalization capability. For example, the traditional FFE and DFE are essentially FIR filters with high-pass characteristics, and their peak compensation frequency is fixed at the Nyquist frequency. CTLE mainly compensates for channel attenuation by increasing the high-frequency components of the signal. The zero-pole pair enhancement technology it adopts makes it face the problems of inevitable noise amplification and fixed compensation slope; further, the FFE in the SerDes transmitter mostly adopts the de-emphasis equalization method of the low-frequency components of the attenuated signal, that is, it presents the characteristics of a high-pass filter to compensate for the low-pass attenuation of the channel, but this method will cause the signal output amplitude to decrease, resulting in a decrease in the transmitter output swing. In addition, in the existing related technologies, the interval between two adjacent taps of FFE is an integer interval (i.e., one UI, unit symbol interval). Integer interval-based equalization can eliminate inter-symbol interference of the signal through pre-determination, but this method does not have flexible and adjustable equalization capabilities to cope with the complex and changeable SerDes system working environment, resulting in the signal quality of the transmitter signal of the SerDes system being too low. Summary of the invention

[0005] In view of this, the present application provides a transmitter equalization driving circuit and a method for processing a signal to be transmitted, the main purpose of which is to solve the technical problem of low signal quality of the transmitter signal of the existing SerDes system.

[0006] According to a first aspect of the present invention, a transmitter equalization driving circuit is provided, which is applied to a SerDes transmitter, and the circuit comprises:

[0007] A serialization and retiming module, used for receiving a signal to be transmitted and generating multi-channel parallel data corresponding to the signal to be transmitted;

[0008] A data selector module, the data selector module is connected to the serialization and retiming module, and is used to receive a clock signal corresponding to each channel of the parallel data, and generate front tap data, main tap data, first rear tap data, and second rear tap data based on the multiple channels of parallel data and the clock signal corresponding to each channel of the parallel data;

[0009] Wherein, the pre-tap data and the main tap data are separated by a preset fractional symbol interval as well as the first post-tap data and the main tap data;

[0010] A pulse generating module, the pulse generating module is connected to the data selector module, and is used to receive the front tap data, the main tap data and the first rear tap data, and generate a front tap equalized pulse and a first rear tap equalized pulse;

[0011] A hybrid balanced driving module, the hybrid balanced driving module is connected to the pulse generating module and the data selector module, and is used to receive the front tap balanced pulse, the main tap data, the first rear tap balanced pulse and the second rear tap data, and generate an output signal of the signal to be transmitted.

[0012] According to a second aspect of the present invention, a method for processing a signal to be transmitted is provided, which is applied to the above transmitter equalization driving circuit, and the method comprises:

[0013] Acquire the signal to be transmitted, perform delay processing on the signal to be transmitted, and obtain front tap data, main tap data, first rear tap data, and second rear tap data respectively corresponding to the signal to be transmitted;

[0014] The phase difference between the front tap data and the main tap data and between the main tap data and the first rear tap data is a preset fractional symbol interval, and the phase difference between the main tap data and the second rear tap data is an integer symbol interval;

[0015] Generate a pre-tap data pre-emphasis pulse based on a phase difference between the pre-tap data and the main tap data, generate a first rear-tap data pre-emphasis pulse based on a phase difference between the main tap data and the first rear-tap data, and generate a second rear-tap de-emphasis data based on the second rear-tap data;

[0016] The front tap data pre-emphasis pulse, the first rear tap data pre-emphasis pulse, the second rear tap de-emphasis data and the main tap data are superimposed to obtain the output signal.

[0017] A transmitter equalization driving circuit and a method for processing a signal to be transmitted provided by the present invention can align and synchronize the received signal to be transmitted based on a serialization and retiming module to obtain multiple parallel data, and transmit each parallel data to a data selector module. At the same time, a preset clock signal corresponding to each parallel data is sent to the data selector module, so that the data selector module generates front tap data, main tap data, first rear tap data and second rear tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data can be between 0° and 90°, and the specific phase difference value can be predetermined, and multiple clock signals are input into the data selector module; at this time, by adjusting the phase difference between the clock signals corresponding to the parallel data, the front tap data, main tap data, first rear tap data and second rear tap data generated based on the parallel data can be synchronized. There is a specific phase difference between the tap data and the second rear tap data; further, the front tap data, main tap data, first rear tap data and second rear tap data with the specific phase difference are input into the pulse generation module, and based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasizing the main tap data is generated, and based on the phase difference between the main tap data and the first rear tap data, a first rear tap equalization pulse for pre-emphasizing the main tap data is generated; further, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data are input into the hybrid equalization drive module, so that the hybrid equalization drive module obtains an output signal that optimizes the signal swing and the output eye diagram, thereby solving the problem of too low signal quality of the transmitting end signal of the existing SerDes system.

[0018] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 One of the structural schematic diagrams of a transmitter equalization driving circuit provided by an embodiment of the present invention is shown;

[0021] Figure 2 A schematic diagram of de-emphasis equalization based on tap data with integer symbol intervals provided by an embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram of pre-emphasis equalization based on tap data with fractional symbol intervals provided by an embodiment of the present invention is shown;

[0023] Figure 4 A second structural schematic diagram of a transmitter equalization driving circuit provided by an embodiment of the present invention is shown;

[0024] Figure 5 A schematic diagram of the structure of a clock module provided by an embodiment of the present invention is shown;

[0025] Figure 6 A schematic diagram of a balanced pulse width control circuit provided by an embodiment of the present invention is shown;

[0026] Figure 7 A schematic structural diagram of a front-tap equalization pulse generating unit provided by an embodiment of the present invention is shown;

[0027] Figure 8 A schematic structural diagram of a first post-tap equalization pulse generating unit provided by an embodiment of the present invention is shown;

[0028] Fig. 9 A schematic diagram of the structure of an AND gate and an OR gate constituting a front-tap equalized pulse generating unit and a first rear-tap equalized pulse generating unit provided by an embodiment of the present invention is shown;

[0029] Fig.10 The figure shows the waveform of a front-tap equalization pulse and a first rear-tap equalization pulse provided by an embodiment of the present invention;

[0030] Fig.11 A third structural schematic diagram of a transmitter equalization driving circuit provided by an embodiment of the present invention is shown;

[0031] Fig.12 A schematic structural diagram of a forward drive circuit provided by an embodiment of the present invention is shown;

[0032] Fig.13A schematic structural diagram of a negative driving circuit provided by an embodiment of the present invention is shown;

[0033] Fig.14 An equivalent circuit diagram of a conventional main tap driving circuit and a conventional first rear tap driving circuit of integer-interval de-emphasis equalization, as well as an equivalent circuit diagram of a main tap driving circuit and a first rear tap driving circuit of fractional-interval pre-emphasis equalization provided by an embodiment of the present invention are shown;

[0034] Fig.15 A swing amplitude analysis diagram provided by an embodiment of the present invention is shown;

[0035] Fig.16 A comparative analysis diagram of normalized power consumption provided by an embodiment of the present invention is shown;

[0036] Fig.17 A schematic diagram of a frequency response curve of a first rear-tap driving circuit provided by an embodiment of the present invention is shown;

[0037] Fig.18 A schematic flow chart of a method for processing a signal to be transmitted provided by an embodiment of the present invention is shown;

[0038] Fig.19 A principle diagram of a method for processing a signal to be transmitted based on a signal to be transmitted provided by an embodiment of the present invention is shown, which performs signal quality enhancement processing on the signal to be transmitted. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0040] The existing SerDes system includes three parts: a transmitter, a wired channel, and a receiver. Among them, the non-ideal factors such as skin effect, dielectric loss, and signal reflection in the wired channel will seriously affect the transmission quality of the signal, causing the eye diagram of the signal received by the signal receiver to shrink or even close. At the same time, with the rapid increase in signal transmission rate, the attenuation of signal quality is more serious, which in turn seriously affects the working range and signal transmission rate of the SerDes system. In order to cope with the above problems, a feedforward equalizer (FFE), a decision feedback equalizer (DFE), and a continuous time linear equalizer (CTLE) are usually set in the SerDes system. However, the above schemes are still limited by a fixed compensation range and equalization capability, and do not have flexible and adjustable equalization capabilities to cope with the complex and changeable working environment of the SerDes system, resulting in the signal quality of the transmitter signal of the SerDes system being too low.

[0041] In view of the above problems, in one embodiment, Figure 1 As shown, a transmitter equalization driving circuit is provided, and the circuit is applied to a SerDes transmitter as an example for explanation. The circuit includes a serialization and retiming module 1000, a data selector module 2000, a pulse generation module 3000, and a hybrid equalization driving module. Here, the transmitter equalization driving circuit can realize the transmission of four-level pulse amplitude modulation (Four Pulse Amplitude Modulation, PAM4) signals and non-return-to-zero (Non-Return-to-Zero, NRZ) signals. This embodiment is explained by taking the transmitter equalization driving circuit transmitting a PAM4 signal as an example, and other similar types of signals are also applicable to this embodiment.

[0042] Specifically, the serialization and retiming module 1000 is used to receive the signal to be transmitted and generate multiple parallel data corresponding to the signal to be transmitted. Among them, the serialization and retiming module 1000 can be an integrated serialization circuit and retiming circuit, and the signal to be transmitted can be a PAM4 signal, which is 64 parallel data, divided into 32 high-order parallel data and 32 low-order parallel data. The high-order parallel data and the low-order parallel data can be processed based on two identical transmitter equalization driving circuits, and the principle of signal processing of the two is the same; in the embodiment of the present application, the transmitter equalization driving circuit for processing high-order parallel data is used as an example for explanation, and the workflow for processing low-order parallel data can refer to the workflow for processing high-order parallel data, which will not be repeated here.

[0043] Specifically, by inputting the signal to be transmitted into the serialization circuit in the serialization and retiming module 1000, 4 parallel data corresponding to the signal to be transmitted can be obtained, and the 4 parallel data are input into the retiming circuit for signal alignment and synchronization to obtain 4 parallel data with a rate that is one-fourth of the final transmission signal rate. Here, the 4 parallel data can be delayed and beat in sequence to obtain 4 parallel data with a preset unit code element interval (UI) between adjacent parallel data. In this embodiment, the above-mentioned preset code element interval can be 1UI.

[0044] Furthermore, the data selector module 2000 is connected to the serialization and retiming module 1000, and is used to receive a clock signal corresponding to each channel of the parallel data, and generate front tap data, main tap data, first rear tap data and second rear tap data based on the multiple channels of parallel data and the clock signal corresponding to each channel of the parallel data.

[0045] Among them, the clock signal is pre-configured by relevant staff, and the phase difference between each clock signal can be pre-selected and input into the data selector module 2000. Here, the clock signal can be a four-phase clock, each clock signal corresponds to a parallel data, and is used to adjust the phase difference between the parallel data; when the phase difference between the first clock signal and the second clock signal, the second clock signal and the third clock signal, and the third clock signal and the fourth clock signal received by the data selector module 2000 is 90°, the data phase difference between the front tap data and the main tap data, the main tap data and the first rear tap data, and the first rear tap data and the second rear tap data output by the data selector module 2000 is 1UI, at this time, the front tap data and the main tap data, the main tap data and the first rear tap data, and the first rear tap data and the second rear tap data are separated by an integer UI. In the embodiment of the present application, the phase difference between the first clock signal corresponding to the first parallel data and the second clock signal corresponding to the second parallel data received by the data selector module 2000 can be pre-selected in the range of 0° to 90° to adjust the phase difference α between the front tap data and the main tap data. PRE UI, where α PRE As the tap delay coefficient, its value range is 0 to 1, α PRE The value range of α is determined by the phase difference between the first clock signal and the second clock signal. The closer the phase difference is to 0°, the PRE The closer it is to 0, the closer the phase difference is to 90°. PRE The closer it is to 1.

[0046] Furthermore, the phase difference between the second clock signal corresponding to the second parallel data and the third clock signal corresponding to the third parallel data received by the data selector module 2000 can be pre-selected within the range of 0° to 90°, so as to adjust the phase difference α between the main tap data and the first post-tap data. PPST1 UI, where α PPST1 As the tap delay coefficient, its value range is 0 to 1, α PPST1 The value range of α is determined by the phase difference between the second clock signal and the third clock signal. The closer the phase difference is to 0°, the PPST1 The closer it is to 0, the closer the phase difference is to 90°. PPST1The closer to 1. Further, the second clock signal corresponding to the second parallel data and the fourth clock signal corresponding to the fourth parallel data received by the data selector module 2000 can be the same. Based on the above method, the pre-tap data generated by the data selector module can be separated from the main tap data by a preset fractional symbol interval, the first post-tap data can be separated from the main tap data by a preset fractional symbol interval; the pre-tap data can be separated from the second post-tap data by a preset integer symbol interval.

[0047] Further, the pulse generation module 3000 is connected to the data selector module 2000, and is used to receive the front tap data, the main tap data, and the first rear tap data, and generate a front tap equalization pulse and a first rear tap equalization pulse. Figure 2 The principle diagram of de-emphasis equalization based on the existing tap data with integer code element interval is given, such as Figure 2 As shown in the figure, the FFE in the SerDes transmitter is usually adopted as follows Figure 2 In the low-frequency component de-emphasis equalization mode of the attenuated signal shown, the input data reaches the main tap element 2 through the buffer 1, and the input data reaches the rear tap element 4 through the buffer 1 and the 1UI delay unit 3. The main tap pre-equalization data that has not been equalized is subtracted from the rear tap pre-equalization data that has been delayed by 1UI (that is, the input data that has not been equalized and reaches the rear tap) to achieve de-emphasis equalization. In this case, the FFE presents a high-pass filter characteristic to compensate for the high-frequency attenuation of the channel, but this method will cause the signal output amplitude to decrease (from -1 to 1 to -1+G to 1-G, where G is the equalization strength of the rear tap), resulting in a decrease in the transmitter swing. Based on this, in this embodiment, the main tap data and the second rear tap data are separated by an integer symbol interval, and the rear tap pre-equalization data can be generated based on the second rear tap data according to the above principle to achieve de-emphasis on the output signal, and an integer interval de-emphasis transmitter equalization driving circuit is obtained.

[0048] Furthermore, Figure 3 The principle diagram of pre-emphasis equalization based on tap data with fractional symbol interval is given to solve the problem of reduced output swing caused by traditional de-emphasis equalization method. Figure 3In the pre-emphasis equalization method for improving the high-frequency components of the signal, the input data reaches the main tap element 2 and the rear tap element 4 through the buffer 1, and at the same time, the input data reaches the rear tap element 4 through the buffer 1 and the αUI (α, i.e., the tap delay coefficient, the variation range is 0-1) delay unit 5, and the two-way data reaching the rear tap element 4 are calculated in the rear tap element 4 to obtain a pre-emphasis equalization pulse with a width of αUI. Pre-emphasis equalization is achieved by superimposing the pre-emphasis equalization pulse generated in the rear tap element 4 on the data before the main tap equalization. In this case, FFE also presents a high-pass filter characteristic to compensate for the attenuation of the high-frequency components of the channel, and this pre-emphasis equalization method does not cause the problem of reducing the output swing, but has the effect of increasing the output swing and reducing power consumption. At the same time, by adjusting the tap delay coefficient α, an expandable compensation range and flexible equalization can be achieved. Based on this, in this embodiment, the front tap data and the first rear tap data are respectively spaced apart by a fraction of the code element interval between the main tap data. According to the above principle, the front tap equalization pulse and the first rear tap equalization pulse can be generated based on the front tap data, the first rear tap data and the main tap data to pre-emphasize the output signal and obtain a transmitter equalization driving circuit with fractional interval pre-emphasis.

[0049] Specifically, since the phase difference between the pre-tap data and the main tap data output by the data selector module 2000 is α PRE UI, the phase difference between the first post-tap data and the main tap data is α PPST1 UI(α PRE With α PPST1 The values ​​of are all between 0 and 1), and the pulse generation module 3000 can generate pulses with widths of α PRE UI and alpha PPST1 The front-tap equalized pulse of UI and the first rear-tap equalized pulse serve as pre-emphasized equalized pulses for pre-emphasizing the data signal.

[0050] Further, the hybrid balanced driving module 4000 is connected to the pulse generating module 3000 and the data selector module 2000, and is used to receive the front tap balanced pulse, the main tap data, the first rear tap balanced pulse and the second rear tap data, and generate the output signal of the signal to be transmitted. Specifically, the hybrid balanced driving module 4000 can receive the front tap balanced pulse and the first rear tap balanced pulse from the pulse generating module 3000, and receive the main tap data and the second rear tap data from the data selector module 2000, wherein a buffer (not shown in the figure) can be provided on the data path between the hybrid balanced driving module 4000 and the data selector module 2000 to optimize the transmission rate of the main tap data and the second rear tap data. Further, the hybrid balanced driving module 4000 can generate the rear tap balanced pre-data based on the second rear tap data, and superimpose the main tap data based on the front tap balanced pulse, the first rear tap balanced pulse and the rear tap balanced pre-data to obtain the optimized output signal, and transmit it based on the channel.

[0051] The transmitter equalization driving circuit provided in this embodiment can align and synchronize the received transmission signal based on the serialization and retiming module to obtain multiple parallel data, and transmit each parallel data to the data selector module. At the same time, a preset clock signal corresponding to each parallel data is sent to the data selector module, so that the data selector module generates front tap data, main tap data, first rear tap data and second rear tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data can be between 0° and 90°, and the specific phase difference value can be determined in advance, and multiple clock signals are input to the data selector module; at this time, by adjusting the phase difference between the clock signals corresponding to the parallel data, the front tap data, main tap data, first rear tap data and second rear tap data generated based on the parallel data can be synchronized. The first and second rear tap data have a specific phase difference; further, the front tap data, the main tap data, the first rear tap data and the second rear tap data with the specific phase difference are input into the pulse generation module, and based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasizing the main tap data is generated, and based on the phase difference between the main tap data and the first rear tap data, a first rear tap equalization pulse for pre-emphasizing the main tap data is generated; further, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data are input into the hybrid equalization drive module, so that the hybrid equalization drive module obtains an output signal that optimizes the signal swing and the output eye diagram, thereby solving the problem of low signal quality of the transmitter signal of the existing SerDes system.

[0052] In one embodiment, Figure 4As shown, the data selector module 2000 includes a plurality of data selectors, each of which is connected to the serialization and retiming module 1000, and each of which is used to receive one channel of parallel data and the clock signal corresponding to the parallel data. The data selector may be a 4:1 data selector, which is used to convert the received parallel data into serial data; the plurality of data selectors include a front tap data selector 2100, a main tap data selector 2200, a first rear tap data selector 2300, and a second rear tap data selector 2400, and the parallel data includes a first parallel data, a second parallel data, a third parallel data, and a fourth parallel data. Specifically, the front tap data selector 2100 is used to receive the first parallel data, the main tap data selector 2200 is used to receive the second parallel data, the first rear tap data selector 2300 is used to receive the third parallel data, and the second rear tap data selector 2400 is used to receive the fourth parallel data.

[0053] Furthermore, the front tap data selector 2100 is also connected to the pulse generation module 3000, and is used to receive the first parallel data and the first clock signal corresponding to the first parallel data, generate the front tap data, and send the front tap data to the pulse generation module 3000; the main tap data selector 2200 can also be connected to the hybrid balanced driving module 4000 through the first buffer 6000, and is connected to the pulse generation module 3000, and is used to receive the second parallel data and the second clock signal corresponding to the second parallel data, generate the main tap data, and send the main tap data to the hybrid balanced driving module 4000 and the The pulse generating module 3000; the first rear-tap data selector 2300 is also connected to the pulse generating module 3000, for receiving the third parallel data and a third clock signal corresponding to the third parallel data, generating the first rear-tap data, and sending the first rear-tap data to the pulse generating module 3000; the second rear-tap data selector 2400 can also be connected to the hybrid balanced driving module 4000 through the second buffer 7000, for receiving the fourth parallel data and a fourth clock signal corresponding to the fourth parallel data, generating the second rear-tap data, and sending the second rear-tap data to the hybrid balanced driving module 4000.

[0054] Furthermore, each group of serial data will pass through a single-ended to differential circuit in the data selector, so that the generated front tap data includes front tap positive differential data DPpre and front tap negative differential data DNpre, so that the generated main tap data includes main tap positive differential data DPmain and main tap negative differential data DNmain, so that the generated first rear tap data includes first rear tap positive differential data DPpst1 and first rear tap negative differential data DNpst1, and so that the generated second rear tap data includes second rear tap positive differential data DPpst2 and second rear tap negative differential data DNpst2. The embodiment provided by the present application can be based on multiple data selectors, so that each data selector can generate serial data corresponding to the parallel data according to the received parallel data and the clock data corresponding to the parallel data, and make the serial data have a specific phase difference to realize subsequent signal processing.

[0055] In one embodiment, Figure 4 As shown, the transmitter equalization driving circuit also includes a clock module 5000, which is connected to the data selector 2000 and is used to receive the original clock signal, and generate the clock signal corresponding to each parallel data in response to the received clock adjustment instruction, and send the clock signal to the data selector 2000 corresponding to the clock signal. Specifically, Figure 5 As shown, the clock module 5000 includes a buffer 5100, a four-phase clock generating circuit 5200 and a balanced pulse width control circuit 5300 connected in series; wherein the buffer 5100 can receive the original clock signal and send it to the four-phase clock generating circuit 5200 to generate a four-phase clock signal; further, the four-phase clock generating circuit 5200 sends the four-phase clock signal to the balanced pulse width control circuit 5300, and the balanced pulse width control circuit 5300 adjusts the phase of the four-phase clock signal based on the preset phase difference between the clock signals sent to each data selector, generates 4 clock signals with specific phase differences between each other, and sends them to the data selector corresponding to the clock signal, so that the front tap data and the main tap data output by the front tap data selector 2100 and the main tap data selector 2200 respectively have a fractional code element interval, and the main tap data and the first rear tap data output by the main tap data selector 2200 and the first rear tap data selector 2300 respectively have a fractional code element interval.

[0056] Furthermore, when the balanced pulse width control circuit is in working state, based on the received four-phase clock signal, it generates three groups of four-phase clocks with a certain phase difference, wherein the four-phase clock corresponding to the front tap data is PH0-90-180-270PRE, the four-phase clock of the main tap data and the second rear tap is PH0-90-180-270MAIN, and the four-phase clock of the first rear tap data is PH0-90-180-270PST1. Furthermore, the four-phase clock of the main tap data can be the same as the four-phase clock of the second rear tap data, where PH0, PH90, PH180 and PH270 represent the four phases of the four-phase clock respectively. The three groups of four-phase clocks generated are used as sampling clocks of the data selector. Further, based on Figure 6 The principle of the balanced pulse width control circuit is explained. Figure 6 As shown in (a), when the traditional integer interval equalization is adopted, under the action of the equalization pulse width control circuit, the phase difference between two adjacent four-phase clocks of PH0-90-180-270PRE, PH0-90-180-270MAIN and PH0-90-180-270PST1 is 90°. Figure 6 In the first phase PH0PRE of the first parallel data, the first phase PH0MAIN of the second parallel data, and the first phase PH0PST1 of the third parallel data, the phase difference between the two adjacent clocks is 90°, and the principles of the other four-phase clocks are the same. After the parallel-to-serial conversion of the 4:1 data selector, the phase difference between each group of the obtained front tap data DPRE, main tap data DMAIN, and first rear tap data DPST1 is 1UI, that is, an integer interval. Figure 6 As shown in (b), when fractional interval equalization is adopted, under the action of the equalization pulse width control circuit, the phase difference between two adjacent groups of four-phase clocks PH0-90-180-270PRE corresponding to the front tap data, the four-phase clock PH0-90-180-270MAIN corresponding to the main tap data and the four-phase clock PH0-90-180-270PST1 corresponding to the first rear tap data can be adjusted, and the adjustment range is 0 to 90°. After the parallel-to-serial conversion of the data selector, the phase difference between the obtained front tap data DPRE and the main tap data DMAIN is α PRE UI, where α PRE The range of variation is 0 to 1, and the difference between the main tap data DMAIN and the first post-tap data DPST1 is α PPST1 UI, where α PPST1 The range of variation is 0 to 1. The above data can be generated by the balanced pulse generation circuit to generate a width of α PRE UI and α PPST1 Pre-emphasized equalized pulses for UI.

[0057] Furthermore, the clock corresponding to the serialization and retiming module can be further divided based on the clock corresponding to the data selector. The embodiment provided by the present application can adjust the phase difference between the clocks based on the clock module, and send clock signals with a preset phase difference between each other to the data selector, so that there is a fractional code element interval between the front tap data and the main tap data, and there is a fractional code element interval between the main tap data and the first rear tap data, and then a pre-emphasis pulse can be generated based on the fractional code element interval between the tap data, thereby improving the output swing and output signal quality of the output signal.

[0058] In one embodiment, Figure 4 As shown, the pulse generation module 3000 includes a front tap equalization pulse generation unit 3100 and a first rear tap equalization pulse generation unit 3200. The front tap equalization pulse generation unit 3100 is connected to the front tap data selector 2100 and the main tap data selector 2200, respectively, for receiving the front tap data and the main tap data, generating the front tap equalization pulse, and sending the front tap equalization pulse to the hybrid equalization driving module 4000.

[0059] Specifically, the front tap data includes front tap positive differential data DPpre and front tap negative differential data DNpre, the main tap data includes main tap positive differential data DPmain and main tap negative differential data DNmain; the front tap equalization pulse includes: a first positive front tap equalization pulse ENPpre, a first negative front tap equalization pulse ENNpre, a second positive front tap equalization pulse EPPpre, and a second negative front tap equalization pulse EPNpre. The front tap positive differential data DPpre and the front tap negative differential data DNpre are a group of differential signals generated by a front tap data selector.

[0060] Furthermore, the front tap balanced pulse generating unit includes a first AND gate and a first OR gate, such as Figure 7As shown, the first input end of the first AND gate 3110 and the first input end of the first OR gate 3120 are respectively connected to the first output end of the front tap data selector for receiving the front tap positive differential data DPpre, the second input end of the first AND gate 3110 and the second input end of the first OR gate 3120 are respectively connected to the first output end of the main tap data selector for receiving the main tap negative differential data DNmain, the output end of the first AND gate 3110 is connected to the hybrid balanced driving module for sending the first positive front tap equalization pulse ENPpre to the hybrid balanced driving module, and the output end of the first OR gate 3120 is connected to the hybrid balanced driving module for sending the first negative front tap equalization pulse ENNpre to the hybrid balanced driving module.

[0061] Furthermore, the pre-tap balanced pulse generating unit further includes a second AND gate and a second OR gate, such as Figure 7 As shown, the first input end of the second AND gate 3130 and the first input end of the second OR gate 3140 are respectively connected to the second output end of the front tap data selector for receiving the front tap negative differential data DNpre, the second input end of the second AND gate 3130 and the second input end of the second OR gate 3140 are respectively connected to the second output end of the main tap data selector for receiving the main tap positive differential data DPmain, the output end of the second AND gate 3130 is connected to the hybrid balanced driving module for sending the second positive front tap equalization pulse EPPpre to the hybrid balanced driving module, and the output end of the second OR gate 3140 is connected to the hybrid balanced driving module for sending the second negative front tap equalization pulse EPNpre to the hybrid balanced driving module.

[0062] Further, such as Figure 4As shown, the first rear tap equalization pulse generating unit 3300 is connected to the main tap data selector 2200 and the first rear tap data selector 2300 respectively, and is used to receive the main tap data and the first rear tap data, generate the first rear tap equalization pulse, and send the first rear tap equalization pulse to the hybrid equalization driving module 4000. Further, the first rear tap data includes the first rear tap positive differential data DPpst1 and the first rear tap negative differential data DNpst1; the second rear tap data includes the second rear tap positive differential data DPpst2 and the second rear tap negative differential data DNpst2; the first rear tap equalization pulse includes: a first positive first rear tap equalization pulse ENPpst1, a first negative first rear tap equalization pulse ENNpst1, a second positive first rear tap equalization pulse EPPpst1, and a second negative first rear tap equalization pulse EPNpst1.

[0063] The first post-tap equalization pulse generating unit 3300 includes a third AND gate and a third OR gate. Figure 8 As shown, the first input end of the third AND gate 3310 and the first input end of the third OR gate 3320 are respectively connected to the first output end of the first rear tap data selector, for receiving the first rear tap positive differential data DPpst1, the second input end of the third AND gate 3310 and the second input end of the third OR gate 3320 are respectively connected to the first output end of the main tap data selector, for receiving the main tap negative differential data DNmain, the output end of the third AND gate 3310 is connected to the hybrid balanced driving module, for sending the first positive first rear tap equalization pulse ENPpst1 to the hybrid balanced driving module, and the output end of the third OR gate 3320 is connected to the hybrid balanced driving module, for sending the first negative first rear tap equalization pulse ENNpst1 to the hybrid balanced driving module.

[0064] Furthermore, the first post-tap equalization pulse generating unit further includes a fourth AND gate and a fourth OR gate, such as Figure 8As shown, the first input end of the fourth AND gate 3330 and the first input end of the fourth OR gate 3340 are respectively connected to the second output end of the first rear tap data selector, for receiving the first rear tap negative differential data DNpst1, the second input end of the fourth AND gate 3330 and the second input end of the fourth OR gate 3340 are respectively connected to the second output end of the main tap data selector, for receiving the main tap positive differential data DPmain, the output end of the fourth AND gate 3330 is connected to the hybrid balanced driving module, for sending the second positive first rear tap equalizing pulse EPPpst1 to the hybrid balanced driving module, and the output end of the fourth OR gate 3340 is connected to the hybrid balanced driving module, for sending the second negative first rear tap equalizing pulse EPNpst1 to the hybrid balanced driving module.

[0065] Among them, the sizes of transistors constituting the first AND gate, the second AND gate, the third AND gate, the fourth AND gate, the first OR gate, the second OR gate, the third OR gate and the fourth OR gate are optimized to minimize parasitics and increase operating speed; the sizes of the above-mentioned AND gates and OR gates are optimized based on the waveform characteristics of their corresponding input signals.

[0066] Further, combined with Fig. 9 , Fig.10 The principle of the front tap equalized pulse generating unit generating the first positive front tap equalized pulse ENPpre, the first negative front tap equalized pulse ENNpre, the second positive front tap equalized pulse EPPpre and the second negative front tap equalized pulse EPNpre, and the principle of the first rear tap equalized pulse generating unit generating the first positive first rear tap equalized pulse ENPpst1, the first negative first rear tap equalized pulse ENNpst1, the second positive first rear tap equalized pulse EPPpst1 and the second negative first rear tap equalized pulse EPNpst1 are explained: Taking the generation process of the first positive front tap equalized pulse ENPpre as an example, Fig. 9 As shown, only when Fig. 9 The first AND gate shown in (a) and Fig. 9 The rising edge of the first positive forward tap equalization pulse ENPpre can only be generated when the two input signals of the first OR gate shown in (b), the front tap positive differential data DPpre and the main tap negative differential data DNmain, turn from logic low to logic high, wherein the front tap positive differential data DPpre is input by interface A, and the main tap negative differential data DNmain is input by interface B. Since the rising edge of the front tap positive differential data DPpre always appears after the rising edge of the main tap negative differential data DNmain, the rising edge of the first positive forward tap equalization pulse ENPpre is determined by the rising edge of the front tap positive differential data DPpre. Therefore, Fig. 9The pull-up transistor M1 in (a) controlled by the main tap negative differential data DNmain can be set to a small size to reduce parasitic capacitance, and the pull-down transistor M2 can be set to a large size to achieve low transmission impedance. These transistor size optimizations in the two-input AND gate are also applicable to the transistors in the two-input OR gate because they have opposite push-pull structures (the pull-up network of the AND gate is the same as the pull-down network structure of the OR gate, and the pull-down network of the AND gate is the same as the pull-up network structure of the OR gate). Therefore, Fig. 9 The transistors M1 and M3 in (a) can be set to a small size, and the transistors M2 and M4 can be set to a large size, so that the balanced pulse generating circuit can minimize parasitics and improve the operating speed.

[0067] Further, such as Fig.10 (a) illustrates a waveform diagram of a front tap equalizing pulse generated by a front tap equalizing pulse generating unit, including the front tap positive differential data DPpre and the front tap negative differential data DNpre used to generate the front tap equalizing pulse, as well as the waveform diagram of the main tap data main tap positive differential data DPmain and the main tap negative differential data DNmain, and the waveform diagram of the generated first positive front tap equalizing pulse ENPpre, first negative front tap equalizing pulse ENNpre, second positive front tap equalizing pulse EPPpre, and second negative front tap equalizing pulse EPNpre. Fig.10 It can be seen from FIG. 1 that by adjusting the delay (α between the front tap positive differential data DPpre and the front tap negative differential data DNpre and the main tap positive differential data DPmain and the main tap negative differential data DNmain PRE , in the figure α PRE =1), the widths of the first positive forward tap equalized pulse ENPpre, the first negative forward tap equalized pulse ENNpre, the second positive forward tap equalized pulse EPPpre, and the second negative forward tap equalized pulse EPNpre generated as pre-emphasized equalized pulses can be adjusted. Fig.10(b) illustrates a waveform diagram of a first rear-tap equalized pulse as a first rear-tap equalized pulse generated by a first rear-tap equalized pulse generating unit, including a waveform diagram of main tap positive differential data DPmain, main tap negative differential data DNmain, first rear-tap positive differential data DPpst1 and first rear-tap negative differential data DNpst1 used to generate the first rear-tap equalized pulse, and a waveform diagram of the first positive first rear-tap equalized pulse ENPpst1, first negative first rear-tap equalized pulse ENNpst1, second positive first rear-tap equalized pulse EPPpst1 and second negative first rear-tap equalized pulse EPNpst1 generated as the first rear-tap equalized pulse. It can be seen from the figure that by adjusting the delay (α) between the main tap positive differential data DPmain and the main tap negative differential data DNmain and the first rear-tap positive differential data DPpst1 or the first rear-tap negative differential data DNpst1, the first rear-tap equalized pulse ENPpst1 can be generated. PPST1 , in the figure α PPST1 =0.5), the widths of the first positive first rear tap equalization pulse ENPpst1, the first negative first rear tap equalization pulse ENNpst1, the second positive first rear tap equalization pulse EPPpst1, and the second negative first rear tap equalization pulse EPNpst1 generated as pre-emphasized equalization pulses can be adjusted. In the embodiment provided by the present application, the front tap pre-emphasized equalization pulse and the first rear tap pre-emphasized equalization pulse are generated before and after the main tap data edge, respectively, and the pulse width can be flexibly adjusted. Due to the tap delay α PRE UI and α PPST1 UI can be flexibly adjusted under the action of the equalization pulse width control circuit, so based on the front tap and the first rear tap, flexibly adjusted fractional interval pre-emphasis equalization can be achieved.

[0068] In one embodiment, Fig.11As shown, the hybrid balanced driving module 4000 includes a hybrid balanced driving unit 4100 and a bias circuit unit 4200. Specifically, the hybrid balanced driving unit 4100 is connected to the pulse generation module 3000 and the data selector module 2000, and is used to receive the front tap balanced pulse, the main tap data, the first rear tap balanced pulse and the second rear tap data, and generate the output signal of the signal to be transmitted. Further, the bias circuit unit 4200 is connected to the hybrid balanced driving unit 4100, and is used to generate and send a bias signal for controlling the amplitude of the output signal to the hybrid balanced driving unit 4100 in response to the received signal amplitude instruction. The bias signal includes a positive forward tap bias signal VPpre, a negative forward tap bias signal VNpre, a positive main tap bias signal VPmain, a negative main tap bias signal VNmain, a positive first rear tap bias signal VPpst1, a negative first rear tap bias signal VNpst1, a positive second rear tap bias signal VPpst2, and a negative second rear tap bias signal VNpst2. The embodiment provided by the present application can generate a bias signal based on a bias circuit unit to control the amplitude of the pre-emphasis of the signal, thereby improving the controllability of the amplitude of the output signal.

[0069] In one embodiment, Fig.11As shown, the hybrid balanced driving unit 4100 includes a positive driving circuit 4110, a negative driving circuit 4120 and a signal output circuit 4130, wherein the positive driving circuit 4110 is used to receive the first positive forward tap equalization pulse ENPpre, the main tap negative differential data DNmain, the first positive first rear tap equalization pulse ENPpst1, the second rear tap positive differential data DPpst2, the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the negative main tap bias signal VNmain, the positive first rear tap bias signal VPpst1, the negative first rear tap bias signal VNpst1, the negative second rear tap bias signal VNpst2, the first negative first rear tap equalization pulse ENNpst1 and the first Negative forward tap equalizing pulse ENNpre, generates positive mixed output data; the negative driving circuit 4120 is used to receive the second positive forward tap equalizing pulse EPPpre, the main tap positive differential data DPmain, the second positive first rear tap equalizing pulse EPPpst1, the second rear tap negative differential data DNpst2, the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the negative main tap bias signal VNmain, the positive first rear tap bias signal VPpst1, the negative first rear tap bias signal VNpst1, the negative second rear tap bias signal VNpst2, the second negative first rear tap equalizing pulse EPNpst1 and the second negative forward tap equalizing pulse EPNpre, to generate negative mixed output data. Furthermore, the signal output circuit 4130 is connected to the positive driving circuit 4110 and the negative driving circuit 4120 to obtain the positive mixed output data and the negative mixed output data, and is used to generate the output signal based on the positive mixed output data and the negative mixed output data.

[0070] Further, such as Fig.12 As shown, the forward drive circuit includes multiple forward sub-circuits, each of which is connected via a forward circuit connection point C1 arranged on each of the forward sub-circuits, and the forward sub-circuit includes a forward front tap drive circuit 4111, a forward main tap drive circuit 4112, a forward first rear tap drive circuit 4113 and a forward second rear tap drive circuit 4114, wherein the forward main tap drive circuit is provided with a forward signal output terminal TXP.

[0071] Further, such as Fig.12As shown, the forward tap driving circuit 4111 adopts an SST structure, including a first resistor R1 and a first current bias transistor P1, a first control pulse transistor P2, a second current bias transistor N3 and a second control pulse transistor N4 connected in series, wherein the first current bias transistor P1 can be a PMOS current bias transistor, the first control pulse transistor P2 can be a PMOS control pulse transistor, the second current bias transistor N3 can be an NMOS current bias transistor, and the second control pulse transistor N4 can be an NMOS control pulse transistor; the source of the first current bias transistor P1 is connected to a first power supply (not shown in the figure), the drain of the first current bias transistor P1 is connected to the source of the first control pulse transistor P2, and the first current bias transistor P1 is connected to the source of the first control pulse transistor P2. The drain of a control pulse transistor P2 is connected to the drain of the second current bias transistor N3, the source of the second current bias transistor N3 is connected to the drain of the second control pulse transistor N4, the first resistor R1 is connected in parallel between the source and drain of the second control pulse transistor N4, the source of the second control pulse transistor N4 is grounded, the forward circuit connection point C1 is set between the first control pulse transistor P2 and the second current bias transistor N3, and the forward forward tap drive circuit 4111 is used to connect the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the first negative forward tap equalizing pulse ENNpre and the first positive forward tap equalizing pulse ENPpre to the forward drive circuit.

[0072] Specifically, the gate of the first current bias transistor P1 is connected to the first output end of the bias circuit unit for receiving the positive forward tap bias signal VPpre, the gate of the first control pulse transistor P2 is connected to the output end of the first OR gate for receiving the first negative forward tap equalizing pulse ENNpre, the gate of the second current bias transistor N3 is connected to the second output end of the bias circuit unit for receiving the negative forward tap bias signal VNpre, and the gate of the second control pulse transistor N4 is connected to the output end of the first AND gate for receiving the first positive forward tap equalizing pulse ENPpre.

[0073] Further, the forward main tap driving circuit 4112 includes a second resistor R2, a first terminal resistor Rt1, and a third current biasing transistor N5 and a first switch tube S1 connected in series, wherein the forward main tap driving circuit 4112 adopts a tailless CML structure, the third current biasing transistor N5 can be an NMOS current biasing transistor, and the first switch tube S1 can be an NMOS switch tube, which are used to realize integer interval de-emphasis balancing while ensuring the driving capability of the hybrid balanced driving circuit; the first end of the first terminal resistor Rt1 is connected to the second power supply (not shown in the figure), and the second end of the first terminal resistor Rt1 is connected to the third current biasing transistor N5. The drain of the body tube N5, the source of the third current bias transistor N5 is connected to the drain of the first switch tube S1, the second resistor R2 is connected in parallel between the source and the drain of the first switch tube S1, the source of the first switch tube S1 is grounded, the positive signal output terminal TXP is set at the second end of the first terminal resistor Rt1, the positive circuit connection point C1 is set between the positive signal output terminal TXP and the third current bias transistor N5, and the positive main tap driving circuit 4112 is used to connect the negative main tap bias signal VNmain and the main tap negative differential data DNmain to the positive driving circuit.

[0074] Among them, the gate of the third current bias transistor N5 is connected to the third output end of the bias circuit unit for receiving the negative main tap bias signal VNmain, and the gate of the first switch tube S1 is connected to the first output end of the main tap data selector for receiving the main tap negative differential data DNmain.

[0075] Furthermore, the forward first rear tap drive circuit 4113 includes a third resistor R3 and a fourth current bias transistor P5, a third control pulse transistor P6, a fifth current bias transistor N7 and a fourth control pulse transistor N8 connected in series, wherein the first rear tap drive circuit 4113 adopts an SST structure, the fourth current bias transistor P5 can be a PMOS current bias transistor, the third control pulse transistor P6 can be a PMOS control pulse transistor, the fifth current bias transistor N7 can be an NMOS current bias transistor, and the fourth control pulse transistor N8 can be an NMOS control pulse transistor; the source of the fourth current bias transistor P5 is connected to a third power supply (not shown in the figure), the drain of the fourth current bias transistor P5 is connected to the source of the third control pulse transistor P6, and the The drain of the third control pulse transistor P6 is connected to the drain of the fifth current bias transistor N7, the source of the fifth current bias transistor N7 is connected to the drain of the fourth control pulse transistor N8, the third resistor R3 is connected in parallel between the source and drain of the fourth control pulse transistor N8, the source of the fourth control pulse transistor N8 is grounded, the forward circuit connection point C1 is set between the third control pulse transistor P6 and the fifth current bias transistor N7, and the forward first rear tap drive circuit 4113 is used to connect the forward first rear tap bias signal VPpst1, the negative first rear tap bias signal VNpst1, the first negative first rear tap equalizing pulse ENNpst1 and the first positive first rear tap equalizing pulse ENPpst1 to the forward drive circuit.

[0076] Among them, the gate of the fourth current bias transistor P5 is connected to the fourth output end of the bias circuit unit, for receiving the positive first rear tap bias signal VPpst1, the gate of the third control pulse transistor P6 is connected to the output end of the third OR gate, for receiving the first negative first rear tap equalization pulse ENNpst1, the gate of the fifth current bias transistor N7 is connected to the fifth output end of the bias circuit unit, for receiving the negative first rear tap bias signal VNpst1, and the gate of the fourth control pulse transistor N8 is connected to the output end of the third AND gate, for receiving the first positive first rear tap equalization pulse ENPpst1.

[0077] Further, the forward second rear tap driving circuit 4114 includes a fourth resistor R4 and a sixth current bias transistor N9 and a second switch tube S2 connected in series, the forward circuit connection point C1 is set at the drain of the sixth current bias transistor N9, the source of the sixth current bias transistor N9 is connected to the drain of the second switch tube S2, the fourth resistor R4 is connected in parallel between the source and the drain of the second switch tube S2, the source of the second switch tube S2 is grounded, and the forward second rear tap driving circuit 4114 is used to connect the negative second rear tap bias signal VNpst2 and the second rear tap positive differential data DPpst2 to the forward driving circuit. Among them, the gate of the sixth current bias transistor N9 is connected to the sixth output end of the bias circuit unit for receiving the negative second rear tap bias signal VNpst2, and the gate of the second switch tube S2 is connected to the first output end of the second rear tap data selector for receiving the second rear tap positive differential data DPpst2.

[0078] Here, the PMOS current bias transistor and the NMOS current bias transistor can adjust the equalization strength of the pre-emphasis by adjusting the current flowing through the transistor, and the PMOS control pulse transistor and the NMOS control pulse transistor can realize intermittent switching under the control of the first positive front tap equalization pulse ENPpre, the first negative front tap equalization pulse ENNpre, the first positive first rear tap equalization pulse ENPpst1 and the first negative first rear tap equalization pulse ENNpst1 contained in the pre-emphasis equalization pulse. Furthermore, the first terminal resistor RT1 is used to achieve terminal impedance matching and reduce signal reflection. The product of the output drive current of the hybrid equalization drive unit and the first terminal resistor RT1 determines the swing of the output signal. When the equalization is not turned on, the output drive current is determined by the NMOS current bias transistor (main tap current) of the forward main tap drive circuit. After turning on the equalization, the pre-emphasis equalization of the front tap equalization pulse and the first rear tap equalization pulse and the de-emphasis equalization of the second rear tap data respectively generate the front tap current, the first rear tap current and the second rear tap current under the control of the pre-emphasis equalization pulse and the de-emphasis equalization, so that the output drive current increases or decreases.

[0079] Further, the main tap negative differential data DNmain and the negative main tap bias signal VNmain enter the positive main tap driving circuit 4111 with a tailless CML structure, and obtain an unbalanced output signal at the positive signal output terminal TXP. After the first positive forward tap equalization pulse ENPpre, the first negative forward tap equalization pulse ENNpre, the positive forward tap bias signal VPpre, and the negative forward tap bias signal VNpre enter the positive forward tap driving circuit 4111 with an SST structure, they are superimposed with the unbalanced output signal at the positive signal output terminal TXP, thereby achieving pre-emphasis equalization. After the first positive first rear tap equalization pulse ENPpst1, the first negative first rear tap equalization pulse ENNpst1, the positive first rear tap bias signal VPpst1 and the negative first rear tap bias signal VNpst1 enter the positive first rear tap driving circuit 4113 with SST structure, they are superimposed with the unbalanced output signal at the positive signal output terminal TXP, thereby realizing pre-emphasis equalization. After the second rear tap positive differential data DPpst2 and the negative second rear tap bias signal VNpst2 enter the positive second rear tap driving circuit 4114 with tailless CML structure, they are offset with the unbalanced output signal at the positive signal output terminal TXP, thereby realizing de-emphasis equalization. The data before equalization realizes hybrid balanced drive under the joint action of the positive front tap driving circuit 4111, the positive main tap driving circuit 4112, the positive first rear tap driving circuit 4113 and the positive second rear tap driving circuit.

[0080] Further, such as Fig.13 As shown, the negative driving circuit includes a plurality of negative sub-circuits, and each of the negative sub-circuits is connected through a negative circuit connection point C2 set on each of the negative sub-circuits. Further, the negative sub-circuit includes a negative forward tap driving circuit 4121, a negative main tap driving circuit 4122, a negative first rear tap driving circuit 4123, and a negative second rear tap driving circuit 4124, wherein the negative main tap driving circuit is provided with a negative signal output terminal TXN. Further, a signal output circuit is connected to the positive signal output terminal and the negative signal output terminal, and is used to generate the output signal in combination with the positive mixed output data and the negative mixed output data.

[0081] Further, the negative forward tap driving circuit 4121 includes a fifth resistor R5 and a seventh current bias transistor P10, a fifth control pulse transistor P11, an eighth current bias transistor N12 and a sixth control pulse transistor N13 connected in series, the source of the seventh current bias transistor P10 is connected to a fourth power supply (not shown in the figure), the drain of the seventh current bias transistor P10 is connected to the source of the fifth control pulse transistor P11, the drain of the fifth control pulse transistor P11 is connected to the drain of the eighth current bias transistor N12, the source of the eighth current bias transistor N12 is connected to the The drain of the sixth control pulse transistor N13 is connected, the fifth resistor R5 is connected in parallel between the source and the drain of the sixth control pulse transistor N13, the source of the sixth control pulse transistor N13 is grounded, the negative circuit connection point C2 is set between the fifth control pulse transistor P11 and the eighth current bias transistor N12, and the negative forward tap drive circuit is used to connect the positive forward tap bias signal VPpre, the negative forward tap bias signal VNpre, the second negative forward tap equalizing pulse EPNpre and the second negative forward tap equalizing pulse EPNpre to the negative drive circuit.

[0082] Among them, the gate of the seventh current bias transistor P10 is connected to the seventh output terminal of the bias circuit unit for receiving the negative forward tap bias signal VNpre, the gate of the fifth control pulse transistor P11 is connected to the output terminal of the second OR gate for receiving the second negative forward tap equalizing pulse EPNpre, the gate of the eighth current bias transistor N12 is connected to the eighth output terminal of the bias circuit unit for receiving the positive forward tap bias signal VPpre, and the gate of the sixth control pulse transistor N13 is connected to the output terminal of the second AND gate for receiving the second positive forward tap equalizing pulse EPPpre.

[0083] Further, the negative main tap driving circuit includes a sixth resistor R6, a second terminal resistor Rt2, and a ninth current bias transistor N14 and a third switch tube S3 connected in series, the first end of the second terminal resistor Rt2 is connected to a sixth power supply (not shown in the figure), the second end of the second terminal resistor Rt2 is connected to the drain of the ninth current bias transistor N14, the source of the ninth current bias transistor N14 is connected to the drain of the third switch tube S3, the sixth resistor R6 is connected in parallel between the source and the drain of the third switch tube S3, the source of the third switch tube S3 is grounded, and the negative The circuit connection point C2 is arranged between the ninth current bias transistor N14 and the second terminal resistor Rt2, and the negative main tap driving circuit 4122 is used to connect the positive main tap bias signal VPmain and the main tap positive differential data DPmain to the negative driving circuit; wherein, the gate of the ninth current bias transistor N14 is connected to the ninth output end of the bias circuit unit for receiving the positive main tap bias signal VPmain, and the gate of the third switch tube S3 is connected to the second output end of the main tap data selector for receiving the main tap positive differential data DPmain.

[0084] Further, the negative first rear tap driving circuit 4123 includes a seventh resistor R7 and a tenth current bias transistor P15, a seventh control pulse transistor P16, an eleventh current bias transistor N17 and an eighth control pulse transistor N18 connected in series, the source of the tenth current bias transistor P15 is connected to a sixth power supply (not shown in the figure), the drain of the tenth current bias transistor P15 is connected to the source of the seventh control pulse transistor P16, the drain of the seventh control pulse transistor P16 is connected to the drain of the eleventh current bias transistor N17, the source of the eleventh current bias transistor N17 is connected to the eighth control pulse transistor The drain of the eighth control pulse transistor N18 is connected, the seventh resistor R7 is connected in parallel between the source and the drain of the eighth control pulse transistor N18, the source of the eighth control pulse transistor N18 is grounded, the negative circuit connection point C2 is set between the seventh control pulse transistor P16 and the eleventh current bias transistor N17, and the negative first rear tap drive circuit 4123 is used to connect the second negative first rear tap equalizing pulse EPNpst1, the second positive first rear tap equalizing pulse EPPpst1, the positive first rear tap bias signal VPpst1 and the negative first rear tap bias signal VNpst1 to the negative drive circuit.

[0085] Among them, the gate of the tenth current bias transistor P15 is connected to the tenth output terminal of the bias circuit unit, for receiving the negative first rear tap bias signal VNpst1, the gate of the seventh control pulse transistor P16 is connected to the output terminal of the fourth OR gate, for receiving the second negative first rear tap equalizing pulse EPNpst1, the gate of the eleventh current bias transistor N17 is connected to the eleventh output terminal of the bias circuit unit, for receiving the positive first rear tap bias signal VPpst1, and the gate of the eighth control pulse transistor N18 is connected to the output terminal of the fourth AND gate, for receiving the second negative first rear tap equalizing pulse EPNpst1.

[0086] Further, the negative second rear tap driving circuit 4124 includes an eighth resistor R8 and a twelfth current bias transistor N19 and a fourth switch tube S4 connected in series, the negative circuit connection point C2 is set at the drain of the twelfth current bias transistor N19, the source of the twelfth current bias transistor N19 is connected to the drain of the fourth switch tube S4, the source and drain of the fourth switch tube S4 are connected in parallel with the eighth resistor R8, the source of the fourth switch tube S4 is grounded, and the negative circuit connection point C2 is set at the drain of the twelfth current bias transistor N19, the source of the twelfth current bias transistor N19 is connected to the drain of the fourth switch tube S4, the eighth resistor R8 is connected in parallel between the source and the drain of the fourth switch tube S4, the source of the fourth switch tube S4 is grounded, and the negative circuit connection point C2 is set at the drain of the twelfth current bias transistor N19, the source of the twelfth current bias transistor N19 is connected to the drain of the fourth switch tube S4 ... eighth resistor R8 is connected in parallel between the source and the drain of the fourth switch tube S4. The second rear tap driving circuit 4124 is used to connect the negative second rear tap bias signal VNpst2 and the second rear tap negative differential data DNpst2 to the negative driving circuit; wherein, the gate of the twelfth current bias transistor N19 is connected to the twelfth output end of the bias circuit unit, for receiving the positive second rear tap bias signal VPpst2, and the gate of the fourth switch tube S4 is connected to the second output end of the second rear tap data selector, for receiving the second rear tap negative differential data DNpst2.

[0087] Further, the seventh current bias transistor P10 and the tenth current bias transistor P15 can be PMOS current bias transistors, the fifth control pulse transistor P11 and the seventh control pulse transistor P16 can be PMOS control pulse transistors, the eighth current bias transistor N12 and the eleventh current bias transistor N17 can be NMOS current bias transistors, the sixth control pulse transistor N13 and the eighth control pulse transistor N18 can be NMOS control pulse transistors, the ninth current bias transistor N14 and the twelfth current bias transistor N19 can be NMOS current bias transistors, and the third switch tube S3 and the fourth switch tube S4 can be NMOS switch tubes; further, the negative front tap driving circuit 4121 and the negative first rear tap driving circuit 4123 can be SST structures, and the negative main tap driving circuit 4122 and the negative second rear tap driving circuit 4124 can be tailless CML structures. Further, the process of the negative driving circuit generating negative mixed output data is similar to the process of the positive driving circuit generating positive mixed output data, which will not be repeated here.

[0088] The embodiments provided in the present application can respectively obtain various signals generated by the data selector module and the pulse generation module based on the positive driving circuit and the negative driving circuit, pre-emphasize the main tap data based on the front tap equalization pulse and the first rear tap equalization pulse with a code element interval that is a fraction of the main tap data interval, de-emphasize the main tap data based on the second rear tap data with a code element interval that is an integer of the main tap data interval, and finally superimpose to obtain an output signal for output, thereby optimizing the swing of the output signal and significantly improving the signal quality of the output signal. Compared with the traditional integer interval de-emphasis equalization, the fractional interval pre-emphasis equalization can achieve an expandable compensation range and flexibly adjustable equalization, thereby reducing the power consumption of the driver while ensuring a high output swing of the signal.

[0089] Furthermore, Fig.14 (a) shows a circuit schematic diagram of a conventional main tap driving circuit and a conventional first rear tap driving circuit of integer interval de-emphasis equalization. The main tap driving circuit and the first rear tap driving circuit adopt a tailless CML structure. Fig.14 (b) illustrates the equivalent circuit schematic diagram of the main tap driving circuit and the first rear tap driving circuit of the fractional interval pre-emphasis equalization used in the present invention, wherein the main tap driving circuit can refer to the positive main tap driving circuit and the negative main tap driving circuit in the present application, and the first rear tap driving circuit can refer to the positive first rear tap driving circuit and the negative first rear tap driving circuit in the present application; specifically, the main tap driving circuit adopts a tailless CML structure, and the first rear tap driving circuit adopts an SST structure. Next, by analyzing Fig.14 (a) shows a conventional main tap driving circuit and a conventional first rear tap driving circuit of integer interval de-emphasis equalization, and Fig.14 The circuit working principle of the main tap driving circuit and the first rear tap driving circuit of the fractional interval pre-emphasis equalization adopted by the present invention shown in (b) is obtained. Fig.14 (a) and Fig.14 The comparison of output swing and power consumption of the two circuits shown in (b) is used to illustrate the conclusions.

[0090] Furthermore, Fig.15 The swing analysis diagram of FFE based on de-emphasis in the left half shows Fig.14 (a) is the corresponding circuit output swing analysis diagram, Fig.15 The swing analysis diagram of FFE based on pre-emphasis in the right half gives Fig.14 (b) is the corresponding circuit output swing analysis diagram. Specifically, Fig.14 The conventional integer interval de-emphasis circuit for implementing integer interval de-emphasis in (a) outputs a common mode voltage V CM，DE and single-ended output swing SWDE The calculation method of is shown in formula (1):

[0091]

[0092] Among them, V DD is the power supply voltage, I MAIN and I PST1 Represent the current of the main tap driving circuit and the current of the first rear tap driving circuit respectively, R T Indicates the terminal resistance. Minimum output voltage It can be obtained by formula (2):

[0093]

[0094] To ensure Fig.14 The transistor M1 in the circuit works in the saturation region, and the minimum output voltage The conditions that should be met are shown in formula (3):

[0095]

[0096] Among them, VN MAIN and V TH1 Represent the gate voltage and threshold voltage of transistor M1 respectively. Substituting formula (2) into formula (3) yields formula (4):

[0097]

[0098] In contrast, for Fig.14 (b) Example of fractional-interval pre-emphasis circuit, output common-mode voltage V CM,PE and the single-ended output swing AW PE The calculation methods are shown in formula (5):

[0099]

[0100] Comparing formula (1) with formula (5), it can be found that the first rear tap driving circuit of integer interval de-emphasis directly causes the output common mode voltage to decrease due to the tailless CML structure. However, the first rear tap driving circuit of fractional interval pre-emphasis has no effect on the output common mode voltage due to the SST structure, since its pull-up current and pull-down current are statistically equal. Fig.14 (b) The single-ended output swing of the circuit of the example can be expressed as follows:

[0101]

[0102] Combining formula (5) and formula (6), we can get Fig.14 (b) Example of fractionally spaced pre-emphasis circuit ratio Fig.14 (a) The example integer interval de-emphasis circuit has a larger output swing. This conclusion is Fig.15 The above conclusions can be further extended to Fig.12 and forward drive circuit and Fig.13 In the negative driving circuit shown, by adopting the front tap driving circuit and the first rear tap driving circuit with fractional interval pre-emphasis, the hybrid balanced driving circuit can obtain a larger output swing.

[0103] Further, such as Fig.16 A comparative analysis of the normalized power consumption of the pre-emphasis equalization used in this embodiment and the traditional de-emphasis equalization is shown in FIG. Fig.14 (a) The example integer interval de-emphasis circuit adopts a tailless CML structure, and the main tap driving circuit and the first rear tap driving circuit continuously receive power from the power supply V DD The current drawn from the de-emphasis power consumption P DE It can be shown as formula (7):

[0104] P DE =(I MAIN +I PST1 )V DD (7)

[0105] Among them, I MAIN is the main tap driving circuit current, I PST1 is the first rear tap driving circuit current.

[0106] From the above formula (1), it can be seen that when the output swing and power supply voltage of the circuit are fixed, the total current IMAIN+IPST1 is also fixed. Therefore, under different equalization strengths, the power consumption of the integer interval de-emphasis circuit is fixed.

[0107] In contrast, for Fig.14 (b) An example of a fractional-interval pre-emphasis circuit, which uses a tailless CML structure to continuously drive the main tap from the power supply V DD The current is extracted from the circuit. The first rear tap driving circuit using the SST structure realizes intermittent switching under the control of the first negative first rear tap equalizing pulse ENNpst1, the first positive first rear tap equalizing pulse ENPpst1, the second negative first rear tap equalizing pulse EPNpst1 and the second positive first rear tap equalizing pulse EPPpst1 as pre-emphasized equalizing pulses. Mathematical statistical analysis shows that the edge density of the pseudo-random binary sequence is about 50%, that is, the generated pre-emphasized equalizing pulse occupies 50% of the number of input sequence symbols. Since the width of the pre-emphasized equalizing pulse is α PST1UI can be adjusted freely, and the first rear tap driving circuit only draws current from the power supply when the pre-emphasis equalization pulse arrives, so the pre-emphasis power consumption P PE It can be shown as formula (8):

[0108]

[0109] Among them, V DD，PE is the power supply voltage of the front tap driving circuit and the first rear tap driving circuit. Further, a coefficient β=I PST1 / I MAIN , then the equilibrium strength G can be expressed as formula (9):

[0110] G=20log 10 [(1+β)(1-β)] (9)

[0111] By changing β, while ensuring that the total current IMAIN+IPST1 is fixed, and normalizing PPE relative to PDE, the normalized power consumption under different balancing intensities can be obtained as shown in formula (10):

[0112]

[0113] visible, Fig.16 Example of different score coefficients α obtained based on tests PST1 Normalized power consumption curve of pre-emphasis equalization. It can be seen that when the equalization strength and fractional coefficient α PST1 When set to 6dB and 0.5 respectively, fractional interval pre-emphasis equalization can save 18% of power consumption. The above conclusion can be further extended to Fig.12 and Fig.13 In the positive driving circuit and the negative driving circuit shown in FIG. 1 , the front tap driving circuit and the first rear tap driving circuit using fractional interval pre-emphasis have advantages in terms of power consumption. At the same time, as the equalization strength increases, this low power consumption advantage becomes more prominent, and by appropriately reducing the fractional coefficient α PST1 It is also possible to achieve the function of reducing power consumption.

[0114] Further, in Fig.14 (b) Based on the exemplary fractional interval pre-emphasis circuit, the present invention further analyzes the frequency response characteristics of the fractional interval equalization. Here, the first rear tap driving circuit is taken as an example for explanation: Fig.14 (b) The transfer function expression of the circuit of the example is shown in formula (11):

[0115]

[0116] Where β = I PST1 / I MAIN , αPST1 is the fractional coefficient. Further, the amplitude-frequency response function can be obtained as shown in formula (12):

[0117]

[0118] When α PST1 When ωT=π, the amplitude reaches the maximum value, and the corresponding frequency compensation range is shown in formula (13):

[0119]

[0120] From formula (13), we can know that reducing the fractional coefficient α PST1 The frequency compensation range can be effectively improved. Fig.17 Examples are given at different fractional coefficients α PST1 The frequency response curve of the first rear tap driving circuit is shown in Figure 1, where β is taken as 1 / 4. It can be seen that as the fractional coefficient α PST1 The frequency compensation range of the first rear tap driving circuit continues to expand. The above conclusion can be further extended to Fig.12 and Fig.13 In the driving circuit shown in the figure, the front tap driving circuit and the first rear tap driving circuit using fractional interval pre-emphasis can be adjusted by adjusting the corresponding fractional coefficient α PRE and α PST1 To achieve a scalable frequency compensation range that exceeds the compensation range of the Nyquist frequency and flexible and adjustable equalization.

[0121] A transmitter equalization driving circuit provided by the present invention can align and synchronize the received transmission signal based on the serialization and retiming module to obtain multiple parallel data, and transmit each parallel data to multiple data selector modules respectively, and send a preset clock signal corresponding to each parallel data to the data selector module based on a clock module including an equalization pulse width control circuit, so that the data selector module generates front tap data, main tap data, first rear tap data and second rear tap data. Here, the phase difference between the clock signals corresponding to adjacent parallel data can be between 0° and 90°, and the specific phase difference value can be determined in advance, and multiple clock signals are input into the data selector module; at this time, by adjusting the phase difference between the clock signals corresponding to the parallel data, the front tap data, main tap data and second rear tap data generated based on the parallel data can be synchronized. There is a specific phase difference between the front tap data, the main tap data, the first rear tap data and the second rear tap data; further, the front tap data, the main tap data, the first rear tap data and the second rear tap data with the specific phase difference are input into the pulse generation module, and based on the phase difference between the front tap data and the main tap data, a front tap equalization pulse for pre-emphasizing the main tap data is generated, and based on the phase difference between the main tap data and the first rear tap data, a first rear tap equalization pulse for pre-emphasizing the main tap data is generated; further, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data are input into the hybrid equalization driving module, so that the hybrid equalization driving module obtains an output signal that optimizes the signal swing and the output eye diagram, thereby solving the problem of too low signal quality of the transmitting end signal of the existing SerDes system.

[0122] Further, such as Fig.18 As shown, the present application provides a method for processing a signal to be transmitted, which is applied to the above transmitter equalization driving circuit, and the method includes:

[0123] 101. Acquire the signal to be transmitted, perform delay processing on the signal to be transmitted, and obtain front tap data, main tap data, first rear tap data, and second rear tap data respectively corresponding to the signal to be transmitted.

[0124] Among them, the phase difference between the front tap data and the main tap data and between the main tap data and the first rear tap data is a preset fractional code element interval, and the phase difference between the main tap data and the second rear tap data is an integer code element interval; further, the fractional code element interval is a non-integer code element interval.

[0125] Specifically, after the signal to be transmitted passes through the buffer, the signal to be transmitted can be delayed based on clock signals with different phase differences. As an example, the signal to be transmitted can be delayed by a 2UI delay unit to obtain main tap data, and the main tap data can be delayed by a 2UI delay unit to obtain second rear tap data, so that the main tap data and the second rear tap data are separated by an integer symbol interval. The delay effect of the delay unit can be achieved based on the clock signal. Further, (2-α PRE ) The delay unit of UI performs delay processing on the transmitted signal to obtain the front tap data, where α PRE is not an integer, so that the pre-tap data and the main tap data are separated by a fraction of UI; further, by (2-α PST1 ) The delay unit of UI performs delay processing on the main tap data to obtain the first post-tap data, where α PST1 is not an integer, so that the main tap data and the first rear tap data are separated by a fraction of the symbol interval. Here, the front tap data, the main tap data, the first rear tap data, and the second rear tap data can be acquired based on the data selector module.

[0126] 102. Generate a front tap data pre-emphasis pulse based on the phase difference between the front tap data and the main tap data, generate a first rear tap data pre-emphasis pulse based on the phase difference between the main tap data and the first rear tap data, and generate a second rear tap de-emphasis data based on the second rear tap data.

[0127] Specifically, the front tap data and the main tap data can be input into a pulse generation module, and based on the phase difference between the front tap data and the main tap data, a front tap data pre-emphasis pulse is generated; further, the main tap data and the first rear tap data are input into a pulse generation module, and based on the phase difference between the first rear tap data and the main tap data, a first rear tap data pre-emphasis pulse is generated; further, the second rear tap data is input into a hybrid balanced driving module to generate second rear tap de-emphasis data.

[0128] 103. Superimpose the front-tap data pre-emphasis pulse, the first rear-tap data pre-emphasis pulse, the second rear-tap de-emphasis data, and the main tap data to obtain the output signal.

[0129] Specifically, further, the second rear tap de-emphasis data, the front tap data pre-emphasis pulse, the first rear tap data pre-emphasis pulse and the main tap data may be superimposed through a hybrid equalization driving module to obtain an output signal.

[0130] Further, such as Fig.19The schematic diagram of the signal quality enhancement processing of the signal to be transmitted based on the processing method of the signal to be transmitted provided in this embodiment involves a main tap element 30, a front tap element 20 and a first rear tap element 40 using fractional interval pre-emphasis, and a second rear tap element 50 using integer interval de-emphasis. Fig.19 The data to be transmitted before equalization shown in (a) passes through the buffer 10 and (2-α PRE ) UI delay unit 60 gets the front tap data, such as Fig.19 The data to be transmitted before equalization shown in (a) passes through the buffer 10 and the first 2UI delay unit 70 to obtain the main tap data, such as Fig.19 The data to be transmitted before equalization shown in (a) passes through the buffer 10, the first 2UI delay unit 70 and (2+α PST1 ) The first post-tap data is obtained after the delay unit 80 of UI, such as Fig.19 The data to be transmitted before equalization shown in (a) is passed through the buffer 10 and the first 2UI delay unit 70 and the second 2UI delay unit 90 to obtain the second post-tap data. The pre-tap data and the main tap data are passed through the equalization pulse generating circuit to obtain the following: Fig.19 (b) As shown in FIG. 1 , the pre-tap data pre-emphasis pulse PRE of the pre-tap pre-emphasis equalization pulse, the main tap data and the first post-tap data are obtained after passing through the equalization pulse generation circuit. Fig.19 The first post-tap data pre-emphasis pulse PST1 as the first post-tap pre-emphasis equalization pulse shown in (b), and the second post-tap data is obtained after passing through the buffer 10 as shown in Fig.19 (b) shows the second post-tap de-emphasis data PST2. Under the joint action of the pre-tap data pre-emphasis pulse PRE, the first post-tap data pre-emphasis pulse PST1 and the second post-tap de-emphasis data PST2, Fig.19 The main tap data MAIN shown in (b) as the data before equalization is finally superimposed into Fig.19 (b) shows the output data OUT as the output terminal data of the driver. Here, the front tap element 20 corresponds to the positive front tap driving circuit and the negative front tap driving circuit mentioned above, the main tap element 30 corresponds to the positive main tap driving circuit and the negative main tap driving circuit mentioned above, the first rear tap element 40 corresponds to the positive first rear tap driving circuit and the negative first rear tap driving circuit mentioned above, and the second rear tap element 50 corresponds to the positive second rear tap driving circuit and the negative second rear tap driving circuit mentioned above.

[0131] from Fig.19 As can be seen from the waveform diagram in (b), the width of the pre-emphasis equalization pulse in the pre-tap data pre-emphasis pulse PRE is α PRE UI, where α PREIt is determined by the delay between the pre-tap data and the main tap data, and the range of variation is 0 to 1. The width of the pre-emphasized equalization pulse in the first post-tap data pre-emphasized pulse PST1 as shown in 19(b) is α PPST1 UI, where α PPST1 Determined by the delay between the main tap data and the first rear tap data, the range of variation is 0 to 1. By adjusting the delay between the front tap element 20 or the first rear tap element 40 and the main tap element 30, the pre-emphasis equalization pulse width can be flexibly adjusted. The positive front tap driving circuit, the negative front tap driving circuit, the positive first rear tap driving circuit, and the negative first rear tap driving circuit of the hybrid equalization driving module designed in this embodiment use pre-emphasis equalization to increase the high-frequency components of the signal, and the positive second rear tap driving circuit and the negative second rear tap driving circuit use de-emphasis equalization to attenuate the low-frequency components of the signal. The combination of pre-emphasis and de-emphasis equalization can realize the compensation of the low-frequency components and high-frequency components of the signal from many aspects. At the same time, pre-emphasis equalization can make up for the problem of reduced signal output swing caused by de-emphasis equalization. The pre-emphasis equalization adopted by the positive front tap driving circuit, the negative front tap driving circuit, the positive first rear tap driving circuit, and the negative first rear tap driving circuit is based on fractional intervals. By flexibly adjusting the width of the pre-emphasis equalization pulse (the width range is 0-1UI), an expandable compensation range, that is, a compensation range beyond the Nyquist frequency, and flexibly adjustable equalization can be achieved.

[0132] The processing method of the signal to be transmitted provided in this embodiment can be based on a method combining fractional interval pre-emphasis equalization with integer interval de-emphasis equalization, which can achieve a compensation range beyond the Nyquist frequency and comprehensive compensation for the low-frequency and high-frequency components of the transmission signal. At the same time, pre-emphasis equalization can effectively compensate for the problem of reduced output swing caused by de-emphasis equalization. Pre-emphasis equalization controlled by pulses with adjustable width can also further reduce the power consumption of the driver through intermittent operation.

[0133] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform, or by hardware. By applying the technical solution of the present application, first, the signal to be transmitted is obtained, and the signal to be transmitted is delayed to obtain the front tap data, main tap data, first rear tap data and second rear tap data corresponding to the signal to be transmitted respectively; wherein the phase difference between the front tap data and the main tap data and between the main tap data and the first rear tap data is separated by a preset fraction of the symbol interval, and the phase difference between the main tap data and the second rear tap data is separated by an integer bit of the symbol interval; then, based on the phase difference between the front tap data and the main tap data, a front tap data pre-emphasis pulse is generated, and based on the phase difference between the main tap data and the first rear tap data, a first rear tap data pre-emphasis pulse is generated, and based on the second rear tap data, a second rear tap de-emphasis data is generated; finally, the front tap data pre-emphasis pulse, the first rear tap data pre-emphasis pulse, the second rear tap de-emphasis data and the main tap data are superimposed to obtain the output signal. Compared with the prior art, the signal quality of the output signal can be improved.

[0134] Those skilled in the art will appreciate that the accompanying drawings are only schematic diagrams of a preferred implementation scenario, and the modules or processes in the accompanying drawings are not necessarily necessary for implementing the present application. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario can be distributed in the devices of the implementation scenario according to the description of the implementation scenario, or can be changed accordingly and located in one or more devices different from the present implementation scenario. The modules of the above-mentioned implementation scenario can be combined into one module, or can be further split into multiple submodules.

[0135] The above serial numbers of this application are only for description and do not represent the advantages and disadvantages of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of this application, but this application is not limited to them, and any changes that can be thought of by technicians in this field should fall within the scope of protection of this application.

Claims

1. A transmitter equalization driving circuit, applied to a SerDes transmitter, characterized in that: The circuit comprises: A serialization and retiming module, used for receiving a signal to be transmitted and generating multi-channel parallel data corresponding to the signal to be transmitted; A data selector module, the data selector module is connected to the serialization and retiming module, and is used to receive a clock signal corresponding to each channel of the parallel data, and generate front tap data, main tap data, first rear tap data, and second rear tap data based on the multiple channels of parallel data and the clock signal corresponding to each channel of the parallel data; Wherein, the pre-tap data and the main tap data are separated by a preset fractional symbol interval as well as the first post-tap data and the main tap data; A pulse generating module, the pulse generating module is connected to the data selector module, and is used to receive the front tap data, the main tap data and the first rear tap data, and generate a front tap equalized pulse and a first rear tap equalized pulse; A hybrid balanced driving module, the hybrid balanced driving module is connected to the pulse generating module and the data selector module, and is used to receive the front tap balanced pulse, the main tap data, the first rear tap balanced pulse and the second rear tap data, and generate an output signal of the signal to be transmitted.

2. The transmitter equalization driving circuit according to claim 1, characterized in that: The data selector module comprises: A plurality of data selectors, each of which is connected to the serialization and retiming module, and each of which is used to receive one channel of the parallel data and the clock signal corresponding to the parallel data; The plurality of data selectors include a front tap data selector, a main tap data selector, a first rear tap data selector, and a second rear tap data selector, and the parallel data include first parallel data, second parallel data, third parallel data, and fourth parallel data; The front-tap data selector is also connected to the pulse generation module, and is used to receive the first parallel data and a first clock signal corresponding to the first parallel data, generate the front-tap data, and send the front-tap data to the pulse generation module; The main tap data selector is also connected to the hybrid balanced driving module and the pulse generating module, and is used to receive the second parallel data and a second clock signal corresponding to the second parallel data, generate the main tap data, and send the main tap data to the hybrid balanced driving module; The first post-tap data selector is also connected to the pulse generation module, and is used to receive the third parallel data and a third clock signal corresponding to the third parallel data, generate the first post-tap data, and send the first post-tap data to the pulse generation module; The second rear-tap data selector is also connected to the hybrid balanced driving module, and is used to receive the fourth parallel data and a fourth clock signal corresponding to the fourth parallel data, generate the second rear-tap data, and send the second rear-tap data to the hybrid balanced driving module.

3. The transmitter equalization driving circuit according to claim 2, characterized in that: The transmitter balanced driving circuit also includes: A clock module, the clock module is connected to the data selector, and is used to receive the original clock signal, and generate the clock signal corresponding to each parallel data in response to the received clock adjustment instruction, and send the clock signal to the data selector corresponding to the clock signal respectively.

4. The transmitter equalization driving circuit according to claim 2, characterized in that: The pulse generation module comprises: A front tap equalization pulse generating unit, the front tap equalization pulse generating unit is connected to the front tap data selector and the main tap data selector respectively, is used to receive the front tap data and the main tap data, generate the front tap equalization pulse, and send the front tap equalization pulse to the hybrid equalization driving module; A first rear-tap equalizing pulse generating unit, wherein the first rear-tap equalizing pulse generating unit is respectively connected to the main tap data selector and the first rear tap data selector, and is used for receiving the main tap data and the first rear tap data, generating the first rear tap equalizing pulse, and sending the first rear tap equalizing pulse to the hybrid equalizing driving module.

5. The transmitter equalization driving circuit according to claim 3, characterized in that: The front tap data includes front tap positive differential data and front tap negative differential data, and the main tap data includes main tap positive differential data and main tap negative differential data; The front tap equalizing pulse includes: a first positive front tap equalizing pulse, a first negative front tap equalizing pulse, a second positive front tap equalizing pulse and a second negative front tap equalizing pulse; The front tap equalization pulse generating unit comprises a first AND gate and a first OR gate, wherein the first input end of the first AND gate and the first input end of the first OR gate are respectively connected to the first output end of the front tap data selector for receiving the front tap positive differential data, the second input end of the first AND gate and the second input end of the first OR gate are respectively connected to the first output end of the main tap data selector for receiving the main tap negative differential data, the output end of the first AND gate is connected to the hybrid equalization driving module for sending the first positive front tap equalization pulse to the hybrid equalization driving module, and the output end of the first OR gate is connected to the hybrid equalization driving module for sending the first negative front tap equalization pulse to the hybrid equalization driving module; The front tap equalization pulse generating unit also includes a second AND gate and a second OR gate, wherein the first input end of the second AND gate and the first input end of the second OR gate are respectively connected to the second output end of the front tap data selector for receiving the front tap negative differential data, the second input end of the second AND gate and the second input end of the second OR gate are respectively connected to the second output end of the main tap data selector for receiving the main tap positive differential data, the output end of the second AND gate is connected to the hybrid equalization driving module for sending the second positive front tap equalization pulse to the hybrid equalization driving module, and the output end of the second OR gate is connected to the hybrid equalization driving module for sending the second negative front tap equalization pulse to the hybrid equalization driving module.

6. The transmitter equalization driving circuit according to claim 5, characterized in that: The first rear tap data includes first rear tap positive differential data and first rear tap negative differential data; The second rear tap data includes second rear tap positive differential data and second rear tap negative differential data; The first rear-tap equalizing pulse includes: a first positive first rear-tap equalizing pulse (ENPpst1), a first negative first rear-tap equalizing pulse, a second positive first rear-tap equalizing pulse and a second negative first rear-tap equalizing pulse; The first rear-tap equalization pulse generating unit comprises a third AND gate and a third OR gate, wherein the first input end of the third AND gate and the first input end of the third OR gate are respectively connected to the first output end of the first rear-tap data selector for receiving the first rear-tap positive differential data, the second input end of the third AND gate and the second input end of the third OR gate are respectively connected to the first output end of the main tap data selector for receiving the main tap negative differential data, the output end of the third AND gate is connected to the hybrid equalization driving module for sending the first positive first rear-tap equalization pulse to the hybrid equalization driving module, and the output end of the third OR gate is connected to the hybrid equalization driving module for sending the first negative first rear-tap equalization pulse to the hybrid equalization driving module; The first rear-tap equalizing pulse generating unit also includes a fourth AND gate and a fourth OR gate, wherein the first input end of the fourth AND gate and the first input end of the fourth OR gate are respectively connected to the second output end of the first rear-tap data selector for receiving the first rear-tap negative differential data, the second input end of the fourth AND gate and the second input end of the fourth OR gate are respectively connected to the second output end of the main tap data selector for receiving the main tap positive differential data, the output end of the fourth AND gate is connected to the hybrid equalizing driving module for sending the second positive first rear-tap equalizing pulse to the hybrid equalizing driving module, and the output end of the fourth OR gate is connected to the hybrid equalizing driving module for sending the second negative first rear-tap equalizing pulse to the hybrid equalizing driving module.

7. The transmitter equalization driving circuit according to claim 6, characterized in that: The hybrid balanced driving module comprises: A hybrid balanced driving unit, the hybrid balanced driving unit is connected to the pulse generating module and the data selector module, and is used to receive the front tap balanced pulse, the main tap data, the first rear tap balanced pulse and the second rear tap data, and generate an output signal of the signal to be transmitted; A bias circuit unit is connected to the hybrid balanced driving unit and is used to generate and send a bias signal for controlling the amplitude of the output signal to the hybrid balanced driving unit in response to a received signal amplitude instruction.

8. The transmitter equalization driving circuit according to claim 7, characterized in that: The bias signal includes a positive forward tap bias signal, a negative forward tap bias signal, a positive main tap bias signal, a negative main tap bias signal, a positive first rear tap bias signal, a negative first rear tap bias signal, a positive second rear tap bias signal, and a negative second rear tap bias signal; The hybrid balanced driving unit comprises: A forward drive circuit, wherein the forward drive circuit comprises a plurality of forward sub-circuits, each of the forward sub-circuits being connected via a forward circuit connection point arranged on each of the forward sub-circuits, the forward sub-circuit comprising a forward front tap drive circuit, a forward main tap drive circuit, a forward first rear tap drive circuit and a forward second rear tap drive circuit, wherein the forward main tap drive circuit is provided with a forward signal output terminal; The forward driving circuit is used to receive the first positive forward tap equalizing pulse, the main tap negative differential data, the first positive first rear tap equalizing pulse, the second rear tap positive differential data, the positive forward tap bias signal, the negative forward tap bias signal, the negative main tap bias signal, the positive first rear tap bias signal, the negative first rear tap bias signal, the negative second rear tap bias signal, the first negative first rear tap equalizing pulse and the first negative forward tap equalizing pulse, and generate forward mixed output data; The hybrid balanced driving unit also includes: A negative driving circuit, wherein the negative driving circuit comprises a plurality of negative sub-circuits, each of the negative sub-circuits being connected via a negative circuit connection point arranged on each of the negative sub-circuits, the negative sub-circuits comprising a negative front tap driving circuit, a negative main tap driving circuit, a negative first rear tap driving circuit and a negative second rear tap driving circuit, wherein the negative main tap driving circuit is provided with a negative signal output terminal; The negative driving circuit is used to receive the second positive forward tap equalizing pulse, the main tap positive differential data, the second positive first rear tap equalizing pulse, the second rear tap negative differential data, the positive forward tap bias signal, the negative forward tap bias signal, the positive main tap bias signal, the positive first rear tap bias signal, the negative first rear tap bias signal, the positive second rear tap bias signal, the second negative first rear tap equalizing pulse and the second negative forward tap equalizing pulse to generate negative mixed output data; The hybrid balanced driving unit also includes: A signal output circuit is connected to the positive signal output terminal and the negative signal output terminal, and is used to generate the output signal based on the positive mixed output data and the negative mixed output data.

9. The transmitter equalization driving circuit according to claim 8, characterized in that: The forward tap driving circuit comprises a first resistor and a first current bias transistor, a first control pulse transistor, a second current bias transistor and a second control pulse transistor connected in series, the source of the first current bias transistor is connected to a first power supply, the drain of the first current bias transistor is connected to the source of the first control pulse transistor, the drain of the first control pulse transistor is connected to the drain of the second current bias transistor, the source of the second current bias transistor is connected to the drain of the second control pulse transistor, the first resistor is connected in parallel between the source and drain of the second control pulse transistor, the source of the second control pulse transistor is grounded, the forward circuit connection point is arranged between the first control pulse transistor and the second current bias transistor, and the forward tap driving circuit is used to connect the positive forward tap bias signal, the negative forward tap bias signal, the first negative forward tap equalizing pulse and the first positive forward tap equalizing pulse to the forward driving circuit; The forward main tap driving circuit comprises a second resistor, a first terminal resistor, and a third current bias transistor and a first switch tube connected in series, wherein the first end of the first terminal resistor is connected to the second power supply, the second end of the first terminal resistor is connected to the drain of the third current bias transistor, the source of the third current bias transistor is connected to the drain of the first switch tube, the second resistor is connected in parallel between the source and the drain of the first switch tube, the source of the first switch tube is grounded, the forward signal output end is arranged at the second end of the first terminal resistor, the forward circuit connection point is arranged between the forward signal output end and the third current bias transistor, and the forward main tap driving circuit is used to connect the negative main tap bias signal and the main tap negative differential data to the forward driving circuit; The forward first rear-tap driving circuit comprises a third resistor and a fourth current bias transistor, a third control pulse transistor, a fifth current bias transistor and a fourth control pulse transistor connected in series, the source of the fourth current bias transistor is connected to a third power supply, the drain of the fourth current bias transistor is connected to the source of the third control pulse transistor, the drain of the third control pulse transistor is connected to the drain of the fifth current bias transistor, the source of the fifth current bias transistor is connected to the drain of the fourth control pulse transistor, the third resistor is connected in parallel between the source and the drain of the fourth control pulse transistor, the source of the fourth control pulse transistor is grounded, the forward circuit connection point is set between the third control pulse transistor and the fifth current bias transistor, and the forward first rear-tap driving circuit is used to connect the forward first rear-tap bias signal, the negative first rear-tap bias signal, the first negative first rear-tap equalizing pulse and the first positive first rear-tap equalizing pulse to the forward driving circuit; The forward second rear tap driving circuit includes a fourth resistor and a sixth current bias transistor and a second switch tube connected in series. The forward circuit connection point is set at the drain of the sixth current bias transistor. The source of the sixth current bias transistor is connected to the drain of the second switch tube. The fourth resistor is connected in parallel between the source and the drain of the second switch tube. The source of the second switch tube is grounded. The forward second rear tap driving circuit is used to connect the negative second rear tap bias signal and the second rear tap positive differential data to the forward driving circuit.

10. The transmitter equalization driving circuit according to claim 8, characterized in that: The negative forward tap driving circuit comprises a fifth resistor and a seventh current bias transistor, a fifth control pulse transistor, an eighth current bias transistor and a sixth control pulse transistor connected in series, the source of the seventh current bias transistor is connected to a fourth power supply, the drain of the seventh current bias transistor is connected to the source of the fifth control pulse transistor, the drain of the fifth control pulse transistor is connected to the drain of the eighth current bias transistor, the source of the eighth current bias transistor is connected to the drain of the sixth control pulse transistor, the fifth resistor is connected in parallel between the source and the drain of the sixth control pulse transistor, the source of the sixth control pulse transistor is grounded, the negative circuit connection point is set between the fifth control pulse transistor and the eighth current bias transistor, and the negative forward tap driving circuit is used to connect the positive forward tap bias signal, the negative forward tap bias signal, the second negative forward tap equalizing pulse and the second negative forward tap equalizing pulse to the negative driving circuit; The negative main tap driving circuit includes a sixth resistor, a second terminal resistor, and a ninth current bias transistor and a third switch tube connected in series, wherein the first end of the second terminal resistor is connected to the sixth power supply, the second end of the second terminal resistor is connected to the drain of the ninth current bias transistor, the source of the ninth current bias transistor is connected to the drain of the third switch tube, the sixth resistor is connected in parallel between the source and the drain of the third switch tube, the source of the third switch tube is grounded, the negative circuit connection point is arranged between the ninth current bias transistor and the second terminal resistor, and the negative main tap driving circuit is used to connect the positive main tap bias signal and the main tap positive differential data to the negative driving circuit; The negative first rear tap driving circuit includes a seventh resistor and a tenth current bias transistor, a seventh control pulse transistor, an eleventh current bias transistor and an eighth control pulse transistor connected in series, the source of the tenth current bias transistor is connected to a sixth power supply, the drain of the tenth current bias transistor is connected to the source of the seventh control pulse transistor, the drain of the seventh control pulse transistor is connected to the drain of the eleventh current bias transistor, the source of the eleventh current bias transistor is connected to the drain of the eighth control pulse transistor, the seventh resistor is connected in parallel between the source and the drain of the eighth control pulse transistor, the source of the eighth control pulse transistor is grounded, the negative circuit connection point is set between the seventh control pulse transistor and the eleventh current bias transistor, and the negative first rear tap driving circuit is used to connect the second negative first rear tap equalizing pulse, the second positive first rear tap equalizing pulse, the positive first rear tap bias signal and the negative first rear tap bias signal to the negative driving circuit; The negative second rear tap driving circuit includes an eighth resistor and a twelfth current bias transistor and a fourth switch tube connected in series. The negative circuit connection point is set at the drain of the twelfth current bias transistor. The source of the twelfth current bias transistor is connected to the drain of the fourth switch tube. The eighth resistor is connected in parallel between the source and the drain of the fourth switch tube. The source of the fourth switch tube is grounded. The negative second rear tap driving circuit is used to connect the positive second rear tap bias signal and the second rear tap negative differential data to the negative driving circuit.

11. A method for processing a signal to be transmitted, characterized in that: The method is applied to the transmitter equalization driving circuit according to any one of claims 1 to 10, and the method comprises: Acquire the signal to be transmitted, perform delay processing on the signal to be transmitted, and obtain front tap data, main tap data, first rear tap data, and second rear tap data respectively corresponding to the signal to be transmitted; The phase difference between the front tap data and the main tap data and between the main tap data and the first rear tap data is a preset fractional symbol interval, and the phase difference between the main tap data and the second rear tap data is an integer symbol interval; Generate a pre-tap data pre-emphasis pulse based on a phase difference between the pre-tap data and the main tap data, generate a first rear-tap data pre-emphasis pulse based on a phase difference between the main tap data and the first rear-tap data, and generate a second rear-tap de-emphasis data based on the second rear-tap data; The front tap data pre-emphasis pulse, the first rear tap data pre-emphasis pulse, the second rear tap de-emphasis data and the main tap data are superimposed to obtain the output signal.

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