Transceiver anomaly detection system and anomaly detection method

Abstract

The invention discloses an anomaly detection system and anomaly detection method for a transceiver, the system comprises a baseband chip and the transceiver which are in communication connection, and the baseband chip generates a first detection instruction when meeting an anomaly detection condition; the transceiver responds to the first detection instruction to construct a first detection loop used for transmitting a local oscillator signal, and the first detection loop comprises a receiving channel in the transceiver; the baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal; the transceiver responds to the second detection instruction to construct a second detection loop comprising any first to-be-detected device in the receiving channel; and the baseband chip generates a first detection result used for representing that the first to-be-detected device is abnormal according to the reference digital signal and the first digital signal transmitted by the second detection loop. Through the method, the combination of channel-level and unit-level anomaly detection is realized, when the transceiver is abnormal, the abnormal position is accurately positioned, and the stability and reliability of a communication system are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission and testing, and in particular to an abnormality detection system and an abnormality detection method for a transceiver. Background Art

[0002] In the related art, since the transceiver is easy to recycle, it is only necessary to detect the abnormal type without accurately locating the abnormal position. The abnormal transceiver can be subsequently recycled and returned to the factory for repair.

[0003] However, the transceiver detection method in the related art cannot meet the detection requirements for transceivers that are difficult to recover intact, such as transceivers mounted on ocean buoys. Summary of the invention

[0004] The present invention provides a transceiver abnormality detection system and an abnormality detection method, which are used to solve the problem that the transceiver abnormality detection method in the prior art can only realize remote channel level detection and therefore cannot meet the detection requirements of transceivers that are difficult to recover intact.

[0005] In a first aspect, an embodiment of the present invention provides a transceiver abnormality detection system, including a baseband chip and a transceiver in communication connection, wherein:

[0006] The transceiver constructs a first detection loop for transmitting a local oscillator signal in response to a first detection instruction, wherein the first detection instruction is generated by the baseband chip when an abnormal detection condition is met, and the first detection loop includes a receiving channel in the transceiver;

[0007] In response to a second detection instruction, the transceiver constructs a second detection loop including any one of the first devices under test in the receiving channel, so that the baseband chip generates a first detection result for characterizing an abnormality of the first device under test based on a reference clock signal and a first digital signal transmitted by the second detection loop, wherein the second detection instruction is generated by the baseband chip based on the reference clock signal and the local oscillator signal.

[0008] In the transceiver abnormality detection system provided by the embodiment of the present invention, when the abnormality detection condition is met, the baseband chip generates a first detection instruction for controlling the transceiver to perform abnormality detection, and receives the local oscillator signal transmitted in the first detection loop constructed by the transceiver through the first detection instruction. Since the first detection loop includes a receiving channel, by comparing the local oscillator signal and the reference clock signal, channel-level transceiver abnormality detection can be achieved, that is, whether the receiving channel in the first detection loop is abnormal can be detected; in addition, after determining that the receiving channel is abnormal, a second detection instruction for controlling the transceiver to construct a second detection loop is generated. Since the second detection loop includes any one of the first devices under test in the receiving channel, by comparing the first digital signal transmitted by the second detection loop with the reference digital signal, unit-level transceiver abnormality detection can be achieved, that is, whether the first device under test in the receiving channel is abnormal can be detected. Through the above method, the combination of channel-level abnormality detection and unit-level abnormality detection is realized, so that when the transceiver is abnormal, the abnormal position can be more accurately located, the efficiency of abnormal location is improved, and the stability and reliability of the communication system are enhanced.

[0009] In an optional implementation, the transceiver further includes a digital front end, a transmission channel, a detection unit and a clock unit, wherein:

[0010] The receiving channel, the digital front end and the transmitting channel are electrically connected in sequence, the detection unit is electrically connected to the digital front end, the receiving channel, the transmitting channel and the clock unit respectively, and the clock unit is electrically connected to the receiving channel and the transmitting channel respectively;

[0011] The first detection loop is constructed in the following way:

[0012] The transceiver parses the first detection instruction through the digital front end to obtain a first control signal;

[0013] The transceiver, through the detection unit, under the control of the first control signal, conducts a path between the output end of the clock unit and the input end of the receiving channel to construct the first detection loop.

[0014] In the above system, under the control of the first control signal obtained by parsing the first detection instruction, the transceiver turns on the path between the output end of the clock unit and the input end of the receiving channel to realize the construction of the first detection loop. The local oscillator signal output by the clock unit is transmitted to the baseband chip through the first detection loop, so that the baseband chip determines whether the path for transmitting the local oscillator signal is abnormal based on the received local oscillator signal, thereby realizing channel-level abnormality detection of the transceiver.

[0015] In an optional implementation, the transceiver further includes a storage unit, which is electrically connected to the digital front end, wherein:

[0016] The first control signal is obtained by:

[0017] The transceiver parses the first detection instruction through the digital front end to obtain a first detection mode;

[0018] The transceiver determines the first control signal through the digital front end according to the first detection mode and based on the corresponding relationship between the detection mode and the control signal stored in the storage unit.

[0019] In an optional implementation, the second detection loop is constructed in the following manner:

[0020] The transceiver parses the second detection instruction through the digital front end to obtain a second control signal;

[0021] The transceiver, through the detection unit, under the control of the second control signal, sequentially conducts the paths between the multiple detection ends of the receiving channel and the detection reference end of the transmitting channel to construct the second detection loop;

[0022] Among them, the detection reference end of the transmitting channel is a detection end among the multiple detection ends of the transmitting channel that is closest to the output end of the transmitting channel, or any detection end among the other detection ends, and the other detection end is a detection end among the multiple detection ends of the transmitting channel except the detection end that is closest to the output end of the transmitting channel.

[0023] In the above system, the transceiver, under the control of the second control signal obtained by parsing the second detection instruction, respectively turns on the paths between the different detection ends of the receiving channel and the detection reference end of the transmitting channel to realize the construction of the second detection loop, and sends the first digital signal transmitted through the second detection loop to the baseband chip, so that the baseband chip determines whether the first device under test in the path for transmitting the first digital signal is abnormal based on the received first digital signal, thereby realizing unit-level abnormality detection of the transceiver.

[0024] In an optional implementation manner, the second control signal is obtained in the following manner:

[0025] The transceiver parses the second detection instruction through the digital front end to obtain a second detection mode;

[0026] The transceiver determines the second control signal through the digital front end according to the second detection mode and based on the corresponding relationship between the detection mode and the control signal.

[0027] In an optional implementation, the second detection instruction is generated in the following manner:

[0028] The baseband chip calculates the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculates the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0029] When the baseband chip detects that the first frequency difference is not within a first preset frequency threshold range, or the first power difference is not within a first power threshold range, the second detection instruction is generated.

[0030] In an optional implementation, the first detection result is generated in the following manner:

[0031] The baseband chip calculates a difference between a frequency value of the first digital signal and a frequency value of the reference digital signal to obtain a second frequency difference, and calculates a difference between a power value of the first digital signal and a power value of the reference digital signal to obtain a second power difference;

[0032] When the baseband chip detects that the second frequency difference is not within a second preset frequency threshold range, or the second power difference is not within a second power threshold range, the first detection result is generated.

[0033] In an optional implementation, the transceiver is further used for:

[0034] The transceiver constructs a third detection loop for transmitting a second digital signal in response to a third detection instruction, wherein the third detection loop includes a transmission channel corresponding to the receiving channel in the first detection loop, and the third detection instruction is generated by the baseband chip when it is detected that the first frequency difference is within the first preset frequency threshold range and the first power difference is within the first power threshold range;

[0035] In response to a fourth detection instruction, the transceiver constructs a fourth detection loop including any one second device under test in the transmission channel, so that the baseband chip generates a second detection result for characterizing the abnormality of the second device under test based on the reference digital signal and the third digital signal transmitted by the fourth detection loop, wherein the fourth detection instruction is generated by the baseband chip based on the reference digital signal and the second digital signal.

[0036] In the above system, after the baseband chip detects that the receiving channel is normal, a third detection instruction is generated for controlling the transceiver to construct a third detection loop. Since the third detection loop includes a transmitting channel corresponding to the receiving channel, by comparing the second digital signal transmitted by the third detection loop with the reference digital signal, channel-level transceiver abnormality detection can be achieved, that is, whether the transmitting channel in the third detection loop is abnormal can be detected; in addition, after determining that the transmitting channel is abnormal, a fourth detection instruction is generated for controlling the transceiver to construct a fourth detection loop. Since the fourth detection loop includes any second device under test in the transmitting channel, by comparing the third digital signal transmitted by the fourth detection loop with the reference digital signal, unit-level transceiver abnormality detection can be achieved, that is, whether the second device under test in the transmitting channel is abnormal can be detected. Through the above method, the combination of channel-level abnormality detection and unit-level abnormality detection is achieved, so that when the transceiver is abnormal, the abnormal position can be more accurately located, the efficiency of abnormal location is improved, and the stability and reliability of the communication system are enhanced.

[0037] In an optional implementation, the third detection loop is constructed in the following manner:

[0038] The transceiver parses the third detection instruction through the digital front end to obtain a third control signal;

[0039] The transceiver, through the detection unit, under the control of the third control signal, conducts the path between the output end of the transmission channel and the input end of the reception channel to construct the third detection loop.

[0040] In the above system, the transceiver, under the control of the third control signal obtained by parsing the third detection instruction, turns on the path between the output end of the transmitting unit and the input end of the receiving channel to realize the construction of the third detection loop, and transmits the second digital signal transmitted by the third detection loop to the baseband chip, so that the baseband chip determines whether there is an abnormality in the transmission of the transmitting channel based on the received second digital signal, thereby realizing channel-level abnormality detection of the transceiver.

[0041] In an optional implementation manner, the third control signal is obtained in the following manner:

[0042] The transceiver parses the third detection instruction through the digital front end to obtain a third detection mode;

[0043] The transceiver determines the third control signal through the digital front end according to the third detection mode and based on the corresponding relationship between the detection mode and the control signal.

[0044] In an optional implementation, the fourth detection loop is constructed in the following manner:

[0045] The transceiver parses the fourth detection instruction through the digital front end to obtain a fourth control signal;

[0046] The transceiver, through the detection unit, under the control of the fourth control signal, sequentially conducts the paths between the multiple detection ends of the transmission channel and the detection reference end of the receiving channel to construct the fourth detection loop;

[0047] Among them, the detection reference end of the receiving channel is a detection end among the multiple detection ends of the receiving channel that is closest to the input end of the receiving channel, or any detection end among the other detection ends, and the other detection end is a detection end among the multiple detection ends of the receiving channel except the detection end that is closest to the input end of the receiving channel.

[0048] In the above system, the transceiver, under the control of the fourth control signal obtained by parsing the fourth detection instruction, respectively turns on the paths between different detection ends of the transmission channel and the detection reference end of the receiving channel to realize the construction of the fourth detection loop, and sends the third digital signal transmitted through the fourth detection loop to the baseband chip, so that the baseband chip determines whether the second device under test in the transmission path is abnormal based on the received third digital signal, thereby realizing unit-level abnormality detection of the transceiver.

[0049] In an optional implementation manner, the fourth control signal is obtained in the following manner:

[0050] The transceiver parses the fourth detection instruction through the digital front end to obtain a fourth detection mode;

[0051] The transceiver determines the fourth control signal through the digital front end according to the fourth detection mode and based on the corresponding relationship between the detection mode and the control signal.

[0052] In an optional implementation, the fourth detection instruction is generated in the following manner:

[0053] The baseband chip calculates a difference between a frequency value of the second digital signal and a frequency value of the reference digital signal to obtain a third frequency difference, and calculates a difference between a power value of the second digital signal and a power value of the reference digital signal to obtain a third power difference;

[0054] When the baseband chip detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, the fourth detection is generated.

[0055] In an optional implementation, the second detection result is generated in the following manner:

[0056] The baseband chip calculates a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculates a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference;

[0057] When the baseband chip detects that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, the second detection result is generated.

[0058] In an optional implementation, after the transceiver constructs the first detection loop for transmitting the local oscillator signal and before responding to the second detection instruction, it is further used to:

[0059] The detection signal sent by the baseband chip is received through the digital front end, and the loopback signal is generated according to the detection signal, so that the baseband chip receives the loopback signal.

[0060] In the above system, after determining that there is an abnormality in the first detection loop, the baseband chip sends a detection signal to the digital front end in the transceiver. If the baseband chip receives a loopback signal generated by the digital front end based on the detection signal, it means that the digital front end is normal. If the baseband chip does not receive the loopback signal generated by the digital front end based on the detection signal, it means that there is an abnormality in the digital front end, thereby determining the location of the abnormal device in the transceiver and realizing unit-level abnormality detection of the transceiver.

[0061] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0062] The baseband chip receives a message signal for indicating that data reception by the external device is abnormal;

[0063] The frequency error of the baseband chip receiving data is greater than a preset error threshold;

[0064] The number of times that the baseband chip fails to verify data is greater than a preset number threshold;

[0065] The baseband chip detects that a preset time threshold is reached.

[0066] In an optional implementation, the receiving channel includes a first amplifier, a first mixer, a first filter, a first automatic gain controller and an analog-to-digital converter electrically connected in sequence, wherein:

[0067] The input end of the first amplifier serves as the input end of the receiving channel, the output end of the analog-to-digital converter serves as the output end of the receiving channel, and the clock end of the first mixer is electrically connected to the first output end of the clock unit;

[0068] The output end of the first amplifier, the output end of the first mixer, the output end of the first filter and the output end of the first automatic gain controller serve as multiple detection ends of the receiving channel;

[0069] The transmitting channel includes a digital-to-analog converter, a second automatic gain controller, a second filter, a second mixer and a second amplifier which are electrically connected in sequence, wherein:

[0070] The input end of the digital-to-analog converter serves as the input end of the transmitting channel, the output end of the second amplifier serves as the output end of the transmitting channel, and the clock end of the second mixer is electrically connected to the second output end of the clock unit;

[0071] The output end of the digital-to-analog converter, the output end of the second automatic gain controller, the output end of the second filter and the output end of the second mixer serve as multiple detection ends of the transmission channel.

[0072] In an optional implementation, the detection unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a transmitting auxiliary interface, a receiving auxiliary interface, a first attenuator, and a second attenuator, wherein:

[0073] A first end of the first switch is electrically connected to an output end of the first amplifier, a second end of the first switch is electrically connected to a third output end of the clock unit, a first end of the second switch is electrically connected to an output end of the first mixer, a first end of the third switch is electrically connected to an output end of the first filter, and a first end of the fourth switch is electrically connected to an output end of the first automatic gain controller;

[0074] The third end of the first switch, the fourth end of the first switch, the second end of the second switch, the second end of the third switch and the second end of the fourth switch are all electrically connected to the output end of the auxiliary receiving interface, and the input end of the auxiliary receiving interface is electrically connected to the output end of the first attenuator;

[0075] A first end of the fifth switch is electrically connected to the output end of the digital-to-analog converter, a first end of the sixth switch is electrically connected to the output end of the second automatic gain controller, a first end of the seventh switch is electrically connected to the output end of the second filter, a first end of the eighth switch is electrically connected to the output end of the second mixer, and a second end of the eighth switch is electrically connected to the fourth output end of the clock unit;

[0076] The second end of the fifth switch, the second end of the sixth switch, the second end of the seventh switch, the third end of the eighth switch and the fourth end of the eighth switch are all electrically connected to the input end of the transmission auxiliary interface, and the output end of the transmission auxiliary interface is electrically connected to the input end of the first attenuator;

[0077] A first end of the ninth switch is electrically connected to an input end of the first amplifier, a second end of the ninth switch is electrically connected to an output end of the second attenuator, and a third end of the ninth switch is electrically connected to a receiving end of the transceiver;

[0078] A first end of the tenth switch is electrically connected to the output end of the second amplifier, a second end of the tenth switch is electrically connected to the first end of the eleventh switch, and a third end of the tenth switch serves as a transmitting end of the transceiver;

[0079] The second end of the eleventh switch is electrically connected to the fifth output end of the clock unit, and the third end of the eleventh switch is electrically connected to the input end of the second attenuator;

[0080] The first controlled end of the first switch, the second controlled end of the first switch, the controlled end of the second switch, the controlled end of the third switch, the controlled end of the fourth switch, the controlled end of the fifth switch, the controlled end of the sixth switch, the controlled end of the seventh switch, the first controlled end of the eighth switch, the second controlled end of the eighth switch, the controlled end of the ninth switch, the controlled end of the tenth switch and the controlled end of the eleventh switch are all electrically connected to the control end of the digital front end.

[0081] The above system controls the closing of different switches in the detection unit to realize the construction of different detection loops, thereby realizing abnormal detection of the channel or the device under test in the constructed detection loop, and then more accurately locating the abnormal position when an abnormality occurs in the transceiver, improving the efficiency of abnormality locating, and enhancing the stability and reliability of the communication system.

[0082] In a second aspect, an embodiment of the present invention provides a method for detecting an abnormality of a transceiver, which is applied to an abnormality detection system of a transceiver as described in any one of the first aspects above, and the method includes:

[0083] When the abnormal detection condition is met, the baseband chip generates a first detection instruction, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver;

[0084] The baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one of the first devices under test in the receiving channel, wherein the second detection loop is used to transmit the first digital signal;

[0085] The baseband chip generates a first detection result for characterizing an abnormality of the first device under test according to a reference digital signal and the first digital signal.

[0086] In an optional implementation, the baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal, including:

[0087] The baseband chip calculates the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculates the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0088] When the baseband chip detects that the first frequency difference is not within a first preset frequency threshold range, or the first power difference is not within a first power threshold range, the second detection instruction is generated.

[0089] In an optional implementation manner, the baseband chip generates a first detection result for characterizing that the first device under test is abnormal according to the reference digital signal and the first digital signal, including:

[0090] The baseband chip calculates a difference between a frequency value of the first digital signal and a frequency value of the reference digital signal to obtain a second frequency difference, and calculates a difference between a power value of the first digital signal and a power value of the reference digital signal to obtain a second power difference;

[0091] When the baseband chip detects that the second frequency difference is not within a second preset frequency threshold range, or the second power difference is not within a second power threshold range, the first detection result is generated.

[0092] In an optional embodiment, the method further includes:

[0093] When detecting that the first frequency difference is within the first preset frequency threshold range and the first power difference is within the first power threshold range, the baseband chip generates a third detection instruction, so that the transceiver responds to the third detection instruction and constructs a third detection loop for transmitting a second digital signal, wherein the third detection loop includes a transmission channel corresponding to the reception channel in the first detection loop;

[0094] The baseband chip generates a fourth detection instruction according to the reference digital signal and the second digital signal, so that the transceiver responds to the fourth detection instruction and constructs a fourth detection loop including any second device under test in the transmission channel, wherein the fourth detection loop is used to transmit the third digital signal;

[0095] The baseband chip generates a second detection result for characterizing that the second device under test is abnormal according to the reference digital signal and the third digital signal.

[0096] In an optional implementation manner, the baseband chip generates a fourth detection instruction according to the reference digital signal and the second digital signal, including:

[0097] The baseband chip calculates a difference between a frequency value of the second digital signal and a frequency value of the reference digital signal to obtain a third frequency difference, and calculates a difference between a power value of the second digital signal and a power value of the reference digital signal to obtain a third power difference;

[0098] When the baseband chip detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, the fourth detection instruction is generated.

[0099] In an optional implementation, the baseband chip generates a second detection result for characterizing that the second device under test is abnormal according to the reference digital signal and the third digital signal, including:

[0100] The baseband chip calculates a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculates a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference;

[0101] When the baseband chip detects that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, the second detection result is generated.

[0102] In an optional implementation, after the baseband chip generates the first detection instruction and before generating the second detection instruction, the baseband chip further includes:

[0103] Sending a detection signal to the transceiver so that the transceiver generates the loopback signal according to the detection signal;

[0104] The loopback signal is received.

[0105] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0106] The baseband chip receives a message signal for indicating that data reception by the external device is abnormal;

[0107] The frequency error of the baseband chip receiving data is greater than a preset error threshold;

[0108] The number of times that the baseband chip fails to verify data is greater than a preset number threshold;

[0109] The baseband chip detects that a preset time threshold is reached.

[0110] In a third aspect, an embodiment of the present invention provides a transceiver abnormality detection device, which is applied to the transceiver abnormality detection system as described in any one of the first aspects above, and the device includes:

[0111] A first processing module, configured to generate a first detection instruction when an abnormal detection condition is met, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver;

[0112] A second processing module, configured to generate a second detection instruction according to a reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one first device under test in the receiving channel, wherein the second detection loop is used to transmit a first digital signal;

[0113] The third processing module is used to generate a first detection result for characterizing that the first device under test is abnormal according to a reference digital signal and the first digital signal.

[0114] In a fourth aspect, an embodiment of the present invention provides a baseband chip, applied to the abnormality detection system of the transceiver as described in any one of the first aspects above, the baseband chip comprising:

[0115] A memory for storing executable instructions;

[0116] A processor is used to read and execute the executable instructions stored in the memory to implement the steps of the transceiver abnormality detection method as described in any one of the embodiments of the second aspect above.

[0117] For the technical effects that may be achieved by the transceiver abnormality detection method disclosed in the second aspect, the transceiver abnormality detection device disclosed in the third aspect, and the baseband chip disclosed in the fourth aspect, please refer to the technical effects that can be achieved by the first aspect or various possible schemes in the first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0119] Figure 1 A schematic diagram of the structure of an abnormality detection system for a transceiver provided by an embodiment of the present invention;

[0120] Figure 2 A schematic diagram of the circuit structure of an abnormality detection system for a transceiver provided by an embodiment of the present invention;

[0121] Figure 3 A schematic diagram of the working process of a transceiver abnormality detection system provided by an embodiment of the present invention;

[0122] Figure 4 A schematic diagram of the structure of a first detection loop in an abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0123] Figure 5 A schematic diagram of the structure of a second detection loop in an abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0124] Figure 6 A schematic diagram of the structure of a second detection loop in another abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0125] Figure 7 A schematic diagram of the structure of a second detection loop in another abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0126] Figure 8 A schematic diagram of the structure of a second detection loop in another abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0127] Fig. 9A schematic diagram of the structure of a third detection loop in an abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0128] Fig.10 A schematic diagram of the structure of a fourth detection loop in an abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0129] Fig.11 A schematic diagram of the structure of a fourth detection loop in another abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0130] Fig.12 A schematic diagram of the structure of a fourth detection loop in another abnormality detection system of a transceiver provided by an embodiment of the present invention;

[0131] Fig.13 A schematic diagram of a complete working process of an abnormality detection system for a transceiver provided by an embodiment of the present invention;

[0132] Fig.14 A schematic diagram of a flow chart of a transceiver abnormality detection method provided by an embodiment of the present invention;

[0133] Fig.15 A schematic diagram of the module structure of an abnormality detection device for a transceiver provided by an embodiment of the present invention;

[0134] Fig.16 A schematic diagram of the structure of a baseband chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0135] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0136] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0137] As mentioned above, since transceivers are easy to recycle, the transceiver abnormality detection method in the related art only needs to detect the abnormality type, and then recycle the abnormal transceiver and return it to the factory for repair.

[0138] The transceiver abnormality detection method in the related art is usually:

[0139] A standard receiving / transmitting channel is added to the outside of the transceiver, and a detection loop including the receiving channel under test and the standard transmitting channel is established. By comparing the signal transmitted by the standard transmitting channel with the signal transmitted by the receiving channel under test, it is determined whether the receiving channel under test is abnormal; or a detection loop including the transmitting channel under test and the standard receiving channel is established. By comparing the signal transmitted by the transmitting channel under test with the signal transmitted by the standard receiving channel, it is determined whether the transmitting channel under test is abnormal.

[0140] However, the transceiver anomaly detection method in the related art can only realize channel-level anomaly detection of the transceiver, and cannot lock the exact anomaly location. For transceivers that are difficult to recover intact, for example, transceivers set in an ocean floating environment, the method in the related art cannot meet the anomaly detection needs of such transceivers, which brings additional costs, workload and difficulty for maintenance personnel to subsequently find the cause of the anomaly and optimize the design in a targeted manner.

[0141] Based on this, an embodiment of the present invention provides a transceiver abnormality detection system and an abnormality detection method, which performs unit-level abnormality detection on the transceiver and accurately locates the position of the abnormal device, thereby improving the accuracy and efficiency of the transceiver abnormality detection and enhancing the stability and reliability of the communication system.

[0142] Embodiment 1

[0143] Figure 1 FIG. 1 shows a schematic diagram of a structure of an abnormality detection system for a transceiver provided by an embodiment of the present invention. Figure 1 As shown, the transceiver abnormality detection system 100 includes a baseband chip 101 and a transceiver 102 that are communicatively connected, wherein:

[0144] In one or more embodiments, the baseband chip 101 may be integrated into a terminal device.

[0145] In one or more embodiments, the transceiver 102 may be integrated into a transceiver chip, that is, the transceiver 102 exists in the form of a transceiver chip.

[0146] It should be noted that in the transceiver 102 provided in the embodiment of the present invention, the number of the transmitting channels 113 is greater than or equal to one, the number of the receiving channels 111 is greater than or equal to one, the number of the detecting units 114 is greater than or equal to one, and the number of the transmitting channels 113, the number of the receiving channels 111, and the number of the detecting units 114 may be the same or different, and the embodiment of the present invention does not impose any restrictions on this. For example, the transceiver 102 may be a one-receive-one-transmit transceiver, a multi-receive-multi-transmit transceiver, a one-receive-multi-transmit transceiver, or a multi-receive-one-transmit transceiver.

[0147] The following embodiments are described by taking the transceiver 102 as a transceiver that transmits and receives data as an example:

[0148] In an optional embodiment, if Figure 1 As shown, the transceiver 102 includes a clock unit 110, a receiving channel 111, a digital front end (DFE) 112, a transmitting channel 113 and a detection unit 114, wherein:

[0149] The first communication end of the digital front end 112 is communicatively connected to the baseband chip 101, the input end of the digital front end 112 is electrically connected to the output end of the receiving channel 111, and the output end of the digital front end 112 is electrically connected to the input end of the transmitting channel 113;

[0150] The input end of the receiving channel 111, the multiple detection ends of the receiving channel 111, the output end of the transmitting channel 113, and the multiple detection ends of the transmitting channel 113 are all electrically connected to the detection unit 114, the clock input end of the receiving channel 111 is electrically connected to the first output end of the clock unit 110, and the clock input end of the transmitting channel 113 is electrically connected to the second output end of the clock unit 110;

[0151] The third output terminal of the clock unit 110 , the fourth output terminal of the clock unit 110 , and the fifth output terminal of the clock unit 110 are all electrically connected to the detection unit 114 .

[0152] In one or more embodiments, Figure 1 As shown, the transceiver 102 can be communicatively connected with the external circuit 103 to receive a signal sent by the external circuit 103 or send a signal to the external circuit 103 .

[0153] In an optional embodiment, if Figure 1 As shown, the transceiver 102 further includes a storage unit 115, wherein:

[0154] The communication terminal of the storage unit 115 is electrically connected to the second communication terminal of the digital front end 112 .

[0155] In an optional embodiment, if Figure 2 As shown, the receiving channel 111 includes a first amplifier 1110, a first mixer (MIXER) 1111, a first filter (FILTER) 1112, a first automatic gain controller (Automatic Gain Control, AGC) 1113 and an analog to digital converter (Analog to Digital Converter, ADC) 1114 which are electrically connected in sequence, wherein:

[0156] The input end of the first amplifier 1110 serves as the input end of the receiving channel 111, the output end of the analog-to-digital converter 1114 serves as the output end of the receiving channel 111, and the clock end of the first mixer 1111 is electrically connected to the first output end of the clock unit 110;

[0157] The output end of the first amplifier 1110 , the output end of the first mixer 1111 , the output end of the first filter 1112 , and the output end of the first automatic gain controller 1113 serve as multiple detection ends of the receiving channel 111 .

[0158] In one or more embodiments, the first amplifier 1110 may be a low noise amplifier (Low Noise Amplifier, LNA).

[0159] In an optional embodiment, if Figure 2 As shown, the transmitting channel 113 includes a digital to analog converter (DAC) 1130, a second automatic gain controller 1131, a second filter 1132, a second mixer 1133 and a second amplifier 1134 which are electrically connected in sequence, wherein:

[0160] The input end of the digital-to-analog converter 1130 serves as the input end of the transmission channel 113, the output end of the second amplifier 1134 serves as the output end of the transmission channel 113, and the clock end of the second mixer 1133 is electrically connected to the second output end of the clock unit 110;

[0161] The output end of the digital-to-analog converter 1130 , the output end of the second automatic gain controller 1131 , the output end of the second filter 1132 , and the output end of the second mixer 1133 serve as multiple detection ends of the transmission channel 113 .

[0162] In one or more embodiments, the second amplifier 1134 may be a power amplifier (PA).

[0163] In an optional embodiment, if Figure 2As shown, the detection unit 114 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a transmission auxiliary interface 1140, a reception auxiliary interface 1141, a first attenuator 1142 and a second attenuator 1143, wherein:

[0164] A first end of the first switch K1 is electrically connected to an output end of the first amplifier 1110, a second end of the first switch K1 is electrically connected to a third output end of the clock unit 110, a first end of the second switch K2 is electrically connected to an output end of the first mixer 1111, a first end of the third switch K3 is electrically connected to an output end of the first filter 1112, and a first end of the fourth switch K4 is electrically connected to an output end of the first automatic gain controller 1113;

[0165] The third end of the first switch K1, the fourth end of the first switch K1, the second end of the second switch K2, the second end of the third switch K3 and the second end of the fourth switch K4 are all electrically connected to the output end of the auxiliary receiving interface 1141, and the input end of the auxiliary receiving interface 1141 is electrically connected to the output end of the first attenuator 1142;

[0166] A first end of the fifth switch K5 is electrically connected to the output end of the digital-to-analog converter 1130, a first end of the sixth switch K6 is electrically connected to the output end of the second automatic gain controller 1131, a first end of the seventh switch K7 is electrically connected to the output end of the second filter 1132, a first end of the eighth switch K8 is electrically connected to the output end of the second mixer 1133, and a second end of the eighth switch K8 is electrically connected to the fourth output end of the clock unit 110;

[0167] The second end of the fifth switch K5, the second end of the sixth switch K6, the second end of the seventh switch K7, the third end of the eighth switch K8, and the fourth end of the eighth switch K8 are all electrically connected to the input end of the transmission auxiliary interface 1140, and the output end of the transmission auxiliary interface 1140 is electrically connected to the input end of the first attenuator 1142;

[0168] A first end of the ninth switch K9 is electrically connected to the input end of the first amplifier 1110, a second end of the ninth switch K9 is electrically connected to the output end of the second attenuator 1143, and a third end of the ninth switch K9 is electrically connected to the receiving end of the transceiver 102;

[0169] A first end of the tenth switch K10 is electrically connected to the output end of the second amplifier 1134, a second end of the tenth switch K10 is electrically connected to a first end of the eleventh switch K11, and a third end of the tenth switch K10 serves as a transmitting end of the transceiver 102;

[0170] A second end of the eleventh switch K11 is electrically connected to the fifth output end of the clock unit 110 , and a third end of the eleventh switch K11 is electrically connected to the input end of the second attenuator 1143 ;

[0171] A first controlled end of the first switch K1, a second controlled end of the first switch K1, a controlled end of the second switch K2, a controlled end of the third switch K3, a controlled end of the fourth switch K4, a controlled end of the fifth switch K5, a controlled end of the sixth switch K6, a controlled end of the seventh switch K7, a first controlled end of the eighth switch K8, a second controlled end of the eighth switch K8, a controlled end of the ninth switch K9, a controlled end of the tenth switch K10 and a controlled end of the eleventh switch K11 are all electrically connected to the control end of the digital front end.

[0172] In one or more embodiments, the second switch K2 , the third switch K3 , the fourth switch K4 , the fifth switch K5 , the sixth switch K6 , and the seventh switch K7 are all differential switches.

[0173] It should be noted that, in the embodiment of the present invention, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7 can be differential switches, double-pole single-throw switches, or other switch components, and the embodiment of the present invention does not impose any restrictions on this.

[0174] In one or more embodiments, the first switch K1 and the eighth switch K8 are both two-way single-pole single-throw switches.

[0175] In one or more embodiments, the ninth switch K9 , the tenth switch K10 , and the eleventh switch K11 are all single-pole double-throw switches.

[0176] In one or more embodiments, the transmission auxiliary interface 1140 includes at least two differential intermediate frequency auxiliary interfaces and one single-ended radio frequency auxiliary interface, and the reception auxiliary interface 1141 also includes at least two differential intermediate frequency auxiliary interfaces and one single-ended radio frequency auxiliary interface.

[0177] In one or more embodiments, the first attenuator 1142 and the second attenuator 1143 are both digitally controlled attenuators with adjustable attenuation.

[0178] In an optional embodiment, if Figure 2 As shown, the clock unit 110 includes a clock buffer 1100, a first phase-locked loop (PLL) 1101 and a second phase-locked loop 1102, wherein:

[0179] The first output end of the clock buffer 1100 is electrically connected to the input end of the first phase-locked loop 1101, and the second output end of the clock buffer 1100 is electrically connected to the input end of the second phase-locked loop 1102, for buffering the clock signal provided by the external clock source;

[0180] The first output end of the first phase-locked loop 1101 is electrically connected to the clock end of the first mixer 1111 as the first output end of the clock unit 110, and the second output end of the first phase-locked loop 1101 is electrically connected to the second end of the first switch K1 as the third output end of the clock unit 110;

[0181] The first output end of the second phase-locked loop 1102 is electrically connected to the clock end of the second mixer 1133, serving as the second output end of the clock unit 110. The second output end of the second phase-locked loop 1102 is electrically connected to the second end of the eighth switch K8, serving as the fourth output end of the clock unit 110. The third output end of the second phase-locked loop 1102 is electrically connected to the second end of the eleventh switch K11, serving as the fifth output end of the clock unit 110.

[0182] Based on Figure 2 The circuit structure diagram of the transceiver abnormality detection system 100 is shown in FIG. Figure 3 As shown in the figure, the system implements anomaly detection through the following steps:

[0183] Step S301, when the abnormality detection condition is met, the baseband chip 101 generates a first detection instruction which is sent to the transceiver 102;

[0184] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0185] Condition 1: the baseband chip 101 receives a message signal indicating that data received by the external device is abnormal;

[0186] In one or more embodiments, the external device may be a ground control base.

[0187] In one or more embodiments, the message signal may be a short message signal.

[0188] In a specific implementation, when an external device detects that an abnormality occurs in its received data, it sends a message signal to the baseband chip 101 to notify the baseband chip 101 to start abnormality detection, that is, the baseband chip 101 generates a first detection instruction and sends the first detection instruction to the digital front end 112 in the transceiver 102.

[0189] Condition 2: The frequency error of the baseband chip 101 receiving data is greater than a preset error threshold;

[0190] In a specific implementation, the baseband chip 101 detects the frequency of its own received data. When it is detected that the error between the frequency of its own received data and the reference frequency exceeds a preset error threshold, it is considered that the transceiver has an abnormality. At this time, the baseband chip 101 generates a first detection instruction and sends the first detection instruction to the digital front end 112 in the transceiver 102.

[0191] It should be noted that the preset error threshold in the embodiment of the present invention is an empirical value, which can be flexibly set according to actual business requirements, and the embodiment of the present invention does not impose any restrictions on this. For example, the preset error threshold can be set to 0.1.

[0192] Condition 3: The number of times that the baseband chip 101 fails to verify data is greater than a preset number threshold;

[0193] In a specific implementation, the baseband chip 101 verifies the data it receives. When it detects that the number of verification data failures is greater than a preset threshold, it is considered that the transceiver is abnormal. At this time, the baseband chip 101 generates a first detection instruction and sends the first detection instruction to the digital front end 112 in the transceiver 102.

[0194] It should be noted that the preset number of times threshold in the embodiment of the present invention is an empirical value, which can be flexibly set according to actual business needs, and the embodiment of the present invention does not impose any restrictions on this. For example, the preset number of times threshold can be set to 5 times.

[0195] Condition 4: the baseband chip 101 detects that a preset time threshold has been reached.

[0196] In a specific implementation, the baseband chip 101 will automatically generate a first detection instruction once every preset time threshold to perform abnormality detection and feed back the detection result.

[0197] It should be noted that the preset duration threshold in the embodiment of the present invention is an empirical value and can be flexibly set according to actual business requirements, and the embodiment of the present invention does not impose any restrictions on this. For example, the preset duration threshold can be set to 8 hours.

[0198] Step S302, the transceiver 102 constructs a first detection loop for transmitting a local oscillator signal in response to a first detection instruction, wherein the first detection loop includes a receiving channel 111 in the transceiver 102;

[0199] In an optional implementation, the first detection loop is constructed in the following manner:

[0200] The digital front end 112 analyzes the first detection instruction to obtain a first control signal;

[0201] Under the control of the first control signal, the detection unit 114 turns on the path between the output end of the clock unit 110 and the input end of the receiving channel 111 to construct a first detection loop.

[0202] In one or more embodiments, the first detection instruction is used to perform channel-level detection on the receiving channel 111 of the transceiver 102 .

[0203] In a specific implementation, after the digital front end 112 receives the first detection instruction sent by the baseband chip 101, the first detection instruction is parsed to obtain a first control signal for controlling the detection unit 114, wherein the first control signal can be obtained in the following two ways:

[0204] Method 1:

[0205] In an optional implementation, the digital front end 112 parses the first detection instruction to obtain a first detection mode; and determines a first control signal according to the first detection mode and based on a correspondence between the detection mode and the control signal stored in the storage unit 115 .

[0206] In one or more embodiments, the digital front end 112 searches for a control signal corresponding to the first detection mode in the correspondence between the detection modes and the control signals stored in the storage unit 115 , and uses the searched control signal as the first control signal.

[0207] Method 2:

[0208] In an optional implementation, the digital front end 112 parses the first detection instruction to directly obtain the first control signal.

[0209] For example, Figure 4 As shown, under the control of the first control signal, the detection unit 114 turns on the path between the first end and the second end of the ninth switch K9, and turns on the path between the second end and the third end of the eleventh switch K11, thereby turning on the path between the third output end of the second phase-locked loop 1102 and the input end of the first amplifier 1110, thereby realizing the construction of the first detection loop, that is, the first detection loop is: the second phase-locked loop 1102→the second attenuator 1143→the first amplifier 1110→the first mixer 1111→the first filter 1112→the first automatic gain controller 1113→the analog-to-digital converter 1114→the digital front end 112;

[0210] After the first detection loop is constructed, the second phase-locked loop 1102 processes the clock signal stored in the clock buffer 1100 and outputs it. The local oscillator signal output by the second phase-locked loop 1102 is amplified, mixed, filtered, and analog-to-digital converted by the first detection loop, and then transmitted to the digital front end 112; the digital front end 112 sends the received signal to the baseband chip 101.

[0211] In the above system, under the control of the first control signal obtained by parsing the first detection instruction, the transceiver turns on the path between the output end of the clock unit and the input end of the receiving channel to realize the construction of the first detection loop. The local oscillator signal is transmitted to the baseband chip through the first detection loop, so that the baseband chip determines whether the path for transmitting the local oscillator signal is abnormal based on the received local oscillator signal, thereby realizing channel-level abnormality detection of the transceiver.

[0212] Step S303, the baseband chip 101 generates a second detection instruction or a third detection instruction sent to the transceiver 102 according to the reference clock signal and the local oscillator signal;

[0213] In one or more embodiments, the reference clock signal is a clock signal stored in the baseband chip 101 .

[0214] In a specific implementation, the baseband chip 101 compares the reference clock signal and the local oscillator signal, and generates a second detection instruction according to the comparison result, wherein the second detection instruction can be determined in the following manner:

[0215] In an optional implementation, the baseband chip 101 calculates the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculates the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0216] When the baseband chip 101 detects that the first frequency difference is not within the first preset frequency threshold range, or the first power difference is not within the first power threshold range, a second detection instruction is generated.

[0217] In one or more embodiments, the first preset frequency threshold range and the first power threshold range can be flexibly set according to actual business requirements. For example, the first preset frequency threshold range can be: -10Hz to +10Hz; the first power threshold range can be: -1dB to +1dB.

[0218] In a specific implementation, if the first frequency difference does not fall within the first preset frequency threshold range, or the first power difference does not fall within the first power threshold range, the baseband chip 101 determines that there is an abnormality in the first detection path;

[0219] Exemplarily, the first preset frequency threshold range is set to -10Hz to +10Hz; the first power threshold range is -1dB to +1dB, and it is assumed that the first frequency difference calculated by the baseband chip 101 is 9Hz, and the first power difference is 1.3dBm. Since 9Hz is within the range of -10Hz to +10Hz, but 1.3dBm exceeds the range of -1dB to +1dB, the baseband chip 101 determines that there is an abnormality in the first detection path.

[0220] Since the first detection path includes the multiple first DUTs in the receiving channel 111 and the digital front end 112, before performing unit-level detection on the multiple first DUTs in the receiving channel 111 according to the second detection instruction, the following operations may be performed:

[0221] In an optional embodiment, the digital front end 112 obtains a preset character string stored in the storage unit 115 according to its own built-in detection program, and sends the preset character string to the baseband chip 101, so that the baseband chip 101 determines whether there is an abnormality in the digital front end 112 based on the comparison result of the received character string and the preset character string stored in itself.

[0222] In one or more embodiments, if the character string received by the baseband chip 101 is consistent with the preset character string stored in itself, the receiving part of the digital front end 112 is determined to be normal; if the character string received by the baseband chip 101 is inconsistent with the preset character string stored in itself, the receiving part of the digital front end 112 is determined to be abnormal.

[0223] In an optional implementation, the digital front end 112 receives a detection signal sent by the baseband chip 101 , and generates a loopback signal according to the detection signal, so that the baseband chip 101 receives the loopback signal.

[0224] In a specific implementation, after receiving the detection signal, the digital front end 112 generates a loopback signal in response to the detection signal and according to a built-in digital data loopback mode configured in the digital front end 112 itself.

[0225] In one or more embodiments, if the baseband chip 101 receives a loopback signal fed back by the digital front end 112, it is determined that both the receiving part and the transmitting part of the digital front end 112 are normal, and a second detection instruction is generated; if the baseband chip 101 does not receive the loopback signal fed back by the digital front end 112, it is determined that the receiving part and / or the transmitting part of the digital front end 112 are abnormal, and the abnormal information is reported and remotely controlled in an emergency manner.

[0226] The above method, which reports abnormal information in an emergency manner, can reduce the interference to the reporting of abnormal information caused by the interaction of conventional low-orbit satellite information.

[0227] In the above system, after determining that there is an abnormality in the first detection loop, the baseband chip sends a detection signal to the digital front end in the transceiver. If the baseband chip receives a loopback signal generated by the digital front end based on the detection signal, it means that the digital front end is normal. If the baseband chip does not receive the loopback signal generated by the digital front end based on the detection signal, it means that there is an abnormality in the digital front end, thereby determining the location of the abnormal device in the transceiver and realizing unit-level abnormality detection of the transceiver.

[0228] Step S304, if the transceiver 102 receives the second detection instruction, the transceiver 102 constructs a second detection loop including any one of the first devices under test in the receiving channel 111 in response to the second detection instruction;

[0229] In one or more embodiments, the first device under test in the receiving channel 111 includes: a first amplifier 1110 , a first mixer 1111 , a first filter 1112 , a first automatic gain controller 1113 , and an analog-to-digital converter 1114 .

[0230] In step S305 , the baseband chip 101 generates a first detection result for characterizing an abnormality of the first device under test according to the reference digital signal and the first digital signal transmitted by the second detection loop.

[0231] In one or more embodiments, the reference digital signal is a digital signal generated by the baseband chip 101 .

[0232] In a specific implementation, after the baseband chip 101 generates a reference digital signal, it sends the reference digital signal to the receiving part of the digital front end 112; the digital front end 112 transmits the received reference digital signal via a corresponding detection loop, and receives the digital signal after being transmitted via the corresponding detection loop; the transmitting part of the digital front end 112 sends the received digital signal to the baseband chip 101; the baseband chip 101 compares the reference digital signal stored in itself with the digital signal sent by the digital front end 112.

[0233] In an optional implementation, the second detection loop is constructed in the following manner:

[0234] The digital front end 112 analyzes the second detection instruction to obtain a second control signal;

[0235] Under the control of the second control signal, the detection unit 114 sequentially connects the paths between the multiple detection terminals of the receiving channel 111 and the detection reference terminal of the transmitting channel 113 to construct a second detection loop;

[0236] Among them, the detection reference end of the transmission channel 113 is a detection end among the multiple detection ends of the transmission channel 113 that is closest to the output end of the transmission channel 113, or any detection end among the other detection ends, and the other detection ends are detection ends among the multiple detection ends of the transmission channel 113 except the detection end that is closest to the output end of the transmission channel 113.

[0237] In such Figure 2 In the circuit structure diagram shown, the transmission auxiliary interface 1140 includes three differential intermediate frequency auxiliary interfaces, namely, an interface connected to the fifth switch K5, an interface connected to the sixth switch K6, and an interface connected to the seventh switch K7, and one single-ended RF auxiliary interface, namely, an interface connected to the eighth switch K8.

[0238] In one or more embodiments, if the detection reference end of the transmission channel 113 corresponds to the intermediate frequency auxiliary interface in the transmission auxiliary interface 1140, the detection reference end can be any one of the detection end corresponding to the output end of the digital-to-analog converter 1130, the detection end corresponding to the output end of the second automatic gain controller 1131, and the detection end corresponding to the output end of the second filter 1132; if the detection reference end of the transmission channel 113 corresponds to the radio frequency auxiliary interface in the transmission auxiliary interface 1140, the detection reference end can be the detection end corresponding to the output end of the second mixer 1133.

[0239] In the following embodiments, the output end of the digital-to-analog converter 1130 is used as the detection reference end, which is connected to the intermediate frequency auxiliary interface in the transmission auxiliary interface 1140; the detection end corresponding to the output end of the second mixer 1133 is used as the detection reference end, which is connected to the radio frequency auxiliary interface in the transmission auxiliary interface 1140:

[0240] In an optional implementation, the second control signal is obtained in the following manner:

[0241] The digital front end 112 parses the second detection instruction to obtain a second detection mode; and determines a second control signal according to the second detection mode and based on the correspondence between the detection mode and the control signal stored in the storage unit 115 .

[0242] It should be noted that the method for determining the second control signal in the embodiment of the present invention is similar to that for the first control signal. The specific implementation method may refer to the method for determining the first control signal, and therefore will not be described in detail.

[0243] For example, Figure 5As shown, the detection unit 114, under the control of the second control signal 1, closes the fourth switch K4 and the fifth switch K5, and turns on the path between the output end of the digital-to-analog converter 1130 and the input end of the analog-to-digital converter 1114, thereby realizing the construction of the second detection loop 1, that is, the second detection loop 1 is: digital front end 112→digital-to-analog converter 1130→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→analog-to-digital converter 1114→digital front end 112. At this time, the first device under test in the second detection loop 1 is the analog-to-digital converter 1114. After the second detection loop 1 is constructed, the baseband chip 101 will obtain the first digital signal 1 transmitted in the second detection loop 1 through the digital front end 112.

[0244] In a specific implementation, the baseband chip 101 compares the reference digital signal with the first digital signal 1. According to the comparison result, there are the following two situations:

[0245] Scenario 1:

[0246] In an optional implementation, the baseband chip 101 calculates the difference between the frequency value of the first digital signal 1 and the frequency value of the reference digital signal to obtain a second frequency difference 1, and calculates the difference between the power value of the first digital signal 1 and the power value of the reference digital signal to obtain a second power difference 1;

[0247] If the baseband chip 101 detects that the second frequency difference 1 is not within the second preset frequency threshold range, or the second power difference 1 is not within the second power threshold range, a first detection result is generated.

[0248] In one or more embodiments, the second preset frequency threshold range and the second power threshold range can be flexibly set according to actual business requirements.

[0249] It should be noted that there is no restrictive size relationship between the first preset frequency threshold range and the second preset frequency threshold range, and there is no restrictive size relationship between the first power threshold range and the second power threshold range.

[0250] Exemplarily, since in the aforementioned process, the digital front end 112 has been detected for abnormalities and it has been determined that the digital front end 112 is normal, the devices that may be abnormal in the second detection loop 1 are the digital-to-analog converter 1130 and the analog-to-digital converter 1114. At this time, the first detection result is: the digital-to-analog converter 1130 and / or the analog-to-digital converter 1114 are abnormal, and the first detection result is reported.

[0251] Scenario 2:

[0252] In an optional embodiment, if the baseband chip 101 detects that the second frequency difference 1 is within the second preset frequency threshold range, and the second power difference 1 is within the second power threshold range, it is determined that the first device under test in the second detection loop 1 is normal, and a second control signal 2 is generated to enable the transceiver 2 to perform abnormality detection on the next first device under test in the receiving channel 111.

[0253] In scenario 2, combined with the above abnormality detection process, it has been determined that the digital front end 112, the digital-to-analog converter 1130, and the analog-to-digital converter 1114 in the transceiver 102 are all normal, and the remaining first DUT in the receiving channel 111 is determined in the following manner:

[0254] For example, Figure 6 As shown, the detection unit 114, under the control of the second control signal 2, closes the third switch K3 and the fifth switch K5, and turns on the path between the output end of the digital-to-analog converter 1130 and the input end of the first automatic gain controller 1113, thereby realizing the construction of the second detection loop 2, that is, the second detection loop 2 is: digital front end 112→digital-to-analog converter 1130→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→first automatic gain controller 1113→analog-to-digital converter 1114→digital front end 112, at this time, the first device under test in the second detection loop 2 is the first automatic gain controller 1113; after the second detection loop 2 is constructed, the baseband chip 101 will obtain the first digital signal 2 transmitted in the second detection loop 2 through the digital front end 112;

[0255] The baseband chip 101 calculates the difference between the frequency value of the first digital signal 2 and the frequency value of the reference digital signal to obtain a second frequency difference 2, and calculates the difference between the power value of the first digital signal 2 and the power value of the reference digital signal to obtain a second power difference 2;

[0256] If the baseband chip 101 detects that the second frequency difference 2 is not within the second preset frequency threshold range, or the second power difference 2 is not within the second power threshold range, it is determined that the first device under test in the second detection loop 2 is abnormal, that is, the first automatic gain controller 1113 is abnormal, and a first detection result for characterizing the abnormality of the first automatic gain controller 1113 is generated, and the first detection result is reported;

[0257] If the baseband chip 101 detects that the second frequency difference 2 is within the second preset frequency threshold range, and the second power difference 2 is within the second power threshold range, it is determined that the first device under test in the second detection loop 2 is normal, that is, the first automatic gain controller 1113 is normal, and a second control signal 3 is generated to enable the transceiver 102 to perform abnormality detection on the next first device under test in the receiving channel 111.

[0258] If it is detected that the first automatic gain controller 1113 is normal, it can be known from the above abnormality detection process that the digital front end 112, the digital-to-analog converter 1130, the analog-to-digital converter 1114 and the first automatic gain controller 1113 in the transceiver 102 are all normal, and the remaining first devices under test in the receiving channel 111 are further determined in the following manner:

[0259] For example, Figure 7 As shown, the detection unit 114 closes the second switch K2 and the fifth switch K5 under the control of the second control signal 3, and turns on the path between the output end of the digital-to-analog converter 1130 and the input end of the first filter 1112, thereby realizing the construction of the second detection loop 3, that is, the second detection loop 3 is: digital front end 112→digital-to-analog converter 1130→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→first filter 1112→first automatic gain controller 1113→analog-to-digital converter 1114→digital front end 112, at this time, the first device under test in the second detection loop 3 is the first filter 1112; after the second detection loop 3 is constructed, the baseband chip 101 will obtain the first digital signal 3 transmitted in the second detection loop 3 through the digital front end 112;

[0260] The baseband chip 101 calculates the difference between the frequency value of the first digital signal 3 and the frequency value of the reference digital signal to obtain a second frequency difference 3, and calculates the difference between the power value of the first digital signal 3 and the power value of the reference digital signal to obtain a second power difference 3;

[0261] If the baseband chip 101 detects that the second frequency difference 3 is not within the second preset frequency threshold range, or the second power difference 3 is not within the second power threshold range, it is determined that the first device under test in the second detection loop 3 is abnormal, that is, the first filter 1112 is abnormal, and a first detection result for characterizing the abnormality of the first filter 1112 is generated, and the first detection result is reported;

[0262] If the baseband chip 101 detects that the second frequency difference 3 is within the second preset frequency threshold range, and the second power difference 3 is within the second power threshold range, it is determined that the first device under test in the second detection loop 3 is normal, that is, the first filter 1112 is normal, and a second control signal 4 is generated to enable the transceiver 102 to perform abnormality detection on the next first device under test in the receiving channel 111.

[0263] If the first filter 1112 is detected to be normal, it can be known from the above abnormality detection process that the digital front end 112, the digital-to-analog converter 1130, the analog-to-digital converter 1114, the first automatic gain controller 1113 and the first filter 1112 in the transceiver 102 are all determined to be normal, and the remaining first devices under test in the receiving channel 111 are further determined in the following manner:

[0264] For example, Figure 8 As shown, under the control of the second control signal 4, the detection unit 114 closes the first switch K1, and turns on the path between the second end and the fourth end of the eighth switch K8, and turns on the path between the fourth output end of the second phase-locked loop 1102 and the input end of the first mixer 1111, so as to realize the construction of the second detection loop 4, that is, the second detection loop 4 is: the second phase-locked loop 1102→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→first mixer 1111→first filter 1112→first automatic gain controller 1113→analog-to-digital converter 1114→digital front end 112, at this time, the first device under test in the second detection loop 3 is the first mixer 1111; after the second detection loop 4 is constructed, the baseband chip 101 will obtain the first digital signal 4 transmitted in the second detection loop 4 through the digital front end 112;

[0265] The baseband chip 101 calculates the difference between the frequency value of the first digital signal 4 and the frequency value of the reference clock signal to obtain a second frequency difference 4, and calculates the difference between the power value of the first digital signal 4 and the power value of the reference clock signal to obtain a second power difference 4;

[0266] If the baseband chip 101 detects that the second frequency difference 4 is not within the second preset frequency threshold range, or the second power difference 4 is not within the second power threshold range, it is determined that the first device under test in the second detection loop 4 is abnormal, that is, the first mixer 1111 is abnormal, and a first detection result for characterizing the abnormality of the first mixer 1111 is generated, and the first detection result is reported;

[0267] If the baseband chip 101 detects that the second frequency difference 4 is within the second preset frequency threshold range, and the second power difference 4 is within the second power threshold range, then it is determined that the first device to be tested in the second detection loop 4 is normal, that is, the first mixer 1111 is normal; since in the aforementioned abnormality detection process, it has been determined that the digital front end 112, the digital-to-analog converter 1130, the analog-to-digital converter 1114, the first automatic gain controller 1113 and the first filter 1112 in the transceiver 102 are all normal, it can be directly determined that the abnormal device is the first amplifier 1110 in the receiving channel 111. At this time, a first detection result for characterizing the abnormality of the first amplifier 1110 is generated, and the first detection result is reported.

[0268] In the manner described in the above example, a plurality of second detection loops are gradually constructed by using a method of controlling variables to implement unit-level detection of the transceiver 102 .

[0269] In one or more embodiments, the detection order of the components in the receiving channel 111 may be: first amplifier 1110 , first mixer 1111 , first filter 1112 , first automatic gain controller 1113 , analog-to-digital converter 1114 .

[0270] In one or more embodiments, the detection order of the components in the receiving channel 111 may be: analog-to-digital converter 1114 , first automatic gain controller 1113 , first filter 1112 , first mixer 1111 , and first amplifier 1110 .

[0271] It should be noted that when performing abnormality detection on the receiving channel of the transceiver, the order of the first DUT in the above example is only for reference, and the first DUT may also be detected for abnormality in other orders, and the embodiment of the present invention does not impose any limitation on this.

[0272] In the above system, the transceiver, under the control of the second control signal obtained by parsing the second detection instruction, respectively turns on the paths between the different detection ends of the receiving channel and the detection reference end of the transmitting channel to realize the construction of the second detection loop, and sends the first digital signal transmitted through the second detection loop to the baseband chip, so that the baseband chip determines whether the first device under test in the path for transmitting the first digital signal is abnormal based on the received first digital signal, thereby realizing unit-level abnormality detection of the transceiver.

[0273] In one or more embodiments, if the baseband chip 101 detects that the first frequency difference is within the first preset frequency threshold range and the first power difference is within the first power threshold range, it is determined that all components in the first detection loop are normal. At this time, the baseband chip 101 generates a third detection instruction sent to the transceiver 101 to perform abnormality detection on the transmission channel 113:

[0274] Step S306, if the transceiver 102 receives the third detection instruction, the transceiver 102 constructs a third detection loop for transmitting the second digital signal in response to the third detection instruction, wherein the third detection loop includes a transmission channel 113 corresponding to the reception channel 111 in the first detection loop;

[0275] In an optional implementation, the third detection loop is constructed in the following manner:

[0276] The digital front end 112 analyzes the third detection instruction to obtain a third control signal;

[0277] Under the control of the third control signal, the detection unit 114 connects the path between the output end of the transmitting channel 113 and the input end of the receiving channel 111 to construct a third detection loop.

[0278] In one or more embodiments, the third detection instruction is used to perform channel-level detection on the transmit channel 113 of the transceiver 102 .

[0279] In an optional implementation manner, the third control signal is obtained in the following manner:

[0280] The digital front end 112 parses the third detection instruction to obtain a third detection mode; and determines a third control signal according to the third detection mode and based on the correspondence between the detection mode and the control signal stored in the storage unit 115 .

[0281] It should be noted that the method for determining the third control signal in the embodiment of the present invention is similar to that for the first control signal. The specific implementation method may refer to the method for determining the first control signal, and therefore will not be described in detail.

[0282] For example, Fig. 9 As shown, under the control of the third control signal, the detection unit 114 turns on the path between the first end and the second end of the ninth switch K9, turns on the path between the first end and the second end of the tenth switch K10, and turns on the path between the first end and the third end of the eleventh switch K11, thereby turning on the path between the output end of the second amplifier 1134 and the input end of the first amplifier 1110, thereby realizing the construction of the third detection loop, that is, the third detection loop is: digital front end 112→digital-to-analog converter 1130→second automatic gain controller 1131→second filter 1132→→second mixer 1133→second amplifier 1134→second attenuator 1143→first amplifier 1110→first mixer 1111→first filter 1112→first automatic gain controller 1113→analog-to-digital converter 1114→digital front end 112; after the third detection loop is constructed, the baseband chip 101 will obtain the second digital signal transmitted in the third detection loop through the digital front end 112.

[0283] In the above system, the transceiver, under the control of the third control signal obtained by parsing the third detection instruction, turns on the path between the output end of the transmitting unit and the input end of the receiving channel to realize the construction of the third detection loop, and transmits the second digital signal transmitted by the third detection loop to the baseband chip, so that the baseband chip determines whether there is an abnormality in the transmission of the transmitting channel based on the received second digital signal, thereby realizing channel-level abnormality detection of the transceiver.

[0284] Step S307, the baseband chip 101 generates a fourth detection instruction sent to the transceiver 101 according to the reference digital signal and the second digital signal;

[0285] In an optional implementation, the baseband chip 101 calculates the difference between the frequency value of the second digital signal and the frequency value of the reference digital signal to obtain a third frequency difference, and calculates the difference between the power value of the second digital signal and the power value of the reference digital signal to obtain a third power difference;

[0286] If the baseband chip 101 detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, a fourth detection instruction for characterizing that the transmission channel 113 is abnormal is generated.

[0287] In a specific implementation, since it has been determined that all devices in the receiving channel 111 and the digital front end 112 are normal in the aforementioned abnormality detection process, when the baseband chip 101 detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, it indicates that there is an abnormality in the transmitting channel 113.

[0288] In an optional embodiment, if the baseband chip 101 detects that the third frequency difference is within the second preset frequency threshold range, and the third power difference is within the second power threshold range, it is determined that all components in the transceiver 102 are normal, and the external input signal is abnormal, and the abnormal information is reported.

[0289] Step S308, the transceiver 102 constructs a fourth detection loop including any second device under test in the transmitting channel 113 in response to the fourth detection instruction;

[0290] In one or more embodiments, the second device under test in the transmitting channel 113 includes: a digital-to-analog converter 1130 , a second automatic gain controller 1131 , a second filter 1132 , a second mixer 1133 , and a second amplifier 1134 .

[0291] In an optional implementation, the fourth detection loop is constructed in the following manner:

[0292] The digital front end 112 analyzes the fourth detection instruction to obtain a fourth control signal;

[0293] Under the control of the fourth control signal, the detection unit 114 sequentially connects the paths between the multiple detection terminals of the transmitting channel 113 and the detection reference terminal of the receiving channel 111 to construct a fourth detection loop;

[0294] Among them, the detection reference end of the receiving channel 111 is a detection end among the multiple detection ends of the receiving channel 111 that is closest to the input end of the receiving channel 111, or any detection end among the other detection ends, and the other detection ends are detection ends among the multiple detection ends of the receiving channel 111 except the detection end that is closest to the input end of the receiving channel 111.

[0295] In such Figure 2 In the circuit structure diagram shown, the receiving auxiliary interface 1141 also includes 3 differential intermediate frequency auxiliary interfaces, namely, an interface connected to the fourth switch K4, an interface connected to the third switch K3, an interface connected to the second switch K2, and 1 single-ended RF auxiliary interface, namely, an interface connected to the first switch K1.

[0296] In one or more embodiments, if the detection reference end of the receiving channel 111 corresponds to the intermediate frequency auxiliary interface in the receiving auxiliary interface 1141, the detection reference end can be any one of the detection end corresponding to the output end of the first automatic gain controller 1113, the detection end corresponding to the output end of the first filter 1112, and the detection end corresponding to the output end of the first mixer 1111; if the detection reference end of the receiving channel 111 corresponds to the radio frequency auxiliary interface in the receiving auxiliary interface 1141, the detection reference end can be the detection end corresponding to the output end of the first amplifier 1110.

[0297] In the following embodiments, the detection end corresponding to the output end of the first automatic gain controller 1113 is used as the detection reference end, which is connected to the intermediate frequency auxiliary interface in the receiving auxiliary interface 1141; the detection end corresponding to the output end of the first amplifier 1110 is used as the detection reference end, which is connected to the radio frequency auxiliary interface in the receiving auxiliary interface 1141:

[0298] In an optional implementation manner, the fourth control signal is obtained in the following manner:

[0299] The digital front end 112 parses the fourth detection instruction to obtain a fourth detection mode; and determines a fourth control signal according to the fourth detection mode and based on the correspondence between the detection mode and the control signal stored in the storage unit 115 .

[0300] It should be noted that the method for determining the fourth control signal in the embodiment of the present invention is similar to that for the first control signal. The specific implementation method may refer to the method for determining the first control signal, and therefore will not be described in detail.

[0301] Step S309: the baseband chip 101 generates a second detection result for characterizing that the second device under test is abnormal according to the reference clock signal and the third digital signal transmitted by the fourth detection loop.

[0302] In an optional implementation, the baseband chip 101 calculates the difference between the frequency value of the third digital signal and the frequency value of the reference digital signal to obtain a fourth frequency difference, and calculates the difference between the power value of the third digital signal and the power value of the reference digital signal to obtain a fourth power difference;

[0303] If the baseband chip 101 detects that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, a second detection result for characterizing that the second device under test is abnormal is generated.

[0304] For example, Figure 5 As shown, the detection unit 114 controls the fourth switch K4 and the fifth switch K5 to close again to construct the second detection loop 1, that is, the second detection loop 1 is: digital front end 112→digital-to-analog converter 1130→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→analog-to-digital converter 1114→digital front end 112;

[0305] The baseband chip 101 acquires the first digital signal 1 transmitted in the second detection loop 1 through the digital front end 112, and since it has been determined in the aforementioned abnormality detection process that all devices in the receiving channel 111 and the digital front end 112 are normal, if the baseband chip 101 detects that the second frequency difference 1 is not within the second preset frequency threshold range, or the second power difference 1 is not within the second power threshold range, it is determined that the digital-to-analog converter 1130 is abnormal, and the abnormal information is reported;

[0306] If the baseband chip 101 detects that the second frequency difference 1 is within the second preset frequency threshold range and the second power difference 1 is not within the second power threshold range, it is determined that the digital-to-analog converter 1130 is normal and a fourth control signal 1 is generated to enable the transceiver 3 to perform an abnormality detection on the next second device under test in the transmission channel 113.

[0307] For example, Fig.10 As shown, under the control of the fourth control signal 1, the detection unit 114 closes the fourth switch K4 and the sixth switch K6, and turns on the path between the output end of the second automatic gain controller 1131 and the input end of the analog-to-digital converter 1114, thereby realizing the construction of the fourth detection loop 1, that is, the fourth detection loop 1 is: digital front end 112→digital-to-analog converter 1130→second automatic gain controller 1131→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→analog-to-digital converter 1114→digital front end 112. At this time, the second device under test in the fourth detection loop 1 is the second automatic gain controller 1131. After the fourth detection loop 1 is constructed, the baseband chip 101 will obtain the third digital signal 1 transmitted in the fourth detection loop 1 through the digital front end 112.

[0308] The baseband chip 101 calculates the difference between the frequency value of the third digital signal 1 and the frequency value of the reference digital signal to obtain a fourth frequency difference 1, and calculates the difference between the power value of the third digital signal 1 and the power value of the reference digital signal to obtain a fourth power difference 1;

[0309] If the baseband chip 101 detects that the fourth frequency difference 1 is not within the second preset frequency threshold range, or the fourth power difference 1 is not within the second power threshold range, it is determined that the second device under test in the fourth detection loop 1 is abnormal, that is, the second automatic gain controller 1131 is abnormal, and a second detection result for characterizing the abnormality of the second automatic gain controller 1131 is generated, and the second detection result is reported;

[0310] If the baseband chip 101 detects that the fourth frequency difference 1 is within the second preset frequency threshold range, and the fourth power difference 1 is within the second power threshold range, it is determined that the second device under test in the fourth detection loop 1 is normal, that is, the second automatic gain controller 1131 is normal, and a fourth control signal 2 is generated to enable the transceiver 102 to perform abnormality detection on the next second device under test in the transmission channel 113.

[0311] If the second automatic gain controller 1131 is detected to be normal, it can be known from the above abnormality detection process that the digital front end 112, the receiving channel 111 and the digital-to-analog converter 1130 in the transceiver 102 are all normal, and the remaining second devices under test in the transmitting channel 113 are further determined in the following manner:

[0312] For example, Fig.11 As shown, under the control of the fourth control signal 2, the detection unit 114 closes the fourth switch K4 and the seventh switch K7, and turns on the path between the output end of the second filter 1132 and the input end of the analog-to-digital converter 1114, thereby realizing the construction of the fourth detection loop 2, that is, the fourth detection loop 2 is: digital front end 112→digital-to-analog converter 1130→second automatic gain controller 1131→second filter 1132→transmitting auxiliary interface 1140→first attenuator 1142→receiving auxiliary interface 1141→analog-to-digital converter 1114→digital front end 112, at this time, the second device under test in the fourth detection loop 2 is the second filter 1132; after the fourth detection loop 2 is constructed, the baseband chip 101 will obtain the third digital signal 2 transmitted in the fourth detection loop 2 through the digital front end 112.

[0313] The baseband chip 101 calculates the difference between the frequency value of the third digital signal 2 and the frequency value of the reference digital signal to obtain a fourth frequency difference 2, and calculates the difference between the power value of the third digital signal 2 and the power value of the reference digital signal to obtain a fourth power difference 2;

[0314] If the baseband chip 101 detects that the fourth frequency difference 2 is not within the second preset frequency threshold range, or the fourth power difference 2 is not within the second power threshold range, it is determined that the second device under test in the fourth detection loop 2 is abnormal, that is, the second filter 1132 is abnormal, and a second detection result for characterizing the abnormality of the second filter 1132 is generated, and the second detection result is reported;

[0315] If the baseband chip 101 detects that the fourth frequency difference 2 is within the second preset frequency threshold range, and the fourth power difference 2 is within the second power threshold range, it is determined that the second device under test in the fourth detection loop 2 is normal, that is, the second filter 1132 is normal, and a fourth control signal 3 is generated to enable the transceiver 102 to perform abnormality detection on the next second device under test in the transmission channel 113.

[0316] If the second filter 1132 is detected to be normal, it can be known from the above abnormality detection process that the digital front end 112, the receiving channel 111, the digital-to-analog converter 1130 and the second automatic gain controller 1131 in the transceiver 102 are all normal, and the remaining second devices under test in the transmitting channel 113 are further determined in the following manner:

[0317] For example, Fig.12 As shown, under the control of the fourth control signal 3, the detection unit 114 turns on the path between the first end and the third end of the first switch K1, turns on the path between the first end and the third end of the eighth switch K8, and turns on the path between the output end of the second mixer 1133 and the input end of the first mixer 1111, thereby realizing the construction of the fourth detection loop 3, that is, the fourth detection loop 3 is: digital front end 112→digital-to-analog converter 1130→second automatic gain controller 1131→second filter 1132→second Mixer 1133 → transmitting auxiliary interface 1140 → first attenuator 1142 → receiving auxiliary interface 1141 → first mixer 1111 → first filter 1112 → first automatic gain controller 1113 → analog-to-digital converter 1114 → digital front end 112. At this time, the second device under test in the fourth detection loop 3 is the second mixer 1133; after the fourth detection loop 3 is constructed, the baseband chip 101 will obtain the third digital signal 3 transmitted in the fourth detection loop 3 through the digital front end 112.

[0318] The baseband chip 101 calculates the difference between the frequency value of the third digital signal 3 and the frequency value of the reference digital signal to obtain a fourth frequency difference 3, and calculates the difference between the power value of the third digital signal 3 and the power value of the reference digital signal to obtain a fourth power difference 3;

[0319] If the baseband chip 101 detects that the fourth frequency difference 3 is not within the second preset frequency threshold range, or the fourth power difference 3 is not within the second power threshold range, it is determined that the second device under test in the fourth detection loop 2 is abnormal, that is, the second mixer 1133 is abnormal, and a second detection result for characterizing the abnormality of the second mixer 1133 is generated, and the second detection result is reported;

[0320] If the baseband chip 101 detects that the fourth frequency difference 3 is within the second preset frequency threshold range, and the fourth power difference 3 is within the second power threshold range, then it is determined that the second device to be tested in the fourth detection loop 2 is normal, that is, the second mixer 1133 is normal; since in the aforementioned abnormality detection process, it has been determined that the digital front end 112, the receiving channel 111, the digital-to-analog converter 1130, the second automatic gain controller 1131 and the second filter 1132 in the transceiver 102 are all normal, then the abnormal device can be directly determined to be the second amplifier 1134 in the transmitting channel 113. At this time, a second detection result for characterizing the abnormality of the second amplifier 1134 is generated, and the second detection result is reported.

[0321] In the manner described in the above example, a plurality of fourth detection loops are gradually constructed by using a method of controlling variables to implement unit-level detection of the transceiver 102 .

[0322] In one or more embodiments, the detection order of the components in the transmitting channel 113 may be: digital-to-analog converter 1130 , second automatic gain controller 1131 , second filter 1132 , second mixer 1133 , and second amplifier 1134 .

[0323] In one or more embodiments, the detection order of the components in the transmitting channel 113 may be: the second amplifier 1134 , the second mixer 1133 , the second filter 1132 , the second automatic gain controller 1131 , and the digital-to-analog converter 1130 .

[0324] It should be noted that when performing abnormality detection on the transmitting channel of the transceiver, the order of the second DUTs in the above example is only for reference, and the second DUTs may also be detected for abnormality in other orders, and the embodiment of the present invention does not impose any limitation on this.

[0325] In the above system, the transceiver, under the control of the fourth control signal obtained by parsing the fourth detection instruction, respectively turns on the paths between different detection ends of the transmission channel and the detection reference end of the receiving channel to realize the construction of the fourth detection loop, and sends the third digital signal transmitted through the fourth detection loop to the baseband chip, so that the baseband chip determines whether the second device under test in the transmission path is abnormal based on the received third digital signal, thereby realizing unit-level abnormality detection of the transceiver.

[0326] In the abnormality detection system of the transceiver provided by the embodiment of the present invention, when the abnormality detection condition is met, the baseband chip generates a first detection instruction for controlling the transceiver to perform abnormality detection, and receives a local oscillator signal transmitted in a first detection loop constructed by the transceiver through the first detection instruction. Since the first detection loop includes a receiving channel, channel-level transceiver abnormality detection can be implemented by comparing the local oscillator signal and the reference clock signal, that is, it can be detected whether the receiving channel in the first detection loop is abnormal.

[0327] In addition, after determining that the receiving channel is abnormal, a second detection instruction for controlling the transceiver to build a second detection loop is generated. Since the second detection loop includes any first device under test in the receiving channel, by comparing the first digital signal transmitted by the second detection loop with the reference digital signal, the abnormality detection of the transceiver at the unit level can be realized, that is, it can be detected whether the first device under test in the receiving channel is abnormal;

[0328] In addition, after the baseband chip detects that the receiving channel is normal, it generates a third detection instruction for controlling the transceiver to build a third detection loop. Since the third detection loop includes a transmitting channel corresponding to the receiving channel, by comparing the reference digital signal of the second digital signal transmitted by the third detection loop, channel-level transceiver abnormality detection can be achieved, that is, it can be detected whether the transmitting channel in the third detection loop is abnormal;

[0329] In addition, after determining that an abnormality exists in the transmission channel, a fourth detection instruction is generated for controlling the transceiver to construct a fourth detection loop. Since the fourth detection loop includes any second device under test in the transmission channel, by comparing the third digital signal and the reference digital signal transmitted by the fourth detection loop, unit-level transceiver abnormality detection can be achieved, that is, it can be detected whether the second device under test in the transmission channel is abnormal.

[0330] Through the above method, the combination of channel-level anomaly detection and unit-level anomaly detection is realized, so that when an abnormality occurs in the transceiver, the abnormal position can be located more accurately, the efficiency of abnormality positioning is improved, and the stability and reliability of the communication system are enhanced.

[0331] Fig.13 A complete flow chart of an anomaly detection method based on an anomaly detection system of a transceiver is shown, comprising the following steps:

[0332] Step S1301, start anomaly detection;

[0333] Step S1302, constructing a first detection loop and determining whether it is abnormal, if so, executing step S1303, otherwise, executing step S1304;

[0334] Step S1303, detecting whether the digital front end is abnormal, if so, executing step S1305, otherwise, executing step S1306;

[0335] Step S1304, constructing a third detection loop and determining whether it is abnormal, if so, executing step S1315, otherwise, executing step S1316;

[0336] Step S1305, reporting the detection result of the digital front end abnormality;

[0337] Step S1306, construct the second detection loop 1, and determine whether it is abnormal, if so, execute step S1307, otherwise, execute step S1308;

[0338] Step S1307, reporting the detection result of the abnormality of the analog-to-digital converter and / or the digital-to-analog converter;

[0339] Step S1308, construct the second detection loop 2, and determine whether it is abnormal, if so, execute step S1309, otherwise, execute step S1310;

[0340] Step S1309, reporting the detection result of the abnormality of the first automatic gain controller;

[0341] Step S1310, construct the second detection loop 3, and determine whether it is abnormal, if so, execute step S1311, otherwise, execute step S1312;

[0342] Step S1311, reporting the detection result of the first filter abnormality;

[0343] Step S1312, construct the second detection loop 4, and determine whether it is abnormal, if so, execute step S1313, otherwise, execute step S1314;

[0344] Step S1313, reporting the detection result of the abnormality of the first mixer;

[0345] Step S1314, reporting the detection result of the first amplifier being abnormal;

[0346] Step S1315, re-construct the second detection loop 1 and determine whether it is abnormal. If so, execute step S1317, otherwise, execute step S1318;

[0347] Step S1316, reporting the detection result that all components in the transceiver are normal and the external input signal is abnormal;

[0348] Step S1317, reporting the detection result of the abnormality of the digital-to-analog converter;

[0349] Step S1318, construct the fourth detection loop 1, and determine whether it is abnormal, if so, execute step S1319, otherwise, execute step S1320;

[0350] Step S1319, reporting the detection result of the abnormality of the second automatic gain controller;

[0351] Step S1320, construct the fourth detection loop 2, and determine whether it is abnormal, if so, execute step S1321, otherwise, execute step S1322;

[0352] Step S1321, reporting the detection result of the second filter abnormality;

[0353] Step S1322, construct the fourth detection loop 3, and determine whether it is abnormal, if so, execute step S1323, otherwise, execute step S1324;

[0354] Step S1323, reporting the detection result of the abnormality of the second mixer;

[0355] Step S1324, reporting the detection result of the abnormality of the second amplifier;

[0356] Step S1325, abnormality detection ends.

[0357] Embodiment 2

[0358] Based on the same concept, an embodiment of the present invention also provides an abnormality detection method for a transceiver, which is applied to an abnormality detection system for a transceiver provided in any of the above embodiments. Since this method is the method in an embodiment of the present invention, and the principle of solving the problem by this method is similar to that of the system, the implementation of this method can refer to the implementation of the abnormality detection system of the transceiver, and the repeated parts will not be repeated.

[0359] like Fig.14 As shown, the method comprises the following steps:

[0360] Step S1401, when the abnormal detection condition is met, the baseband chip generates a first detection instruction, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver;

[0361] Step S1402: the baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one of the first devices under test in the receiving channel, wherein the second detection loop is used to transmit the first digital signal;

[0362] Step S1403: The baseband chip generates a first detection result for characterizing that the first device under test is abnormal according to the reference digital signal and the first digital signal.

[0363] In an optional implementation manner, the baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal, including:

[0364] The baseband chip calculates the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculates the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0365] When the baseband chip detects that the first frequency difference is not within the first preset frequency threshold range, or the first power difference is not within the first power threshold range, a second detection instruction is generated.

[0366] In an optional implementation manner, the baseband chip generates a first detection result for characterizing that the first device under test is abnormal according to the reference digital signal and the first digital signal, including:

[0367] The baseband chip calculates the difference between the frequency value of the first digital signal and the frequency value of the reference digital signal to obtain a second frequency difference, and calculates the difference between the power value of the first digital signal and the power value of the reference digital signal to obtain a second power difference;

[0368] When the baseband chip detects that the second frequency difference is not within the second preset frequency threshold range, or the second power difference is not within the second power threshold range, a first detection result is generated.

[0369] In an optional embodiment, the method further includes:

[0370] When detecting that the first frequency difference is within a first preset frequency threshold range and the first power difference is within a first power threshold range, the baseband chip generates a third detection instruction, so that the transceiver responds to the third detection instruction and constructs a third detection loop for transmitting the second digital signal, wherein the third detection loop includes a transmission channel corresponding to the reception channel in the first detection loop;

[0371] The baseband chip generates a fourth detection instruction according to the reference digital signal and the second digital signal, so that the transceiver responds to the fourth detection instruction and constructs a fourth detection loop including any one second device under test in the transmission channel, wherein the fourth detection loop is used to transmit the third digital signal;

[0372] The baseband chip generates a second detection result for characterizing that the second device under test is abnormal according to the reference digital signal and the third digital signal.

[0373] In an optional implementation manner, the baseband chip generates a fourth detection instruction according to the reference digital signal and the second digital signal, including:

[0374] The baseband chip calculates the difference between the frequency value of the second digital signal and the frequency value of the reference digital signal to obtain a third frequency difference, and calculates the difference between the power value of the second digital signal and the power value of the reference digital signal to obtain a third power difference;

[0375] When the baseband chip detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, a fourth detection instruction is generated.

[0376] In an optional implementation manner, the baseband chip generates a second detection result for characterizing that the second device under test is abnormal according to the reference digital signal and the third digital signal, including:

[0377] The baseband chip calculates a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculates a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference;

[0378] When the baseband chip detects that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, a second detection result is generated.

[0379] In an optional implementation manner, after the baseband chip generates the first detection instruction and before generating the second detection instruction, the method further includes:

[0380] Sending a detection signal to the transceiver so that the transceiver generates a loopback signal according to the detection signal;

[0381] Receive loopback signal.

[0382] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0383] The baseband chip receives a message signal for indicating that the external device receives data abnormally;

[0384] The frequency error of the baseband chip receiving data is greater than a preset error threshold;

[0385] The number of baseband chip verification data failures is greater than the preset number threshold;

[0386] The baseband chip detects that the preset time threshold has been reached.

[0387] Embodiment 3

[0388] Based on the same concept, an embodiment of the present invention also provides an abnormality detection device for a transceiver, which is applied to an abnormality detection system for a transceiver provided in any of the above embodiments. Since the device is the device in the method of the embodiment of the present invention, and the principle of solving the problem by the device is similar to that of the method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0389] like Fig.15 As shown, the above device includes the following modules:

[0390] A first processing module 1501 is used to generate a first detection instruction when an abnormal detection condition is met, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver;

[0391] A second processing module 1502 is used to generate a second detection instruction according to the reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one of the first devices under test in the receiving channel, wherein the second detection loop is used to transmit the first digital signal;

[0392] The third processing module 1503 is used to generate a first detection result for characterizing an abnormality of the first device under test according to the reference digital signal and the first digital signal.

[0393] In an optional implementation, the second processing module 1502 is specifically configured to:

[0394] Calculate the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculate the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0395] When it is detected that the first frequency difference is not within the first preset frequency threshold range, or the first power difference is not within the first power threshold range, a second detection instruction is generated.

[0396] In an optional implementation manner, the third processing module 1503 is specifically configured to:

[0397] Calculating a difference between a frequency value of the first digital signal and a frequency value of a reference digital signal to obtain a second frequency difference, and calculating a difference between a power value of the first digital signal and a power value of the reference digital signal to obtain a second power difference;

[0398] When it is detected that the second frequency difference is not within the second preset frequency threshold range, or the second power difference is not within the second power threshold range, a first detection result is generated.

[0399] In an optional embodiment, the above device further includes:

[0400] a fourth processing module, configured to generate a third detection instruction when detecting that the first frequency difference is within a first preset frequency threshold range and the first power difference is within a first power threshold range, so that the transceiver responds to the third detection instruction and constructs a third detection loop for transmitting the second digital signal, wherein the third detection loop includes a transmission channel corresponding to the reception channel in the first detection loop;

[0401] a fifth processing module, configured to generate a fourth detection instruction according to the reference digital signal and the second digital signal, so that the transceiver responds to the fourth detection instruction and constructs a fourth detection loop including any one second device under test in the transmission channel, wherein the fourth detection loop is used to transmit the third digital signal;

[0402] The sixth processing module is used to generate a second detection result for characterizing that the second device under test is abnormal according to the reference digital signal and the third digital signal.

[0403] In an optional implementation, the fifth processing module is specifically configured to:

[0404] Calculating a difference between a frequency value of the second digital signal and a frequency value of the reference digital signal to obtain a third frequency difference, and calculating a difference between a power value of the second digital signal and a power value of the reference digital signal to obtain a third power difference;

[0405] When it is detected that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, a fourth detection instruction is generated.

[0406] In an optional implementation manner, the sixth processing module is specifically configured to:

[0407] Calculating a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculating a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference;

[0408] When it is detected that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, a second detection result is generated.

[0409] In an optional embodiment, the above device further includes a seventh processing module;

[0410] The fourth processing module is used to send a detection signal to the transceiver so that the transceiver generates a loopback signal according to the detection signal; and receive the loopback signal.

[0411] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0412] A message signal is received for indicating that the external device receives data abnormally;

[0413] The frequency error of the received data is greater than a preset error threshold;

[0414] The number of failed verifications is greater than the preset threshold.

[0415] It is detected that the preset time threshold has been reached.

[0416] Embodiment 4

[0417] Based on the same concept, an embodiment of the present invention also provides a baseband chip, which is applied to an abnormality detection system of a transceiver provided in any of the above embodiments. Since the baseband chip is the baseband chip in the method of the embodiment of the present invention, and the principle of solving the problem by the baseband chip is similar to that of the method, the implementation of the baseband chip can refer to the implementation of the method, and the repeated parts will not be repeated.

[0418] Refer to the following Fig.16 The baseband chip 160 according to this embodiment of the present invention will be described. Fig.16 The baseband chip 160 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0419] like Fig.16 As shown, the components of the baseband chip 160 may include but are not limited to: the at least one processor 161 mentioned above, the at least one memory 162 storing instructions executable by the processor 161;

[0420] In a possible implementation, the processor 161 implements the following steps by running executable instructions:

[0421] When an abnormal detection condition is met, a first detection instruction is generated, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver;

[0422] Generate a second detection instruction according to the reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one of the first devices under test in the receiving channel, wherein the second detection loop is used to transmit the first digital signal;

[0423] A first detection result for characterizing an abnormality of the first device under test is generated according to the reference digital signal and the first digital signal.

[0424] In an optional implementation manner, the processor 161 is specifically configured to:

[0425] Calculate the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculate the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference;

[0426] When it is detected that the first frequency difference is not within the first preset frequency threshold range, or the first power difference is not within the first power threshold range, a second detection instruction is generated.

[0427] In an optional implementation manner, the processor 161 is specifically configured to:

[0428] Calculating a difference between a frequency value of the first digital signal and a frequency value of a reference digital signal to obtain a second frequency difference, and calculating a difference between a power value of the first digital signal and a power value of the reference digital signal to obtain a second power difference;

[0429] When it is detected that the second frequency difference is not within the second preset frequency threshold range, or the second power difference is not within the second power threshold range, a first detection result is generated.

[0430] In an optional implementation, the processor 161 is further configured to:

[0431] When it is detected that the first frequency difference is within a first preset frequency threshold range and the first power difference is within a first power threshold range, a third detection instruction is generated, so that the transceiver responds to the third detection instruction and constructs a third detection loop for transmitting the second digital signal, wherein the third detection loop includes a transmission channel corresponding to the reception channel in the first detection loop;

[0432] Generate a fourth detection instruction according to the reference digital signal and the second digital signal, so that the transceiver responds to the fourth detection instruction and constructs a fourth detection loop including any one second device under test in the transmission channel, wherein the fourth detection loop is used to transmit the third digital signal;

[0433] A second detection result for characterizing an abnormality of the second device under test is generated according to the reference digital signal and the third digital signal.

[0434] In an optional implementation manner, the processor 161 is specifically configured to:

[0435] Calculating a difference between a frequency value of the second digital signal and a frequency value of the reference digital signal to obtain a third frequency difference, and calculating a difference between a power value of the second digital signal and a power value of the reference digital signal to obtain a third power difference;

[0436] When it is detected that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, a fourth detection instruction is generated.

[0437] In an optional implementation manner, the processor 161 is specifically configured to:

[0438] Calculating a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculating a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference;

[0439] When it is detected that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, a second detection result is generated.

[0440] In an optional implementation, the processor 161 is further configured to:

[0441] A detection signal is sent to the transceiver so that the transceiver generates a loopback signal according to the detection signal; and the loopback signal is received.

[0442] In an optional implementation, the abnormality detection condition includes any one of the following conditions:

[0443] A message signal is received for indicating that the external device receives data abnormally;

[0444] The frequency error of the received data is greater than a preset error threshold;

[0445] The number of failed verifications is greater than the preset threshold.

[0446] It is detected that the preset time threshold has been reached.

[0447] The present application is described above with reference to the block diagrams and / or flow charts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that a block of the block diagram and / or flow chart diagram and a combination of blocks of the block diagram and / or flow chart diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing device create a method for implementing the functions / actions specified in the block diagram and / or flow chart block.

[0448] Accordingly, the present application may also be implemented with hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium for use by or in conjunction with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that may contain, store, communicate, transmit, or convey a program for use by or in conjunction with an instruction execution system, device, or apparatus.

[0449] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A transceiver abnormality detection system, characterized in that: It includes a baseband chip and a transceiver for communication connection, wherein: The transceiver constructs a first detection loop for transmitting a local oscillator signal in response to a first detection instruction, wherein the first detection instruction is generated by the baseband chip when an abnormal detection condition is met, and the first detection loop includes a receiving channel in the transceiver; In response to a second detection instruction, the transceiver constructs a second detection loop including any one of the first devices under test in the receiving channel, so that the baseband chip generates a first detection result for characterizing an abnormality of the first device under test based on a reference digital signal and a first digital signal transmitted by the second detection loop, wherein the second detection instruction is generated by the baseband chip based on a reference clock signal and the local oscillator signal.

2. The system according to claim 1, characterized in that The transceiver further includes a digital front end, a transmission channel, a detection unit and a clock unit, wherein: The receiving channel, the digital front end and the transmitting channel are electrically connected in sequence, the detection unit is electrically connected to the digital front end, the receiving channel, the transmitting channel and the clock unit respectively, and the clock unit is electrically connected to the receiving channel and the transmitting channel respectively; The first detection loop is constructed in the following way: The transceiver parses the first detection instruction through the digital front end to obtain a first control signal; The transceiver, through the detection unit, under the control of the first control signal, conducts a path between the output end of the clock unit and the input end of the receiving channel to construct the first detection loop.

3. The system according to claim 2, characterized in that The transceiver further includes a storage unit, which is electrically connected to the digital front end, wherein: The first control signal is obtained by: The transceiver parses the first detection instruction through the digital front end to obtain a first detection mode; The transceiver determines the first control signal through the digital front end according to the first detection mode and based on the corresponding relationship between the detection mode and the control signal stored in the storage unit.

4. The system according to claim 3, characterized in that The second detection loop is constructed in the following way: The transceiver parses the second detection instruction through the digital front end to obtain a second control signal; The transceiver, through the detection unit, under the control of the second control signal, sequentially conducts the paths between the multiple detection ends of the receiving channel and the detection reference end of the transmitting channel to construct the second detection loop; Among them, the detection reference end of the transmitting channel is a detection end among the multiple detection ends of the transmitting channel that is closest to the output end of the transmitting channel, or any detection end among the other detection ends, and the other detection end is a detection end among the multiple detection ends of the transmitting channel except the detection end that is closest to the output end of the transmitting channel.

5. The system according to claim 4, characterized in that The second control signal is obtained by: The transceiver parses the second detection instruction through the digital front end to obtain a second detection mode; The transceiver determines the second control signal through the digital front end according to the second detection mode and based on the corresponding relationship between the detection mode and the control signal.

6. The system according to claim 1, wherein: The second detection instruction is generated in the following manner: The baseband chip calculates the difference between the frequency value of the digital signal corresponding to the local oscillator signal and the frequency value of the reference clock signal to obtain a first frequency difference, and calculates the difference between the power value of the digital signal corresponding to the local oscillator signal and the power value of the reference clock signal to obtain a first power difference; When the baseband chip detects that the first frequency difference is not within a first preset frequency threshold range, or the first power difference is not within a first power threshold range, the second detection instruction is generated.

7. The system according to claim 1, characterized in that The first detection result is generated by: The baseband chip calculates a difference between a frequency value of the first digital signal and a frequency value of the reference digital signal to obtain a second frequency difference, and calculates a difference between a power value of the first digital signal and a power value of the reference digital signal to obtain a second power difference; When the baseband chip detects that the second frequency difference is not within a second preset frequency threshold range, or the second power difference is not within a second power threshold range, the first detection result is generated.

8. The system according to claim 3, characterized in that The transceiver is also used for: The transceiver constructs a third detection loop for transmitting a second digital signal in response to a third detection instruction, wherein the third detection loop includes a transmission channel corresponding to the receiving channel in the first detection loop, and the third detection instruction is generated by the baseband chip when it is detected that the first frequency difference is within the first preset frequency threshold range and the first power difference is within the first power threshold range; In response to a fourth detection instruction, the transceiver constructs a fourth detection loop including any one second device under test in the transmission channel, so that the baseband chip generates a second detection result for characterizing the abnormality of the second device under test based on the reference digital signal and the third digital signal transmitted by the fourth detection loop, wherein the fourth detection instruction is generated by the baseband chip based on the reference digital signal and the second digital signal.

9. The system according to claim 8, characterized in that The third detection loop is constructed in the following way: The transceiver parses the third detection instruction through the digital front end to obtain a third control signal; The transceiver, through the detection unit, under the control of the third control signal, conducts the path between the output end of the transmission channel and the input end of the reception channel to construct the third detection loop.

10. The system according to claim 9, characterized in that The third control signal is obtained by: The transceiver parses the third detection instruction through the digital front end to obtain a third detection mode; The transceiver determines the third control signal through the digital front end according to the third detection mode and based on the corresponding relationship between the detection mode and the control signal.

11. The system according to claim 8, characterized in that The fourth detection loop is constructed in the following manner: The transceiver parses the fourth detection instruction through the digital front end to obtain a fourth control signal; The transceiver, through the detection unit, under the control of the fourth control signal, sequentially conducts the paths between the multiple detection ends of the transmission channel and the detection reference end of the receiving channel to construct the fourth detection loop; Among them, the detection reference end of the receiving channel is a detection end among the multiple detection ends of the receiving channel that is closest to the input end of the receiving channel, or any detection end among the other detection ends, and the other detection end is a detection end among the multiple detection ends of the receiving channel except the detection end that is closest to the input end of the receiving channel.

12. The system according to claim 11, characterized in that The fourth control signal is obtained by: The transceiver parses the fourth detection instruction through the digital front end to obtain a fourth detection mode; The transceiver determines the fourth control signal through the digital front end according to the fourth detection mode and based on the corresponding relationship between the detection mode and the control signal.

13. The system of claim 8, wherein: The fourth detection instruction is generated in the following manner: The baseband chip calculates a difference between a frequency value of the second digital signal and a frequency value of the reference digital signal to obtain a third frequency difference, and calculates a difference between a power value of the second digital signal and a power value of the reference digital signal to obtain a third power difference; When the baseband chip detects that the third frequency difference is not within the second preset frequency threshold range, or the third power difference is not within the second power threshold range, the fourth detection is generated.

14. The system of claim 8, wherein: The second detection result is generated by: The baseband chip calculates a difference between a frequency value of the third digital signal and a frequency value of the reference digital signal to obtain a fourth frequency difference, and calculates a difference between a power value of the third digital signal and a power value of the reference digital signal to obtain a fourth power difference; When the baseband chip detects that the fourth frequency difference is not within the second preset frequency threshold range, or the fourth power difference is not within the second power threshold range, the second detection result is generated.

15. The system according to any one of claims 1 to 14, characterized in that: After the transceiver constructs a first detection loop for transmitting a local oscillator signal and before responding to a second detection instruction, the transceiver is further configured to: The detection signal sent by the baseband chip is received through the digital front end, and the loopback signal is generated according to the detection signal, so that the baseband chip receives the loopback signal.

16. The system according to any one of claims 1 to 14, characterized in that: The abnormality detection condition includes any one of the following conditions: The baseband chip receives a message signal for indicating that data reception by the external device is abnormal; The frequency error of the baseband chip receiving data is greater than a preset error threshold; The number of times that the baseband chip fails to verify data is greater than a preset number threshold; The baseband chip detects that a preset time threshold is reached.

17. The system according to any one of claims 1 to 14, characterized in that: The receiving channel includes a first amplifier, a first mixer, a first filter, a first automatic gain controller and an analog-to-digital converter which are electrically connected in sequence, wherein: The input end of the first amplifier serves as the input end of the receiving channel, the output end of the analog-to-digital converter serves as the output end of the receiving channel, and the clock end of the first mixer is electrically connected to the first output end of the clock unit; The output end of the first amplifier, the output end of the first mixer, the output end of the first filter and the output end of the first automatic gain controller serve as multiple detection ends of the receiving channel; The transmitting channel includes a digital-to-analog converter, a second automatic gain controller, a second filter, a second mixer and a second amplifier which are electrically connected in sequence, wherein: The input end of the digital-to-analog converter serves as the input end of the transmitting channel, the output end of the second amplifier serves as the output end of the transmitting channel, and the clock end of the second mixer is electrically connected to the second output end of the clock unit; The output end of the digital-to-analog converter, the output end of the second automatic gain controller, the output end of the second filter and the output end of the second mixer serve as multiple detection ends of the transmission channel.

18. The system of claim 17, wherein: The detection unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a transmission auxiliary interface, a reception auxiliary interface, a first attenuator and a second attenuator, wherein: A first end of the first switch is electrically connected to an output end of the first amplifier, a second end of the first switch is electrically connected to a third output end of the clock unit, a first end of the second switch is electrically connected to an output end of the first mixer, a first end of the third switch is electrically connected to an output end of the first filter, and a first end of the fourth switch is electrically connected to an output end of the first automatic gain controller; The third end of the first switch, the fourth end of the first switch, the second end of the second switch, the second end of the third switch and the second end of the fourth switch are all electrically connected to the output end of the auxiliary receiving interface, and the input end of the auxiliary receiving interface is electrically connected to the output end of the first attenuator; A first end of the fifth switch is electrically connected to the output end of the digital-to-analog converter, a first end of the sixth switch is electrically connected to the output end of the second automatic gain controller, a first end of the seventh switch is electrically connected to the output end of the second filter, a first end of the eighth switch is electrically connected to the output end of the second mixer, and a second end of the eighth switch is electrically connected to the fourth output end of the clock unit; The second end of the fifth switch, the second end of the sixth switch, the second end of the seventh switch, the third end of the eighth switch and the fourth end of the eighth switch are all electrically connected to the input end of the transmission auxiliary interface, and the output end of the transmission auxiliary interface is electrically connected to the input end of the first attenuator; A first end of the ninth switch is electrically connected to an input end of the first amplifier, a second end of the ninth switch is electrically connected to an output end of the second attenuator, and a third end of the ninth switch is electrically connected to a receiving end of the transceiver; A first end of the tenth switch is electrically connected to the output end of the second amplifier, a second end of the tenth switch is electrically connected to the first end of the eleventh switch, and a third end of the tenth switch serves as a transmitting end of the transceiver; The second end of the eleventh switch is electrically connected to the fifth output end of the clock unit, and the third end of the eleventh switch is electrically connected to the input end of the second attenuator; The first controlled end of the first switch, the second controlled end of the first switch, the controlled end of the second switch, the controlled end of the third switch, the controlled end of the fourth switch, the controlled end of the fifth switch, the controlled end of the sixth switch, the controlled end of the seventh switch, the first controlled end of the eighth switch, the second controlled end of the eighth switch, the controlled end of the ninth switch, the controlled end of the tenth switch and the controlled end of the eleventh switch are all electrically connected to the control end of the digital front end.

19. A method for detecting anomalies of a transceiver, characterized in that: The abnormality detection system for a transceiver according to any one of claims 1 to 18, the method comprising: When the abnormal detection condition is met, the baseband chip generates a first detection instruction, so that the transceiver responds to the first detection instruction and constructs a first detection loop for transmitting a local oscillator signal, wherein the first detection loop includes a receiving channel in the transceiver; The baseband chip generates a second detection instruction according to the reference clock signal and the local oscillator signal, so that the transceiver responds to the second detection instruction and constructs a second detection loop including any one of the first devices under test in the receiving channel, wherein the second detection loop is used to transmit the first digital signal; The baseband chip generates a first detection result for characterizing an abnormality of the first device under test according to a reference digital signal and the first digital signal.

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