A high-power instrument bus host sending circuit based on a comparator

Abstract

This invention proposes a comparator-based high-power instrument bus master transmission circuit to address the technical problems of high cost and poor compatibility in existing industrial instrument fieldbuses. The invention includes a master controller connected to a signal isolation circuit, which in turn is connected to a signal conversion circuit. The signal conversion circuit is connected to the fieldbus and further connected to a power control and protection circuit and a communication acceleration circuit. The power control and protection circuit is connected to a power supply. The power control and protection circuit is connected to the master controller, and the signal isolation circuit is connected to the communication acceleration circuit. This invention utilizes multiple comparator chips and adds a communication acceleration function circuit, enabling high-speed data transmission at the same bit rate within the bus system, as well as data transmission at different baud rates. This improves the bus's anti-interference capability and load capacity, and solves the problem of communication interference caused by parasitic capacitance and inductance of slave devices and wires in long-distance cabling and with a large number of slave devices.

Description

Technical Field

[0001] This invention relates to the technical field of instrumentation, and more particularly to a high-power instrument bus host transmission circuit. Background Technology

[0002] Field instrument bus communication generally adopts a master-slave half-duplex bus transmission architecture. Currently, there are various bus communication methods on the market, such as two-bus, three-bus, and four-bus. Among them, two-bus is widely used in various instrument systems due to its low cost, simple structure, long communication distance, and strong scalability.

[0003] Existing industrial instrument fieldbus systems generally use bus methods such as RS485, M-BUS, and POWERBUS. Among them, RS485 bus typically requires four-wire communication, with two power supplies and two differential signal lines for communication. This solution is expensive, has weak load capacity, low communication speed, poor anti-interference ability, and short communication distance, and is gradually being phased out by the market. M-BUS and POWERBUS are newer two-wire communication methods that use downlink voltage communication and uplink current loop communication. Their communication lines can provide both power and communication. Although their communication methods have certain advantages, this communication system requires dedicated M-BUS or POWERBUS communication chips for data transmission, resulting in higher costs, poor scalability, lower communication speed, and susceptibility to factors such as bus parasitic capacitance and inductance, thus limiting its application range.

[0004] Utility model patent application number 202322374653.3 discloses an anti-interference communication converter, belonging to the field of communication technology. It includes: an external power supply circuit for power supply; a first conversion circuit connected to the external power supply circuit for voltage conversion; a power isolation circuit connected to the external power supply circuit for isolating voltage from the external power supply circuit; a second conversion circuit connected to the power isolation circuit; an RS485 signal transceiver circuit connected to the first conversion circuit for switching the sending and receiving states of the 485 communication signal; and a controller connected to the RS485 signal transceiver circuit for receiving, sending, and processing signals. This utility model enables bus communication between a host controller with a 232 bus interface and field sensors and actuators with a 485 bus interface. It facilitates field data acquisition or detection and control of downlink control commands, data transmission, automatic control, and remote operation, while also providing data isolation transmission and protection against overvoltage-induced safety accidents. However, it has a low transmission rate and poor load capacity when communicating over long distances in the field. It is also prone to damage when multiple slave devices upload data at the same time. This type of communication method has been gradually phased out by the market. Summary of the Invention

[0005] To address the technical problems of high cost and poor compatibility of existing industrial instrument fieldbuses, this invention proposes a high-power instrument bus host transmitting circuit based on a comparator. This instrument bus communication circuit, implemented with discrete components, can significantly reduce product manufacturing costs. It also incorporates signal isolation circuitry and is directly compatible with the serial TTL interface signals output by existing main control circuits.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows: a high-power instrument bus host transmitting circuit based on a comparator includes a host controller, wherein the host controller is connected to a signal isolation circuit, the signal isolation circuit is connected to a signal conversion circuit, the signal conversion circuit is connected to a fieldbus, the signal conversion circuit is also connected to a power control and protection circuit and a communication acceleration circuit, and the power control and protection circuit is connected to a power supply; the power control and protection circuit is connected to the host controller, and the signal isolation circuit is connected to the communication acceleration circuit.

[0007] Preferably, the signal conversion circuit includes a first comparator and a first switching circuit. One input terminal of the first comparator is connected to the output signal of the signal isolation circuit, and the other input terminal of the first comparator is connected to the first reference voltage circuit. The output terminal of the first comparator is connected to one input terminal of the first switching circuit, and the other input terminal of the first switching circuit is connected to the output terminal of the power control and protection circuit. The output terminal of the first switching circuit is connected to the fieldbus through diode D1.

[0008] Preferably, the communication acceleration circuit includes a second comparator, a third comparator, and a MOSFET Q3. One input terminal of each of the second and third comparators is connected to the output signal of the signal isolation circuit. The other input terminal of the second comparator is connected to the second reference voltage circuit, and the other input terminal of the third comparator is connected to the third reference voltage circuit. The output terminals of both the second and third comparators are connected to the gate of the MOSFET Q3. The drain of the MOSFET Q3 is connected to the fieldbus, and the source of the MOSFET Q3 is grounded.

[0009] Preferably, the first reference voltage circuit, the second reference voltage circuit, and the third reference voltage circuit each include a first resistor and a second resistor connected in series. One end of the first resistor is connected to the output terminal of the power control and protection circuit, and the other end of the first resistor is connected to one end of the second resistor. The other end of the first resistor and one end of the second resistor are connected as output terminals to the other input terminal of the first comparator, the second comparator, or the third comparator. A first capacitor is connected in parallel across the two ends of the second resistor.

[0010] Preferably, the output voltage of the first reference voltage circuit of the first comparator is the intermediate voltage of the output signal of the signal isolation circuit, and the output voltage of the first reference voltage circuit of the first comparator is located between the output voltages of the second reference voltage circuit of the second comparator and the third reference voltage circuit of the third comparator.

[0011] Preferably, the power control and protection circuit includes a switching circuit, an overload protection circuit, and a power control circuit. One input terminal of the switching circuit is connected to the power supply, and the other input terminal of the switching circuit is connected to both the overload protection circuit and the power control circuit. The output terminal of the switching circuit obtains an output voltage through the overload protection circuit.

[0012] Preferably, the power control circuit includes a power isolation circuit and a MOSFET Q6. The input terminal of the power isolation circuit is connected to the host controller, the output terminal of the power isolation circuit is connected to the gate of the MOSFET Q6, the source of the MOSFET Q6 is grounded, and the drain of the MOSFET Q6 is connected to the other input terminal of the switching circuit.

[0013] Preferably, the overload protection circuit includes a resettable fuse and a transistor Q5. The base of transistor Q5 is connected to the output terminal of the switching circuit and one end of the resettable fuse through resistor R24. The emitter of transistor Q5 is connected to one end of resistor R22. The collector of transistor Q5 is connected to the other input terminal of the switching circuit. The other end of the resettable fuse is connected to the other end of resistor R22. One end of resistor R22 receives the output voltage.

[0014] Preferably, the switching circuit includes a PMOS transistor Q4. The gate of the PMOS transistor Q4 is connected to one end of resistor R23, one end of resistor R25, and the collector of transistor Q5 in the overload protection circuit. The other end of resistor R25 is connected to the drain of MOS transistor Q6. The drain of PMOS transistor Q4 is connected to the positive terminal of the power supply. The source of PMOS transistor Q4 is connected to the other end of resistor R23 and one end of the resettable fuse in the overload protection circuit.

[0015] Preferably, both the signal isolation circuit and the power isolation circuit include a first transistor and an optocoupler. The base of the first transistor is connected to the input signal and is grounded through a third resistor. The collector of the first transistor is connected to one input terminal of the optocoupler. One output terminal of the optocoupler serves as the output terminal. The other input terminal of the optocoupler, the other output terminal of the optocoupler, and the source of the first transistor are all grounded. One input terminal of the optocoupler and the collector of the first transistor are both connected to a 5V voltage through a fourth resistor. One output terminal of the optocoupler is connected to one end of a fifth resistor and a sixth resistor, respectively. The other end of the fifth resistor is connected to a positive voltage, and the other end of the sixth resistor is grounded.

[0016] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention uses multiple comparator chips and adds a communication acceleration circuit, which can increase the same-signal bit rate of the bus system from the commonly used 4800 to a high-speed data transmission of over 19200. It enables data transmission at different baud rates on the bus, improves the bus's anti-interference capability and load capacity, and solves the problem of the impact of parasitic capacitance and inductance of slave devices and wires on communication during long-distance cabling and with a large number of slave devices. Reliable transmission over a distance of over 3000 meters can be achieved. The signal conversion circuit uses high-power MOSFETs, enabling a continuous drive capability of over 70A, increasing the number of slave devices it can handle. This invention also adds an overload protection circuit, providing protection against instantaneous and continuous overloads, thus improving the overall stability of the circuit. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit block diagram of the present invention.

[0019] Figure 2 for Figure 1 The circuit diagram of the signal transmission circuit shown is shown.

[0020] Figure 3 This is a circuit diagram of the power control circuit of the present invention.

[0021] Figure 4 This is a graph of the output voltage signal of the signal isolation circuit of the present invention.

[0022] Figure 5 This is a schematic diagram of the output voltage signals of the three comparators of the present invention.

[0023] In the diagram, 1 is the host controller, 2 is the signal isolation circuit, 3 is the signal conversion circuit, 4 is the power control and protection circuit, 41 is the power control circuit, 42 is the overload protection circuit, 43 is the switching circuit, 5 is the power supply, 6 is the communication acceleration circuit, and 7 is the fieldbus. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] like Figure 1 As shown, a high-power instrument bus host transmitting circuit based on a comparator includes a host controller 1. The host controller 1 is connected to a signal isolation circuit 2, which is connected to a signal conversion circuit 3. The signal conversion circuit 3 is connected to a fieldbus 7, and the signal conversion circuit 3 is also connected to a power control and protection circuit 4 and a communication acceleration circuit 6. The power control and protection circuit 4 is connected to a power supply 5. The power control and protection circuit 4 is connected to the host controller 1, and the signal isolation circuit 2 is connected to the communication acceleration circuit 6. Figure 1 As shown, the circuit implementation process of the present invention is as follows: the host controller 1 sends a TTL signal to the signal isolation circuit 2. The signal isolation circuit 2 is used to isolate and protect the host controller 1 from interference from the fieldbus 7. The isolated signal drives the high-power MOS transistor Q1 through the comparator of the signal conversion circuit 3, converting the weak digital signal into a high-power voltage signal from the power supply 5. This voltage signal is generated by the power supply 5 and output to the fieldbus 7 after passing through the power control and protection circuit 4 and the signal conversion circuit 3. The communication acceleration circuit 6 is used to accelerate the conversion rate of the signal conversion circuit 3, thereby improving communication quality and communication efficiency.

[0026] Instrument bus communication systems typically consist of a master system and several slave systems. The transmission method primarily involves sending data commands to slave devices via voltage changes in downstream communication. When sending voltage, the master device's TTL serial port signal is converted into a voltage signal ranging from 0 to VCC. Upstream communication relies on the slave devices changing the load current on their buses to achieve reliable data transmission. This invention converts traditional serial TTL signals into voltage signals ranging from 0 to VCC. When there is no signal transmission on the bus, the signal line outputs VCC power. This VCC power supply uses a high-power MOSFET, which can provide a significant power boost to the slave devices. Upon receiving the signal, the slave devices generate a current signal to produce a response. The master output circuit of this invention has a simple structure, low cost, requires no dedicated communication chip, offers high communication speed, and strong anti-interference capability.

[0027] like Figure 2As shown, signal isolation circuit 2 includes transistor Q2 and optocoupler U1. The base of transistor Q2 is connected to the input signal, i.e., the TTL signal sent by host controller 1, through resistor R1. Resistor R1 is the current-limiting resistor for the TTL signal and can also be used with resistor R8 to divide the voltage and set the start-up time of transistor Q2. The base of transistor Q2 is grounded through resistor R8. Resistor R8 serves both as a voltage divider and as a default operating state for the circuit when the TTL signal is floating. The collector of transistor Q2 is connected to the input terminal A of optocoupler U1. The output terminal C of optocoupler U1 is used as the output terminal to obtain the SIGNAL signal. The other input terminal K of optocoupler U1, the other output terminal E of optocoupler U1, and the emitter of transistor Q2 are all grounded. The input terminal A of optocoupler U1 and the collector of transistor Q2 are both connected to a 5V voltage through resistor R2. Resistor R2 is a current-limiting resistor supplying power to the internal LED of optocoupler U1. R2 ensures that the internal LED of optocoupler U1 operates within its normal current range. The resistance of resistor R2 should be adjusted accordingly when different voltages are connected to the input terminal of optocoupler U1. One output terminal C of optocoupler U1 is connected to one end of resistors R4 and R9. The other end of resistor R4 is connected to the output voltage of signal conversion circuit 3, and the other end of resistor R9 is grounded. Resistors R4 and R9 are voltage divider resistors.

[0028] The signal conversion circuit 3 includes a comparator U2A and a first switching circuit. The inverting input of comparator U2A is connected to the output signal, SIGNAL, of signal isolation circuit 2 via resistor R7. Resistor R7 is a current-limiting resistor, ensuring that the output SIGNAL signal value is not affected by comparator U2A. The non-inverting input of comparator U2A is connected to the first reference voltage circuit. The first reference voltage circuit includes resistors R13 and R18 connected in series. One end of resistor R13 is connected to the voltage +V_1 output by power control and protection circuit 4, and the other end of resistor R13 is connected to one end of resistor R18. The other end of resistor R18 is grounded. Resistors R13 and R18 are voltage divider resistors, which can be used to set the reference voltage at the input of comparator U2A. A capacitor C1 is connected in parallel across resistor R18. Capacitor C1 stabilizes the reference voltage generated by voltage divider resistors R13 and R18, ensuring that noise generated by the +V_1 signal during operation can be effectively filtered out, thus guaranteeing the stability and reliability of the REF_01 reference signal. The midpoint between resistors R13 and R18 serves as the output terminal, connected to the non-inverting input of comparator U2A.

[0029] The output of comparator U2A is connected to one input of the first switching circuit via resistor R6. The other input of the first switching circuit is connected to the output of the power control and protection circuit 4. The output of the first switching circuit is connected to the fieldbus 7 via diode D1. The first switching circuit includes a MOSFET Q1. The gate of MOSFET Q1 is connected to resistor R6, the drain of MOSFET Q1 is connected to the anode of diode D1, and the cathode of diode D1 is connected to BUS+ of fieldbus 7. The other end of fieldbus 7 is BUS- and grounded via resistor R5. Resistor R5 is the sampling resistor of the receiving circuit, usually composed of small resistors. The host controller 1 obtains the signal sent by the slave device by acquiring the voltage signal of resistor R5. A resistor R3 is provided between the source and gate of MOSFET Q1. During operation, when comparator U2A outputs a low level, resistors R6 and R3 generate a voltage divider, creating a voltage value between pins 1 and 3 of MOSFET Q1 that can drive MOSFET Q1 to operate, causing MOSFET Q1 to conduct and output a high-level signal. Resistors R3 and R6 divide the voltage to drive MOSFET Q1. When comparator U2A fails, resistor R3 pulls the supply voltage to pin 1 of MOSFET Q1 to +V_1, turning MOSFET Q1 off. The source of MOSFET Q1 receives the output voltage +V_1 signal.

[0030] The protected TLL signal output by the host controller 1 drives transistor Q2. After passing through optocoupler U1, a variable voltage signal—SIGNAL signal—is output at the output terminal of optocoupler U1. After passing through optocoupler U1, it drives comparator U2A, which can quickly turn MOSFET Q1 on and off, thereby sending high and low level signals to slave devices. Diode D1 is used to isolate the high voltage reverse surge caused by bus parasitic inductance and parasitic capacitance after MOSFET Q1 is turned off.

[0031] As a feasible solution, to improve the system's data transmission speed and reduce the impact of bus parasitic capacitance and inductance, a communication acceleration function circuit was added at BUS+, such as... Figure 2As shown, the communication acceleration circuit 6 includes comparator U2B, a comparator, and an N-type MOSFET Q3. The inverting inputs of both comparator U2B and comparator U3A are connected to the signal voltage signal—SIGNAL—output from the signal isolation circuit 2. The non-inverting input of comparator U2B is connected to the second reference voltage circuit, and the non-inverting input of comparator U3A is connected to the third reference voltage circuit. The output of comparator U2B is connected to the gate of MOSFET Q3 through resistor R11. The drain of MOSFET Q3 is connected to BUS+ of the fieldbus 7. The output of comparator U3A is connected to the gate of MOSFET Q3 through resistor R16. The source of MOSFET Q3 is grounded. Resistors R11 and R16 are composed of small-value resistors, typically 100Ω, used for current limiting to ensure that when comparator U2B or U3A is working, it can quickly pull the voltage at pin 1 of MOSFET Q3 to near 0V, causing it to turn off quickly. The gate of MOSFET Q3 is connected to one end of resistors R10 and R21, respectively. The other end of resistor R10 is connected to the output voltage +V_1, and the other end of resistor R21 is grounded. Resistors R10 and R21 form a voltage divider, dividing the voltage of the output voltage +V_1 signal to provide a normal turn-on voltage for MOSFET Q3. Figure 2 As shown, comparators U2B and U3A together form an AND gate circuit to simultaneously drive the MOSFET Q3 to turn on and off. When the N-type MOSFET Q3 is on, it can quickly pull the parasitic voltage on the bus to a low level, enabling fast data transmission.

[0032] The second reference voltage circuit includes resistors R14 and R19 connected in series, with capacitor C2 connected in parallel across resistor R19. One end of resistor R14 is connected to the output voltage +V_1, and the other end of resistor R14 is connected to one end of resistor R19. The other end of resistor R19 is grounded. The other end of resistor R14 and one end of resistor R19 serve as output terminals connected to the non-inverting input terminal of comparator U2B. The third reference voltage circuit includes resistors R15 and R20 connected in series, with capacitor C2 connected in parallel across resistor R20. One end of resistor R15 is connected to the output voltage +V_1, and the other end of resistor R15 is connected to one end of resistor R20. The other end of resistor R19 is grounded. The other end of resistor R15 and one end of resistor R20 serve as output terminals connected to the non-inverting input terminal of comparator U3A.

[0033] The output voltage of the first reference voltage circuit of the comparator U2A is the intermediate voltage of the output signal of the signal isolation circuit 2. The output voltage of the first reference voltage circuit of the first comparator U2A is located between the output voltages of the second reference voltage circuit of the comparator U2B and the third reference voltage circuit of the comparator U3A.

[0034] To ensure the normal operation of the circuit, appropriate reference voltage and signal acquisition points need to be set for the comparator. The signal acquisition point should be set at the voltage signal output after the TLL signal output from the host controller 1 passes through the optocoupler U1, such as... Figure 2 The SIGNAL signal is shown below. When the phototransistor of the optocoupler U1 receives the light signal emitted by the light-emitting diode, the voltage signal output from its pin 4 is as follows: Figure 4 As shown, during the signal rise and fall, a voltage signal with a steep rise and a steep fall will be output. When setting the reference voltage, the voltages at points b and e should be set as the reference points for comparator U2A, the voltages at points a and f as the reference voltages for comparator U2B, and the voltages at points c and d as the reference voltages for comparator U3A. This reference voltage value is compared with the SIGNAL signal voltage, and the waveforms of the output voltage values ​​after passing through comparators U2A, U2B, and U3A are shown below. Figure 5 As shown, when the voltage rises and falls, the voltage change point of comparator U2A is exactly located at the midpoint between comparators U2B and U3A. By setting the three reference voltage values, it can be ensured that MOSFET Q3 only starts to conduct after MOSFET Q1 is turned off, and MOSFET Q1 only starts to conduct after MOSFET Q3 is turned off. This avoids damage to the devices caused by MOSFETs Q1 and Q3 conducting simultaneously, and also accelerates the discharge for bus data transmission.

[0035] like Figure 3 As shown, the power control and protection circuit 4 includes a switching circuit 43, an overload protection circuit 42, and a power control circuit 41. One input terminal of the switching circuit 43 is connected to the power supply 5, and the other input terminal of the switching circuit 43 is connected to both the overload protection circuit 42 and the power control circuit 41. The output terminal of the switching circuit 43 obtains its output voltage through the overload protection circuit 42. The switching circuit 43 is powered by the +V bus of the power supply 5.

[0036] The power control circuit 41 includes a power isolation circuit and a MOSFET Q6. The input terminal of the power isolation circuit is connected to the host controller 1, and the output terminal of the power isolation circuit is connected to the gate of the MOSFET Q6. The source of the MOSFET Q6 is grounded, and the drain of the MOSFET Q6 is connected to the other input terminal of the switching circuit 43 through a resistor R25. When the MOSFET Q6 is turned on, resistors R25 and R23 divide the voltage to generate a voltage value that can drive the PMOS transistor Q4 to start normally, thus starting the PMOS transistor Q4 and providing a power supply labeled +V_1 to the subsequent circuits.

[0037] The switching circuit 43 includes a PMOS transistor Q4. The gate of PMOS transistor Q4 is connected to one end of resistor R23, one end of resistor R25, and the collector of transistor Q5 in the overload protection circuit 42. The other end of resistor R25 is connected to the drain of MOS transistor Q6. The drain of PMOS transistor Q4 is connected to the positive terminal of power supply 5. The source of PMOS transistor Q4 is connected to the other end of resistor R23 and one end of the resettable fuse F1 in the overload protection circuit 42. Resistors R23 and R25 are connected in series for voltage division. When MOS transistor Q6 is turned off, resistor R23 can pull up the voltage at pin 1 of PMOS transistor Q4, thus turning off the power supply to PMOS transistor Q4. Diodes are connected in anti-parallel to MOS transistors Q1, Q3, Q4, and Q6.

[0038] The power isolation circuit includes transistor Q7 and optocoupler U5. The base of transistor Q7 is connected to the switching signal of host controller 1 through resistor R30, which is a current-limiting protection resistor and typically has a small resistance. Resistor R30 is grounded through resistor R31 and connected to a 5V voltage through resistor R27. Resistors R27 and R31 form a voltage divider network, providing a voltage for the start-up of transistor Q7 and also adapting to the input level of the ON / OFF signal. When ON / OFF is floating, it ensures that the power supply to the network is off. The collector of transistor Q7 is connected to the input terminal A of optocoupler U5. The output terminal C of optocoupler U5 serves as the output terminal. The input terminal K of optocoupler U5, the output terminal E of optocoupler U5, and the emitter of transistor Q7 are all grounded. The input terminal A of optocoupler U5 and the collector of transistor Q7 are both connected to a 5V voltage through resistor R29. Resistor R29 provides a current-limiting resistor for the internal LED AK of optocoupler U5. When transistor Q7 is open, optocoupler U5 emits light to generate a signal. When transistor Q7 is on, pins 1 and 2 of optocoupler U5 are short-circuited, and the internal LED does not emit light. The output terminal C of optocoupler U5 is connected to one end of resistors R26 and R28. The other end of resistor R26 is connected to the positive terminal of power supply 5, the negative terminal of power supply 5 is grounded, and the other end of resistor R28 is grounded. Resistors R26 and R28 form a voltage divider resistor, providing a bias voltage for MOSFET Q6. The output terminal C of optocoupler U5 is connected to the gate of MOSFET Q6. The voltage division generated by resistors R26 and R28 ensures that MOSFET Q6 can be switched normally when optocoupler U5 is working.

[0039] Among them, optocoupler U5 is used to isolate the IO signal output by host controller 1, and N-type MOSFET Q6 is used to switch the PMOS transistor Q4 for the main power supply. During normal operation, when the ON / OFF level is high, transistor Q7 is turned on, and at this time the gate of MOSFET Q6 is high and turned on, thereby starting PMOS transistor Q4 to turn on and realize the power supply of the entire system.

[0040] The overload protection circuit 42 includes a resettable fuse F1 and a transistor Q5. The base of transistor Q5 is connected to the output terminal of the switching circuit 43 and one end of the resettable fuse F1 via a resistor R24. The emitter of transistor Q5 is connected to one end of a resistor R22, and the collector of transistor Q5 is connected to the other input terminal of the switching circuit 43. The other end of the resettable fuse F1 is connected to the other end of a resistor R22, and the output voltage is obtained from one end of resistor R22. The overload protection circuit 42 of this invention includes instantaneous overload and continuous overload protection, respectively composed of... Figure 3 Resistors R22 and R24, resettable fuse F1, and transistor Q5 are shown to provide overload protection. During a momentary overload, due to the slow response of the resettable fuse F1, an overvoltage greater than 0.9V is generated across resistor R22. At this time, transistor Q5 conducts, short-circuiting pins 1 and 3 of PMOS transistor Q4, thereby shutting off the power supply to the entire system to achieve overload protection. During sustained overload, the internal resistance of the resettable fuse F1 increases, providing continuous protection for the system.

[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high power instrument bus master transmitter circuit based on a comparator, comprising a master controller (1), characterized in that, The host controller (1) is connected to the signal isolation circuit (2), the signal isolation circuit (2) is connected to the signal conversion circuit (3), the signal conversion circuit (3) is connected to the fieldbus (7), the signal conversion circuit (3) is also connected to the power control and protection circuit (4) and the communication acceleration circuit (6) respectively, and the power control and protection circuit (4) is connected to the power supply (5); the power control and protection circuit (4) is connected to the host controller (1), and the signal isolation circuit (2) is connected to the communication acceleration circuit (6); The communication acceleration circuit (6) includes a second comparator, a third comparator, and a MOS transistor Q3. The inverting input terminals of the second and third comparators are connected to the output signal of the signal isolation circuit (2). The non-inverting input terminal of the second comparator is connected to the second reference voltage circuit, and the non-inverting input terminal of the third comparator is connected to the third reference voltage circuit. The output terminals of the second and third comparators are connected to the gate of the MOS transistor Q3. The drain of the MOS transistor Q3 is connected to the fieldbus (7), and the source of the MOS transistor Q3 is grounded.

2. The comparator-based high power instrument bus master transmit circuit of claim 1, wherein, The signal conversion circuit (3) includes a first comparator and a first switching circuit. The inverting input of the first comparator is connected to the output signal of the signal isolation circuit (2), and the non-inverting input of the first comparator is connected to the first reference voltage circuit. The output of the first comparator is connected to one input of the first switching circuit, and the other input of the first switching circuit is connected to the output of the power control protection circuit (4). The output of the first switching circuit is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the fieldbus (7).

3. The comparator-based high power instrument bus master drive circuit of claim 2, wherein, The first reference voltage circuit, the second reference voltage circuit, and the third reference voltage circuit all include a first resistor and a second resistor connected in series. One end of the first resistor is connected to the output terminal of the power control protection circuit (4), and the other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is grounded. The other end of the first resistor and one end of the second resistor are connected as output terminals to the inverting input terminals of the first comparator, the second comparator, or the third comparator. A first capacitor is connected in parallel across the two ends of the second resistor.

4. The comparator-based high power instrument bus master drive circuit of claim 2, wherein, The output voltage of the first reference voltage circuit of the first comparator is the middle voltage of the output signal of the signal isolation circuit (2), and the output voltage of the first reference voltage circuit of the first comparator is located in the middle of the output voltage of the second reference voltage circuit of the second comparator and the third reference voltage circuit of the third comparator.

5. The comparator-based high power instrument bus master drive circuit of any of claims 1-4, wherein, The power control and protection circuit (4) includes a switching circuit (43), an overload protection circuit (42), and a power control circuit (41). One input terminal of the switching circuit (43) is connected to the power supply (5), and the other input terminal of the switching circuit (43) is connected to the overload protection circuit (42) and the power control circuit (41) respectively. The output terminal of the switching circuit (43) obtains the output voltage through the overload protection circuit (42).

6. The high-power instrument bus host transmitting circuit based on a comparator according to claim 5, characterized in that, The power control circuit (41) includes a power isolation circuit and a MOSFET Q6. The input terminal of the power isolation circuit is connected to the host controller (1), the output terminal of the power isolation circuit is connected to the gate of the MOSFET Q6, the source of the MOSFET Q6 is grounded, and the drain of the MOSFET Q6 is connected to the other input terminal of the switching circuit (43).

7. The high-power instrument bus host transmitting circuit based on a comparator according to claim 6, characterized in that, The overload protection circuit (42) includes a resettable fuse and a transistor Q5. The base of transistor Q5 is connected to the output terminal of the switching circuit (43) and one end of the resettable fuse through resistor R24. The emitter of transistor Q5 is connected to one end of resistor R22. The collector of transistor Q5 is connected to the other input terminal of the switching circuit (43). The other end of the resettable fuse is connected to the other end of resistor R22. One end of resistor R22 receives the output voltage.

8. The comparator-based high-power instrument bus master transmission circuit according to claim 6 or 7, characterized in that, The switching circuit (43) includes a PMOS transistor Q4. The gate of the PMOS transistor Q4 is connected to one end of resistor R23, one end of resistor R25, and the collector of transistor Q5 in the overload protection circuit (42). The other end of resistor R25 is connected to the drain of MOS transistor Q6. The drain of PMOS transistor Q4 is connected to the positive terminal of power supply (5). The source of PMOS transistor Q4 is connected to the other end of resistor R23 and one end of the resettable fuse in the overload protection circuit (42).

9. The high-power instrument bus host transmitting circuit based on a comparator according to claim 6, characterized in that, The signal isolation circuit (2) and the power isolation circuit both include a first transistor and an optocoupler. The base of the first transistor is connected to the input signal. The base of the first transistor is grounded through a third resistor. The collector of the first transistor is connected to one input terminal of the optocoupler. One output terminal of the optocoupler is used as the output terminal. The other input terminal of the optocoupler, the other output terminal of the optocoupler, and the source of the first transistor are all grounded. One input terminal of the optocoupler and the collector of the first transistor are both connected to a 5V voltage through a fourth resistor. One output terminal of the optocoupler is connected to one end of a fifth resistor and a sixth resistor, respectively. The other end of the fifth resistor is connected to a positive voltage, and the other end of the sixth resistor is grounded.

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