Radio frequency controller and electronic device

Abstract

Embodiments of the present application provide a radio frequency controller and an electronic device, which are used to improve the success rate of data transmission. The electronic device comprises a central processor and the radio frequency controller. The radio frequency controller comprises a switching network, at least one frame timer and at least one timing processor. The at least one frame timer and the at least one timing processor are connected with the timing switching network. The central processor is configured to determine a target frame timer corresponding to a first task from the at least one frame timer and determine a target timing processor corresponding to the first task from the at least one timing processor when the first task is started. The target frame timer is configured to perform frame counting. The timing switching network is configured to associate the target frame timer with the target timing processor. The target timing processor is configured to execute the first task when the count value of the target frame timer is the same as a time parameter stored in the target timing processor.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more particularly to a radio frequency controller and electronic device. Background Technology

[0002] In wireless communication systems, the most common method to synchronize data transmission between electronic devices and the network is through a radio frequency (RF) controller. For example, the RF controller compares the time parameters stored in its frame timing module and timing processing module. Data transmission occurs when the count value in the frame timing module matches the time parameter stored in the timing processing module.

[0003] However, in dual-mode or multi-mode systems, when switching from one communication mode to another, it may be necessary to adjust the phase of the frame timing module. After the phase of the frame timing module is adjusted, the radio frequency controller may trigger data transmission at the wrong time, resulting in data transmission failure. Summary of the Invention

[0004] This application provides a radio frequency controller and electronic device for improving the success rate of data transmission.

[0005] In a first aspect, a radio frequency (RF) controller is provided, which can be disposed in an electronic device. The electronic device includes a central processing unit (CPU) and the RF controller, the CPU being connected to the RF controller. The RF controller includes a switching network, at least one frame timer, and at least one timing processor, the at least one frame timer and the at least one timing processor being connected to the timing switching network. The CPU is configured to, upon initiation of a first task, determine a target frame timer corresponding to the first task from the at least one frame timer, and determine a target timing processor corresponding to the first task from the at least one timing processor. The target frame timer is configured to perform frame counting. The timing switching network is configured to associate the target frame timer with the target timing processor. The target timing processor is configured to execute the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

[0006] In one possible implementation, the radio frequency controller further includes a first arbitrator connected to the at least one timing processor, for determining whether a data transmission instruction output by the target timing processor conflicts with data transmission instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor among the at least one timing processors.

[0007] In one possible implementation, the first arbitrator is specifically configured to: determine the data transmission interface indicated by the data transmission instruction output by each of the at least one timing processor; if the first data transmission instruction output by the target timing processor is the same as the data transmission interface indicated by the second data transmission instruction output by the first timing processor in the other timing processors, then determine that the data transmission instructions output by the target timing processor and the first timing processor conflict.

[0008] In one possible implementation, the radio frequency controller further includes an interface control module connected to the first arbiter, the interface control module including at least one data transmission interface.

[0009] In one possible implementation, the radio frequency controller further includes at least one instruction cache module, which corresponds one-to-one with the at least one data transmission interface.

[0010] In one possible implementation, the first arbitrator is further configured to: when a first data transmission instruction output by the target timing processor conflicts with a second data transmission instruction output by a first timing processor among the other timing processors, determine the execution order of the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor; and input the first data transmission instruction and the second data transmission instruction into a first instruction cache module among the at least one instruction cache module based on the execution order, wherein the first instruction cache module corresponds to a first data transmission interface, and the first data transmission interface is the data transmission interface indicated by the first data transmission instruction and the second data transmission instruction.

[0011] In one possible implementation, the radio frequency controller further includes a data memory connected to the at least one timing processor for storing intermediate data generated by the at least one timing processor when performing a task, and / or task data required by the at least one timing processor to perform a task.

[0012] In one possible implementation, the radio frequency controller further includes a second arbitrator, which is connected to the at least one timing processor and the data memory. The second arbitrator is used to determine whether the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor among the at least one timing processors.

[0013] In one possible implementation, the second arbitrator is further configured to: determine the execution order of the first data read / write instruction and the second data read / write instruction according to the priority of the target timing processor and the second timing processor when the first data read / write instruction output by the target timing processor conflicts with the second data read / write instruction output by the second timing processor among the other timing processors.

[0014] In a second aspect, a data transmission method is provided, which can be applied to the electronic device described in the first aspect. The method includes: when a first task is started, determining a target frame timer corresponding to the first task from at least one frame timer, determining a target timing processor corresponding to the first task from the at least one timing processor, and executing the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

[0015] In one possible implementation, the method further includes: determining whether the data transmission instruction output by the target timing processor conflicts with the data transmission instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor among the at least one timing processors.

[0016] In one possible implementation, determining whether a data transmission instruction output by the target timing processor conflicts with data transmission instructions output by other timing processors includes: determining the data transmission interface indicated by the data transmission instruction output by each of the at least one timing processors; if the first data transmission instruction output by the target timing processor is the same as the data transmission interface indicated by the second data transmission instruction output by the first timing processor in the other timing processors, then determining that the data transmission instructions output by the target timing processor and the first timing processor conflict.

[0017] In one possible implementation, the method further includes: when a first data transmission instruction output by the target timing processor conflicts with a second data transmission instruction output by a first timing processor among the other timing processors, executing the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor.

[0018] In one possible implementation, the method further includes: determining whether the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor among the at least one timing processors.

[0019] In one possible implementation, determining whether the data read / write instructions output by the target timing processor conflict with data read / write instructions output by other timing processors includes: when the first data read / write instruction output by the target timing processor conflicts with the second data read / write instruction output by the second timing processor among the other timing processors, determining the execution order of the first data read / write instruction and the second data read / write instruction according to the priority of the target timing processor and the second timing processor.

[0020] Thirdly, an electronic device is provided, comprising the radio frequency controller and central processing unit as described in any one of the first aspects above.

[0021] Fourthly, a communication device is provided, the device comprising:

[0022] Memory, used to store program instructions;

[0023] A processor is configured to invoke program instructions stored in the memory and execute the steps included in either of the methods described in accordance with the obtained program instructions.

[0024] Fifthly, a computationally readable storage medium is provided, the computationally readable storage medium storing computer-executable instructions for causing a computer to perform the steps included in any of the methods described in the second aspect.

[0025] Sixthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to execute the data transmission method described in the various possible implementations above.

[0026] In this embodiment, the radio frequency processor may include multiple frame timers, allowing the central processing unit to configure separate frame timers for different communication modes in a dual-mode or multi-mode system. This eliminates the need to adjust the phase of the frame timers when switching from one communication mode to another, reducing the probability of data transmission commands being triggered at incorrect times and improving data transmission success rate. Furthermore, in this embodiment, the radio frequency processor may also include multiple timing processors, enabling different timing processors to store data transmission commands for different communication modes in a dual-mode or multi-mode system. The timing of the data transmission commands stored in different timing processors is related to their corresponding communication mode. Therefore, even when switching from one communication mode to another, and even if the phase of the frame timers is adjusted, triggering data transmission commands at incorrect times can be avoided, further improving data transmission success rate.

[0027] In addition, in this embodiment, the timing processor can be scheduled as a shared resource, without the need to design frame timers and timing processors in pairs. That is, in a certain communication mode, at most all timing processors can be called to execute timing tasks, so that multiple tasks can be parallelized, effectively improving resource utilization. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application.

[0029] Figure 1 This is a schematic diagram of the structure of an electronic device;

[0030] Figure 2 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of the structure of a timing processor;

[0032] Figure 4 This is a schematic diagram of the structure of a radio frequency controller provided in an embodiment of this application;

[0033] Figure 5 A flowchart illustrating a data transmission method provided in an embodiment of this application;

[0034] Figure 6 This is a schematic diagram of the communication device in an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0036] The terms "first" and "second" in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive protection. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. The term "multiple" in this application can mean at least two, for example, two, three, or more, and the embodiments of this application do not impose limitations.

[0037] The design concept of this application is described below.

[0038] As mentioned earlier, in wireless communication systems, the most common method to synchronize data transmission between electronic devices and the network is through a radio frequency controller. For example, in a Time Division Synchronous Code Division Multiple Access (D-SCDMA) system, to receive information from a specific time slot, the timing processing module of an electronic device stores at least two instructions: a data reception start instruction and a data reception stop instruction. These instructions contain time parameters. The timing processing module compares the time parameters in each instruction with the count value of the frame timing module. When the count value of the frame timing module matches the time parameter in the data reception start instruction, the interface control module is triggered to start receiving data; when the count value of the frame timing module matches the time parameter in the data reception stop instruction, the interface control module is triggered to stop receiving data.

[0039] However, in dual-mode or multi-mode systems, when switching from one communication mode to another, it is often necessary to adjust the phase of the frame timing module for the current communication mode. Once the phase of the frame timing module is adjusted, it may affect the triggering of instructions already configured in the timing processing module before the adjustment. For example, if the data reception start instruction 1 and data reception stop instruction 1 were stored in the timing processing module before the phase of the frame timing module was adjusted, then after the phase of the frame timing module is adjusted, the data reception start instruction 1 and data reception stop instruction 1 may be triggered at the wrong time, resulting in data reception failure.

[0040] In related technologies, one solution to address this technical problem is to pair frame timing modules and timing processors to support multiple communication modes. However, under multiple communication modes, configuring the number of timing processors according to the type of communication mode may lead to design redundancy, resulting in low resource utilization of timing processors. Furthermore, under the same communication mode, multiple timing tasks can only be processed serially, resulting in low data transmission efficiency.

[0041] Therefore, this application provides a radio frequency (RF) controller that can be applied to an electronic device. The electronic device includes the RF controller and a central processing unit (CPU). The RF controller includes a timing switching network, at least one frame timer, and at least one timing processor. The CPU can flexibly configure the association between the frame timers and the timing processors, allowing a timing processor to be associated with different frame timers at different times, reducing the number of timing processors required. Furthermore, the timing processors can be scheduled as shared resources, eliminating the need for paired design of frame timers and timing processors. That is, in a given communication mode, up to all timing processors can be invoked to execute timing tasks, enabling multiple tasks to run in parallel and effectively improving resource utilization.

[0042] After introducing the design concept of the embodiments of this application, the following is a brief introduction to the application scenarios to which the technical solutions of the embodiments of this application can be applied. It should be noted that the application scenarios described below are only for illustrating the embodiments of this application and are not intended to limit the scope. In specific implementation, the technical solutions provided by the embodiments of this application can be flexibly applied according to actual needs.

[0043] In this embodiment, the provided radio frequency controller can be applied to electronic devices. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this application. The electronic device includes a central processing unit (CPU) and a radio frequency (RF) controller. The CPU can generate instruction files and data files according to the requirements of upper-layer software. The instruction files include time parameters indicating the time of data transmission, and the data files can include task data required by the RF controller to perform its tasks. After generating the instruction files and data files, the CPU can send them to the RF controller.

[0044] Based on the above, the radio frequency controller provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0045] Please see Figure 2 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. The radio frequency controller can be applied to... Figure 1The electronic device shown. The radio frequency controller includes at least one frame timer (such as...). Figure 1 The frame timer 1, frame timer 2, ..., frame timer m shown), timing switching network, and at least one timing processor (such as...) Figure 1 The given sequence processors are 1, 2, ..., n, where m and n are positive integers.

[0046] A central processing unit is configured to, when a first task is started, determine the target frame timer corresponding to the first task from at least one (e.g., m) frame timers, and determine the target timing processor corresponding to the first task from at least one (e.g., n) timing processors.

[0047] A frame timer is used to synchronize and track wireless frames in electronic devices, i.e., to count them. The counting frequency is determined by the timing control accuracy requirements. For example, the chip rate of TD-SCDMA is 1.28 MHz, and the timing control accuracy requirement is one-eighth of a chip, so the frame timer counting frequency is 10.24 MHz.

[0048] A timing exchange network is used to associate the target frame timer with the target timing processor.

[0049] A timing processor is used to perform a data transfer task when its stored timing parameters match the count value of the associated frame timer. For example, a target timing processor performs this first task when its stored timing parameters match the count value of the target frame timer.

[0050] Optionally, m can be related to the number of communication modes included in the current communication system. For example, if the current communication system includes 4 communication modes, then m can be less than or equal to 4. When m = 4, one frame timer can correspond to one communication mode, so when switching from one communication mode to another, it is not necessary to adjust the phase of the frame timer.

[0051] In this embodiment of the application, when the electronic device transmits data with the network (e.g., to start a first task), the central processing unit of the electronic device can generate instruction files and data files according to the requirements of the upper-layer software, and determine at least one idle timing processor from the n timing processors, and determine a target timing processor for executing the first task from the at least one idle timing processor.

[0052] For example, the central processing unit (CPU) can determine the target timing processor from the at least one idle timing processor based on the importance of the first task. For instance, during baseband chip design, the n timing processors can be prioritized. When the CPU determines that the first task is of high importance, it can determine the timing processor with the highest priority among the at least one idle timing processors as the target timing processor. Optionally, if the RF controller includes multiple data transmission interfaces, the priorities of the n timing processors can be different for different data transmission interfaces. For example, if the RF controller includes two interfaces, namely interface 1 and interface 2, and n = 3, then for interface 1, the three timing processors are arranged in descending order of priority, for example, timing processor 2, timing processor 3, and timing processor 1; for interface 2, the three timing processors are arranged in descending order of priority, for example, timing processor 1, timing processor 2, and timing processor 3.

[0053] Alternatively, the central processing unit may randomly select a timing processor from the at least one idle timing processor and determine that timing processor as the target timing processor. It should be noted that the above method of determining the target timing processor is merely an example; in specific implementations, the target timing processor can be determined in other ways, and this application embodiment does not limit this approach.

[0054] Furthermore, the central processing unit (CPU) can determine the target frame timer corresponding to the first task from m frame timers based on the current communication mode of the electronic device. For example, if the number of frame timers is the same as the number of communication modes included in the current communication system, the CPU can pre-configure the association between frame timers and communication modes. When the first task starts, the CPU can determine the current communication mode of the electronic device and identify the frame timer associated with that communication mode as the target frame timer. Optionally, the frame timer corresponding to the first task can be a frame timer corresponding to other tasks, wherein the other tasks and the first task belong to the same communication mode.

[0055] Alternatively, the central processing unit (CPU) can randomly select one frame timer from the m frame timers and designate that frame timer as the target frame timer. Optionally, when the CPU randomly selects the target frame timer from the m frame timers, if the current phase of the target frame timer differs from the phase corresponding to the current communication mode, the CPU can also adjust the phase of the target frame timer based on the current communication mode.

[0056] After determining the target frame timer and the target timing processor, the central processing unit can send configuration information to the timing exchange network, which includes information for instructing the target frame timer and the target timing processor.

[0057] The timing exchange network can determine the target frame timer and the target timing processor based on this configuration information, and configure the target frame timer and the target timing processor to be associated.

[0058] Optionally, after determining the target timing processor, the central processing unit can write the generated instruction file into the random access memory (RAM) of the target timing processor. The target timing processor can then execute the first task based on the timing parameters included in the instruction file stored in its RAM and the corresponding frame timer count value.

[0059] For example, please refer to Figure 3 This is a schematic diagram of the structure of a sequential processor. For example... Figure 3 As shown, the timing processor includes an instruction fetch module, a storage module, a decoding module, and an execution module. The storage module stores instruction files; the instruction fetch module reads instructions from the storage module and caches them; the decoding module decodes the instructions in the instruction fetch module; and the execution module executes the data transmission task when the time indicated by the decoded instruction arrives (i.e., the time indicated by the decoded instruction is the same as the count value of the corresponding frame timer). Optionally, the timing processor may also include a sequence timer, which is controlled by the frame timer and can be started by the frame timer. After the sequence timer is started, the timing processor compares the count value of the sequence timer with the time parameters included in the instructions stored in its storage module. When the time parameters included in the instructions stored in its storage module are the same as the count value of its sequence timer, the data transmission task is executed.

[0060] Optional, please refer to Figure 4 The RF controller also includes a first arbitrator and an interface controller module. The first arbitrator is connected to the n timing processors and is used to determine whether data transmission commands output by the n timing processors conflict. For example, the first arbitrator can determine whether the data transmission command output by the target timing processor conflicts with data transmission commands output by other timing processors among the n timing processors excluding the target timing processor.

[0061] The interface control module includes at least one (e.g., K) data transmission interfaces. This interface control module is connected to the first arbiter and is used to receive data from or send data to the network according to data transmission instructions output by the timing processor. The K data transmission interfaces include, for example, general purpose output (GPO), serial peripheral interface (SPI) / radio frequency front-end (RFFE), transistor-transistor logic (TTL) interface, JESD interface, digital radio frequency (DigRF) interface, etc.

[0062] For example, the first arbitrator can determine the data transfer interface indicated by the data transfer instruction output by each of the n timing processors. If the data transfer instruction (e.g., the second data transfer instruction) output by the first timing processor in the other timing processors and the data transfer instruction (e.g., the first data transfer instruction) output by the target timing processor indicate the same data transfer interface, for example, if the data transfer interface indicated by the first data transfer instruction and the second data transfer instruction are both GPO, then the first arbitrator can determine that the data transfer instructions output by the target timing processor and the first timing processor conflict.

[0063] Optionally, before determining whether there is a conflict between the data transmission instructions output by the n timing processors, the first arbitrator can also determine whether the data transmission times indicated by the data transmission instructions output by the n timing processors are the same, and perform conflict detection on the data transmission instructions with the same data transmission times, that is, determine whether there is a conflict between the data transmission instructions. Taking the aforementioned first data transmission instruction and third data transmission instruction as examples, if the data transmission times indicated by the first data transmission instruction and the third data transmission instruction are different, that is, the execution times of the first task and the second task (the data transmission task corresponding to the third data transmission instruction) are different, it indicates that there is no conflict between the first data transmission instruction and the third data transmission instruction, and conflict detection for the first data transmission instruction and the third data transmission instruction is not required.

[0064] Optionally, the RF controller may further include K instruction cache modules, which may be, for example, first-in-first-out (FIFO) memories. Each of the K instruction cache modules corresponds one-to-one with the aforementioned K data transmission interfaces and is used to cache data transmission instructions for its corresponding interface. For example, instruction cache module 1 corresponds to data transmission interface 1, and instruction cache module 1 is used to cache data transmission instructions indicating data transmission through data transmission interface 1. The K instruction cache modules may be located within the first arbitrator; alternatively, they may be set independently, for example, the K instruction cache modules may be set as independent devices between the first arbitrator and the interface control module. This application does not limit the location of the instruction cache modules. Figure 4 The example is set up with the K instruction cache modules as independent devices.

[0065] When the first arbiter determines that the first data transfer instruction does not conflict with data transfer instructions output by other timing processors, it can input the first data transfer instruction into the instruction cache module corresponding to the data transfer interface indicated by the first data transfer instruction. For example, if the data transfer interface indicated by the first data transfer instruction is data transfer interface i, and the instruction cache module corresponding to data transfer interface i is instruction cache module i, then the first arbiter can input the first data transfer instruction into instruction cache module i.

[0066] When the first arbitrator determines that the first data transmission instruction conflicts with the second data transmission instruction, it can determine the execution order of the first and second data transmission instructions based on the priorities of the target timing processor and the first timing processor. Then, based on this execution order, it inputs the first and second data transmission instructions into a first instruction cache module. This first instruction cache module is the instruction cache module corresponding to the first data transmission interface, and the first data transmission interface is the data transmission interface indicated by the first and second data transmission instructions. Optionally, the priorities of the target timing processor and the first timing processor are the priorities between the timing processors corresponding to the first data transmission interface.

[0067] For example, if the priority of the target timing processor is higher than that of the first timing processor in the priority of the timing processor corresponding to the first data transmission interface, the first arbitrator can first input the first data transmission instruction into the first instruction cache module, and then input the second data transmission instruction into the first instruction cache module. In this way, since the first instruction cache module is a first-in-first-out memory, the first data transmission instruction can be executed first.

[0068] Optionally, the first arbitrator can also feed back the conflict information of the timing processors to the central processing unit (CPU), so that the CPU can monitor the conflict information during the operation of the timing processors in real time and take corresponding measures. For example, it can instruct the higher-priority timing processors to re-execute the task corresponding to the conflicting data transfer instruction, or modify the execution time of other instructions related to the conflicting data transfer instruction.

[0069] Optionally, the RF controller may further include a data memory connected to the n timing processors for storing intermediate data generated by the n timing processors during task execution and / or task data required by the n timing processors for task execution. The task data required by the n timing processors for task execution is, for example, generated by the aforementioned central processing unit (CPU) according to the requirements of the upper-layer software. For instance, the task data required by the target timing processor is data included in a data file generated by the CPU according to the requirements of the upper-layer software. The intermediate data generated by the n timing processors during task execution includes, for example, operands, condition lists, etc. In this way, the RF controller can act as a coprocessor to reduce the processing load on the CPU, helping to improve the autonomous control capability of the RF controller.

[0070] Optionally, when the multiple timing processors read and write data from the data memory, there may be conflicts, such as two timing processors reading or writing data from the data memory at the same time. Therefore, in this embodiment, the radio frequency controller may further include a second arbitrator, which is connected to the n timing processors and the data storage module, and is used to determine whether the data read and write instructions output by the n timing processors conflict.

[0071] For example, the second arbitrator can determine whether the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by other timing processors. If the target timing processor and the second timing processor output data read / write instructions simultaneously, it is considered that the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by the second timing processor; if there is no other timing processor among the other timing processors that outputs data read / write instructions simultaneously with the target timing processor, it is considered that the data read / write instructions output by the target timing processor do not conflict with the data read / write instructions output by other timing processors.

[0072] If the second arbitrator determines that the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by the second timing processor, the second arbitrator can further determine the execution order of the first and second data read / write instructions based on the priorities of the target processor and the second timing processor. For example, if the priority of the target timing processor is higher than that of the second timing processor, the second arbitrator determines to execute the first data read / write instruction first. This priority, for example, is configured during the baseband chip design and may differ from the aforementioned priorities.

[0073] When the target timing processor has finished executing all the instructions stored in its RAM, it can send an instruction message to the central processing unit to indicate that the task has ended, so that the central processing unit can report to the upper-level software and complete the first task.

[0074] In this embodiment, compared to a traditional RF controller, a timing exchange network is added between the timing processor and the frame timer, enabling flexible pairing of the frame timer and the timing processor without binding. Furthermore, a first arbitrator is added between the interface control module and the timing processor, resolving the problem of data transmission command conflicts from multiple timing processors. Additionally, a data memory is added to store complex task data (i.e., data required for task execution and data generated during task execution), enhancing the RF controller's autonomous control capability, reducing the processing pressure on the central processing unit, and a second arbitrator is added between the data memory and the timing processor, resolving the problem of data read / write command conflicts from multiple timing processors.

[0075] Based on the same inventive concept, embodiments of this application provide a data transmission method, which can be implemented by... Figure 1 , Figure 2 or Figure 4 The aforementioned electronic device is implemented. Please refer to [the documentation / reference]. Figure 5 This is a flowchart of a data transmission method provided in an embodiment of this application.

[0076] S501: When the first task starts, determine the target frame timer corresponding to the first task from at least one frame timer, and determine the target timing processor corresponding to the first task from at least one timing processor.

[0077] S502: When it is determined that the count value of the target frame timer is the same as the time parameter stored in the target timing processor, execute the first task.

[0078] Optionally, before performing the first task, the electronic device may also determine whether the data transmission instructions output by the target timing processor conflict with the data transmission instructions output by other timing processors, wherein the other timing processors are timing processors other than the target timing processor among the at least one (e.g., n) timing processors.

[0079] For example, an electronic device can determine whether the data transmission interface indicated by the data transmission instruction output by each of the n timing processors is the same. If the data transmission interface indicated by the first data transmission instruction output by the target timing processor is the same as that indicated by the second data transmission instruction output by any of the other timing processors (e.g., the first timing processor), then it is determined that the data transmission instruction output by the target timing processor conflicts with that of the first timing processor.

[0080] When an electronic device determines that a first data transmission instruction output by a target timing processor conflicts with a second data transmission instruction output by a first timing processor, it can also determine the execution order of the first data transmission instruction and the second data transmission instruction based on the priorities of the target timing processor and the first timing processor.

[0081] Optionally, the electronic device can also determine whether the data read / write instructions output by the target timing processor conflict with the data read / write instructions output by other timing processors. If the first data read / write instruction output by the target timing processor conflicts with the second data read / write instruction output by the second timing processor in other timing processors, the electronic device can determine the execution order of the first data read / write instruction and the second data read / write instruction according to the priority of the target timing processor and the second timing processor.

[0082] It should be noted that the technical features involved in the aforementioned embodiments of electronic devices can all be referenced to the implementation process corresponding to the data transmission method in the embodiments of this application, and will not be repeated here.

[0083] Based on the same inventive concept, embodiments of this application provide a communication device. Please refer to... Figure 6 As shown, the communication device includes at least one processor 601 and a memory 602 connected to the at least one processor. In this embodiment, the specific connection medium between the processor 601 and the memory 602 is not limited. Figure 6 Taking the connection between processor 601 and memory 602 via bus 600 as an example, bus 600 in... Figure 6 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. The 600 bus can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0084] In this embodiment of the application, the memory 602 stores instructions that can be executed by at least one processor 601. By executing the instructions stored in the memory 602, at least one processor 601 can perform the steps included in the aforementioned data transmission method.

[0085] The processor 601 serves as the control center of the communication device. It connects to various parts of the communication device via various interfaces and lines, and performs overall monitoring by running or executing instructions stored in the memory 602 and accessing data stored in the memory 602, thus controlling the various functions and processing data of the communication device. Optionally, the processor 601 may include one or more processing units. The processor 601 may integrate an application processor and a modem processor. The application processor primarily handles the operating system and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0086] Processor 601 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the data transmission method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0087] Memory 602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 602 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 602 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 602 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0088] By designing and programming the processor 601, the code corresponding to the data transmission method described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to execute the steps of the aforementioned data transmission method during operation. How to design and program the processor 601 is a technique known to those skilled in the art, and will not be elaborated here.

[0089] Based on the same inventive concept, embodiments of this application also provide a computationally readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the steps of the aforementioned data transmission method.

[0090] In some possible implementations, various aspects of the data transmission bit method provided in this application can also be implemented in the form of a program product, which includes program code that, when the program product is run on a communication device, causes the detection device to perform the steps in the data transmission method according to the various exemplary embodiments of this application described above.

[0091] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0092] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0093] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0094] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0095] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A radio frequency controller, characterized by The application is applied to an electronic device, the electronic device comprises a central processor and a radio frequency controller, the central processor is connected with the radio frequency controller, the radio frequency controller comprises a timing exchange network, at least one frame timer and at least one timing processor, the at least one frame timer and the at least one timing processor are connected with the timing exchange network, wherein, The central processor is used for determining a target frame timer corresponding to a first task from the at least one frame timer, determining a target timing processor corresponding to the first task from the at least one timing processor and configuring the association relationship of the target frame timer and the target timing processor when the first task is started, wherein each timing processor in the at least one timing processor is associated with different frame timers at different time points; The target frame timer is used for frame counting; The timing exchange network is used for associating the target frame timer with the target timing processor; The target timing processor is used for executing the first task when the count value of the target frame timer is the same as the time parameter stored in the target timing processor.

2. The radio frequency controller of claim 1, wherein, The radio frequency controller further comprises a first arbitrator connected with the at least one timing processor, which is used for determining whether the data transmission instruction output by the target timing processor conflicts with the data transmission instruction output by other timing processors, the other timing processors being the timing processors in the at least one timing processor except the target timing processor.

3. The radio frequency controller of claim 2, wherein, The first arbitrator is specifically used for: Determining the data transmission interface indicated by the data transmission instruction output by each timing processor in the at least one timing processor; If the first data transmission instruction output by the target timing processor is the same as the data transmission interface indicated by the second data transmission instruction output by the first timing processor in the other timing processors, it is determined that the data transmission instructions output by the target timing processor and the first timing processor conflict.

4. The radio frequency controller of claim 3, wherein, The radio frequency controller further comprises an interface control module connected with the first arbitrator, and the interface control module comprises at least one data transmission interface.

5. The radio frequency controller of claim 4, wherein, The radio frequency controller further comprises at least one instruction cache module corresponding to the at least one data transmission interface one by one.

6. The radio frequency controller of claim 5, wherein, The first arbitrator is further used for: When the first data transmission instruction output by the target timing processor conflicts with the second data transmission instruction output by the first timing processor in the other timing processors, determining the execution order of the first data transmission instruction and the second data transmission instruction according to the priority of the target timing processor and the first timing processor; Based on the execution order, inputting the first data transmission instruction and the second data transmission instruction into a first instruction cache module in the at least one instruction cache module, the first instruction cache module corresponding to a first data transmission interface, and the first data transmission interface being the data transmission interface indicated by the first data transmission instruction and the second data transmission instruction.

7. The radio frequency controller of any one of claims 1-6, wherein, The radio frequency controller further comprises a data storage connected with the at least one timing processor, for storing intermediate data generated by the at least one timing processor when performing a task, and / or task data required by the at least one timing processor to perform a task.

8. The radio frequency controller of claim 7, wherein, The radio frequency controller further comprises a second arbitrator connected with the at least one timing processor and the data storage, for determining whether a data read / write instruction output by a target timing processor conflicts with a data read / write instruction output by another timing processor, the another timing processor being a timing processor other than the target timing processor among the at least one timing processor.

9. The radio frequency controller of claim 8, wherein, The second arbitrator is further configured to: determine an execution order of the first data read / write instruction and the second data read / write instruction according to priorities of the target timing processor and the second timing processor when the first data read / write instruction output by the target timing processor conflicts with the second data read / write instruction output by the second timing processor among the another timing processor.

10. An electronic device, comprising: A central processing unit comprising the radio frequency controller according to any one of claims 1-9.

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