Laterally diffused metal oxide semiconductor device with reduced gate charge and time dependent dielectric breakdown

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device with reduced gate charge and time dependent dielectric breakdown. An LDMOS with reduced gate charge and time dependent dielectric breakdown is provided. An apparatus includes a substrate including a first well having a first doping and a second well region having a second doping; a source electrode formed in the first well; and a gate comprising an undoped block and a doped block. The undoped block is disposed at least partially on the source, the first well, and the second well. The doped block is disposed at least partially on the second well.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document and the patent disclosure as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for gate charge and time-dependent dielectric breakdown reduction in laterally diffused metal oxide semiconductor (LDMOS) fin-based field effect transistors. Background Art

[0004] LDMOS field effect transistors (FETs) have been widely adopted as a replacement for complementary metal oxide semiconductor (CMOS) technology for high voltage applications. The traditional figure of merit (FOM) for LDMOS performance is given as the gate charge (Qg) multiplied by the drain-source on-resistance (R DS(ON) ), or Qg*R DS(on) Conventional LDMOS structures exhibit relatively high Qg, and both split-gate and conventional gate architectures suffer from hot carrier injection (HCI) induced TDDB burnout.

[0005] Thus, methods, systems, and apparatus are provided for a LDMOS architecture with reduced Qg and TDDB. Summary of the invention

[0006] In one aspect, the present disclosure provides a device comprising: a substrate comprising a first well having a first doping and a second well region having a second doping; a source formed in the first well; and a gate comprising an undoped block and a doped block, the undoped block being at least partially disposed on the source, the first well and the second well, wherein the doped block is at least partially disposed on the second well.

[0007] In another aspect, the present disclosure provides a semiconductor device comprising: a source; a drain; and a gate disposed on a substrate, the gate comprising an undoped region and a doped region, the undoped region being at least partially disposed on the source, wherein the doped region is disposed between the drain and the source.

[0008] In another aspect, the present disclosure provides a device comprising: a substrate comprising a first well having a first doping and a second well region having a second doping; and a gate comprising an undoped block and a doped block, the undoped block being at least partially disposed on the first well and the second well, wherein the doped block is at least partially disposed on the second well. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1A is a schematic top view of an LDMOS FET with reduced Qg and TDDB according to various embodiments;

[0011] Figure 1B is a schematic top view of an alternative LDMOS FET with reduced Qg and TDDB according to various embodiments;

[0012] Figure 2A is a schematic diagram of a cross section of an LDMOS FET with reduced Qg and TDDB according to various embodiments;

[0013] Figure 2B is a schematic diagram of a cross-section of an alternative LDMOS FET with reduced Qg and TDDB according to various embodiments; and

[0014] Figure 3 is a schematic diagram of an LDMOS portion of a bipolar, CMOS, and LDMOS (BCDMOS) FET with reduced Qg and TDDB according to various embodiments. DETAILED DESCRIPTION

[0015] Various embodiments describe a LDMOS device with reduced Qg and TDDB.

[0016] In some embodiments, an apparatus for an LDMOS FET with reduced Qg and TDDB is provided. The apparatus includes: a substrate including a first well having a first doping and a second well region having a second doping; a source formed in the first well; and a gate including an undoped block and a doped block. The undoped block is at least partially disposed on the source, the first well, and the second well. The doped block is at least partially disposed on the second well.

[0017] In another embodiment, a semiconductor device having an LDMOS FET with reduced Qg and TDDB is provided. The semiconductor device includes a source, a drain, and a gate disposed on a substrate, the gate including an undoped region and a doped region. The undoped region is at least partially disposed on the source, and the doped region is disposed between the drain and the source.

[0018] In another embodiment, an apparatus for LDMOS with reduced Qg and TDDB is provided. The apparatus includes: a substrate including a first well with a first doping and a second well region with a second doping; and a gate including an undoped block and a doped block, the undoped block being at least partially disposed on the first well and the second well, wherein the doped block is at least partially disposed on the second well.

[0019] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reasons, it should not be considered that a single or multiple features of any described embodiment are essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0020] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0021] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0022] Similarly, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may be present.

[0023] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative position and / or direction between various parts of an object and / or component.

[0024] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0025] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically indicated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". In addition, the use of the terms "including" and "having" and other forms such as "includes", "included", "has", "have" and "had" should be considered non-exclusive. In addition, terms such as "element" or "component" cover elements and components that make up one unit and elements and components that make up more than one unit, unless otherwise specifically stated.

[0026] As used herein, the phrase "at least one of..." preceding a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; in contrast, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where the desired selection is "at least one of each of A, B, C," or alternatively "at least one of A, at least one of B, and at least one of C," it is so explicitly described.

[0027] The FOM of LDMOS has traditionally been given as Qg*R DS(ON) Conventional approaches to improve FOM exhibit high Qg. These may include drain extension, surface implant processes, and split gate architectures. These approaches exhibit high Qg. Furthermore, TDDB and burnout have occurred in these designs when under HCI stress.

[0028] In some embodiments, a proposed LDMOS architecture provides reduced Qg and TDDB, including a split-gate architecture. By providing an n gate that does not receive heavy doping (e.g., for heavy n-type doping) + , or for heavily p-doped p + ) and does not receive a corresponding lightly doped drain (LDD) implant (e.g., NLDD for n-type LDD, or PLDD for p-type LDD), the effective thickness of the gate oxide increases due to the polysilicon depletion effect. This in turn reduces Qg, and further reduces the vertical electric field (which reduces TDDB). As a result, gate leakage current is reduced.

[0029] Figure 1A 1 is a schematic top view of an LDMOS FET 100A (hereinafter “LDMOS 100A”) with reduced Qg and TDDB according to various embodiments. LDMOS 100A includes a gate 105 having an undoped block 110 and a doped block 115, a source region 120, a first well 125, a second well 130, a trench isolation region 135, and a drain region 140, and a substrate 145. It should be noted that Figure 1A Various features and components of the LDMOS 100A are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of the LDMOS 100A may be possible and in accordance with various embodiments.

[0030] In various embodiments, the structure of LDMOS 100A is disposed on a substrate 145. Thus, substrate 145 may be a semiconductor substrate, such as (but not limited to) bulk silicon. In some embodiments, substrate 145 includes a lightly doped (“p - " or "n - ”) region. For example, in the case of n-type LDMOS (NLDMOS), the substrate 145 may be lightly boron doped (eg, p - ) in which well regions (e.g., p-well and n-well) may be formed. Thus, a well refers to a doped region formed within substrate 145 that serves as the "body" or "main body" of LDMOS 100A, on which (or in which) other components of the device are formed, such as gate 105, source region 120, trench isolation region 135, and drain region 140.

[0031] In the above embodiments, and in the additional embodiments described below, boron and phosphorus are provided as non-limiting examples, and it should be understood that in other embodiments, other dopants may be utilized. For example, suitable dopants may include, but are not limited to, pentavalent atoms (e.g., arsenic, phosphorus, antimony, bismuth, lithium, etc.) for n-type doping and trivalent atoms (e.g., indium, aluminum, gallium, boron, etc.) for p-type doping.

[0032] In various embodiments, the source region 120, the first well 125, the second well 130, the trench isolation region 135, and the drain region 140 may be formed in the substrate 145. Figure 2A , 2B As discussed in more detail in FIG. 3 , the source region 120 , the first well 125 , the second well 130 , the trench isolation region 135 , and the drain region 140 may be formed by doping different regions of the substrate 145 .

[0033] In some embodiments, the substrate 145 may include one or more heavily doped (“p-type”) layers doped with an n-type dopant (eg, phosphorus) and a p-type dopant (eg, boron). + " or "n + ”) region. In some examples, n + or p + The regions may include source regions 120 and / or drain regions 140. Other doped regions of the substrate 145 include a first well 125 having a first doping and a second well 130 having a second doping different from the first doping. In some examples, the LDMOS 100A may be an NLDMOS. Thus, the first well 125 may have a p-type doping (e.g., a p-well), and the second well 130 may have an n-type doping (e.g., an n-well). Furthermore, in the NLDMOS, the source and drain regions 120, 140 are formed as n-type wells of the substrate 145. + Doped region.

[0034] In various examples, the gate 105 is disposed on the substrate 145, above at least a portion of the source region 120, the first well 125, the second well 130, and the trench isolation region 135. In various examples, the gate 105 can be formed via an epitaxial process in which the gate can be grown or otherwise deposited on the substrate 145. Thus, in some examples, the gate 105 can be a polysilicon (e.g., polycrystalline silicon) gate formed of a polysilicon material. In other examples, the gate 105 can be a partially or fully silicided polysilicon gate (as will be described below with respect to Figure 2A , 2B and 3 are described in more detail).

[0035] In various embodiments, gate 105 includes undoped block 110 and doped block 115. As used herein, the term "block" refers to a piece of gate material (e.g., polysilicon, metal oxide, or other gate dielectric material) that forms a structural gate and / or a region of gate 105. In some examples, doped block 115 of gate 105 may be doped via ion implantation. In some embodiments, doped block 115 may be doped with LDD and / or heavy doping (e.g., n + 、p +) implantation, thereby receiving both light doping and heavy doping. In some examples, the implantation is NLDD / n + implantation, whereby the doping block 115 receives light n-type doping and / or heavy n-type (n + ) doping. Therefore, as used herein, "implantation" refers to the doping process by ion implantation into the corresponding structure. Therefore, in some examples, the doping block 115 can receive NLDD and n + Both are doped to form a doped portion of the gate 105 .

[0036] In various embodiments, the gate 105 further includes an undoped block 110 that does not receive doping. For example, in some embodiments, n + And NLDD implant (or other implant) may not be applied to the undoped block 110 of gate 105, thereby forming an undoped portion of gate 105. As used herein, implant refers to a doping process into a structure such as doped block 115 of gate 105 via masking and ion implantation.

[0037] Thus, the gate 105 includes both the undoped portion 110 and the doped portion 115. Due to the polysilicon depletion effect, the undoped portion 110 of the gate 105 extends the effective thickness of the gate oxide. Qg is then reduced, and the vertical electric field is also reduced (which in turn mitigates TDDB). Therefore, the gate leakage current is also reduced.

[0038] In various embodiments, the source region 120 may be formed within the substrate 145 and disposed at least partially below the undoped block 110 and at least partially to the left of the undoped block 110. The first well 125 is disposed directly adjacent to the source region 120 to the right of the source region 120 and below the undoped block 110. The second well 130 is disposed directly adjacent to the first well 125 to the right of the first well 125. The second well 130 is further disposed at least partially below the undoped block 110 and the doped block 115 of the gate 105. In some examples, the second well 130 may be disposed below the doped block 115 but not below the undoped block 110. In other words, the doped block 115 may be disposed on the second well 125 up to the boundary between the first well 125 and the second well 130. The undoped block 110 may then be disposed at least partially on the first well 125 but not on the second well 130. In some examples, the trench isolation region 135 may be disposed directly adjacent to the second well 130 and on the right side of the second well 130. The trench isolation region 135 may be disposed at least partially under a doped region of the gate (e.g., doped block 115). The drain region 140 may be disposed directly adjacent to the trench isolation region 135 and on the right side of the trench isolation region 135.

[0039] Therefore, in some embodiments, the source region 120 may be heavily doped (eg, heavily n-doped (n +) or p-type heavily doped (p + )) region, disposed on a first side of the undoped block 110 of the gate 105, and at least partially disposed below the undoped region of the gate (e.g., the undoped block 110). In some examples, the source region 120 may be interchangeably referred to as the "source" or "source / drain" of the LDMOS 100A. In some further embodiments, the source region 120 may be formed as a raised source / drain (RSD) structure. In some further embodiments, the source region 120 may be part of a fin (e.g., as in a FinFET device).

[0040] Similarly, the drain region 140 may be heavily doped (eg, n + or p + ) region, disposed on a second side of the gate 105 opposite to the first side (e.g., the right side of the doped block 115). In some examples, the drain region 140 may be interchangeably referred to as the "drain" or "drain / source" of the LDMOS 100A. In some further embodiments, the drain region 140 may be formed as a raised source / drain (RSD) structure like the source region 120. In some further embodiments, the source region may be part of a fin (e.g., as in a FinFET device). The fin may be heavily doped and formed as part of the drain (also referred to as the "drain / source").

[0041] In various examples, the substrate 145 further includes trench isolation regions, such as trench isolation regions 135. The trench isolation regions may be trenches formed in the substrate and filled with an oxide material. In some examples, the trench isolation regions 135 may be shallow trench isolation (STI) regions. In other examples, the trench isolation regions 135 may be deep trench isolation (DTI) regions. The trench isolation regions are filled trench regions that are configured to mitigate leakage currents between different components, in this example, electric fields and / or leakage currents between source and drain regions 120, 140. It is known that STI structures can enhance HCI-induced TDDB. Therefore, in various embodiments, the undoped block 110 of the gate 105 and the corresponding increase in the effective thickness of the gate 105 reduce the effect of HCI-induced TDDB.

[0042] Figure 1B 1 is a schematic top view of an alternative configuration of an LDMOS FET 100B (hereinafter “LDMOS 100B”) with reduced Qg and TDDB according to various embodiments. LDMOS 100B includes a gate 105 having an undoped block 110 and a doped block 115, a source region 120, a first well 125, a second well 130, a trench isolation region 135, and a drain region 140, and a substrate 145. It should be noted that Figure 1BVarious features and components of the LDMOS 100B are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of the LDMOS 100B may be possible and according to various embodiments.

[0043] and Figure 1A Compared to the LDMOS 100A of FIG. 1 , the gate 105 of the LDMOS 100B is a split gate architecture, in which the structure of the gate is "split" into two separate gate structures (e.g., gate structures that are spaced apart and not in direct contact on the surface of the substrate 145), rather than a single gate FET as shown in the LDMOS 100A. In the depicted embodiment, the undoped block 110 is separated (e.g., separated) from the doped block 115, forming a split gate. Therefore, in some embodiments, there is a gap between the undoped block 110 and the doped block 115, separating the undoped and doped blocks 110, 115 above the second well 130. Specifically, the undoped block 110 is at least partially disposed above the source region 120, the first well 125, and at least partially above the second well 130.

[0044] Figure 2A 1 is a schematic diagram of a cross section of LDMOS 100A, 200A taken across line 11 according to various embodiments. The cross-sectional view of LDMOS 200A shows different parts and structures described above but blocked in the top view. Thus, LDMOS 200A includes a substrate 205 having an undoped / lightly doped region 210, a first well 215, a second well 220, a first trench isolation region 225, a second trench isolation region 230, a third trench isolation region 235, a gate 240 having an undoped block 245 and a doped block 250, a cap 265, a source region 255, and a drain region 260. It should be noted that Figure 2A Various features and components of the LDMOS 200A are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of the LDMOS 200A may be possible and in accordance with various embodiments.

[0045] As shown in the cross-sectional view, the substrate 205 may include an undoped / lightly doped region 210 on which the first and second wells 215, 220 are formed. In various examples, the undoped / lightly doped region 210 of the substrate 205 may be lightly doped instead. For example, in NLDMOS, the undoped / lightly doped region 205 is lightly boron doped (e.g., p-type). In various examples, the substrate 205 further includes a first well 215 and a second well 220. In various examples, the first and second wells 215, 220 may be heavily doped regions of the substrate 205. For example, in NLDMOS, the first well 215 may be a p-type doped (e.g., boron doped) "p-well", and the second well 220 may be an n-type doped (e.g., phosphorus doped) "n-well". In various examples, the substrate 205 further includes trench isolation regions, such as first to third trench isolation regions 225 to 235. The trench isolation region may be a trench formed in the substrate and filled with an oxide material. In some examples, one or more of the first, second, and third trench isolation regions 225 to 235 may be a shallow trench isolation (STI) region. In some examples, one or more of the first, second, and third trench isolation regions 225 to 235 may be a deep trench isolation (DTI) region.

[0046] As previously mentioned Figure 1A As described, gate 240 may include undoped block 245 and doped block 250. In some embodiments, LDMOS 200A may be an NLDMOS, and NLDD and / or n + Implantation may be applied to doped block 250, giving it one or more of a light n-type doping and a heavy n-type doping. In other embodiments such as PLDMOS, PLDD and / or p + Implantation may be applied to doping block 250. Thus, doping block 250 may be a doping block that applies NLDD / PLDD and / or n + / p + The undoped and doped blocks 245, 250 may be regions of the gate 240 to which the implantation is applied, and the undoped blocks 245 may be regions to which the implantation is not applied. As previously described, the undoped and doped blocks 245, 250 may be portions of the structure of the gate 240 and are formed as blocks of dielectric material (or portions of dielectric material forming the gate 240). In some examples, the undoped and doped blocks 245, 250 may be blocks (or regions of blocks) of polysilicon forming the gate 240.

[0047] Thus, in various examples, the gate 240 may further include a cap 265. The cap 265 may extend over the entire gate 240, or partially extend over the gate 240. In some examples, the partial cap 265 may cover at least a portion of the undoped block 245 and the doped block 250. In some examples, the cap 265 may be a salicide (e.g., salicide) and / or polysilicide cap 265 grown and / or deposited on the gate 240.

[0048] Figure 2B is a schematic diagram of a cross section of LDMOS 100B, 200B taken across line xx according to various embodiments. Figure 1B As described, compared to LDMOS 200A, in the depicted example, the gate 240 is a split gate, wherein the undoped block 245 is separated (e.g., separated) from the doped block 250 to form a split gate. Therefore, in some embodiments, there is a gap between the undoped block 245 and the doped block 250, and the gap is formed above the second well 220. Specifically, the undoped block 245 is at least partially disposed above the source region 255, the first well 215, and at least partially located above the second well 220.

[0049] Figure 3 3 is a schematic diagram of a cross-section of an LDMOS portion of a BCDMOS FET 300 (hereinafter “BCDMOS 300”) according to various embodiments. The BCDMOS 300 includes a substrate 305 having an undoped / lightly doped region 310, a set of first wells 315a, 315b, a second well 320, a set of first trench isolation regions 325a, 325b, a set of second trench isolation regions 330a, 330b, a first gate 340a having a first undoped block 345a and a first doped block 350a, first and second caps 365a, 365b, a second gate 340b having a first undoped block 345a and a first doped block 350a, a first source region 355a, a second source region 355b, and a drain region 360. It should be noted that Figure 3 Various components and elements of the BCDMOS 300 are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of the BCDMOS 300 may be possible and in accordance with various embodiments.

[0050] Like LDMOS 200A, BCDMOS 300 may have a continuous single gate (rather than a separate gate). However, compared to LDMOS 200A, BCDMOS 300 includes two gates (a first gate 340a and a second gate 340b). Each gate 340a, 340b includes a corresponding undoped block 345a, 345b and a doped block 350a, 350b. BCDMOS 300 may include two connected LDMOS devices sharing a drain region 360, wherein the LDMOS devices are flipped in orientation. For example, the first LDMOS may have a source-gate-drain configuration (e.g., from left to right, a first source region 355a, a first gate 340a, followed by a drain region 360). The second LDMOS may have a drain-gate-source configuration (e.g., from left to right, a drain region 360, a second gate 340b, followed by a second source region 355b). Furthermore, the BCDMOS 300 may include a second well 320 that may include two second trench isolation regions 330 a , 330 b disposed on either side of the drain region 360 , separating the drain region 360 from respective source regions 355 a , 355 b .

[0051] In various examples, the gates 340a, 340b may further include respective caps 365a, 365b. The first and second caps 365a, 365b may cover the entire respective gates 340a, 340b, or partially cover the respective gates 340a, 340b (e.g., partially extend over them). In some examples, the partial caps 365a, 365b may cover at least a portion of the respective undoped blocks 345a, 345b and the respective doped blocks 350a, 350b. In some examples, the caps 365a, 365b may be salicide (e.g., salicide) and / or polysilicon silicide grown and / or deposited on the respective gates 340a, 340b.

[0052] As depicted, the second gate 340b includes a second undoped block 345b and a doped block 350b. The second gate 340b may be in a configuration flipped from the first gate 340a, with the second doped block 350b disposed on the left side, over the second well 320 and the second trench isolation region 330b, and the doped block 345b disposed on the right side, over the second well 320, the first well 315b, and the second source region 355b.

[0053] It should be understood that in other embodiments, other gate configurations may be utilized. For example, in some embodiments, one or more of the gates 340a, 340b may be split gates, where the undoped blocks 345a, 345b and the doped blocks 350a, 350b are separated, as previously described with respect to Figure 1B and 2BAs previously described, in various embodiments, the gates 340a, 340b may be formed of polysilicon. In each of these configurations, the undoped blocks 345a, 345b of the respective gates 340a, 340b increase the effective thickness of the respective gates 340a, 340b, reducing Qg and HCI-induced TDDB.

[0054] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may instead be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, according to several embodiments, this functionality may be distributed throughout various other system components.

[0055] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context indicates otherwise. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized into alternative structural architectures and / or incorporated into other described systems. Therefore, although those embodiments are described with or without some features for ease of description and in order to illustrate aspects of various embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context indicates otherwise. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a substrate including a first well region having a first doping and a second well region having a second doping; a source electrode formed in the first well; and The gate includes an undoped block and a doped block, wherein the undoped block is at least partially disposed on the source, the first well, and the second well, wherein the doped block is at least partially disposed on the second well.

2. The apparatus of claim 1, wherein the gate is a split gate, wherein the doped and undoped blocks are separated. The device of claim 1 , wherein the gate is formed of polysilicon. The apparatus of claim 1 , wherein the first doping is p-type doping and the second doping is n-type doping. 5 . The apparatus of claim 1 , wherein the source is a heavily n-doped region in the first well.

6. The apparatus of claim 1, wherein the doping block applies at least one of a lightly doped implant or a heavily doped implant.

7. The apparatus of claim 6, wherein the doped block uses an n-type lightly doped drain implant and an n-type heavily doped implant.

8. The apparatus of claim 6, wherein the implantation comprises light and heavy doping of the same type as the second doping.

9. The apparatus of claim 1, wherein the substrate includes a shallow trench isolation region formed in the second well, wherein the shallow trench isolation region is disposed between a drain formed in the second well and the source, wherein the doped block is at least partially disposed on the shallow trench isolation region.

10. A semiconductor device comprising: source; Drain; and The gate is disposed on the substrate, and includes an undoped region and a doped region, wherein the undoped region is at least partially disposed on the source, and wherein the doped region is disposed between the drain and the source.

11. The semiconductor device of claim 10, wherein the gate is a split gate, wherein the doped and undoped regions are separate respective blocks of dielectric material. 12 . The semiconductor device according to claim 10 , wherein the gate is formed of polysilicon. 13 . The semiconductor device according to claim 10 , wherein the doping block is implanted with at least one of a lightly doped implant or a heavily doped implant.

14. The semiconductor device of claim 13, wherein the doped block is implanted with an n-type lightly doped drain implant and an n-type heavily doped implant.

15. The semiconductor device of claim 10, wherein the substrate includes a shallow trench isolation region disposed between the drain and source, wherein the doped block is at least partially disposed on the shallow trench isolation region.

16. An apparatus comprising: a substrate including a first well region having a first doping and a second well region having a second doping; and A gate includes an undoped block and a doped block, wherein the undoped block is at least partially disposed on the first well and the second well, wherein the doped block is at least partially disposed on the second well.

17. The apparatus of claim 16, wherein the gate is a split gate, wherein the doped and undoped blocks are separate blocks of dielectric material.

18. The apparatus of claim 16, wherein the gate is formed of polysilicon.

19. The apparatus of claim 16, wherein the first doping is p-type doping and the second doping is n-type doping.

20. The apparatus of claim 19, wherein the doped blocks apply at least one of an n-type lightly doped drain implant and an n-type heavily doped implant.

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