Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. The thin film transistor includes: an active layer on a base substrate; a sub-conductive material layer on the active layer; a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; and a conductive material layer on the active layer. The active layer includes: a channel portion partially overlapping the gate electrode; a first connection portion connected to one side of the channel portion; and a second connection portion connected to the other side of the channel portion. The sub conductive material layer comprises a source electrode conductive material layer located on the first connecting part; and a drain conductive material layer on the second connection portion. A conductive material layer is disposed on the channel portion and on the same layer as the sub-conductive material layer.

Description

Technical Field

[0001] The present invention relates to a transistor and a display device including the transistor. Background Art

[0002] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on glass substrates or plastic substrates, they are widely used as switching devices for organic light emitting devices or display devices such as liquid crystal display devices.

[0003] Based on the material constituting the active layer, the thin film transistor can be divided into an amorphous silicon thin film transistor using amorphous silicon as the active layer, a polycrystalline silicon thin film transistor using polycrystalline silicon as the active layer, and an oxide semiconductor thin film transistor using an oxide semiconductor as the active layer.

[0004] Amorphous silicon thin film transistors (a-Si TFTs) have the advantages of short manufacturing process time and low production cost because amorphous silicon can be deposited in a short time to form an active layer, but have the disadvantages of being limited to use in active matrix organic light emitting devices (AMOLEDs) due to low mobility, poor current driving capability and threshold voltage variation.

[0005] Polycrystalline silicon thin film transistors (poly-Si TFTs) are made by crystallizing amorphous silicon after depositing it. Since a process of crystallizing amorphous silicon is required in the manufacturing process of polycrystalline silicon thin film transistors, the manufacturing cost increases as the number of processes increases, and since the crystallization process is performed at a high process temperature, it is difficult to apply polycrystalline silicon thin film transistors to large-area devices. In addition, due to its polycrystalline characteristics, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0006] In an oxide semiconductor thin film transistor (TFT), since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, it is easy to obtain the desired physical properties. In addition, due to the properties of the oxide, since the oxide semiconductor is transparent, it is also conducive to the realization of a transparent display.

[0007] In an oxide semiconductor thin film transistor (oxide semiconductor TFT), if a high mobility material is used in an active layer to improve the current characteristics of the transistor, the reliability of the transistor may be problematic, and when a short channel is implemented, the threshold voltage Vth of the transistor shifts to negative (-). Therefore, research is being conducted to improve the current characteristics without having problems with the reliability of the transistor and the negative (-) shift of the threshold voltage Vth. Summary of the invention

[0008] One embodiment of the present invention is to provide a thin film transistor having improved current characteristics by including a conductive material layer disposed on a channel portion.

[0009] One embodiment of the present invention is to provide a thin film transistor having improved current characteristics without excessively shifting a threshold voltage Vth in a negative (-) direction by including a conductive material layer disposed on a channel portion.

[0010] One embodiment of the present invention is to provide a thin film transistor including a conductive material layer provided on a channel portion and maintaining current characteristics even when the width of the channel portion is small.

[0011] Another embodiment of the present invention is to provide a display device including such a thin film transistor.

[0012] In addition to the objects of the present disclosure as described above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0013] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing the following thin film transistor: the thin film transistor includes: an active layer, the active layer is located on a base substrate; a sub-conductive material layer, the sub-conductive material layer is located on the active layer; a gate electrode, the gate electrode is spaced apart from the active layer and at least partially overlaps with the active layer; and a conductive material layer, the conductive material layer is located on the active layer. The active layer includes: a channel portion, the channel portion partially overlaps with the gate electrode; a first connecting portion, the first connecting portion is connected to one side of the channel portion; and a second connecting portion, the second connecting portion is connected to the other side of the channel portion; the sub-conductive material layer includes: a source conductive material layer, the source is located on the first connecting portion; and a drain conductive material layer, the drain conductive material layer is located on the second connecting portion; the conductive material layer is disposed on the channel portion and on the same layer as the sub-conductive material layer.

[0014] In a plan view, an area of ​​the conductive material layer in the channel portion may be 5% to 40% based on a total area of ​​the channel portion.

[0015] Each of the source conductive material layer and the drain conductive material layer may overlap portions of the first connection portion and the second connection portion.

[0016] Each of the source conductive material layer and the drain conductive material layer may be disposed on the entire surface of the first connection portion and the second connection portion.

[0017] The conductive material layer may include a first conductive material layer and a second conductive material layer disposed at a distance from each other.

[0018] The first conductive material layer may be disposed closer to the first connection portion than the second conductive material layer.

[0019] In a plan view, the first conductive material layer and the second conductive material layer may be disposed on any shortest line connecting the first connection portion and the second connection portion.

[0020] In a plan view, the first conductive material layer and the second conductive material layer may not be disposed on any shortest line connecting the first connection portion and the second connection portion.

[0021] The first conductive material layer may include a first sub-conductive material layer and a second sub-conductive material layer disposed at an interval from each other, and the second conductive material layer may include a first sub-conductive material layer and a second sub-conductive material layer disposed at an interval from each other.

[0022] The conductive material layer may include a third conductive material layer disposed at the same distance from each of the first connection portion and the second connection portion in a plan view.

[0023] When the channel length direction of the active layer is a first direction and the width direction of the active layer is a second direction, the conductive material layer may include a fourth conductive material layer having a length in the second direction greater than a length in the first direction.

[0024] Based on the second direction, both ends of the fourth conductive material layer may contact both ends of the channel portion.

[0025] When the channel length direction of the active layer is a first direction and the width direction of the active layer is a second direction, the conductive material layer may include a fifth conductive material layer having a length in the first direction greater than a length in the second direction.

[0026] Based on the first direction, the fifth conductive material layer may be disposed in the channel portion.

[0027] Each distance between the fifth conductive material layer and the first and second connection portions may be 1 μm or more based on the first direction.

[0028] A region of the channel portion overlapping the conductive material layer may have a higher carrier concentration than a region not overlapping the conductive material layer.

[0029] The sub-conductive material layer may include at least one selected from metal and transparent conductive oxide (TCO).

[0030] The conductive material layer may be formed of the same material as the sub-conductive material layer.

[0031] The active layer may include at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO).

[0032] Another configuration of the present invention provides a display device including a thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a plan view of a thin film transistor according to one embodiment of the present invention.

[0035] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0036] Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0037] Figure 4 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0038] Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0039] Figure 6 It is along Figure 4 A cross-sectional view taken along line II-II'.

[0040] Figure 7 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.

[0041] Figure 8is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.

[0042] Fig. 9 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0043] Fig.10 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0044] Fig.11 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0045] Fig.12 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0046] Fig.13 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0047] Fig.14 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0048] Fig.15 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0049] Fig.16 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0050] Fig.17 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0051] Fig.18 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0052] Fig.19A and Fig.19B is a plan view of thin film transistors according to comparative examples and examples.

[0053] Fig. 20 It shows that according to Fig.19A and Fig.19B A graph showing the current characteristics of a thin film transistor.

[0054] Fig.21 is a graph illustrating a change in threshold voltage (Vth) according to a change in the area of ​​a conductive material layer.

[0055] Fig. 22 is a schematic diagram of a display device according to an embodiment of the present invention.

[0056] Fig.23 is a schematic diagram of a shift register.

[0057] Fig.24 yes Fig. 22 Circuit diagram of any pixel.

[0058] Fig.25 yes Fig.24 A floor plan of pixels.

[0059] Fig.26 It is along Fig.25 A cross-sectional view taken along line III-III'.

[0060] Fig. 27 is a circuit diagram of any pixel of a display device according to another embodiment of the present invention.

[0061] Fig.28 is a circuit diagram of any pixel of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0062] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0063] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the illustrated details. Throughout the specification, the same reference numerals represent the same elements. In the following description, when it is determined that the detailed description of the related known functions or configurations unnecessarily obscures the important points of the present disclosure, the detailed description will be omitted.

[0064] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless referred to otherwise.

[0065] When configuring an element, the element is interpreted as including an error band even if not explicitly described.

[0066] When describing a positional relationship, for example, when the positional relationship is described as "on," "above," "below," and "beside," one or more parts may be disposed between two other parts, unless "only" or "directly" is used.

[0067] Spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to easily describe the relationship of one element or elements to another element or elements, as shown in the accompanying drawings. It will be understood that these terms are intended to cover different orientations of the device in addition to the orientations depicted in the accompanying drawings. For example, if the device shown in the figure is reversed, a device described as being arranged "below" or "below" another device may be arranged "above" the other device. Thus, the exemplary term "below or below" may include both "below or below" and "above" orientations. Similarly, the exemplary term "above" or "on" may include both "above" and "below or below" orientations.

[0068] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0069] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0070] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each element of the first element, the second element, and the third element.

[0071] The features of the various embodiments of the present disclosure may be partially or entirely connected to each other or combined with each other, and may interoperate and drive each other differently as those skilled in the art can fully understand. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0072] When adding reference numerals to components of each of the drawings describing embodiments of the present disclosure, the same components may have the same numerals as those displayed on other drawings.

[0073] In the embodiments of the present disclosure, for ease of description, a source electrode and a drain electrode are distinguished, and the source electrode and the drain electrode can be interchanged. A source electrode can be a drain electrode, and vice versa. In addition, in another embodiment, a source electrode of any embodiment can be a drain electrode, and in another embodiment, a drain electrode of any embodiment can be a source electrode.

[0074] In some embodiments of the present disclosure, for ease of description, the source region is separated from the source electrode, and the drain region is separated from the drain electrode, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0075] Figure 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view taken along line II'. Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0076] Reference Figure 1 , Figure 2 and Figure 3 , a thin film transistor 100 according to one embodiment of the present invention may include an active layer 130 , a gate electrode 150 , sub-conductive material layers 165 and 175 , and a conductive material layer 135 .

[0077] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , may include a gate electrode 150 spaced apart from and partially overlapping the active layer 130 , sub-conductive material layers 165 and 175 located on the active layer 130 , and a conductive material layer 135 located on the active layer 130 .

[0078] According to one embodiment of the present invention, the thin film transistor 100 may further include a base substrate 110. Figure 2 and Figure 3 , the active layer 130 is disposed on the base substrate 110 .

[0079] The thin film transistor 100 according to an embodiment of the present invention may further include a buffer layer 120. Figure 2 and Figure 3 , the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0080] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Figure 2 and Figure 3 , the gate insulating layer 140 is disposed on the active layer 130 . Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150 .

[0081] According to an embodiment of the present invention, the thin film transistor 100 may further include an interlayer insulating layer 180. Figure 2 and Figure 3 , the interlayer insulating layer 180 is disposed on the gate electrode 150. Specifically, the gate electrode 150 is disposed between the gate insulating layer 140 and the interlayer insulating layer 180.

[0082] According to an embodiment of the present invention, the thin film transistor 100 may further include a source electrode 160 and a drain electrode 170. Figure 1 , Figure 2 and Figure 3 , the source electrode 160 and the drain electrode 170 are disposed on the interlayer insulating layer 180 .

[0083] Hereinafter, components of the thin film transistor 100 according to one embodiment of the present invention will be described in more detail.

[0084] Glass or plastic may be used as the base substrate 110. As the plastic, transparent plastic (eg, polyimide) having a flexible property may be used.

[0085] When polyimide is used as the base substrate 110, heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high-temperature deposition process on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition, etching, etc. may be performed in a state where a polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

[0086] Reference Figure 2 and Figure 3 , the buffer layer 120 may be disposed on the base substrate 110 .

[0087] The buffer layer 120 may be formed on the base substrate 110 and may be formed of an inorganic material or an organic material, and may include, for example, an insulating oxide such as silicon oxide (SiOx), aluminum oxide (Al2O3), or the like.

[0088] The buffer layer 120 blocks impurities such as moisture and oxygen flowing out of the base substrate 110 to protect the active layer 130 , planarizes an upper portion of the base substrate 110 , and may be formed as a single layer or a plurality of layers.

[0089] Reference Figure 2 and Figure 3 , the active layer 130 may be disposed on the buffer layer 120 .

[0090] The active layer 130 may include a channel portion 130 n , a first connection portion 130 a , and a second connection portion 130 b .

[0091] Specifically, the active layer 130 may include a channel portion 130n partially overlapping with the gate electrode 150 in a plan view, a first connection portion 130a connected to one side of the channel portion 130n without overlapping with the gate electrode 150 in a plan view, and a second connection portion 130b connected to the other side of the channel portion 130n without overlapping with the gate electrode 150 in a plan view.

[0092] According to one embodiment of the present invention, the first connection portion 130 a and the second connection portion 130 b are spaced apart from each other with the channel portion 130 n interposed therebetween.

[0093] According to one configuration of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0094] The oxide semiconductor material may include at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO). However, the embodiments of the present invention are not limited thereto, and the active layer 130 may be made of another oxide semiconductor material known in the art.

[0095] The first and second connection portions 130a and 130b may be formed by selective conduction with respect to the active layer 130 made of a semiconductor material. According to one embodiment of the present invention, imparting conductivity to a specific portion of the active layer 130 so that it can function as a conductor is referred to as selective conduction.

[0096] For example, the active layer 130 may be selectively conductive by ion doping. Thus, the first connection portion 130a and the second connection portion 130b may be formed. However, the embodiments of the present invention are not limited thereto, and the active layer 130 may be selectively conductive by other methods known in the art.

[0097] The first connection portion 130a and the second connection portion 130b do not overlap the gate electrode 150. The first connection portion 130a and the second connection portion 130b have excellent conductivity and high mobility compared to the channel portion 130n. Therefore, the first connection portion 130a and the second connection portion 130b can be used as wirings, respectively.

[0098] According to one embodiment of the present invention, the thin film transistor 100 may include sub-conductive material layers 165 and 175 on the active layer 130 .

[0099] Specifically, refer to Figure 1 , Figure 2 and Figure 3 The sub-conductive material layers 165 and 175 may include a source conductive material layer 165 located on the first connection portion 130 a and a drain conductive material layer 175 located on the second connection portion 130 b .

[0100] More specifically, the source conductive material layer 165 and the drain conductive material layer 175 are disposed to be spaced apart from each other with a portion of the channel portion 130 n interposed therebetween.

[0101] Reference Figure 1 , Figure 2 and Figure 3 , the first connection portion 130 a and the second connection portion 130 b may be disposed between the base substrate 110 and the source and drain conductive material layers 165 and 175 , respectively.

[0102] More specifically, the source conductive material layer 165 and the drain conductive material layer 175 may contact the active layer 130 through the first connection portion 130 a and the second connection portion 130 b , respectively.

[0103] According to one embodiment of the present invention, the source conductive material layer 165 is disposed on the first connection portion 130a, and the drain conductive material layer 175 is disposed on the second connection portion 130b. However, the embodiments of the present invention are not limited thereto, and the positions of the source conductive material layer 165 and the drain conductive material layer 175 may be interchanged with each other.

[0104] According to one embodiment of the present invention, each of the source conductive material layer 165 and the drain conductive material layer 175 may overlap a portion of the first connection portion 130a and the second connection portion 130b. Figure 1 , Figure 2 and Figure 3 , a configuration is illustrated in which the source conductive material layer 165 overlaps a portion of the first connection portion 130a and the drain conductive material layer 175 overlaps a portion of the second connection portion 130b.

[0105] However, the embodiments of the present invention are not limited thereto, and each of the source conductive material layer 165 and the drain conductive material layer 175 may be disposed on the entire surface of the first connection portion 130 a and the second connection portion 130 b . Figure 4 , Figure 5 and Figure 6The configuration in which the source conductive material layer 165 is disposed on the entire surface of the first connection portion 130a and the drain conductive material layer 175 is disposed on the entire surface of the second connection portion 130b is illustrated. In addition, although not shown in the figure, a portion of the sub-conductive material layers 165 and 175 may overlap with the gate electrode 150.

[0106] According to one embodiment of the present invention, the sub-conductive material layers 165 and 175 may include at least one selected from metal and transparent conductive oxide (TCO).

[0107] Specifically, the metal may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca) and barium (Ba). The embodiments of the present invention are not limited thereto, and the sub-conductive material layers 165 and 175 may include a metal having a conductive property.

[0108] According to one embodiment of the present invention, the transparent conductive oxide (TCO) may include ITO (InSnO), IZO (InZnO), IO (InO), TO (SnO) and ZO (ZnO). However, the present invention is not limited thereto, and the sub-conductive material layers 165 and 175 may include an oxide having conductivity.

[0109] The sub-conductive material layers 165 and 175 may have reducing properties. The active layer 130 may be selectively conductive by the sub-conductive material layers 165 and 175. According to one embodiment of the present invention, the first connection portion 130a and the second connection portion 130b are in contact with the source conductive material layer 165 and the drain conductive material layer 175, respectively. The regions of the active layer 130 contacting the source conductive material layer 165 and the drain conductive material layer 175 are conductive to form the first connection portion 130a and the second connection portion 130b, respectively.

[0110] Specifically, according to one embodiment of the present invention, portions of the active layer 130 contacting the sub-conductive material layers 165 and 175 may be reduced to form the first connection portion 130 a and the second connection portion 130 b , respectively.

[0111] For example, when the active layer 130 is reduced in contact with and overlaps the sub-conductive material layers 165 and 175, oxygen vacancies occur in the active layer 130, and accordingly, the active layer 130 can be selectively conductive. By selectively reducing the active layer 130, the first connection part 130a and the second connection part 130b can be formed.

[0112] According to one embodiment of the present invention, the thin film transistor 100 may further include a conductive material layer 135 located on the active layer 130 .

[0113] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , the conductive material layer 135 may be disposed on the channel portion 130 n of the active layer 130. More specifically, the conductive material layer 135 is not disposed on the first connection portion 130 a and the second connection portion 130 b of the active layer 130.

[0114] Reference Figure 1 , Figure 2 and Figure 3 , the conductive material layer 135 may be disposed on the same layer as the sub-conductive material layers 165 and 175. The conductive material layer 135 and the sub-conductive material layers 165 and 175 are disposed between the active layer 130 and the gate insulating layer 140.

[0115] According to one embodiment of the present invention, the conductive material layer 135 may have one or more patterns. Specifically, the conductive material layer 135 may have multiple patterns or a single pattern. Figure 1 , Figure 2 and Figure 3 , the configuration in which the conductive material layer 135 is a plurality of patterns is illustrated.

[0116] According to one embodiment of the present invention, when viewed in a plan view, the area of ​​the conductive material layer 135 in the channel portion 130n may be 5% to 40% relative to the entire area of ​​the channel portion 130n. Therefore, the threshold voltage Vth of the thin film transistor according to the present invention is not excessively shifted in the negative (-) direction, and can have excellent on-current characteristics.

[0117] On the other hand, when the area of ​​the conductive material layer 135 in the channel portion 130n is less than 5% relative to the entire area of ​​the channel portion 130n in a plan view, the conductive material layer 135 may be provided in the channel portion 130n in an excessively small amount. Therefore, the on-current characteristics of the thin film transistor according to the present invention may not be effectively improved.

[0118] In addition, when the area of ​​the conductive material layer 135 in the channel portion 130n exceeds 40% relative to the entire area of ​​the channel portion 130n in a plan view, the conductive material layer 135 may be excessively disposed in the channel portion 130n. Therefore, the threshold voltage Vth of the thin film transistor may be excessively shifted in the negative (-) direction.

[0119] In order to improve the on-current characteristics while the threshold voltage Vth of the thin film transistor according to the present invention does not excessively shift in the negative (-) direction, the area of ​​the conductive material layer 135 in the channel portion 130n needs to be adjusted to 5% to 40% based on the entire area of ​​the channel portion 130n. Preferably, the area of ​​the conductive material layer 135 in the channel portion 130n can be adjusted to 10% to 35% based on the entire area of ​​the channel portion 130n, more preferably 15% to 30%.

[0120] Fig.21 is a graph illustrating a change in threshold voltage (Vth) according to a change in the area of ​​a conductive material layer.

[0121] exist Fig.21 In the graph of , the horizontal axis represents the ratio of the area of ​​the conductive material layer 135 to the entire area of ​​the channel portion 130n, and the vertical axis represents the threshold voltage (Vth) of the thin film transistor. Fig. 22 As shown in the graph of , when the threshold voltage (Vth) moves in the negative (-) direction, the threshold voltage (Vth) shifts in the negative (-) direction.

[0122] Reference Fig.21 , it can be seen that as the ratio of the area of ​​the conductive material layer 135 relative to the entire area of ​​the channel portion 130n increases, the threshold voltage Vth gradually shifts in the negative (-) direction.

[0123] Reference Fig.21 , when the area of ​​the conductive material layer 135 is 5% to 40% based on the total area of ​​the channel portion 130n, the threshold voltage Vth is not excessively shifted in the negative (-) direction, and at the same time, it can be seen that the current characteristics are improved.

[0124] On the other hand, when the area of ​​the conductive material layer 135 is less than 5% based on the total area of ​​the channel portion 130 n , the threshold voltage Vth is prevented from excessively shifting in the negative (−) direction, but does not have excellent on-current characteristics.

[0125] In addition, when the area of ​​the conductive material layer 135 exceeds 40% based on the total area of ​​the channel portion 130 n , it can be seen that the threshold voltage Vth is excessively shifted in the negative (−) direction.

[0126] According to one embodiment of the present invention, the conductive material layer 135 may include a first conductive material layer 135a and a second conductive material layer 135b. Specifically, the conductive material layer 135 may include a first conductive material layer 135a and a second conductive material layer 135b that are spaced apart from each other. More specifically, Figure 1 and Figure 2 2 shows a configuration in which the first conductive material layer 135a and the second conductive material layer 135b are spaced apart from each other.

[0127] Reference Figure 1 and Figure 2 , the first conductive material layer 135a is disposed closer to the first connection portion 130a than the second conductive material layer 135b. In addition, the second conductive material layer 135b may be disposed closer to the second connection portion 130b than the first conductive material layer 135a. Therefore, the current characteristics of the thin film transistor according to the present invention may be improved.

[0128] More specifically, the first conductive material layer 135a may be disposed in a region of the channel portion 130n in contact with the first connection portion 130a, and the second conductive material layer 135b may be disposed in a region of the channel portion 130n in contact with the second connection portion 130b.

[0129] According to one embodiment of the present invention, in a plan view, the first conductive material layer 135a and the second conductive material layer 135b may be disposed on any shortest line connecting the first connection portion 130a and the second connection portion 130b. Figure 1 , an arbitrary shortest line LN connecting the first connection portion 130a and the second connection portion 130b is illustrated, and a configuration in which the first conductive material layer 135a and the second conductive material layer 135b are disposed on the arbitrary shortest line LN connecting the first connection portion 130a and the second connection portion 130b is illustrated. However, the embodiments of the present invention are not limited thereto, and the first conductive material layer 135a and the second conductive material layer 135b may not be disposed on the arbitrary shortest line LN connecting the first connection portion 130a and the second connection portion 130b.

[0130] Specifically, refer to Fig. 9 , shows a configuration in which the first conductive material layer 135a and the second conductive material layer 135b are not disposed on any shortest line (not shown) connecting the first connection portion 130a and the second connection portion 130b. Even in this case, the first conductive material layer 135a may be disposed closer to the first connection portion 130a than the second conductive material layer 135b.

[0131] According to one embodiment of the present invention, each of the first conductive material layer 135a and the second conductive material layer 135b may have a plurality of patterns. Specifically, the first conductive material layer 135a may include a first sub-conductive material layer 136a and a second sub-conductive material layer 137a spaced apart from each other. In addition, the second conductive material layer 135b may include a first sub-conductive material layer 136b and a second sub-conductive material layer 137b spaced apart from each other. Fig.13 and Fig.14, it is illustrated that the first sub-conductive material layer 136a and the second sub-conductive material layer 137a are disposed closer to the first connection portion 130a, and it is illustrated that the first sub-conductive material layer 136b and the second sub-conductive material layer 137b are disposed closer to the second connection portion 130b.

[0132] Reference Fig.13 , the first sub-conductive material layer 136a of the first conductive material layer 135a and the first sub-conductive material layer 136b of the second conductive material layer 135b may be disposed on any shortest line (not illustrated) connecting the first connection portion 130a and the second connection portion 130b.

[0133] and Fig.13 compared to, Fig.14 It is shown that the first sub-conductive material layer 136a and the second sub-conductive material layer 137a of the first conductive material layer 135a and the first sub-conductive material layer 136b and the second sub-conductive material layer 137b of the second conductive material layer 135b may not be disposed on any shortest line (not illustrated) connecting the first connection portion 130a and the second connection portion 130b, respectively.

[0134] The embodiments of the present invention are not limited to Fig.13 and 14 The positions of the first sub-conductive material layers 136a and 136b and the second sub-conductive material layers 137a and 137b shown in the figure can be changed. In addition, the first conductive material layer 135a and the second conductive material layer 135b can include a third sub-conductive material layer (not shown), and can include more.

[0135] According to one embodiment of the present invention, when viewed in a plan view, the conductive material layer 135 may include a third conductive material layer 135 c disposed at the same distance from the first connection portion 130 a and the second connection portion 130 b , respectively. Fig.10 A third conductive material layer 135c disposed at the same distance from the first connection portion 130a and the second connection portion 130b, respectively, is shown.

[0136] Specifically, the third conductive material layer 135 c may be disposed at a boundary portion of a region of the channel portion 130 n contacting the first connection portion 130 a and a region of the channel portion 130 n contacting the second connection portion 130 b .

[0137] According to one embodiment of the present invention, the third conductive material layer 135c may have a plurality of patterns. Specifically, the third conductive material layer 135c may include a first sub-conductive material layer 136c and a second sub-conductive material layer 137c spaced apart from each other. Fig.15 The first and second sub-conductive material layers 136c and 137c disposed at the same distance from the first and second connection portions 130a and 130b, respectively, are illustrated.

[0138] One embodiment of the present invention is not limited to Fig.15 The positions of the first sub-conductive material layer 136c and the second sub-conductive material layer 137c are shown, and the positions of the first sub-conductive material layer 136c and the second sub-conductive material layer 137c may be changed. In addition, the third conductive material layer 135c may include a third sub-conductive material layer (not shown), and may include more.

[0139] According to an embodiment of the present invention, when the channel length direction of the active layer 130 is the first direction X and the width direction of the active layer 130 is the second direction Y, the conductive material layer 135 may include a fourth conductive material layer 135d having a length in the second direction Y longer than that in the first direction X. Specifically, Fig.11 The fourth conductive material layer 135d having a length in the second direction Y longer than that in the first direction X is illustrated.

[0140] More specifically, the fourth conductive material layer 135d may be disposed parallel to the second direction Y.

[0141] According to one embodiment of the present invention, both ends of the fourth conductive material layer 135 d may contact both ends of the channel portion 130 n based on the second direction Y. Fig.11 A configuration in which both ends of the fourth conductive material layer 135 d are in contact with both ends of the channel portion 130 n based on the second direction Y is illustrated.

[0142] However, the embodiments of the present invention are not limited thereto, and both ends of the fourth conductive material layer (135d) may not contact both ends of the channel portion (130n) based on the second direction (Y).

[0143] According to one embodiment of the present invention, the fourth conductive material layer 135d may have a plurality of patterns. Specifically, the fourth conductive material layer 135d may include a first sub-conductive material layer 136d and a second sub-conductive material layer 137d spaced apart from each other. Fig.16 The first sub-conductive material layer 136d and the second sub-conductive material layer 137d whose lengths in the second direction Y are greater than their lengths in the first direction X are illustrated.

[0144] The embodiments of the present invention are not limited to Fig.16The positions of the first sub-conductive material layer 136d and the second sub-conductive material layer 137d are shown, and the positions of the first sub-conductive material layer 136d and the second sub-conductive material layer 137d may be changed. In addition, the fourth conductive material layer 135d may include a third sub-conductive material layer (not shown), and may include more.

[0145] in addition, Fig.16 A configuration is shown in which the ends of the first sub-conductive material layer 136d and the second sub-conductive material layer 137d contact the two ends of the channel portion 130n based on the second direction Y, but is not limited thereto, and either end of the first sub-conductive material layer 136d or the second sub-conductive material layer 137d may contact the two ends of the channel portion 130n, and the ends of the first sub-conductive material layer 136d and the second sub-conductive material layer 137d may not contact the two ends of the channel portion 130n.

[0146] According to an embodiment of the present invention, when the channel length direction of the active layer 130 is the first direction X and the width direction of the active layer 130 is the second direction Y, the conductive material layer 135 may include a fifth conductive material layer 135e having a length in the first direction X greater than a length in the second direction Y. Specifically, Fig.12 The fifth conductive material layer 135 e having a length in the first direction X longer than a length in the second direction Y is illustrated.

[0147] More specifically, the fifth conductive material layer 135e may be disposed parallel to the first direction X.

[0148] According to one embodiment of the present invention, the fifth conductive material layer 135e may be disposed in the channel portion 130n with respect to the first direction X. Fig.12 The fifth conductive material layer 135 e disposed in the channel portion 130 n with respect to the first direction X is illustrated.

[0149] More specifically, the fifth conductive material layer 135e is spaced apart from the first connection portion 130a and the second connection portion 130b.

[0150] According to one embodiment of the present invention, the distance between the fifth conductive material layer 135e, the first connection portion 130a, and the second connection portion 130b may be 1 μm or more based on the first direction X.

[0151] Specifically, refer to Fig.12 , when the distance between the fifth conductive material layer 135e and the first connection portion 130a and the second connection portion 130b is L, L may be 1 μm or more. Therefore, the threshold voltage Vth of the thin film transistor according to the present invention is not excessively shifted in the negative (-) direction, and at the same time, the current characteristics can be improved.

[0152] On the other hand, when the distance L between the fifth conductive material layer 135e, the first connection part 130a and the second connection part 130b is less than 1 μm, the distance between the fifth conductive material layer 135e, the first connection part 130a and the second connection part 130b becomes very close, and the conduction of the channel part 130n is excessively performed, so that the threshold voltage Vth of the thin film transistor may be excessively shifted in the negative (-) direction.

[0153] According to one embodiment of the present invention, the fifth conductive material layer 135e may have a plurality of patterns. Specifically, the fifth conductive material layer 135e may include a first sub-conductive material layer 136e and a second sub-conductive material layer 137e spaced apart from each other. Fig.17 , the first sub-conductive material layer 136e and the second sub-conductive material layer 137e are respectively illustrated in the first direction X. Each of the first sub-conductive material layer 136e and the second sub-conductive material layer 137e may be disposed based on the first direction X in the channel portion 130n.

[0154] The embodiments of the present invention are not limited to Fig.17 The positions of the first sub-conductive material layer 136e and the second sub-conductive material layer 137e are shown, and the positions of the first sub-conductive material layer 136e and the second sub-conductive material layer 137e can be changed. In addition, the fifth conductive material layer 135e may include a third sub-conductive material layer (not shown), and may include more than one third sub-conductive material layer.

[0155] According to one embodiment of the present invention, the conductive material layer 135 may have a circular shape, an elliptical shape, a semicircular shape, a semielliptical shape, and a polygonal shape. Fig.18 The conductive material layer 135 is shown to have a circular shape. However, the embodiments of the present invention are not limited thereto, and the conductive material layer 135 may have various plane shapes. For example, the conductive material layer 135 may have a circular plane, an elliptical plane, a semicircular plane, a semielliptical plane, and a polygonal plane, and may have an irregularly shaped plane.

[0156] Fig.18 The configuration in which each of the first sub-conductive material layers 136a and 136b and the second sub-conductive material layers 137a and 137b has a circular shape is shown. However, the embodiments of the present invention are not limited thereto, and any of the first sub-conductive material layers 136a and 136b and the second sub-conductive material layers 137a and 137b may have a different shape.

[0157] According to one embodiment of the present invention, a region of the channel portion 130 n overlapping the conductive material layer 135 may have a higher carrier concentration than a region not overlapping the conductive material layer 135 .

[0158] According to one embodiment of the present invention, the sub-conductive material layers 165 and 175 may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO), and the conductive material layer 135 may also be formed of the same material as the sub-conductive material layers 165 and 175. Therefore, the conductive material layer 135 may have a reducing property.

[0159] Specifically, the portions of the channel portion 130n that contact and overlap with the conductive material layer 135 may be reduced, respectively. For example, when the portion of the channel portion 130n that contacts and overlaps with the conductive material layer 135 is reduced, oxygen vacancies appear in the channel portion 130n, and thus the channel portion 130n may be selectively conductive. Therefore, the region of the channel portion 130n that overlaps with the conductive material layer 135 may have a higher carrier concentration than the region that does not overlap with the conductive material layer 135, and thus the current characteristics of the thin film transistor may be effectively improved.

[0160] Fig.19A and Fig.19B is a plan view of a thin film transistor according to a comparative example and an example, and Fig. 20 It shows that according to Fig.19A and Fig.19B A graph showing the current characteristics of a thin film transistor.

[0161] exist Fig. 20 In the graph of , the horizontal axis represents the gate voltage VG, and the vertical axis represents the logarithmic (log) value of the drain-source current IDS. In addition, Fig. 20 A illustrates the Fig.19A The current characteristics of the thin film transistor, and Fig. 20 B illustrates the Fig.19B Current characteristics of a thin film transistor.

[0162] Fig.19A 1 is a plan view of a thin film transistor according to a comparative example in which the conductive material layer 135 is not provided on the channel portion 130n. Fig.19B 1 is a plan view of a thin film transistor according to an embodiment in which a conductive material layer 135 is disposed on a channel portion 130n. Specifically, although Fig.19B The first conductive material layer 135a and the second conductive material layer 135b are illustrated, but embodiments of the present invention are not limited thereto, and any one of the third conductive material layer 135c, the fourth conductive material layer 135d, and the fifth conductive material layer 135e may be disposed on the channel portion 130n.

[0163] In an embodiment where the conductive material layer 135 is disposed on the channel portion 130n (see Fig.19B ), the region of the channel portion 130n overlapping the conductive material layer 135 can be reduced by the conductive material layer 135 to selectively become a conductor. Therefore, the region of the channel portion 130n overlapping the conductive material layer 135 can have a higher carrier concentration than the region not overlapping the conductive material layer 135, so the current characteristics of the thin film transistor can be effectively improved. In this case, Fig. 20 B shows current characteristics of the thin film transistor according to the embodiment.

[0164] On the other hand, in the comparative example where the conductive material layer 135 is not provided on the channel portion 130n (see Fig.19A ), the conductive material layer 135 is not provided on the channel portion 130n, and therefore there is no region to be selectively made conductive in the channel portion 130n, and therefore the carrier concentration of the channel portion 130n is lower than that of the comparative example, and thus the current characteristics of the thin film transistor cannot be effectively improved. In this case, Fig. 20 A shows the current characteristics of the thin film transistor according to the comparative example.

[0165] According to an embodiment of the present invention, the active layer 130 of the thin film transistor 400 may have a multi-layer structure. For example, the active layer 130 may include a first active layer 131 and a second active layer 132 .

[0166] Specifically, refer to Figure 8 , the active layer 130 may include a first active layer 131 and a second active layer 132 located on the first active layer 131 .

[0167] The first active layer 131 and the second active layer 132 may include the same semiconductor material, or may include different semiconductor materials.

[0168] The first active layer 131 supports the second active layer 132. Therefore, the first active layer 131 is also referred to as a “support layer.” The active layer 130 has a structure consisting of the first active layer 131 and the second active layer 132, and is also referred to as a double-layer structure.

[0169] Although not illustrated in the drawings, the active layer 130 may further include a third active layer 133 located on the second active layer 132 , and the active layer 130 may further include another semiconductor layer.

[0170] According to an embodiment of the present invention, the thin film transistor may further include a gate insulating layer 140 between the active layer 130 and the gate electrode 150. Specifically, the gate insulating layer 140 may cover the entire upper surface of the active layer 130. Figure 2A configuration in which the gate insulating layer 140 covers the entire upper surface of the active layer 130 is illustrated.

[0171] However, embodiments of the present invention are not limited thereto, and the first and second connection portions 130 a and 130 b of the active layer 130 may be exposed from the gate insulating layer 140 .

[0172] The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layer 140 may have a single layer structure or a multi-layer structure. The gate insulating layer 140 protects the channel portion 130n.

[0173] Reference Figure 2 , the gate electrode 150 is disposed on the gate insulating layer 140. The gate electrode 150 overlaps the channel portion 130n of the active layer 130.

[0174] The gate electrode 150 may include an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, and at least one of chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multilayer structure including at least two conductive layers having different physical properties.

[0175] Reference Figure 2 The interlayer insulating layer 180 is disposed on the gate electrode 150 and the gate insulating layer 140. The interlayer insulating layer 180 is an insulating layer made of an insulating material. The interlayer insulating layer 180 may be formed of an organic material, an inorganic material, or a lamination of an organic material layer and an inorganic material layer.

[0176] Reference Figure 2 , the source electrode 160 and the drain electrode 170 are disposed on the interlayer insulating layer 180 .

[0177] Although not illustrated in the drawings, the source electrode 160 and the drain electrode 170 may be disposed on the gate insulating layer 140 and may be disposed on the same layer as the gate electrode 150. The source electrode 160 and the drain electrode 170 may be made of the same material as the gate electrode 150 through the same process.

[0178] Each of the source electrode 160 and the drain electrode 170 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The source electrode 160 and the drain electrode 170 may have a multilayer structure including at least two conductive films having different physical properties.

[0179] Reference Figure 1 and Figure 2 The source electrode 160 and the drain electrode 170 are connected to the active layer 130 through the contact holes, respectively. Specifically, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 by contacting the source conductive material layer 165 and the drain conductive material layer 175, respectively.

[0180] Reference Figure 1 , Figure 2 and Figure 3 , the light blocking layer 111 may be disposed on the base substrate 110. Specifically, the light blocking layer 111 may be disposed between the base substrate 110 and the active layer 130. The light blocking layer 111 overlaps the channel portion 130n. The light blocking layer 111 blocks light incident from the outside, thereby protecting the channel portion 130n.

[0181] The light blocking layer 111 may be formed of a material having a light blocking property. The light blocking layer 111 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to one embodiment of the present invention, the light blocking layer 111 may have electrical conductivity.

[0182] The light blocking layer 111 may be omitted. Figure 1 , Figure 2 and Figure 3 Although not illustrated in the drawings, a buffer layer may be additionally disposed between the base substrate 110 and the light blocking layer 111. The light blocking layer 111 may be electrically connected to one of the source electrode 160 and the drain electrode 170. Figure 2 A configuration in which the light blocking layer 111 is electrically connected to the source electrode 160 is illustrated.

[0183] Fig. 22 is a schematic diagram illustrating a display device 2000 according to still another embodiment of the present disclosure.

[0184] like Fig. 22 As shown, a display device 2000 according to still another embodiment of the present disclosure may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0185] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on the base substrate 110 .

[0186] The controller 340 controls the gate driver 320 and the data driver 330 .

[0187] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal provided from an external system not shown. In addition, the controller 340 samples the input image data input from the external system, realigns the sampled data, and provides the realigned digital image data RGB to the data driver 330.

[0188] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling a shift register may be included in the gate control signal GCS.

[0189] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0190] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0191] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0192] The display device 2000 according to one embodiment of the present disclosure may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 and 1400. According to one embodiment of the present disclosure, the gate driver 320 may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 and 1400.

[0193] The gate driver 320 may include a shift register 350 .

[0194] The shift register 350 sequentially supplies a gate pulse to the gate line GL for one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a time period for outputting one image through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0195] In addition, in another period of one frame (during which the gate pulse is not provided), the shift register 350 provides a gate-off signal capable of turning off the switching device to the gate line GL. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0196] The shift register 350 may include the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , 1100 , 1200 , 1300 , and 1400 described above.

[0197] Fig.23 is a schematic diagram illustrating the shift register 350 .

[0198] Reference Fig.23 , the shift register 350 may include g stages 351 (ST1 to STg).

[0199] The shift register 350 transmits one scan signal SS to the pixel P connected to one gate line GL through one gate line GL. Each of the stages 351 may be connected to one gate line GL. When g gate lines GL are formed in the display panel 310, the shift register 350 may include g stages 351 (ST1 to STg) and may generate g scan signals SS1 to SSg.

[0200] Generally, each stage 351 outputs the gate pulse GP once during one frame, and the gate pulse GP is sequentially output from each stage 351 .

[0201] Fig.24 It is an example Fig. 22 Circuit diagram of any pixel P.

[0202] Fig.24 The circuit diagram of FIG. 7 is an equivalent circuit diagram of a pixel P of the display device 2000 including an organic light emitting diode (OLED) as a display element 710 .

[0203] Reference Fig.24 , the pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. Specifically, the display device 2000 according to an embodiment of the present disclosure may include a pixel driving circuit PDC located on a base substrate 110.

[0204] Fig.24 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. A display device 2000 according to another embodiment of the present disclosure may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 and 1400.

[0205] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

[0206] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0207] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0208] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0209] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray scale of light output from the display element 710 may be controlled.

[0210] Fig.25 yes Fig.24 The pixel plane diagram, and Fig.26 It is along Fig.25 A cross-sectional view taken along line III-III'.

[0211] Reference Fig.25 and Fig.26 , the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the base substrate 110 .

[0212] The base substrate 110 may be made of glass or plastic. As the base substrate 110, plastic having a flexible property (eg, polyimide (PI)) may be used.

[0213] The light blocking layer 111 is disposed on the base substrate 110. The light blocking layer 111 may have a light blocking property. The light blocking layer 111 may block light incident from the outside to protect the active layers A1 and A2.

[0214] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material, and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

[0215] The active layer A1 of the first thin film transistor TR1 and the active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120 .

[0216] The active layers A1 and A2 may include, for example, an oxide semiconductor material. The active layers A1 and A2 may have a multi-layered structure made of an oxide semiconductor material.

[0217] The sub-conductive material layers 165 and 175 may be disposed on the active layers A1 and A2.

[0218] According to one embodiment of the present invention, the sub-conductive material layers 165 and 175 may include at least one selected from metal and transparent conductive oxide (TCO).

[0219] The active layers A1 and A2 may further include a conductive material layer 135. Specifically, the conductive material layer 135 may be disposed on the channel portions of the active layers A1 and A2.

[0220] The gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 covers upper surfaces of the active layers A1 and A2.

[0221] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0222] Although not shown in the drawings, the gate line GL may be disposed on the gate insulating layer 140. The gate electrode G1 of the first thin film transistor TR1 may extend from the gate line GL or may be a part of the gate line GL.

[0223] Reference Fig.25 and Fig.26 , a first capacitor electrode CE1 of the storage capacitor Cst is formed on the gate insulating layer 140. The first capacitor electrode CE1 may be formed of the same material as the gate electrodes G1 and G2 through the same process.

[0224] An interlayer insulating layer 180 is disposed on the gate electrodes G1 and G2 and the first capacitor electrode CE1 .

[0225] The data line DL and the driving power line PL are disposed on the interlayer insulating layer 180. In addition, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 and the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the interlayer insulating layer 180.

[0226] The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL, and may have a structure extending from the data line DL.

[0227] The source electrode S1 of the first thin film transistor TR1 may make contact with a side surface of the active layer A1 of the first thin film transistor TR1 through the first contact hole H1 .

[0228] The drain electrode D1 of the first thin film transistor TR1 contacts the other side surface of the active layer A1 of the first thin film transistor TR1 through the second contact hole H2. The drain electrode D1 of the first thin film transistor TR1 is connected to the first capacitor electrode CE1 through the third contact hole H3. Therefore, the first capacitor electrode CE1 can be connected to the first thin film transistor TR1.

[0229] The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL, and may have a structure extending from the driving power line PL.

[0230] The drain electrode D2 of the second thin film transistor TR2 may contact the side surface of the active layer A2 of the second thin film transistor TR2 through the sixth contact hole H6.

[0231] The source electrode S2 of the second thin film transistor TR2 contacts the other side surface of the active layer A2 of the second thin film transistor TR2 through the fifth contact hole H5. In addition, the source electrode S2 of the second thin film transistor TR2 is connected to the light blocking layer 111 through the fourth contact hole H4. The same voltage as the source electrode S2 of the second thin film transistor TR2 may be applied to the light blocking layer 111 overlapping the second thin film transistor TR2.

[0232] The source electrode S2 of the second thin film transistor TR2 may extend onto the interlayer insulating layer 145 to form a second capacitor electrode CE2 of the storage capacitor Cst.

[0233] According to one embodiment of the present invention, the first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap to form a storage capacitor Cst.

[0234] Reference Fig.25 and Fig.26The planarization layer 190 is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, the drain electrodes D1 and D2, and the second capacitor electrode CE2. The planarization layer 190 planarizes the upper portion of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2. The planarization layer 190 serves as a protective layer.

[0235] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second capacitor electrode CE2 through the seventh contact hole H7 formed in the planarization layer 190. Therefore, the first electrode 711 of the display element 710 may be connected to the source electrode S2 of the second thin film transistor TR2.

[0236] The bank layer 750 is disposed at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0237] The organic light emitting layer 712 is provided on the first electrode 711, and the second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Fig.26 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 2000 according to one embodiment of the present invention is an organic light emitting display device.

[0238] Fig. 27 is a circuit diagram of any pixel of a display device 2100 according to another embodiment of the present invention.

[0239] Fig. 27 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0240] Fig. 27 The pixel P of the illustrated display device 2100 includes an organic light emitting diode OLED, which is a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0241] In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are arranged.

[0242] A data voltage Vdata is supplied to the data line DL, a scan signal SS is supplied to the gate line GL, a driving voltage Vdd for driving pixels is supplied to the driving power line PL, a reference voltage Vref is supplied to the reference line RL, and a sensing control signal SCS is supplied to the sensing control line SCL.

[0243] The pixel driving circuit PDC includes, for example, a first thin film transistor TR1 (switching transistor) connected to the selection line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata sent through the first thin film transistor TR1, and a third thin film transistor TR3 (sensing transistor) for sensing the characteristics of the second thin film transistor TR2.

[0244] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0245] The third thin film transistor TR3 is connected to the first node n1, and the reference line RL between the second thin film transistor TR2 and the display element 710 is turned on or off by the sensing control signal SCS and detects the characteristics of the second thin film transistor TR2 (which is a driving transistor during the sensing period).

[0246] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. A storage capacitor Cst is formed between the second node n2 and the first node n1.

[0247] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0248] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is output from the display element 710 .

[0249] A display device 2100 according to another embodiment of the present invention may include at least one of the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , 1100 , 1200 , 1300 , and 1400 .

[0250] Fig.28 is a circuit diagram of any pixel P of a display device 2200 according to another embodiment of the present invention.

[0251] Fig.28 The pixel P of the display device 2200 shown includes an organic light emitting diode OLED, which is a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0252] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0253] Signal lines DL, EL, GL, PL, SCL, RL that supply drive signals to the pixel drive circuit PDC are arranged in the pixel P.

[0254] and Fig. 27 Compared with the pixel P, Fig.28 The pixel P further includes a light emitting control line EL. A light emitting control signal EM is provided to the light emitting control line EL. Fig. 27 Compared with the pixel driving circuit PDC, Fig.28 The pixel driving circuit PDC further includes a fourth thin film transistor TR4, which is a light emission control transistor for controlling a light emission timing point of the second thin film transistor TR2.

[0255] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0256] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0257] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects characteristics of the third thin film transistor TR3 as a driving transistor during a sensing period.

[0258] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the light emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 to output light from the display element 710 .

[0259] A pixel driving circuit PDC according to another exemplary configuration of the present invention may be formed in various structures other than the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0260] According to the present disclosure, the following advantageous effects can be obtained.

[0261] A thin film transistor according to an embodiment of the present invention may include a conductive material layer disposed on a channel portion, thereby improving current characteristics.

[0262] A thin film transistor according to an embodiment of the present invention includes a conductive material layer disposed on a channel portion, and a threshold voltage Vth is not excessively shifted in a negative (-) direction, and current characteristics can be improved.

[0263] A thin film transistor according to an embodiment of the present invention includes a conductive material layer disposed on a channel portion, and can maintain current characteristics even if the width of the channel portion is small.

[0264] In addition to the above-mentioned effects, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art to which the present invention belongs from such technology and description.

[0265] It is obvious to those skilled in the art that the above disclosure is not limited by the above embodiments and drawings, and various substitutions, modifications and changes can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the present disclosure.

[0266] CROSS-REFERENCE TO RELATED APPLICATIONS

[0267] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0101362, filed on August 3, 2023, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A thin film transistor, comprising: An active layer, the active layer being located on a base substrate; a sub-conductive material layer, wherein the sub-conductive material layer is located on the active layer; a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; as well as a conductive material layer, wherein the conductive material layer is located on the active layer; The active layer comprises: a channel portion, the channel portion partially overlapping the gate electrode; a first connection portion connected to one side of the channel portion; and a second connection portion connected to the other side of the channel portion; The sub-conductive material layer comprises: a source conductive material layer, the source conductive material layer being located on the first connecting portion; and a drain conductive material layer, wherein the drain conductive material layer is located on the second connecting portion, The conductive material layer is disposed on the channel portion and on the same layer as the sub conductive material layer. 2 . The thin film transistor according to claim 1 , wherein in a plan view, an area of ​​the conductive material layer in the channel portion is 5% to 40% based on a total area of ​​the channel portion. 3 . The thin film transistor according to claim 1 , wherein the source conductive material layer and the drain conductive material layer each overlap a portion of the first connection portion and a portion of the second connection portion. 4 . The thin film transistor according to claim 3 , wherein the source conductive material layer and the drain conductive material layer are each disposed on an entire surface of the first connection portion and the second connection portion.

5. The thin film transistor according to claim 1, wherein: The conductive material layer includes a first conductive material layer and a second conductive material layer spaced apart from each other.

6. The thin film transistor according to claim 5, wherein: The first conductive material layer is disposed closer to the first connection portion than the second conductive material layer.

7. The thin film transistor according to claim 5, wherein: In a plan view, the first conductive material layer and the second conductive material layer are disposed on any shortest line connecting the first connection portion and the second connection portion.

8. The thin film transistor according to claim 5, wherein: In a plan view, the first conductive material layer and the second conductive material layer are not disposed on any shortest line connecting the first connection portion and the second connection portion.

9. The thin film transistor according to claim 5, wherein: The first conductive material layer includes a first sub-conductive material layer and a second sub-conductive material layer that are spaced apart from each other, and The second conductive material layer includes a first sub-conductive material layer and a second sub-conductive material layer that are spaced apart from each other.

10. The thin film transistor according to claim 1, wherein: The conductive material layer includes a third conductive material layer disposed at the same distance from each of the first connection portion and the second connection portion in a plan view.

11. The thin film transistor according to claim 1, when the channel length direction of the active layer is a first direction and the width direction of the active layer is a second direction, the conductive material layer includes a fourth conductive material layer, and the length of the fourth conductive material layer in the second direction is longer than the length in the first direction. 12 . The thin film transistor according to claim 11 , wherein both ends of the fourth conductive material layer contact both ends of the channel portion based on the second direction.

13. The thin film transistor according to claim 1, when the channel length direction of the active layer is a first direction and the width direction of the active layer is a second direction, the conductive material layer includes a fifth conductive material layer, and the length of the fifth conductive material layer in the first direction is longer than the length in the second direction.

14. The thin film transistor according to claim 13, wherein: Based on the first direction, the fifth conductive material layer is disposed in the channel portion. 15 . The thin film transistor according to claim 14 , wherein each distance between the fifth conductive material layer and the first connection portion and between the fifth conductive material layer and the second connection portion is 1 μm or more based on the first direction. 16 . The thin film transistor according to claim 1 , wherein a region of the channel portion overlapping the conductive material layer has a higher carrier concentration than a region not overlapping the conductive material layer.

17. The thin film transistor according to claim 1, wherein: The sub-conductive material layer includes at least one selected from metal and transparent conductive oxide TCO.

18. The thin film transistor according to claim 1, wherein: The conductive material layer is formed of the same material as the sub-conductive material layer.

19. The thin film transistor according to claim 1, wherein: The active layer includes at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO).

20. A display device comprising the thin film transistor according to any one of claims 1 to 19.

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