Thin film transistor substrate and display device including same

Abstract

The invention relates to a thin film transistor substrate and a display device including the same. The thin film transistor substrate includes: a thin film transistor on a substrate, the thin film transistor including: an active layer; a conductive material layer; and a gate electrode spaced apart from and partially overlapping the active layer. The active layer includes: a channel region partially overlapping the gate electrode; and source and drain regions connected to respective sides of the channel region. The conductive material layer includes a first conductive material layer and a second conductive material layer on the source region and the drain region, respectively. The first conductive material layer overlaps at least a portion of the channel region. The active layer includes an active hole in which the active layer is not within a region defined by the active layer, and the active hole extends from the channel region to the drain region in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor substrate and a display device including the same. Background Art

[0002] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on glass substrates or plastic substrates, they are widely used as switching devices for display devices such as liquid crystal display devices or organic light emitting devices.

[0003] Based on materials constituting the active layer, thin film transistors can be classified into amorphous silicon thin film transistors using amorphous silicon as an active layer, polycrystalline silicon thin film transistors using polycrystalline silicon as an active layer, and oxide semiconductor thin film transistors using oxide semiconductors as an active layer.

[0004] Amorphous silicon thin film transistors (a-Si TFTs) have the advantages of short manufacturing process time and low production cost because amorphous silicon can be deposited in a short time to form an active layer, but have the disadvantages of being limited to active matrix organic light-emitting devices (AMOLEDs) due to low mobility and poor current driving capability and variation in threshold voltage.

[0005] Polycrystalline silicon thin film transistors (poly-Si TFTs) are manufactured by crystallizing amorphous silicon after depositing it. Since a process of crystallizing amorphous silicon is required in the manufacturing process of polycrystalline silicon thin film transistors, the manufacturing cost increases as the number of processes increases, and since the crystallization process is performed at a high process temperature, it is difficult to apply polycrystalline silicon thin film transistors to large-area devices. In addition, due to its polycrystalline nature, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0006] In an oxide semiconductor thin film transistor (TFT), since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, the desired physical properties can be easily obtained. In addition, due to the properties of the oxide, since the oxide semiconductor is transparent, it is also conducive to the realization of a transparent display.

[0007] In the case of an oxide semiconductor thin film transistor, it may be susceptible to exposure to light or hydrogen, and in this case, a structural change for controlling exposure to light or hydrogen is required. Therefore, a technology for controlling exposure to light or hydrogen is being studied. Summary of the invention

[0008] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a thin film transistor.

[0009] An embodiment of the present disclosure is to provide a thin film transistor substrate including active holes to prevent or inhibit exposure to hydrogen and light.

[0010] An embodiment of the present disclosure is to provide a thin film transistor substrate including an active hole to prevent or suppress a threshold voltage Vth from shifting in a negative (-) direction even if a channel region has a large width.

[0011] An embodiment of the present disclosure is to provide a thin film transistor substrate including a conductive material layer overlapping a channel region to prevent or inhibit exposure to hydrogen and light.

[0012] An embodiment of the present disclosure is to provide a thin film transistor substrate having improved reliability by including a pattern of an active layer and including a conductive material layer overlapping a channel region.

[0013] Embodiments of the present disclosure provide a thin film transistor substrate capable of ensuring capacitor area optimization by including a conductive material layer overlapping a channel region and an active hole.

[0014] Another configuration of the present disclosure is to provide a display device including such a thin film transistor substrate.

[0015] In addition to the above-mentioned objects of the present disclosure, other objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0016] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor substrate, which includes a thin film transistor on a base substrate. The thin film transistor includes: an active layer; a conductive material layer on the active layer; and a gate electrode spaced apart from the active layer and partially overlapping with the active layer. The active layer includes: a channel region partially overlapping with the gate electrode in a plane; a source region connected to one side of the channel region in a plane; and a drain region connected to the other side of the channel region in a plane. The conductive material layer includes: a first conductive material layer on the source region; and a second conductive material layer on the drain region. The first conductive material layer overlaps at least a portion of the channel region, wherein an active hole where the active layer is not provided is provided in an area defined by the active layer, and the active hole protrudes from the gate electrode in the plane in the direction of the drain region.

[0017] A portion of the active hole may overlap with the gate electrode.

[0018] The active hole may be spaced apart from the first conductive material layer in a plan view.

[0019] The second conductive material layer may be spaced apart from the channel region in a plan view.

[0020] The source region and the drain region may be disposed between the base substrate and the first conductive material layer and between the base substrate and the second conductive material layer, respectively, and the first conductive material layer and the second conductive material layer may contact the active layer, respectively.

[0021] It includes a source electrode and a drain electrode spaced apart from each other and contacting a source region and a drain region, and the gate electrode, the source electrode, and the drain electrode may be disposed on the same layer.

[0022] The active hole may have a plurality of sub-active holes, and the plurality of sub-active holes may be spaced apart from each other.

[0023] The conductive material layer may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba) and transparent conductive oxide (TCO).

[0024] When the shortest distance from the drain region to the first conductive material layer is a first length and the shortest length of a region where the first conductive material layer overlaps the gate electrode in a channel length direction of the active layer is a second length, the first length may be longer than the second length.

[0025] A portion of the active hole overlaps with the gate electrode, and the shortest length of the area where the active hole overlaps with the gate electrode in the channel length direction of the active layer is a third length, and the shortest distance from the active hole to the first conductive material layer in the channel length direction of the active layer is a fourth length, and the fourth length can be longer than the third length.

[0026] It may include a light blocking layer on a base substrate, and may further include a storage capacitor disposed in an overlapping region between the light blocking layer and the thin film transistor.

[0027] The storage capacitor may include a first storage capacitor, and the first storage capacitor may include a first capacitor electrode connected to the light blocking layer and a second capacitor electrode connected to the active layer, and the first capacitor electrode and the second capacitor electrode may be spaced apart from each other and overlap each other to form the first capacitor.

[0028] The first storage capacitor may include a third capacitor electrode connected to the gate electrode, and the second capacitor electrode and the third capacitor electrode may be spaced apart from each other and overlap each other to form the second capacitor.

[0029] The second capacitor electrode may include a first layer integrated with any one of the source region and the drain region and a second layer integrated with any one of the first conductive material layer and the second conductive material layer.

[0030] The second capacitor electrode may be disposed between the first capacitor electrode and the third capacitor electrode, and the third capacitor electrode may be connected to the first capacitor electrode.

[0031] The storage capacitor may include a second storage capacitor formed by separating and overlapping the gate electrode and the first conductive material layer.

[0032] The storage capacitor may include a third storage capacitor formed by separating and overlapping the gate electrode and the light blocking layer from each other.

[0033] The third storage capacitor may be formed in a region overlapping the active hole.

[0034] The active layer may include an oxide semiconductor material, and the oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0035] Another configuration of the present disclosure provides a display device including a thin film transistor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0038] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0039] Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0040] Figure 4 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0041] Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0042] Figure 6It is along Figure 4 A cross-sectional view taken along line II-II'.

[0043] Figure 7 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0044] Figure 8 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0045] Fig. 9 is a schematic diagram illustrating a capacitor of the present disclosure.

[0046] Fig.10 is a cross-sectional view of a thin film transistor substrate according to an embodiment for describing a capacitor of the present disclosure.

[0047] Fig.11 is a cross-sectional view of a thin film transistor substrate according to a comparative example for describing a capacitor of the present disclosure.

[0048] Fig. 12A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0049] Fig. 12B It is along Fig. 12A A cross-sectional view taken along line II'.

[0050] Fig.13 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0051] Fig.14 is a schematic diagram of a shift register.

[0052] Fig.15 yes Fig.13 The circuit diagram of any pixel.

[0053] Fig.16 yes Fig.15 A floor plan of pixels.

[0054] Fig.17 It is along Fig.16 A cross-sectional view taken along line III-III'.

[0055] Fig.18 is a circuit diagram of any one pixel of a display device according to another embodiment of the present disclosure.

[0056] Fig.19 is a circuit diagram of any one pixel of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The advantages and features of the present disclosure and methods for implementing the same will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be specifically implemented in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0058] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for the purpose of describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, similar reference numerals represent similar elements. In the following description, when a detailed description of a related known function or configuration is determined to be unnecessarily obscuring the focus of the present disclosure, the detailed description will be omitted.

[0059] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless indicated otherwise.

[0060] In interpreting an element, although not explicitly described, the element is interpreted to include an error range.

[0061] When describing a positional relationship, for example, when the positional relationship is described as "on," "above," "below," and "beside," one or more parts may be disposed between two other parts unless "just" or "directly" is used.

[0062] Spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to easily describe the relationship of one element or elements to another element or elements, as shown in the figures. It will be understood that these terms are intended to cover different orientations of the device in addition to the orientation shown in the figures. For example, if the device shown in the figure is reversed, a device described as being arranged "below" or "under" another device may be arranged "above" the other device. Thus, the exemplary term "below or under" may include the orientations of "below or under" and "above." Similarly, the exemplary term "above" or "on" may include the orientations of "above" and "below or under."

[0063] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0064] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0065] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each element in the first element, the second element, and the third element.

[0066] The features of the various embodiments of the present disclosure may be partially or completely connected or combined with each other, and may interoperate with each other differently and be driven technically as those skilled in the art can fully understand. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0067] When adding reference numerals to components of each of the drawings describing the embodiments of the present disclosure, the same components may have the same symbols as those shown on other drawings.

[0068] In the embodiments of the present disclosure, the source electrode and the drain electrode are distinguished for ease of description, and the source electrode and the drain electrode can be interchanged. The source electrode can be the drain electrode, and vice versa. In addition, the source electrode of any embodiment can be the drain electrode in another embodiment, and the drain electrode of any embodiment can be the source electrode in another embodiment.

[0069] In some embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0070] Figure 1 is a plan view of a thin film transistor substrate 100 according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line II'. Figure 3 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0071] Reference Figure 1 , Figure 2 and Figure 3The thin film transistor substrate 100 according to an embodiment of the present disclosure may include a thin film transistor TFT on a base substrate 110 , and the thin film transistor TFT may include an active layer 130 , a gate electrode 150 , and conductive material layers 165 and 175 .

[0072] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , may include a gate electrode 150 spaced apart from the active layer 130 and partially overlapping the active layer 130 and the conductive material layers 165 and 175 on the active layer 130 .

[0073] According to an embodiment of the present disclosure, the thin film transistor substrate 100 may further include a base substrate 110. Figure 2 and Figure 3 , the active layer 130 is disposed on the base substrate 110 .

[0074] The thin film transistor substrate 100 according to the embodiment of the present disclosure may further include a buffer layer 120. Figure 2 and Figure 3 , the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0075] The thin film transistor substrate 100 according to the embodiment of the present disclosure may further include a gate insulating layer 140. Figure 2 and Figure 3 , the gate insulating layer 140 is disposed on the active layer 130 . Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150 .

[0076] According to an embodiment of the present disclosure, the thin film transistor substrate 100 may further include another layer disposed on the gate electrode 150. In detail, the thin film transistor substrate 100 may further include an interlayer insulating layer 180. Fig.17 , the interlayer insulating layer 180 is disposed on the gate electrode 150. In detail, the gate electrode 150 is disposed between the gate insulating layer 140 and the interlayer insulating layer 180.

[0077] According to an embodiment of the present disclosure, the thin film transistor substrate 100 may further include a source electrode 160 and a drain electrode 170. Figure 1 , Figure 2 and Figure 3 , a source electrode 160 and a drain electrode 170 are disposed on the gate insulating layer 140 .

[0078] Hereinafter, components of the thin film transistor substrate 100 according to an embodiment of the present disclosure will be described in more detail.

[0079] Glass or plastic may be used as the base substrate 110. As the plastic, transparent plastic having flexible properties, for example, polyimide may be used.

[0080] When polyimide is used as the base substrate 110, heat-resistant polyimide that can withstand high temperatures may be used in consideration of performing a high-temperature deposition process on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition, etching, etc. may be performed in a state where the polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

[0081] Reference Figure 2 and Figure 3 , the buffer layer 120 may be disposed on the base substrate 110 .

[0082] The buffer layer 120 may be formed on the base substrate 110 and may be formed of an inorganic material or an organic material. For example, an insulating oxide such as silicon oxide (SiOx), aluminum oxide (Al2O3), etc. may be included.

[0083] The buffer layer 120 blocks impurities such as moisture and oxygen flowing out of the base substrate 110 to protect the active layer 130 , planarizes an upper portion of the base substrate 110 , and may be formed as a single layer or a multi-layer.

[0084] Reference Figure 2 and Figure 3 , the active layer 130 may be disposed on the buffer layer 120 .

[0085] The active layer 130 may include a channel region 130 n , a source region 130 a , and a drain region 130 b .

[0086] Specifically, the active layer 130 may include a channel region 130n partially overlapping the gate electrode 150 in a plane, a source region 130a connected to one side of the channel region 130n in the plane without overlapping the gate electrode 150, and a drain region 130b connected to the other side of the channel region 130n in the plane without overlapping the gate electrode 150.

[0087] According to an embodiment of the present disclosure, the source region 130 a and the drain region 130 b are spaced apart from each other, and the channel region 130 n is interposed therebetween.

[0088] According to the configuration of the present disclosure, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0089] The oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material. However, the embodiments of the present disclosure are not limited thereto, and the active layer 130 may be made of another oxide semiconductor material known in the art.

[0090] The source region 130a and the drain region 130b may be formed by selective conduction with respect to the active layer 130 made of a semiconductor material. According to an embodiment of the present disclosure, conduction is imparted to a specific portion of the active layer 130 so that the same function as a conductor is referred to as selective conduction.

[0091] For example, the active layer 130 may be selectively conductive by ion doping. As a result, the source region 130a and the drain region 130b may be formed. However, the embodiments of the present disclosure are not limited thereto, and the active layer 130 may be selectively conductive by other methods known in the art.

[0092] The source region 130a and the drain region 130b do not overlap the gate electrode 150. The source region 130a and the drain region 130b have better conductivity and higher mobility than the channel region 130n. Therefore, the source region 130a and the drain region 130b can be used as wirings, respectively.

[0093] Reference Figure 1 and Figure 3 , wherein the active hole 135 where the active layer 130 is not disposed is disposed in a region whose edge is defined by the active layer 130. According to an embodiment of the present disclosure, the active hole 135 is disposed in a region defined by the active layer 130 on a plane. Specifically, the active hole 135 may be a region formed by removing a portion of the active layer 130.

[0094] Reference Figure 1 and Figure 3 According to an embodiment of the present disclosure, since the active hole 135 may be referred to as a hole formed in the active layer 130 by removing a portion of the active layer 130 , the hole is referred to as an “active hole”.

[0095] Specifically, according to an embodiment of the present disclosure, the active hole 135 may protrude in a direction from the gate electrode 150 toward the drain region 130 b in a plan view.

[0096] More specifically, the active layer 130 may not be disposed in some regions of the drain region 130 b .

[0097] exist Figure 1 and Figure 3 , a configuration in which the active hole 135 protrudes from the gate electrode 150 in the direction of the drain region 130 b is illustrated in a plan view.

[0098] According to an embodiment of the present disclosure, a portion of the active hole 135 may overlap with the gate electrode 150 . Figure 1 and Figure 3 A configuration in which a portion of the active hole 135 overlaps with the gate electrode 150 is illustrated.

[0099] More specifically, the active layer 130 may not be disposed in some regions of the channel region 130 n .

[0100] According to an embodiment of the present disclosure, the active hole 135 may be formed by patterning the active layer 130. Specifically, the active hole 135 may be a region whose periphery is surrounded by the active layer 130. For example, the active hole 135 may be a portion from which the active layer 130 is partially patterned and removed.

[0101] Generally, when the channel region 130n of the active layer 130 has a large channel width, conductive diffusion may be performed largely in a boundary region between the channel region 130n and the drain region 130b. When conductive diffusion is performed, the threshold voltage (Vth) of the thin film transistor may move in a negative (-) direction, and thus the driving stability of the thin film transistor may be deteriorated.

[0102] When the channel region 130n of the active layer 130 has a small channel width, the conductive diffusion may be reduced at the boundary region between the channel region 130n, the source region 130a, and the drain region 130b. On the contrary, when the channel region 130n of the active layer 130 has a small channel width, the total amount of carriers passing through the channel region 130n of the thin film transistor may be reduced, and the on-current characteristics may be degraded. As a result, when a large amount of current flows through the thin film transistor having a small channel width in the channel region 130n, the thin film transistor may be damaged, and thus the driving stability may be degraded. Therefore, when the active layer 130 has a large channel width, there is a need to control the conductive diffusion.

[0103] According to an embodiment of the present disclosure, when the active hole 135 is formed to overlap the gate electrode 150, the boundary portion of the channel region 130n and the drain region 130b of the active layer 130 is patterned so that conduction is performed in a region other than the active hole in the channel region 130n of the active layer 130. As a result, even when the channel region 130n of the active layer 130 has a large channel width, the width of the region where conduction is performed is narrowed, so that conduction penetration into the channel region 130n can be prevented or controlled, and penetration of light or hydrogen into the channel region 130n of the active layer 130 can be suppressed or prevented.

[0104] According to an embodiment of the present disclosure, the active hole 135 may have a plurality of sub-active holes. Figure 1 The configuration in which the active hole 135 has a plurality of sub-active holes is illustrated. When the active hole 135 has a plurality of sub-active holes, each sub-active hole overlaps at least a portion of the gate electrode 150. In addition, when the active hole 135 has a plurality of sub-active holes, each sub-active hole is spaced apart from each other. However, the embodiments of the present disclosure are not limited thereto, and the active hole 135 may have a single sub-active hole.

[0105] According to an embodiment of the present disclosure, the active hole 135 may have a rectangular shape. However, the embodiment of the present disclosure is not limited thereto, and the active hole 135 according to an embodiment of the present disclosure may have various shapes.

[0106] According to an embodiment of the present disclosure, the thin film transistor substrate 100 may include conductive material layers 165 and 175 on the active layer 130 .

[0107] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , the conductive material layers 165 and 175 may include a first conductive material layer 165 on the source region 130 a and a second conductive material layer 175 on the drain region 130 b .

[0108] More specifically, refer to Figure 1 , Figure 2 and Figure 3 , the first conductive material layer 165 and the second conductive material layer 175 are disposed to be spaced apart from each other with a portion of the channel region 130n interposed therebetween.

[0109] Reference Figure 1 , Figure 2 and Figure 3 The source region 130 a and the drain region 130 b may be disposed between the base substrate 110 and the first conductive material layer 165 and between the base substrate 110 and the second conductive material layer 175 , respectively.

[0110] More specifically, refer to Figure 1 , Figure 2 and Figure 3 , the first conductive material layer 165 and the second conductive material layer 175 may contact the active layer 130 through the source region 130 a and the drain region 130 b , respectively.

[0111] According to an embodiment of the present disclosure, the first conductive material layer 165 may overlap at least a portion of the channel region 130n. Figure 1 , Figure 2 and Figure 3 , a configuration in which the first conductive material layer 165 overlaps the channel region 130 n is illustrated. More specifically, the first conductive material layer 165 may overlap at least a portion of the gate electrode 150 .

[0112] According to an embodiment of the present disclosure, when the first conductive material layer 165 overlaps the channel region 130n, the first conductive material layer 165 can protect the boundary region between the source region 130a and the channel region 130n from external light or hydrogen. Therefore, the channel region 130n of the active layer 130 can be protected from external light or hydrogen.

[0113] According to an embodiment of the present disclosure, the second conductive material layer 175 may not be disposed on the active hole 135. Figure 1 and Figure 3 2 shows a configuration in which the second conductive material layer 175 is not disposed on the active hole 135 .

[0114] According to an embodiment of the present disclosure, the active hole 135 may be disposed to be spaced apart from the first conductive material layer 165. Specifically, the active hole 135 may not overlap with at least a portion of the gate electrode 150. Figure 1 A configuration in which the active hole 135 is disposed to be spaced apart from the first conductive material layer 165 in a plan view is illustrated.

[0115] According to an embodiment of the present disclosure, the first conductive material layer 165 overlaps the channel region 130 n , and the second conductive material layer 175 may be disposed to be spaced apart from the channel region 130 n .

[0116] Specifically, in the case of the source region 130a of the active layer 130, the first conductive material layer 165 may overlap with the channel region 130n to protect the channel region 130n from external light or hydrogen, and in the case of the drain region 130b of the active layer 130, the active hole 135 may overlap with the gate electrode 150 to protect the channel region 130n from external light or hydrogen.

[0117] According to one embodiment of the present disclosure, the conductive material layers 165 and 175 may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO). The conductive material layers 165 and 175 may have reductive properties. According to one embodiment of the present disclosure, the transparent conductive oxide (TCO) may include ITO (InSnO), IZO (InZnO), IO (InO), TO (SnO), and ZO (ZnO).

[0118] The active layer 130 may be selectively conductive through the conductive material layers 165 and 175. According to an embodiment of the present disclosure, the source region 130a and the drain region 130b are respectively in contact with the first conductive material layer 165 and the second conductive material layer 175. The regions of the active layer 130 in contact with the first conductive material layer 165 and the second conductive material layer 175 are conductive to form the source region 130a and the drain region 130b, respectively.

[0119] Specifically, according to an embodiment of the present disclosure, portions of the active layer 130 contacting the conductive material layers 165 and 175 may be reduced to form the source region 130 a and the drain region 130 b , respectively.

[0120] For example, when a portion of the active layer 130 that contacts and overlaps the conductive material layers 165 and 175 is reduced, oxygen vacancies occur in the active layer 130, and thus the active layer 130 may be selectively conductive. By selective reduction of the active layer 130, a source region 130a and a drain region 130b may be formed.

[0121] According to an embodiment of the present disclosure, the active layer 130 may be selectively conductive by the conductive material layers 165 and 175 without a separate conductive treatment such as plasma treatment, ion doping, or ultraviolet treatment.

[0122] Reference Figure 1 , when the shortest distance from the drain region 130b to the first conductive material layer 165 is defined as a first length L1 and the shortest length of the region where the first conductive material layer 165 overlaps the gate electrode 150 in the channel length direction of the active layer 130 is defined as a second length L2, the first length L1 may be longer than the second length L2. Therefore, light and hydrogen incident from the outside of the source region 130a of the active layer 130 may be effectively blocked, and as a result, the reliability of the thin film transistor may be improved.

[0123] On the other hand, when the second length L2 is longer than the first length L1, the first conductive material layer 165 may excessively overlap the gate electrode 150, so that the channel region 130n of the active layer 130 may become excessively conductive. Therefore, the threshold voltage Vth of the thin film transistor may move in a negative (-) direction, and thus the driving stability of the thin film transistor may be deteriorated.

[0124] Reference Figure 1 , if the shortest length of the region where the active hole 135 overlaps the gate electrode 150 in the channel length direction of the active layer 130 is defined as the third length L3, and the shortest distance from the active hole 135 to the first conductive material layer 165 in the channel length direction of the active layer 130 is defined as the fourth length L4, the fourth length L4 may be longer than the third length L3. Therefore, light and hydrogen incident from the outside of the drain region 130b of the active layer 130 may be effectively blocked, and as a result, the reliability of the thin film transistor may be improved.

[0125] On the contrary, when the third length L3 is longer than the fourth length L4, the active hole 135 may excessively penetrate into the channel region 130n, and thus the total amount of carriers passing through the channel region 130n of the thin film transistor may decrease, and the on-current characteristic may be deteriorated. As a result, when a large amount of current flows through the thin film transistor, the thin film transistor may be damaged, and thus the driving stability may be deteriorated.

[0126] According to an embodiment of the present disclosure, the thin film transistor substrate 100 may further include a source electrode 160 and a drain electrode 170 .

[0127] The source electrode 160 and the drain electrode 170 may be disposed on the gate insulating layer 140, and may be disposed on the same layer as the gate electrode 150. The source electrode 160 and the drain electrode 170 may be made of the same material as the gate electrode 150 through the same process.

[0128] Each of the source electrode 160, the drain electrode 170, and the gate electrode 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The source electrode 160, the drain electrode 170, and the gate electrode 150 may have a multilayer structure including at least two conductive films having different physical properties.

[0129] Reference Figure 2 and Figure 3, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 through the contact holes, respectively. Specifically, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 by contacting the first conductive material layer 165 and the second conductive material layer 175, respectively.

[0130] Reference Figure 1 , Figure 2 and Figure 3 , the light blocking layer 111 may be disposed on the base substrate 110. Specifically, the light blocking layer 111 may be disposed between the base substrate 110 and the active layer 130. The light blocking layer 111 overlaps the channel region 130n. The light blocking layer 111 blocks light incident from the outside, thereby protecting the channel region 130n.

[0131] The light blocking layer 111 may be formed of a material having a light blocking property. The light blocking layer 111 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to an embodiment of the present disclosure, the light blocking layer 111 may have electrical conductivity.

[0132] The light blocking layer 111 may be omitted. Figure 1 , Figure 2 and Figure 3 , but a buffer layer may be additionally disposed between the base substrate 110 and the light blocking layer 111. Although not shown, the light blocking layer 111 may be electrically connected to any one of the source electrode 160 and the drain electrode 170. In addition, the light blocking layer 111 may be electrically connected to the gate electrode 150.

[0133] According to an embodiment of the present disclosure, the light blocking layer 111 may be disposed to overlap the front surface of the active layer 130. However, the embodiment of the present disclosure is not limited thereto, and the light blocking layer 111 may be disposed not to overlap some regions of the active layer 130 except the channel region 130n.

[0134] Figure 4 is a plan view of a thin film transistor substrate 200 according to another embodiment of the present disclosure. Figure 5 It is along Figure 4 A cross-sectional view taken along line II'. Figure 6 It is along Figure 4 A cross-sectional view taken along line II-II'.

[0135] According to an embodiment of the present disclosure, the thin film transistor substrate 200 may further include a gate insulating layer 140 between the active layer 130 and the gate electrode 150. The source region 130a and the drain region 130b of the active layer 130 may be exposed from the gate insulating layer 140. Figure 5 and Figure 6 A configuration in which the source region 130 a and the drain region 130 b of the active layer 130 are exposed from the gate insulating layer 140 is illustrated.

[0136] However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layer 140 may cover the entire upper surface of the active layer 130 . Figure 2 and Figure 3 A configuration in which the gate insulating layer 140 covers the entire upper surface of the active layer 130 is shown.

[0137] The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure. The gate insulating layer 140 protects the channel region 130n.

[0138] Figure 7 is a cross-sectional view of a thin film transistor substrate 300 according to another embodiment of the present disclosure, and Figure 8 is a cross-sectional view of a thin film transistor substrate 400 according to another embodiment of the present disclosure.

[0139] According to an embodiment of the present disclosure, the active layer 130 of the thin film transistor substrates 300 and 400 may have a multi-layer structure. For example, the active layer 130 may include a first active layer 131 and a second active layer 132 .

[0140] Specifically, refer to Figure 7 , the active layer 130 may include a first active layer 131 and a second active layer 132 on the first active layer 131 .

[0141] The first active layer 131 and the second active layer 132 may include the same semiconductor material, or may include different semiconductor materials.

[0142] The first active layer 131 supports the second active layer 132. Therefore, the first active layer 131 is also referred to as a “support layer.” The active layer 130 has a structure consisting of the first active layer 131 and the second active layer 132, and is also referred to as a double-layer structure.

[0143] According to an embodiment of the present disclosure, the active layer 130 may further include a third active layer 133 on the second active layer 132 .

[0144] and Figure 7 Compared with the thin film transistor substrate 300, Figure 8 The thin film transistor substrate 400 further includes a third active layer 133 on the second active layer 132. However, the embodiments of the present disclosure are not limited thereto, and the active layer 130 may further include another semiconductor layer.

[0145] Fig. 9 Schematic diagram of a capacitor for explaining the present disclosure. Fig.10 is a cross-sectional view of a thin film transistor substrate according to an embodiment for explaining a capacitor of the present disclosure. Fig.11 is a cross-sectional view of a thin film transistor substrate according to a comparative example for explaining the capacitor of the present disclosure.

[0146] Specifically, Fig. 9 yes Fig.13 1 is a circuit diagram of any pixel P of the display device 1000 , and more specifically, is an equivalent circuit diagram of a pixel P of the display device 1000 including an organic light emitting diode OLED as a display element 710 .

[0147] Reference Fig. 9 The pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710 . Fig. 9 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor.

[0148] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

[0149] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0150] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display element 710 .

[0151] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the first storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0152] Fig. 9 A capacitor that may be generated when a gate voltage VGS is applied to a thin film transistor according to an embodiment of the present disclosure is schematically illustrated.

[0153] like Fig. 9 and Fig.10As shown, when a gate voltage VGS is applied to the thin film transistor, a first parasitic capacitor Cp1 is formed between the source region 130 a of the active layer 130 and the gate electrode 150 , and a second parasitic capacitor Cp2 is formed between the drain region 130 b of the active layer 130 and the gate electrode 150 .

[0154] Fig.10 A configuration is illustrated in which the first conductive material layer 165 on the source region 130 a is spaced apart and overlaps the gate electrode 150 to form the first parasitic capacitor Cp1 and the second conductive material layer 175 is spaced apart from the gate electrode 150 to form the second parasitic capacitor Cp2 .

[0155] on the other hand, Fig.11 A configuration is illustrated in which the first conductive material layer 165 on the source region 130 a forms the first parasitic capacitor Cp1 without overlapping the gate electrode 150 , and the second conductive material layer 175 is spaced apart from the gate electrode 150 to form the second parasitic capacitor Cp2 .

[0156] and Fig.11 Compared with the thin film transistor substrate, since the first conductive material layer 165 on the source region 130a overlaps with the gate electrode 150 Fig.10 The first parasitic capacitor Cp1 is formed in the thin film transistor substrate, so the Fig.10 The first parasitic capacitor Cp1 on the thin film transistor substrate may be larger than the first parasitic capacitor Cp2 formed on the thin film transistor substrate. Fig.11 A first parasitic capacitor Cp1 is formed on the thin film transistor substrate.

[0157] In addition, Fig.11 Compared with the thin film transistor substrate in Fig.10 The second parasitic capacitor Cp2 formed on the thin film transistor substrate in the embodiment can be minimized or reduced and can be smaller than that in the embodiment of the present invention. Fig.11 The second parasitic capacitor Cp2 is formed on the thin film transistor substrate in FIG. 1 because the thin film transistor substrate includes the active hole 135 protruding from the gate electrode 150 to the drain region 130 b and overlapping the gate electrode 150 in a plane.

[0158] According to an embodiment of the present disclosure, Fig.10In the thin film transistor substrate of the present invention, the first parasitic capacitor Cp1 is formed by overlapping the gate electrode 150 with the first conductive material layer 165 on the source region 130a, and the thin film transistor substrate includes an active hole 135 protruding from the gate electrode 150 in the direction of the drain region 130b in a plan view and overlapping the gate electrode 150, so that the first parasitic capacitor Cp1 is maximized or increased and the second parasitic capacitor Cp2 is minimized or reduced. That is, the first parasitic capacitor Cp1 can be larger than the second parasitic capacitor Cp2. Therefore, the first parasitic capacitor Cp1 can be used as the second storage capacitor C2.

[0159] Results, refer to Fig.10 , Fig. 12A and Fig. 12B , when the second storage capacitor C2 is additionally formed on the thin film transistor substrate due to the first parasitic capacitor Cp1, the second storage capacitor C2 may be formed in parallel with the first storage capacitor C1, thereby easily securing a capacitor area and improving space efficiency.

[0160] On the other hand, referring to Fig.11 , in the thin film transistor substrate according to the comparative example, since the first conductive material layer 165 does not overlap the gate electrode 150 , the first parasitic capacitor Cp1 is not sufficiently secured, and thus the capacitor region may not be easily secured.

[0161] In addition, since the thin film transistor substrate according to the comparative example does not include the active hole 135 in the drain region 130b, the second parasitic capacitor Cp2 is not minimized or reduced. Therefore, RC delay caused by the second parasitic capacitor Cp2 may occur, and thus voltage charging becomes difficult. In addition, the second parasitic capacitor Cp2 causes an increase in heat generation and current consumption of the transistor.

[0162] According to an embodiment of the present disclosure, the thin film transistor substrate may include a third storage capacitor. Fig.11 Compared with the thin film transistor substrate, Fig.10 The thin film transistor substrate includes an active hole 135 protruding from the gate electrode 150 in the direction of the drain region 130b in a plan view and overlapping the gate electrode 150, so the gate electrode 150 and the light blocking layer 111 may include a third storage capacitor C3 formed to be spaced apart from and overlap each other.

[0163] According to an embodiment of the present disclosure, the third storage capacitor C3 is formed in a region where the gate electrode 150 and the light blocking layer 111 overlap the active hole 135 .

[0164] Results, refer to Fig.10 , Fig. 12A and Fig. 12B, when the third storage capacitor C3 is additionally formed on the thin film transistor substrate according to the embodiment of the present disclosure, the third storage capacitor C3 may be formed in parallel with the first storage capacitor C1 and the second storage capacitor C2, thereby easily securing a capacitor area and improving space efficiency.

[0165] On the other hand, referring to Fig.11 , since the thin film transistor substrate according to the comparative example does not include the active hole 135, the third storage capacitor C3 may not be ensured, and thus the capacitor area may not be easily ensured.

[0166] Fig. 12A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. Fig. 12B It is along Fig. 12A A cross-sectional view taken along line II'.

[0167] According to an embodiment of the present disclosure, the thin film transistor substrate 500 includes a storage capacitor Cst. Specifically, the storage capacitor Cst may be disposed in an overlapped region between the light blocking layer 111 and the thin film transistor TFT.

[0168] According to an embodiment of the present disclosure, the storage capacitor Cst may include a first storage capacitor C1, and the first storage capacitor C1 may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap each other to form a first capacitor C11.

[0169] According to an embodiment of the present disclosure, the first capacitor electrode CE1 may be connected to the light blocking layer 111 . Fig. 12B A configuration in which the first capacitor electrode CE1 is connected to the light blocking layer 111 is shown.

[0170] According to an embodiment of the present disclosure, the second capacitor electrode CE2 may be connected to the active layer 130. Specifically, the second capacitor electrode CE2 may be connected to one of the source region 130a and the drain region 130b. Fig. 12A , the second capacitor electrode CE2 may be connected to the source region 130a.

[0171] According to another embodiment of the present disclosure, the second capacitor electrode CE2 may include a first layer CE21 and a second layer CE22 on the first layer CE21. The second capacitor electrode CE2 may include: the first layer CE21, which is integrally formed with any one of the source region 130a and the drain region 130b; and the second layer CE22, which is integrally formed with any one of the first conductive material layer 165 and the second conductive material layer 175.

[0172] exist Fig. 12A, a configuration in which the second capacitor electrode CE2 includes a first layer CE21 integrally formed with the source region 130 a and a second layer CE22 integrally formed with the first conductive material layer 165 is illustrated.

[0173] According to an embodiment of the present disclosure, since the second capacitor electrode CE2 may be formed of the active layer 130 and the conductive material layers 165 and 175 , a separate process for forming the second capacitor electrode CE2 is not required, and as a result, space efficiency is improved and the area of ​​the second capacitor electrode CE2 may be increased.

[0174] Reference Fig. 12A and Fig. 12B The thin film transistor substrate 500 according to the embodiment of the present disclosure may further include a third capacitor electrode CE3 connected to the gate electrode 150. The third capacitor electrode CE3 may be made of the same material and the same process as the gate electrode 150, the source electrode 160, and the drain electrode 170.

[0175] According to an embodiment of the present disclosure, the second capacitor electrode CE2 and the third capacitor electrode CE3 may overlap each other to form a second capacitor C12.

[0176] Since the gate electrode 150 and the third capacitor electrode CE3 are connected to each other, the first capacitor electrode CE1 and the third capacitor electrode CE3 may be connected to each other, and the same voltage may be applied to the first capacitor electrode CE1 and the third capacitor electrode CE3.

[0177] Reference Fig. 12A and Fig. 12B , the second capacitor electrode CE2 is disposed between the first capacitor electrode CE1 and the third capacitor electrode CE3. As a result, it is possible to have the same effect as forming two capacitors C11 and C12 with the second capacitor electrode CE2 interposed therebetween.

[0178] Fig.13 is a schematic diagram illustrating a display device 1000 according to still another embodiment of the present disclosure.

[0179] like Fig.13 As shown, a display device 1000 according to still another embodiment of the present disclosure may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0180] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on the base substrate 110 .

[0181] The controller 340 controls the gate driver 320 and the data driver 330 .

[0182] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal provided from an external system not shown. In addition, the controller 340 samples input image data input from the external system, realigns the sampled data, and provides the realigned digital image data RGB to the data driver 330.

[0183] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0184] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0185] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0186] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 will be referred to as a gate-in-panel (GIP) structure. In detail, in the gate-in-panel (GIP) structure, the gate driver 320 may be provided on the base substrate 110.

[0187] The display device 1500 according to one embodiment of the present disclosure may include the above-mentioned thin film transistor substrates 100, 200, 300, 400 and 500. According to one embodiment of the present disclosure, the gate driver 320 may include the above-mentioned thin film transistor substrates 100, 200, 300, 400 and 500.

[0188] The gate driver 320 may include a shift register 350 .

[0189] The shift register 350 sequentially supplies a gate pulse to the gate line GL within one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame means a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0190] In addition, the shift register 350 provides a gate-off signal capable of turning off the switching device to the gate line GL in other periods of a frame when no gate pulse is provided. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0191] The shift register 350 may include the above-described thin film transistor substrates 100 , 200 , 300 , 400 , and 500 .

[0192] Fig.14 is a schematic diagram illustrating an example shift register 350 .

[0193] Reference Fig.14 , the shift register 350 may include g stages 351 (ST1 to STg).

[0194] The shift register 350 transmits one scan signal SS to the pixel P connected to one gate line GL through one gate line GL. Each stage 351 may be connected to one gate line GL. When g gate lines GL are formed in the display panel 310, the shift register 350 may include g stages 351 (ST1 to STg) and may generate g scan signals SS1 to SSg.

[0195] Generally, each stage 351 outputs the gate pulse GP once during one frame, and the gate pulse GP is sequentially output from each stage 351 .

[0196] Fig.15 is an example Fig.13 Circuit diagram of any pixel P.

[0197] Fig.15 The circuit diagram of FIG. 1 is an equivalent circuit diagram of a pixel P of the display device 1000 including an organic light emitting diode (OLED) as a display element 710 .

[0198] Reference Fig.15 , the pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. In detail, the display device 1000 according to one embodiment of the present disclosure may include a pixel driving circuit PDC on a base substrate 110.

[0199] Fig.15 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. A display device 1500 according to another embodiment of the present disclosure may include at least one of the above-described thin film transistor substrates 100, 200, 300, 400, and 500.

[0200] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

[0201] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0202] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0203] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0204] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of light output from the display element 710 may be controlled.

[0205] Fig.16 yes Fig.15 The pixel plane diagram, and Fig.17 It is along Fig.16 A cross-sectional view taken along line III-III'.

[0206] Reference Fig.15 and Fig.16 , the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the base substrate 110 . The first thin film transistor TR1 and the second thin film transistor TR2 include conductive material layers 165 and 175 .

[0207] The base substrate 110 may be made of glass or plastic. As the base substrate 110, plastic having a flexible property, for example, polyimide (PI) may be used.

[0208] The light blocking layer 111 is disposed on the base substrate 110. The light blocking layer 111 may have a light blocking property. The light blocking layer 111 may block light incident from the outside to protect the active layers A1 and A2.

[0209] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

[0210] The first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120 .

[0211] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0212] In the first thin film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 overlaps the gate electrode G1. According to another embodiment of the present disclosure, the source region may be referred to as a source electrode S1, and the drain region may be referred to as a drain electrode D1.

[0213] In the second thin film transistor TR2, the second active layer A2 may include a channel region, a source region and a drain region. The channel region of the second active layer A2 overlaps the gate electrode G2. According to another embodiment of the present disclosure, the source region may be referred to as a source electrode S2, and the drain region may be referred to as a drain electrode D2.

[0214] In the first thin film transistor TR1, the first conductive material layer 165 is disposed on the source region of the first active layer A1 and overlaps the gate electrode G1. In the second thin film transistor TR2, the first conductive material layer 165 is disposed on the source region of the second active layer A2 and overlaps the gate electrode G2.

[0215] Reference Fig.16 and Fig.17 , a portion of the light blocking layer 111 may become a first capacitor electrode CE1 of the first capacitor C11.

[0216] In addition, a portion of the second active layer A2 may be the second capacitor electrode CE2 of the first capacitor C11. Alternatively, it may be the second capacitor electrode CE2 of the second capacitor C12.

[0217] The gate insulating layer 140 is disposed on the first and second active layers A1 and A2. The gate insulating layer 140 may cover the entire upper surfaces of the first and second active layers A1 and A2, or may cover only a portion of the first and second active layers A1 and A2.

[0218] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0219] The gate electrode G1 of the first thin film transistor TR1 overlaps at least a portion of the first active layer A1 of the first thin film transistor TR1. The gate electrode G2 of the second thin film transistor TR2 overlaps at least a portion of the second active layer A2 of the second thin film transistor TR2.

[0220] The source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 are disposed on the gate insulating layer 140. In addition, the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140.

[0221] The source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 are disposed on the same layer as the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2. Specifically, the gate electrode G1, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 and the gate electrode G2, the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the same layer.

[0222] An interlayer insulating layer 180 is disposed on the gate electrodes G1 and G2 , the source electrodes S1 and S2 , and the drain electrodes D1 and D2 .

[0223] The data lines DL and the driving power lines PL are disposed on the interlayer insulating layer 180 .

[0224] The data line DL contacts the first source electrode S1 formed in the first active layer A1 through the first contact hole H1. According to another embodiment of the present disclosure, a portion of the data line DL overlapping the first active layer A1 may be referred to as a first source electrode S1.

[0225] The driving power line PL contacts the second drain electrode D2 formed in the second active layer A2 through the eleventh contact hole H11. According to another embodiment of the present disclosure, a portion of the driving power line PL overlapping the second active layer A2 may be referred to as a second drain electrode D2.

[0226] Reference Fig.16 and Fig.17 , a portion of the gate electrode G2 of the second thin film transistor TR2 may be the third capacitor electrode CE3 of the second capacitor C12.

[0227] Reference Fig.16 and Fig.17 The first capacitor electrode CE1 overlaps with the second capacitor electrode CE2 to form a first capacitor C11. The second capacitor electrode CE2 overlaps with the third capacitor electrode CE3 to form a second capacitor C12.

[0228] Reference Fig.16 and Fig.17, the first bridge BR1 is disposed on the interlayer insulating layer 180. The first bridge BR1 is connected to the first drain electrode D1 through the fourth contact hole H4, and is connected to the third capacitor electrode CE3 of the second capacitor C12 through the fifth contact hole H5.

[0229] Reference Fig.16 and Fig.17 , the third capacitor electrode CE3 is connected to the light blocking layer 111 through the sixth contact hole H6.

[0230] The planarization layer 190 is disposed on the data line DL, the first bridge BR1, and the driving power line PL. The planarization layer 190 planarizes upper portions of the first and second thin film transistors TR1 and TR2, and protects the first and second thin film transistors TR1 and TR2.

[0231] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second source electrode S2 of the second thin film transistor TR2 through the ninth contact hole H9 formed in the planarization layer 190 and the eighth contact hole H8 formed in the interlayer insulating layer 180. As a result, the first electrode 711 can be connected to the second source electrode S2 of the second thin film transistor TR2. In addition, it is connected to the second active layer A2 through the seventh contact hole H7 formed in the gate insulating layer 140.

[0232] The bank layer 750 is disposed at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0233] The organic light emitting layer 712 is provided on the first electrode 711, and the second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Fig.17 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 1000 according to the embodiment of the present disclosure is an organic light emitting display device.

[0234] Fig.18 is a circuit diagram of any one pixel of the display device 1100 according to another embodiment of the present disclosure.

[0235] Fig.18 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0236] Fig.18 The pixel P of the illustrated display device 1100 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0237] Signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are arranged in the pixel P.

[0238] A data voltage Vdata is supplied to the data line DL, a scan signal SS is supplied to the gate line GL, a driving voltage Vdd for driving pixels is supplied to the driving power line PL, a reference voltage Vref is supplied to the reference line RL, and a sensing control signal SCS is supplied to the sensing control line SCL.

[0239] The pixel driving circuit PDC includes, for example, a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of a current output to the display element 710 according to a data voltage Vdata sent through the first thin film transistor TR1, and a third thin film transistor TR3 (sensing transistor) for sensing characteristics of the second thin film transistor TR2.

[0240] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0241] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and the reference line RL, is turned on or off by the sensing control signal SCS, and detects characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0242] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The storage capacitor Cst is formed between the second node n2 and the first node n1.

[0243] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0244] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin film transistor TR2 according to a driving voltage Vdd driving the pixel, and light is output from the display element 710 .

[0245] A display device 1100 according to another embodiment of the present disclosure may include at least one of the thin film transistor substrates 100 , 200 , 300 , 400 , and 500 .

[0246] Fig.19is a circuit diagram of any one pixel P of the display device 1200 according to another embodiment of the present disclosure.

[0247] Fig.19 The pixel P of the illustrated display device 1200 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0248] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0249] Signal lines DL, EL, GL, PL, SCL, and RL that supply driving signals to the pixel driving circuit PDC are arranged in the pixel P.

[0250] and Fig.18 Compared with the pixel P, Fig.19 The pixel P further includes a light emitting control line EL. A light emitting control signal EM is provided to the light emitting control line EL. Fig.18 Compared with the pixel driving circuit PDC, Fig.19 The pixel driving circuit PDC further includes a fourth thin film transistor TR4 which is a light emission control transistor for controlling a light emission time point of the second thin film transistor TR2.

[0251] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0252] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0253] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0254] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the light emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 to output light from the display element 710 .

[0255] The pixel driving circuit PDC according to another exemplary configuration of the present disclosure may be formed in various structures different from the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0256] According to the present disclosure, the following advantageous effects can be obtained.

[0257] The thin film transistor substrate according to an embodiment of the present disclosure may include an active hole to prevent or inhibit hydrogen and light from being exposed to a channel.

[0258] The thin film transistor substrate according to an embodiment of the present disclosure may include an active hole to prevent or suppress a threshold voltage Vth from shifting in a negative (−) direction.

[0259] The thin film transistor substrate according to an embodiment of the present disclosure may include a conductive material layer overlapping a channel region to prevent or inhibit hydrogen and light from being exposed to the channel.

[0260] The thin film transistor substrate according to an embodiment of the present disclosure includes an active hole and includes a conductive material layer overlapping a channel region, thereby having stability and excellent reliability.

[0261] The thin film transistor substrate according to an embodiment of the present disclosure includes an active hole and includes a conductive material layer overlapping a channel region, thereby ensuring optimization of a capacitor area.

[0262] It will be apparent to those skilled in the art that the disclosure described above is not limited to the above-mentioned embodiments and drawings, and that various substitutions, modifications and variations may be made in the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

[0263] CROSS-REFERENCE TO RELATED APPLICATIONS

[0264] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0101894, filed on August 4, 2023, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A thin film transistor substrate, comprising: substrate; a thin film transistor, the thin film transistor being on the substrate, Wherein, the thin film transistor comprises: Active layer; a conductive material layer on the active layer; and a gate electrode spaced apart from the active layer and partially overlapping the active layer, Wherein, the active layer comprises: a channel region partially overlapping the gate electrode in a plan view; A source region connected to one side of the channel region in the plan view; and a drain region connected to the other side of the channel region in the plan view, Wherein, the conductive material layer comprises: a first conductive material layer on the source region; and a second conductive material layer on the drain region, wherein the first conductive material layer overlaps at least a portion of the channel region, wherein the active layer comprises an active hole in which the active layer is not within a region defined by the active layer, and Wherein, in the plan view, the active hole extends from the channel region to the drain region.

2. The thin film transistor substrate according to claim 1, wherein: A portion of the active hole overlaps the gate electrode in the plan view.

3. The thin film transistor substrate according to claim 1, wherein: The active hole is spaced apart from the first conductive material layer in the plan view.

4. The thin film transistor substrate according to claim 1, wherein: The second conductive material layer is spaced apart from the channel region in the plan view.

5. The thin film transistor substrate according to claim 1, wherein: The source region and the drain region are respectively between the substrate and the first conductive material layer and between the substrate and the second conductive material layer, and Wherein, the first conductive material layer and the second conductive material layer are in contact with the active layer respectively.

6. The thin film transistor substrate according to claim 1, further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other and contacting the source region and the drain region, respectively, and in, The gate electrode, the source electrode, and the drain electrode are on the same layer.

7. The thin film transistor substrate according to claim 1, wherein: The active hole has a plurality of sub-active holes, wherein the plurality of sub-active holes are spaced apart from each other, and Each of the plurality of sub-active holes has an elongated shape extending from the channel region to the drain region.

8. The thin film transistor substrate according to claim 1, wherein: The conductive material layer includes at least one selected from titanium Ti, molybdenum Mo, aluminum Al, silver Ag, copper Cu, chromium Cr, tantalum Ta, neodymium Nd, calcium Ca, barium Ba and transparent conductive oxide TCO.

9. The thin film transistor substrate according to claim 1, wherein: The shortest distance from the drain region to the first conductive material layer is a first length, Wherein, in the plan view, in the channel length direction of the active layer, the shortest length of the overlap between the first conductive material layer and the gate electrode is the second length, and Wherein, the first length is longer than the second length.

10. The thin film transistor substrate according to claim 1, wherein: A portion of the active hole overlaps with the gate electrode, Wherein, in the channel length direction of the active layer, the shortest overlapping length of the active hole and the gate electrode is a third length, wherein the shortest distance from the active hole to the first conductive material layer in the channel length direction of the active layer is a fourth length, and Wherein, the fourth length is longer than the third length.

11. The thin film transistor substrate according to claim 1, further comprising: a light blocking layer on the substrate; as well as A storage capacitor is provided in an overlapping region between the light blocking layer and the thin film transistor.

12. The thin film transistor substrate according to claim 11, wherein: The storage capacitor comprises a first storage capacitor, the first storage capacitor comprising: a first capacitor electrode connected to the light blocking layer; and a second capacitor electrode connected to the active layer, and The first capacitor electrode and the second capacitor electrode are spaced apart from each other and overlap each other to form a first capacitor.

13. The thin film transistor substrate according to claim 12, wherein: The first storage capacitor includes a third capacitor electrode connected to the gate electrode, and The second capacitor electrode and the third capacitor electrode are spaced apart from each other and overlap each other to form a second capacitor.

14. The thin film transistor substrate according to claim 12, wherein: The second capacitor electrode comprises: a first layer integrated with any one of the source region and the drain region; and A second layer is integrated with any one of the first conductive material layer and the second conductive material layer.

15. The thin film transistor substrate according to claim 13, wherein: The second capacitor electrode is between the first capacitor electrode and the third capacitor electrode, and Wherein, the third capacitor electrode is connected to the first capacitor electrode.

16. The thin film transistor substrate according to claim 11, wherein: The storage capacitor includes a second storage capacitor formed by separating and overlapping the gate electrode and the first conductive material layer.

17. The thin film transistor substrate according to claim 11, wherein: The storage capacitor includes a third storage capacitor formed by separating and overlapping the gate electrode and the light blocking layer from each other.

18. The thin film transistor substrate according to claim 17, wherein: The third storage capacitor is in a region overlapping the active hole.

19. The thin film transistor substrate according to claim 1, wherein: The active layer includes an oxide semiconductor material, and Among them, the oxide semiconductor material includes at least one of IZO (InZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, ITO (InSnO) based oxide semiconductor material, IGZO (InGaZnO) based oxide semiconductor material, IGZTO (InGaZnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material and FIZO (FeInZnO) based oxide semiconductor material. 20 . A display device comprising the thin film transistor substrate according to claim 1 .

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