Display panel and display device including the same

Abstract

The invention discloses a display panel and a display device comprising the same. The display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display layer including a display element in the second area; a first metal layer in the third region; an organic insulating layer on the first metal layer and including at least one contact portion; and a second metal layer on the organic insulating layer and contacting the first metal layer through at least one contact portion, in which the second metal layer has a first hole, and the organic insulating layer has a second hole or a first recess corresponding to the first hole, and a residual layer in the second hole or the first recess and including a portion of the at least one organic layer overlaps the first metal layer.

Description

[0001] This application is a divisional application of the patent application with application number 202010196170.7 filed on March 19, 2020 and titled “Display panel and display device including the display panel”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2019-0031469 filed in the Korean Intellectual Property Office on March 19, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates to a display panel, and more particularly, to a display panel including an area in which a component is located inside a display area, and a display device including the display panel. Background Art

[0005] Recently, display devices have been used in various ways. Also, as the thickness and weight of display devices decrease, the use of display devices is extended to a wide range of electronic products. At the same time, the resolution of display devices has been improved, and the size of the display area in the display devices has also been increased.

[0006] As the size of a display area in a display device increases, various functions linked to or associated with the display device may be added. As the size of the display area increases, research has been conducted on display devices that arrange various elements in the display area to add various functions. Summary of the invention

[0007] Exemplary embodiments of the present disclosure include a display panel having a first area in which various elements are located in a display area, and a display device including the display panel.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented exemplary embodiments.

[0009] According to an exemplary embodiment of the present disclosure, a display panel includes: a substrate including a first area, a second area, and a third area located between the first area and the second area; a display layer including a pixel circuit located in the second area and a display element electrically connected to the pixel circuit, the display element including a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode and including an emission layer and at least one organic layer; a first metal layer located in the third area; an organic insulating layer located on the first metal layer and including at least one contact portion; and a second metal layer located on the organic insulating layer and contacting the first metal layer through at least one contact portion, wherein the second metal layer has a first hole, and the organic insulating layer has a second hole or a first recess corresponding to the first hole, and a residual layer located in the second hole or the first recess and including a portion of the at least one organic layer overlaps the first metal layer.

[0010] The display panel may further include an inorganic insulating layer between the first metal layer and the organic insulating layer.

[0011] The second hole may expose at least a portion of a top surface of the inorganic insulating layer.

[0012] The second hole may extend into the inorganic insulating layer and may expose at least a portion of a top surface of the first metal layer.

[0013] The at least one contact portion may have a first opening defined in the organic insulating layer and a second opening defined in the inorganic insulating layer, and the first metal layer and the second metal layer may be connected to each other through the at least one contact portion.

[0014] The pixel circuit may include a thin film transistor (TFT) electrically connected to the display element and a storage capacitor, and the second metal layer may include the same material as that of a contact metal layer connecting the display element to the TFT.

[0015] The TFT may include a semiconductor layer, a gate electrode overlapping the semiconductor layer, and a connection electrode electrically connected to the semiconductor layer, and the first metal layer may include the same material as that of the connection electrode.

[0016] The display panel may further include a data line extending in the first direction and configured to transmit a data signal to the display element, wherein the data line includes a same material as that of at least one of the first metal layer and the second metal layer.

[0017] The at least one organic layer may include one or more of a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer.

[0018] The display panel may further include: a partition wall located in the third area and surrounding the first area; and at least one groove each including a first hole and a second hole or a first recess, wherein at least one groove includes a first groove located on a side of the partition wall close to the second area and a second groove located on a side of the partition wall close to the first area.

[0019] The first metal layer may be located below the first groove.

[0020] The first metal layer may overlap each of the first groove and the second groove, and may be discontinuously located under each of the first groove and the second groove.

[0021] The first metal layer may be located under the first groove, the spacer, and the second groove.

[0022] The at least one groove may further include a third groove located closer to the first region than the second groove, wherein a depth defined based on a top surface of the organic insulating layer of each of the first groove and the second groove is smaller than a depth of the third groove.

[0023] The display panel may further include at least one lower insulating layer under the organic insulating layer, wherein the at least one lower insulating layer includes an inorganic insulating layer.

[0024] A bottom surface of the third groove may be located on an imaginary surface between a top surface of the substrate and a top surface of the at least one lower insulating layer.

[0025] The first metal layer may include a floating metal disconnected from the electrical signal.

[0026] The first metal layer may have a ring shape surrounding the first region.

[0027] In a plan view, a width of the first metal layer may be greater than a width of the second hole.

[0028] The at least one contact portion of the organic insulating layer may include a first contact portion and a second contact portion, wherein the at least one groove is located between the first contact portion and the second contact portion.

[0029] The inorganic insulating layer may include a third hole or a second recess corresponding to the second hole and passing through the inorganic insulating layer.

[0030] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel including a substrate, the substrate including a first area, a second area and a third area located between the first area and the second area; and a component including an electronic element positioned corresponding to the first area, wherein the display panel includes: a display layer including a pixel circuit located in the second area and a display element electrically connected to the pixel circuit, and the display element includes a pixel electrode, a counter electrode and an intermediate layer located between the pixel electrode and the counter electrode; and a multilayer film located in the third area and including a first metal layer, a second metal layer located on the first metal layer and an organic insulating layer located between the first metal layer and the second metal layer, the first metal layer and the second metal layer contacting each other through at least one contact portion defined in the organic insulating layer, wherein the multilayer film includes at least one groove adjacent to the contact portion and defined in the multilayer film, and at least one organic layer included in the intermediate layer is disconnected by the at least one groove.

[0031] According to an exemplary embodiment of the present disclosure, a display panel includes: a substrate, including a component area in which components configured to add various functions are located, a display area in which a plurality of pixels configured to display an image are located, and an intermediate area between the component area and the display area; a first metal layer located in the intermediate area and surrounding the component area; an organic insulating layer located on the first metal layer and including at least one contact portion surrounding the component area; a second metal layer located on the organic insulating layer and contacting the first metal layer through at least one contact portion; and at least one groove positioned adjacent to the at least one contact portion and surrounding the component area, each groove having a first hole in the second metal layer and a second hole in the organic insulating layer corresponding to the first hole, and at least one groove being configured to disconnect any organic layer formed above the second metal layer.

[0032] The display panel may further include an inorganic insulating layer between the first metal layer and the organic insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] These and / or other aspects will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 2A and Figure 2B is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 3 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0037] FIG. 4A to FIG. 4D is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure;

[0038] Figure 5 is a plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0039] Figure 6 is an equivalent circuit diagram showing a pixel of a display panel according to an exemplary embodiment of the present disclosure;

[0040] Figure 7 is a plan view showing a portion of a display panel according to an exemplary embodiment of the present disclosure;

[0041] Figure 8 is a plan view showing a portion of a display panel according to an exemplary embodiment of the present disclosure;

[0042] Fig. 9 is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure;

[0043] FIG. 10A to FIG. 10C are cross-sectional views and plan views of a manufacturing process of a display panel according to an exemplary embodiment of the present disclosure;

[0044] Fig.11 is a plan view showing a portion of a display panel according to an exemplary embodiment of the present disclosure;

[0045] Fig.12 is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure;

[0046] Fig.13A and Fig. 13B is a cross-sectional view of a manufacturing process of a display panel according to an exemplary embodiment of the present disclosure;

[0047] Fig.14A , Fig. 14B and Fig.15 is a cross-sectional view of a manufacturing process of a display panel according to an exemplary embodiment of the present disclosure;

[0048] Fig.16 is a plan view showing a portion of a display panel according to an exemplary embodiment of the present disclosure; and

[0049] Fig.17 is a cross-sectional view of a display panel according to an exemplary embodiment of the present disclosure.

[0050] because Figures 1 to 17 The accompanying drawings in the drawings are for illustrative purposes only, so the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity. DETAILED DESCRIPTION

[0051] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are described herein and shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, exemplary embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, exemplary embodiments are described below with reference to the accompanying drawings only to explain various aspects of the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items. Expressions such as "at least one of..." modify the entire column of elements when following a column of elements, rather than modifying individual elements in the column.

[0052] It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms, and the above terms are only used to distinguish one element from another.

[0053] As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. Moreover, "about" as used herein includes the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, taking into account the measurement of interest and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0054] It will be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0055] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, it can be directly formed on the other layer, region or element or intervening layers, regions or elements may be present therebetween.

[0056] When a certain exemplary embodiment of the present disclosure can be implemented differently, the specific processing order may be different from the described order. For example, two processes described successively may be performed substantially simultaneously or in the reverse order of the described order.

[0057] As used herein, expressions such as "A and / or B" may include A, B, or A and B. Expressions such as "at least one of A and B" may include A, B, or A and B.

[0058] It will be understood that when layers, regions, or elements are referred to as being "connected," the layers, regions, or elements may be directly connected, or may be indirectly connected, with intermediate layers, regions, or elements located between them. For example, when layers, regions, or elements are electrically connected, the layers, regions, or elements may be directly electrically connected, and / or may be indirectly electrically connected, with intermediate layers, regions, or elements located between them.

[0059] Figure 1 is a perspective view of a display device 1 according to an exemplary embodiment of the present disclosure.

[0060] refer to Figure 1 The display device 1 includes a first area OA and a display area DA, which is a second area at least partially surrounding the first area OA. The display device 1 can provide a predetermined image by light emitted from a plurality of pixels arranged in the display area DA. In an exemplary embodiment of the present disclosure, the plurality of pixels P (see Figure 5 ) may be arranged in a matrix shape, but the present disclosure is not limited thereto. For example, the plurality of pixels P may be arranged in a honeycomb matrix shape or a diamond shape. The first area OA may be completely surrounded by the display area DA. Figure 2A As described, the first area OA may be an area in which components are located.

[0061] The middle area MA, which is the third area, may be located between the first area OA and the display area DA, and the display area DA may be surrounded by the peripheral area PA, which is the fourth area. The middle area MA and the peripheral area PA may be non-display areas in which no pixels are located. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the peripheral area PA. The first area OA may be completely surrounded by the middle area MA.

[0062] Although the organic light-emitting display device is described as the display device 1 according to the exemplary embodiment of the present disclosure, the present disclosure is not limited thereto. In the exemplary embodiment of the present disclosure, the display device 1 may be a display device such as a quantum dot light-emitting display device. The light-emitting layer of the organic light-emitting display device may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display device may include quantum dots and / or quantum rods.

[0063] Although in Figure 1 A first area OA having a substantially circular shape is provided, but the present disclosure is not limited thereto. The number of first areas OA may be equal to or greater than 2, and the shape of the first area OA may be modified in various ways, such as, for example, a circular shape, an elliptical shape, a polygonal shape, a star shape, or a diamond shape. When two or more first areas OA are provided, the first areas OA may have the same shape or different shapes.

[0064] Figure 2A , Figure 2B and Figure 3 is along Figure 1 1 is a cross-sectional view of a display device 1 according to an exemplary embodiment of the present disclosure, taken along line II-II′.

[0065] refer to Figure 2A , the display device 1 may include a display panel 10, an input sensing layer 40 located on the display panel 10, and an optical function layer 50 located on the input sensing layer 40, and the display panel 10, the input sensing layer 40, and the optical function layer 50 may be covered by a window 60. The display device 1 may be any of various electronic devices, such as, for example, a mobile phone, a laptop computer, or a smart watch.

[0066] The display panel 10 can display an image. The display panel 10 includes pixels arranged in a display area DA. The pixel may include a display element and a pixel circuit connected to the display element. The display element may include, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QD-LED). Alternatively, the display element may include, for example, an electrophoretic element or an electrowetting element.

[0067] The input sensing layer 40 obtains coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be located on the display panel 10. The input sensing layer 40 may detect an external input by using a mutual capacitance method and / or a self-capacitance method. For example, the input sensing layer 40 may obtain information about an external input by a change in capacitance between two sensing electrodes.

[0068] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then may be coupled to the display panel 10 via an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel 10, and in this case, the input sensing layer 40 may be a part of the display panel 10, and the adhesive layer may not be located between the input sensing layer 40 and the display panel 10. For example, the input sensing layer 40 and the display panel 10 may be integrated into a single substrate within the display device 1. Therefore, the thickness of the display device 1 may be reduced. Although Figure 2A The input sensing layer 40 shown in FIG. 1 is located between the display panel 10 and the optical function layer 50 , but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the input sensing layer 40 may be located above the optical function layer 50 .

[0069] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident on the display panel 10 through the window 60. The anti-reflection layer may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include an elongated synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a predetermined orientation. For example, when the polarizer and the phase retarder are both film types, the λ / 4 phase retarder film (or the λ / 2 phase retarder film) may be bonded and laminated to one surface of the polarizer through an OCA layer. The phase retarder and the polarizer may further include a transparent protective film. The phase retarder and the polarizer or the transparent protective film may be defined as the base layer of the anti-reflection layer.

[0070] In an exemplary embodiment of the present disclosure, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of the light emitted by each of the pixels of the display panel 10. Therefore, the desired color can be achieved by filtering the light emitted by each of the pixels with the color filter. In an exemplary embodiment of the present disclosure, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere with each other, thereby reducing the reflectivity of the external light.

[0071] The optical functional layer 50 may include a lens layer. The lens layer may enhance the light extraction efficiency of the light emitted by the display panel 10 or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include a plurality of layers having different refractive indices. In an exemplary embodiment of the present disclosure, a lens array of the lens layer may cover a pixel array, wherein at least one of the lenses may cover at least one of the pixels. The optical functional layer 50 may include both an anti-reflection layer and a lens layer, or may include any one of the anti-reflection layer and the lens layer.

[0072] In an exemplary embodiment of the present disclosure, the optical function layer 50 may be continuously formed after the process of forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer such as an OCA layer may not be located between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0073] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may have an opening. Figure 2AIn the embodiment, the display panel 10 , the input sensing layer 40 , and the optical function layer 50 have first to third openings 10H, 40H, and 50H, respectively, and the first to third openings 10H, 40H, and 50H overlap with each other.

[0074] The first to third openings 10H, 40H, and 50H are formed to correspond to the first area OA.

[0075] In an exemplary embodiment of the present disclosure, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not have an opening. For example, one or two selected from the display panel 10, the input sensing layer 40, and the optical function layer 50 may not have an opening. Alternatively, the display panel 10, the input sensing layer 40, and the optical function layer 50 may not have an opening, such as Figure 3 as shown in .

[0076] The first area OA may be a component area (eg, a sensor area, a camera area, or a speaker area) in which the component 20 for adding various functions as described above is located. The component 20 may be positioned corresponding to the first to third openings 10H, 40H, and 50H, and may be as shown in FIG. Figure 2A As shown in FIG. 1 , the display panel 10 is located below the display panel 10. Alternatively, as shown in FIG. Figure 2B As shown in , the component 20 can be positioned so that at least a portion of the component 20 is inserted into the first to third openings 10H, 40H and 50H. The component 20 can be arranged to overlap the first to third openings 10H, 40H and 50H. Therefore, since the component 20 is assembled to overlap the first to third openings 10H, 40H and 50H in a plan view, it can easily communicate with the outside through the first to third openings 10H, 40H and 50H. Alternatively, as Figure 3 As shown in , the component 20 may be located below the display panel 10 without the through hole.

[0077] The component 20 may include an electronic component positioned corresponding to the first area OA. For example, the component 20 may include an electronic component that uses light or sound. Examples of electronic components may include: a sensor for outputting and / or receiving light, such as an infrared sensor; a camera for receiving light and capturing an image; a sensor for outputting and detecting light or sound to measure distance or recognize fingerprints; a small lamp for outputting light; and a speaker for outputting sound. When the component 20 is an electronic component using light, the component 20 may use light of various wavelength bands, such as visible light, infrared light, or ultraviolet light. In an exemplary embodiment of the present disclosure, the first area OA may be a transmission area through which light and / or sound output from the component 20 to the outside or traveling from the outside to the electronic component can be transmitted. For example, the component 20 may include at least one of a camera, a speaker, a lamp, a light detection sensor, and a heat detection sensor. The component 20 may detect an external object received through the first area OA, or provide a sound signal such as voice to the outside through the first area OA. In addition, the component 20 may include a variety of configurations and is not limited to any one exemplary embodiment.

[0078] In an exemplary embodiment of the present disclosure, when the display device 1 is used as a smart watch or a vehicle instrument panel, the component 20 may be a member such as a clock hand or a pointer indicating predetermined information (e.g., vehicle speed). When the display device 1 includes a clock hand or a vehicle instrument panel, the component 20 may pass through the window 60 and may be exposed to the outside, and the window 60 may have an opening corresponding to the first area OA.

[0079] The component 20 may include an element (or elements) related to the function of the display panel 10 as described above, or may include an element such as an accessory for enhancing the aesthetics of the display panel 10. Since the window 60 may be formed separately from the optical functional layer 50, a layer including the OCA may be located between the window 60 and the optical functional layer 50.

[0080] FIG. 4A to FIG. 4D is a cross-sectional view of a display panel 10 according to an exemplary embodiment of the present disclosure.

[0081] refer to Figure 4A The display panel 10 includes a display layer 200 located on a substrate 100. The substrate 100 may include, for example, a glass material and / or a polymer resin, and may have a multi-layer structure. Figure 4A As shown in the enlarged view of , the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 .

[0082] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, each of the first base layer 101 and the second base layer 103 may include a polymer resin such as, for example, polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The polymer resin may be transparent and may be provided so that at least a portion of the display panel 10 may be easily bent. Alternatively, the substrate 100 may be provided in a rigid state.

[0083] Each of the first barrier layer 102 and the second barrier layer 104, which are barrier layers for preventing penetration of external foreign matter, may have a material including, for example, silicon nitride (SiN x ) or silicon oxide (SiO x For example, the first barrier layer 102 and the second barrier layer 104 may include an inorganic material to prevent oxygen or water flowing through the substrate 100 from penetrating into the display layer 200.

[0084] The display layer 200 includes a plurality of pixels. The display layer 200 may include: a display element layer 200A, which includes a display element located in a display area DA for each pixel; and a pixel circuit layer 200B, which includes an insulating layer and a pixel circuit located in the display area DA for each pixel. The display element may be electrically connected to the pixel circuit. The display element layer 200A may include a pixel electrode, a counter electrode, and a stacked structure located between the pixel electrode and the counter electrode, and each of the display elements may include an OLED. Each of the pixel circuits may include a thin film transistor (TFT) and a storage capacitor.

[0085] The display element of the display layer 200 may be covered by an encapsulation member such as a thin film encapsulation layer 300, and the thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes a substrate 100 including a polymer resin and a thin film encapsulation layer 300 including an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display panel 10 may be enhanced. In addition, in the case of forming a flexible display device, in addition to the substrate 100 including a polymer resin, a plastic film having good ductility may be used to form the window 60.

[0086] The display panel 10 may have a first opening 10H passing through the display panel 10. The first opening 10H may be located in the first area OA, and in this case, the first area OA may be an opening area. Figure 4AIn the embodiment, the substrate 100 and the thin film encapsulation layer 300 respectively have through holes 100H and 300H corresponding to the first opening 10H of the display panel 10. The display layer 200 may also have a through hole 200H corresponding to the first area OA.

[0087] In an exemplary embodiment of the present disclosure, Figure 4B As shown in , the substrate 100 may not have a through hole corresponding to the first area OA. The display layer 200 may have a through hole 200H corresponding to the first area OA. The thin film encapsulation layer 300 may not have a through hole corresponding to the first area OA. In an exemplary embodiment of the present disclosure, as Figure 4C As shown in , the display layer 200 may not have a through hole corresponding to the first area OA. In addition, the substrate 100 may not have a through hole corresponding to the first area OA, and the thin film encapsulation layer 300 may not have a through hole corresponding to the first area OA.

[0088] Although in FIG. 4A to FIG. 4C In the embodiment, the display element layer 200A is not located in the first area OA, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the auxiliary display element layer 200C may be located in the first area OA, such as Figure 4D The auxiliary display element layer 200C may include a display element having a structure and / or an operation method different from that of the display element of the display element layer 200A.

[0089] In an exemplary embodiment of the present disclosure, each pixel of the display element layer 200A may include an active matrix OLED, and each pixel of the auxiliary display element layer 200C may include a passive matrix OLED. When the auxiliary display element layer 200C includes a display element of a passive matrix OLED, the elements constituting the pixel circuit may not be located below the passive matrix OLED. For example, the portion of the pixel circuit layer 200B below the auxiliary display element layer 200C does not include a transistor and a storage capacitor. Therefore, the auxiliary display element layer 200C including the passive matrix OLED uses a simple control scheme and is controlled by an external circuit.

[0090] In an exemplary embodiment of the present disclosure, the auxiliary display element layer 200C may include a display element of the same type as the display element of the display element layer 200A (e.g., an active matrix OLED), and the structure of the pixel circuit below the auxiliary display element layer 200C may be different from the structure of the pixel circuit below the display element layer 200A. For example, the pixel circuit below the auxiliary display element layer 200C (e.g., a pixel circuit including a shielding film between the substrate 100 and the transistor) may have a structure different from the structure of the pixel circuit below the display element layer 200A. Alternatively, the display element of the auxiliary display element layer 200C and the display element of the display element layer 200A may be operated according to different control signals. For example, the display element of the auxiliary display element layer 200C may provide a function different from the function of the display element of the display element layer 200A. A component (e.g., an infrared sensor) that does not require a relatively high transmittance may be located in the first region OA in which the auxiliary display element layer 200C is located. In this case, the first region OA may be a component region or an auxiliary display region.

[0091] Figure 5 is a plan view of a display panel 10 according to an exemplary embodiment of the present disclosure, and Figure 6 is an equivalent circuit diagram illustrating a pixel P of the display panel 10 according to an exemplary embodiment of the present disclosure.

[0092] refer to Figure 5 , the display panel 10 may include a first area OA, a display area DA which is a second area, a middle area MA which is a third area, and a peripheral area PA which is a fourth area. Figure 5 There may be shown a substrate 100 of the display panel 10. For example, the substrate 100 may be understood to include a first area OA, a display area DA, a middle area MA, and a peripheral area PA.

[0093] The display panel 10 includes a plurality of pixels P arranged in a display area DA. Figure 6 As shown in , each of the pixels P includes a pixel circuit PC and an OLED which is a display element connected to the pixel circuit PC. The pixel circuit PC may include a first TFT T1, a second TFT T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, blue light, or white light through the OLED. The display panel 10 may display a predetermined image by light emitted from a plurality of pixels P arranged in the display area DA according to an electrical signal.

[0094] The second TFT T2, i.e., a switching TFT for controlling the on and off of the pixel P, may be connected to the scan line SL and the data line DL, and may transfer a data voltage input from the data line DL to the first TFT T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second TFT T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second TFT T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0095] The first TFT T1, which is a driving TFT, may be connected to a driving voltage line PL and a storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the OLED in response to a voltage stored in the storage capacitor Cst. The OLED may emit light having a predetermined brightness according to the driving current. The on-time of the first TFT T1 may be determined according to the amount of the voltage stored in the storage capacitor Cst. Then, the first TFT T1 may provide the first power supply voltage ELVDD transmitted through the driving voltage line PL to the OLED during the on-time. The counter electrode (e.g., cathode) of the OLED may receive a second power supply voltage ELVSS.

[0096] Although in Figure 6 The pixel circuit PC includes two TFTs and one storage capacitor, but the present disclosure is not limited thereto. The number of TFTs and the number of storage capacitors can be changed in various ways according to the design of the pixel circuit PC. For example, the pixel circuit PC can include three, four, five or more TFTs instead of the above two TFTs.

[0097] Reference again Figure 5 , in a plan view, the middle area MA may surround the first area OA. The middle area MA is an area in which a display element for emitting light, such as an OLED, is not located, and a signal line for applying a signal to pixels P arranged around the first area OA may pass through the middle area MA. A scan driver 1100 for applying a scan signal to each pixel P, a data driver 1200 for applying a data signal to each pixel P, and a main power wiring for supplying a first power voltage ELVDD and a second power voltage ELVSS may be located in the peripheral area PA. Although in Figure 5 The data driver 1200 is positioned adjacent to one side of the substrate 100, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the data driver 1200 may be located on a flexible printed circuit board (FPCB) electrically connected to a pad located on one side of the display panel 10. The FPCB may be bent and electrically connected to the display panel 10. Therefore, the FPCB may output a signal to the display panel 10 or receive a signal from the display panel 10.

[0098] Figure 7 is a plan view showing a portion of the display panel 10 according to an exemplary embodiment of the present disclosure.

[0099] refer to Figure 7 , the pixels P are located in the display area DA around the first area OA. Some pixels P may be spaced apart from each other around the first area OA, and the first area OA may be defined between the pixels P. For example, in a plan view, the pixels P may be located above and below the first area OA, and may be located to the left and right of the first area OA. Since the middle area MA is an area in which the pixels P are not located, in a plan view, the pixels P may be located above and below the middle area MA, and may be located to the left and right of the middle area MA.

[0100] Among the signal lines that apply signals to the pixels P, the signal lines adjacent to the first area OA may bypass the first area OA. Figure 7 In a plan view, at least one of the data lines DL passing through the display area DA may extend in the y direction to apply a data signal to the pixels P located above and below the first area OA, and may detour along the edge of the first area OA in the middle area MA. In a plan view, at least one of the scan lines SL passing through the display area DA may extend in the x direction to apply a scan signal to the pixels P located on the left and right of the first area OA, and may detour along the edge of the first area OA in the middle area MA. For example, the right scan line SL and the left scan line SL may be connected to each other through the bypass portion SL-D and the extension portion SL-L, wherein the bypass portion SL-D of the scan line SL is disposed in the middle area MA and avoids the first area OA.

[0101] The bypass portion SL-D of the scan line SL and the extension portion SL-L of the scan line SL crossing the display area DA may be located on the same layer and may be formed integrally. The bypass portion DL-D1 of at least one of the data lines DL and the extension portion DL-L1 of the data line DL crossing the display area DA may be formed on different layers, and the bypass portion DL-D1 and the extension portion DL-L1 of the data line DL may be connected to each other through the contact hole CNT. The bypass portion DL-D2 of at least one of the data lines DL and the extension portion DL-L2 of the data line DL may be located on the same layer and may be formed integrally.

[0102] One or more grooves G may be located between the first area OA and a portion of the middle area MA where the scan line SL and the data line DL are bypassed. In a plan view, each of the grooves G may have a ring shape surrounding the first area OA, and the grooves G may be spaced apart from each other. A bypass portion SL-D of the scan line SL and bypass portions DL-D1 and DL-D2 of the data line DL may be disposed between the groove G and the display area DA.

[0103] Figure 8 is a plan view of a display panel 10 - 1 according to an exemplary embodiment of the present disclosure, and Fig. 9 is along Figure 8 A cross-sectional view of a display panel 10 - 1 according to an exemplary embodiment of the present disclosure taken along line IX-IX′. FIG. 10A to FIG. 10C 1 are cross-sectional views and plan views of a manufacturing process of a display panel 10 - 1 according to an exemplary embodiment of the present disclosure, which illustrate a middle area MA.

[0104] refer to Figure 8 , a partition wall PW surrounding the first area OA and at least one groove G may be provided in the middle area MA. The partition wall PW may have a ring shape surrounding the first area OA.

[0105] In an exemplary embodiment of the present disclosure, a plurality of grooves G may be provided and may be located on both sides of the partition wall PW. Figure 8 In the embodiment of the present invention, at least one of the grooves G may be provided on the outside of the partition wall PW and adjacent to the display area DA, and the other grooves G among the grooves G may be provided on the inside of the partition wall PW and adjacent to the first area OA. In an exemplary embodiment of the present disclosure, two or more grooves G may be provided on the inside of the partition wall PW and adjacent to the first area OA.

[0106] The first metal layer MTL1 may be positioned to overlap the groove G in the middle area MA. Figure 8 The first metal layer MTL1 overlaps all the grooves G, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first metal layer MTL1 may overlap some of the grooves G. Therefore, the first metal layer MTL1 may not be located under some of the grooves G. Each of the first metal layers MTL1 may have a ring shape surrounding the first area OA.

[0107] refer to Fig. 9 The display area DA of the substrate 100 may include, for example, a glass material or a polymer resin. In an exemplary embodiment of the present disclosure, the substrate 100 may include, for example, Figure 4A The multiple sublayers are shown in the enlarged view.

[0108] A buffer layer 201 for preventing impurities from penetrating into the semiconductor layer Act of the TFT may be formed on the substrate 100. The buffer layer 201 may include a silicon-based material such as SiN x , silicon oxynitride (SiON) or SiO x of an inorganic insulating material, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0109] The pixel circuit PC may be located on the buffer layer 201. The pixel circuit PC includes a TFT and a storage capacitor Cst. The TFT may include a semiconductor layer Act, a gate electrode GE, and a source electrode SE and a drain electrode DE that are connection electrodes. The gate electrode GE may overlap the semiconductor layer Act. The portion of the semiconductor layer Act that overlaps the gate electrode GE may be a channel region of the TFT. Fig. 9 The TFT can correspond to the reference Figure 6 The driving TFT described. The data line DL may be electrically connected to a switching TFT included in the pixel circuit PC. Although as shown in the present exemplary embodiment, the TFT is a top-gate TFT in which the gate electrode GE is located above the semiconductor layer Act and the gate insulating layer 203 is located therebetween, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the TFT may be a bottom-gate TFT.

[0110] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include, for example, amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include: a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or an alloy thereof, and may have a single-layer or multi-layer structure including a conductive material.

[0111] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include, for example, SiO x 、SiN x , SiON, Alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), lanthanum oxide (La 2 O 3 )、ZrO 2 ) or hafnium oxide (HfO 2 The gate insulating layer 203 may have a single-layer or multi-layer structure including an inorganic insulating material.

[0112] The source electrode SE and the drain electrode DE, which are connection electrodes electrically connected to the semiconductor layer Act, may be located on the same layer as the layer of the data line DL and may include the same material as the material of the data line DL. The portion of the semiconductor layer Act connected to the source electrode SE or the drain electrode DE may be doped with an n-type dopant or a p-type dopant. Each of the source electrode SE, the drain electrode DE, and the data line DL may include a material having a high conductivity. Each of the source electrode SE and the drain electrode DE may include: a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or an alloy thereof, and may have a single layer or multilayer structure including a conductive material. In an exemplary embodiment of the present disclosure, each of the source electrode SE, the drain electrode DE, and the data line DL may have a multilayer structure formed of Ti / Al / Ti.

[0113] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other with the first interlayer insulating layer 205 disposed therebetween. The storage capacitor Cst may overlap the TFT. In this regard, Fig. 9 In the embodiment of the present invention, the gate electrode GE of the TFT is the lower electrode CE1 of the storage capacitor Cst. In an exemplary embodiment of the present disclosure, the storage capacitor Cst may not overlap with the TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material including, for example, Ag, Mo, Al, Cu, Cr, Ni, Ti, or an alloy thereof, and may have a single-layer or multi-layer structure including a conductive material.

[0114] Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include, for example, SiO x 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 or HfO 2 Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may have a single-layer or multi-layer structure including an inorganic insulating material.

[0115] The pixel circuit PC including the TFT and the storage capacitor Cst may be covered by the inorganic insulating layer 208. The inorganic insulating layer 208 may prevent the wiring including a metal such as, for example, aluminum (Al), which may be damaged by an etchant during a manufacturing process of the display device, from being exposed to an etching environment. The inorganic insulating layer 208 may extend to the middle area MA and may cover some of the data lines DL and the first metal layer MTL1.

[0116] The inorganic insulating layer 208 may include SiO x 、SiN x and / or SiON, and may have a single-layer or multi-layer structure. In an exemplary embodiment of the present disclosure, the inorganic insulating layer 208 may include SiN x The inorganic insulating layer 208 may have a thickness equal to or greater than about In an exemplary embodiment of the present disclosure, the inorganic insulating layer 208 may have a thickness equal to or greater than about Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately Equal to or greater than approximately or equal to or greater than approximately Alternatively, the inorganic insulating layer 208 may have a thickness of about To date The thickness is within the range of .

[0117] The first organic insulating layer 209 may be positioned on the inorganic insulating layer 208. The first organic insulating layer 209 may have a substantially flat top surface.

[0118] The pixel circuit PC may be electrically connected to the pixel electrode 221. Fig. 9 As shown in , the contact metal layer CM may be further located between the TFT and the pixel electrode 221. The contact metal layer CM may contact the TFT (e.g., contact the drain electrode DE of the TFT) through a contact hole formed in the first organic insulating layer 209, and the pixel electrode 221 may contact the contact metal layer CM through a contact hole formed in the second organic insulating layer 211 formed on the contact metal layer CM. The contact metal layer CM may include a conductive material including, for example, Ag, Mo, Al, Cu, Cr, Ni, Ti, or an alloy thereof, and may have a single-layer or multi-layer structure including a conductive material. In an exemplary embodiment of the present disclosure, the contact metal layer CM may have a multi-layer structure formed of Ti / Al / Ti.

[0119] Each of the first organic insulating layer 209 and the second organic insulating layer 211 may include an organic insulating material such as, for example, a general polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. In an exemplary embodiment of the present disclosure, each of the first organic insulating layer 209 and the second organic insulating layer 211 may include polyimide (PI). In an exemplary embodiment of the present disclosure, each of the first organic insulating layer 209 and the second organic insulating layer 211 may be formed by spin coating.

[0120] The pixel electrode 221 may be formed on the second organic insulating layer 211. The pixel electrode 221 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an exemplary embodiment of the present disclosure, the pixel electrode 221 may include: a reflective film including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an exemplary embodiment of the present disclosure, the pixel electrode 221 may further include a conductive oxide such as ITO, IZO, ZnO or In above / below the reflective film. 2 O 3 The film formed.

[0121] The pixel defining film 215 may be formed on the pixel electrode 221. The pixel defining film 215 may have an opening through which the top surface of the pixel electrode 221 is exposed, and may cover the edge of the pixel electrode 221. The pixel defining film 215 may include an organic insulating material. Alternatively, the pixel defining film 215 may include an organic insulating material such as, for example, SiN x , SiON or SiO x Alternatively, the pixel defining film 215 may include an organic insulating material and an inorganic insulating material.

[0122] The intermediate layer 222 located between the pixel electrode 221 and the counter electrode 223 includes an emission layer 222b and at least one organic layer. The intermediate layer 222 may include a first functional layer 222a located below the emission layer 222b and / or a second functional layer 222c located above the emission layer 222b. The at least one organic layer included in the intermediate layer 222 may include at least one of the first functional layer 222a and the second functional layer 222c. The emission layer 222b may include a high molecular weight or low molecular weight organic material that emits light of a predetermined color. In an exemplary embodiment of the present disclosure, the emission layer 222b may include at least one of a material that emits red light, green light, and blue light, and may include a fluorescent material or a phosphorescent material.

[0123] The first functional layer 222a may have a single layer or a multilayer structure. For example, when the first functional layer 222a is formed of a high molecular weight material, the first functional layer 222a may include a hole transport layer (HTL) having a single layer structure, the single layer structure including, for example, poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer 222a is formed of a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0124] The second functional layer 222c may be omitted. For example, it is preferred that when each of the first functional layer 222a and the emission layer 222b is formed of a high molecular weight material, the second functional layer 222c is formed. The second functional layer 222c may have a single layer or a multilayer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Therefore, at least one organic layer included in the intermediate layer 222 may include one or more of a hole transport layer (HTL), a hole injection layer (HIL), an electron injection layer (EIL) and an electron transport layer (ETL).

[0125] The emission layer 222b of the intermediate layer 222 may be located in the display area DA for each pixel. The emission layer 222b may be patterned to correspond to the pixel electrode 221. Unlike the emission layer 222b, the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may be located in the intermediate area MA and the display area DA. In the intermediate area MA, the first functional layer 222a and / or the second functional layer 222c may be disconnected by the groove G.

[0126] The counter electrode 223 may be formed of a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer including, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 223 may further include a conductive material including ITO, IZO, ZnO, or In 2 O 3 The layer formed on the (semi) transparent layer including the above-mentioned materials. The counter electrode 223 may also be formed in the middle area MA and the display area DA. The first functional layer 222a, the second functional layer 222c and the counter electrode 223 may be formed by thermal evaporation.

[0127] The capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include lithium fluoride (LiF) and may be formed by thermal evaporation. In an exemplary embodiment of the present disclosure, the capping layer 230 may be omitted.

[0128] The spacer 217 may be formed on the pixel defining film 215 and may include an organic insulating material such as PI. Alternatively, the spacer 217 may include an inorganic insulating material, or may include an organic insulating material and an inorganic insulating material.

[0129] The spacer 217 and the pixel defining film 215 may include the same material or different materials. For example, the pixel defining film 215 and the spacer 217 may be formed together by a photolithography process using a half-tone mask. In an exemplary embodiment of the present disclosure, the pixel defining film 215 and the spacer 217 may include PI.

[0130] The OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer, and Fig. 9 , the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. In an exemplary embodiment of the present disclosure, the number of organic encapsulation layers and the number of inorganic encapsulation layers and the stacking order of the organic encapsulation layers and the inorganic encapsulation layers may be changed.

[0131] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include, for example, Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZnO、SiO x 、SiN xand one or more inorganic materials in SiON. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have a single-layer or multi-layer structure including one or more inorganic materials. The first inorganic encapsulation layer 310 may be formed to cover the cap layer 230 located on the counter electrode 223, and may prevent external moisture or oxygen from penetrating into the OLED. The first inorganic encapsulation layer 310 may be formed by a deposition process.

[0132] The organic encapsulation layer 320 may include a polymer-based material. Examples of polymer-based materials may include, for example, acrylic resins, epoxy resins, PI, and polyethylene. In an exemplary embodiment of the present disclosure, the organic encapsulation layer 320 may include acrylate. In an exemplary embodiment of the present disclosure, the organic encapsulation layer 320 may be formed by a solution process such as, for example, a spin coating process, a slit coating process, or an inkjet process. The organic encapsulation layer 320 may provide a flat surface on the first inorganic encapsulation layer 310, and may relieve stress between contacting layers.

[0133] The thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thickness of the first inorganic encapsulation layer 310 may be the same as the thickness of the second inorganic encapsulation layer 330.

[0134] refer to Fig. 9 The middle area MA may include a first sub-middle area SMA1 relatively far from the first area OA and a second sub-middle area SMA2 relatively close to the first area OA. Lines such as data lines DL and scan lines SL and a groove G bypassing the first area OA may be located in the middle area MA.

[0135] For example, the data line DL may be located in the first sub-middle area SMA1. Fig. 9 as shown in . Fig. 9 The data line DL of the first sub-middle area SMA1 corresponds to Figure 7 The first sub middle area SMA1 may be a line area or a bypass area where lines such as the data lines DL are detoured.

[0136] The data lines DL may be alternately arranged with an insulating layer disposed therebetween. For example, adjacent data lines DL are alternately positioned so that one of the adjacent data lines DL is located below the insulating layer (e.g., the first organic insulating layer 209) and the other is located above the insulating layer (e.g., the first organic insulating layer 209). Figure 7As shown in , the bypass portion DL-D1 and the extension portion DL-L1 of at least one of the data lines DL may be formed on different layers, and the bypass portion DL-D2 and the extension portion DL-L2 of at least one of the data lines DL may be located on the same layer. When the data lines DL are alternately positioned while an insulating layer is disposed therebetween, the distance between the data lines DL (e.g., a gap Δd in the x direction or in a plan view) may be reduced. Although the data lines DL are located Fig. 9 In the first sub-middle area SMA1, but Figure 7 The scan line SL (eg, the bypass portion SL-D of the scan line SL) may also be located in the first sub-middle area SMA1.

[0137] One or more grooves G may be located in the second sub-middle area SMA2. An organic layer or multiple organic layers included in the middle layer 222, such as the first functional layer 222a and / or the second functional layer 222c, may be disconnected (or separated) by the groove G. The second sub-middle area SMA2 may be a groove area or a disconnection area (separation area) of the organic layer. For example, the groove G may be formed to disconnect any organic layer in the second sub-middle area SMA2. Similar to the first functional layer 222a and / or the second functional layer 222c, the counter electrode 223 formed by thermal evaporation may be disconnected by the groove G. The cap layer 230 including LiF or the like may also be disconnected by the groove G.

[0138] Some of the layers disconnected by the groove G may remain in the groove G as a residual layer GP. Fig. 9 In the embodiment of the present disclosure, the residual layer GP may be located on the bottom surface of the groove G and may be located on the inorganic insulating layer 208. In an exemplary embodiment of the present disclosure, the residual layer GP in the groove G may include a portion 222aP of the first functional layer 222a, a portion 222cP of the second functional layer 222c, a portion 223P of the counter electrode 223, and a portion 230P of the capping layer 230. In the manufacturing process, they may be sequentially stacked in the groove G in the order of the portion 222aP of the first functional layer 222a, the portion 222cP of the second functional layer 222c, the portion 223P of the counter electrode 223, and the portion 230P of the capping layer 230.

[0139] The groove G may be formed in the multilayer film ML between the substrate 100 and the pixel electrode 221. The multilayer film ML may include: a first sublayer including an organic layer and a second sublayer including an inorganic layer. Fig. 9, the multilayer film ML includes a first metal layer MTL1, an inorganic insulating layer 208, a first organic insulating layer 209, and a second metal layer MTL2. The multilayer film ML may include at least one groove G adjacent to the contact portion CT and defined in the multilayer film ML, and at least one organic layer included in the intermediate layer 222 is disconnected by the at least one groove G.

[0140] The first metal layer MTL1 may be formed on the same layer (second interlayer insulating layer 207) as the layer of the source electrode SE and the drain electrode DE which are the connection electrodes of the TFT, and may be formed by using the same mask process as the mask process of the source electrode SE and the drain electrode DE. The first metal layer MTL1 may include the same material as the source electrode SE and the drain electrode DE. For example, the first metal layer MTL1 may include a metal, and may include three sublayers formed of, for example, Ti / Al / Ti. Since the source electrode SE and the drain electrode DE may be located on the same layer as the layer of the data line DL, and may include the same material as the material of the data line DL, the data line DL may include the same material as the first metal layer MTL1. In an exemplary embodiment of the present disclosure, the first metal layer MTL1 may include a floating metal disconnected from an electrical signal. Unlike the data line DL and the scan line SL, the first metal layer MTL1 is not connected to provide any electrical signal.

[0141] The second metal layer MTL2 may be located on the same layer (first organic insulating layer 209) as the layer of the contact metal layer CM, and may be formed by using the same mask process as the mask process of the contact metal layer CM. The second metal layer MTL2 may include the same material as the material of the contact metal layer CM. For example, the second metal layer MTL2 may include a metal, and may include three sub-layers formed of, for example, Ti / Al / Ti. In an exemplary embodiment of the present disclosure, the data line DL may include the same material as that of at least one of the first metal layer MTL1 and the second metal layer MTL2.

[0142] Will refer to Fig. 9 and Fig. 10A The groove G is described in detail.

[0143] refer to Fig. 9 and Fig. 10A, the groove G of the multilayer film ML may be formed before the process of forming the intermediate layer 222. The groove G may have an undercut structure. The groove G may have a first hole 210h formed in the second metal layer MTL2 and a second hole 209h (or a recess corresponding to the first hole 210h) formed in the first organic insulating layer 209. Therefore, the residual layer GP may be located in the second hole 209h (or a recess corresponding to the first hole 210h), may include a portion of at least one organic layer in the intermediate layer 222, and may overlap with the first metal layer MTL1. Fig. 10A In the embodiment, the first hole 210h and the second hole 209h overlap each other to form a groove G.

[0144] The bottom surface of the groove G may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209. In this regard, Fig. 10A , the bottom surface of the groove G is located on the same imaginary surface as the top surface 208a of the inorganic insulating layer 208. Here, the bottom surface of the groove G has an imaginary surface, and the top surface 208a of the inorganic insulating layer 208 has a real surface. That is, the groove G may expose at least a portion of the top surface 208a of the inorganic insulating layer 208.

[0145] In an exemplary embodiment of the present disclosure, the bottom surface of the groove G may be located at the top surface MTL1a of the first metal layer MTL1 (see Fig. 10C ) and an imaginary surface between the top surface 208a of the inorganic insulating layer 208. In this case, the groove G may include a first hole 210h formed in the second metal layer MTL2, a second hole 209h formed in the first organic insulating layer 209, and a concave portion formed in the inorganic insulating layer 208. The concave portion may be a portion recessed toward the substrate 100 by removing a portion of the inorganic insulating layer 208 while not passing through the inorganic insulating layer 208.

[0146] The end of the second metal layer MTL2 defining the first hole 210h may protrude more toward the center of the groove G than the inner surface of the first organic insulating layer 209 located below the second metal layer MTL2. For example, the first width W1 of the first hole 210h may be less than the second width W2 of the second hole 209h, and the second width W2 of the second hole 209h may be the width of the portion of the second hole 209h below the end of the second metal layer MTL2 defining the first hole 210h. In an exemplary embodiment of the present disclosure, the groove G may be formed by an isotropic etching process, and thus may have an undercut structure. The end of the second metal layer MTL2 protruding toward the center of the groove G and / or the first hole 210h may form a pair of eaves (or a pair of protruding tips PT or a pair of tips PT). As described below, the protruding length d1 of each of the tips PT may be less than the depth h1 of the second hole 209h in the z direction. For example, the protruding length d1 of the tip PT may be, for example, in the range of about 1 μm to about 1.5 μm.

[0147] Although the first end portion of the second metal layer MTL2 forming the tip PT may be exposed, as shown Fig. 9 , but the opposite end, such as the second end 210e (see Fig. 10A ) may be covered by the second organic insulating layer 211.

[0148] The depth h1 of the second hole 209h may be the same as the thickness t1 of the first organic insulating layer 209. Here, the depth h1 of the second hole 209h may be defined based on the top surface of the first organic insulating layer 209, for example, may be measured from the top surface of the first organic insulating layer 209. The depth h1 of the second hole 209h may correspond to the depth of the groove G. In an exemplary embodiment of the present disclosure, the depth of the groove G may be equal to or greater than about 1.5 μm. For example, the depth of the groove G may be equal to or greater than about 2 μm, and preferably, may be equal to or greater than about 3 μm.

[0149] The first organic insulating layer 209 may have a first opening 209OD. The first opening 209OD may be located adjacent to the groove G and may be spaced apart from the groove G by a predetermined interval. In an exemplary embodiment of the present disclosure, the first opening 209OD may be located on both sides of the groove G, such as Fig. 10A For example, one first opening 209OD may be located at a side of the groove G close to the display area DA, and another first opening 209OD may be located at a side of the groove G close to the first area OA.

[0150] The inorganic insulating layer 208 may have a second opening 208OD. The second opening 208OD may correspond to the first opening 209OD. That is, the second opening 208OD may extend from the first opening 209OD. The second opening 208OD and the first opening 209OD may be formed together in a process of forming a contact hole through which the contact metal layer CM and the drain electrode DE in the display area DA are connected to each other.

[0151] The second metal layer MTL2 and the first metal layer MTL1 may directly contact each other through at least one contact portion CT located adjacent to the groove G. Fig. 10A At least one contact portion CT includes a first contact portion CT1 and a second contact portion CT2 between which a groove G is located, but the present disclosure is not limited thereto. For example, two or more grooves G may be formed to be located between the first contact portion CT1 and the second contact portion CT2. Fig. 10B As shown in FIG, the first and second contact portions CT1 and CT2 may extend along the groove G to be spaced apart from each other by a predetermined interval. For example, at least one contact portion CT of the first organic insulating layer 209 may include first and second contact portions CT1 and CT2 between which at least one groove G is located.

[0152] The contact portion CT may include a first opening 209OD defined in the first organic insulating layer 209 and a second opening 208OD defined in the inorganic insulating layer 208. That is, the second metal layer MTL2 may directly contact a layer below the first organic insulating layer 209, for example, the first metal layer MTL1, that is lower than the inorganic insulating layer 208 through the first opening 209OD and the second opening 208OD. The second metal layer MTL2 and the first metal layer MTL1 that contact each other through the first opening 209OD and the second opening 208OD may form an inorganic contact region ICR. Therefore, the inorganic contact region ICR may be formed by a metal-metal contact, thereby providing a better structure in terms of preventing moisture from penetrating into the OLED than a structure having a lower inorganic film (SiON) as a part of the inorganic contact region ICR.

[0153] The layer including the organic material among the layers on the substrate 100 may become a path through which moisture permeates. In an exemplary embodiment of the present disclosure, when the display panel 10-1 includes the following Fig. 9 The through portion 10H corresponding to the first area OA shown in FIG. Figure 2A , Figure 2B , Figure 4A and Figure 4BWhen the first opening 10H shown in FIG. 1 is formed in the through portion 10H, moisture may penetrate through the through portion 10H in a direction parallel to the top surface of the substrate 100 (e.g., an x ​​direction, hereinafter referred to as a lateral direction). However, according to an exemplary embodiment of the present disclosure, the middle area MA includes the inorganic contact area ICR, and thus moisture may be prevented from penetrating into the display area DA through the first organic insulating layer 209. The groove G may also disconnect any organic layers to prevent moisture from penetrating into the display area DA through these organic layers.

[0154] The partition wall PW may be located between the grooves G. The partition wall PW may include a plurality of sub-organic insulating layers stacked sequentially. Fig. 10A As shown in , the partition wall PW may have a structure in which a portion 209P of the first organic insulating layer 209, a portion 211P of the second organic insulating layer 211, a portion 215P of the pixel defining film, and a portion 217P of the spacer 217 are stacked. In an exemplary embodiment of the present disclosure, one or more of the portion 209P of the first organic insulating layer 209, the portion 211P of the second organic insulating layer 211, the portion 215P of the pixel defining film 215, and the portion 217P of the spacer 217 may be omitted, and in this case, the height from the substrate 100 to the top surface of the partition wall PW may be less than the height from the substrate 100 to the top surface of the spacer 217. In an exemplary embodiment of the present disclosure, two or more partition walls PW may be formed in the middle area MA, and the two or more partition walls PW may have the same structure or different structures.

[0155] Fig. 10B It is shown Figure 8 Magnified view of region X.

[0156] refer to Fig. 10A and Fig. 10B , the width W3 of the first metal layer MTL1 may be greater than the second width W2 of the second hole 209h. The second width W2 of the second hole 209h may be the width of the groove G. Here, the second width W2 may be the width of the second hole 209h of the groove G directly below the end of the second metal layer MTL2 defining the first hole 210h. Fig. 10A As shown in FIG. 2 , the width of the groove G may be interpreted as a first width W1 of the first hole 210 h corresponding to the entrance of the groove G. As shown in FIG.

[0157] At least one lower insulating layer may be located below the first organic insulating layer 209, wherein the at least one lower insulating layer may include an inorganic insulating layer 208. Fig. 9 and Fig. 10C , Fig. 10C The display panel 10-1' shown in FIG. Fig. 10AThe display panel 10 - 1 shown in FIG. 1 is different in the shape of the groove G. FIG. Fig. 10C The groove G may include a first hole 210h formed in the second metal layer MTL2, a second hole 209h formed in the first organic insulating layer 209, and a third hole 208h formed in the inorganic insulating layer 208. For example, the inorganic insulating layer 208 may include a third hole 208h or a second concave portion corresponding to the second hole 209h and passing through the inorganic insulating layer 208.

[0158] exist Fig. 10C In the embodiment, the first hole 210h, the second hole 209h, and the third hole 208h overlap each other to form a groove G. The bottom surface of the groove G may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209, and in this regard, Fig. 10C In the embodiment, the bottom surface of the groove G is located on the same imaginary surface as the top surface MTL1a of the first metal layer MTL1. That is, the groove G may expose at least a portion of the top surface MTL1a of the first metal layer MTL1. For example, the second hole 209h may extend into the inorganic insulating layer 208 by forming the third hole 208h, and then may expose at least a portion of the top surface MTL1a of the first metal layer MTL1.

[0159] In the present exemplary embodiment, the depth h1' of the groove G may be the same as the sum of the depths of the second hole 209h and the third hole 208h. Therefore, the depth h1' of the groove G may be greater than the thickness t1 of the first organic insulating layer 209. In an exemplary embodiment of the present disclosure, the depth of the groove G may be equal to or greater than about 1.5 μm. For example, the depth of the groove G may be equal to or greater than about 2 μm, and preferably, may be equal to or greater than about 3 μm.

[0160] Fig.11 is a plan view of a portion of a display panel 10 - 2 according to an exemplary embodiment of the present disclosure, and Fig.12 is along Fig.11 A cross-sectional view of a display panel 10 - 2 according to an exemplary embodiment of the present disclosure taken along line XII-XII′. Fig.13A and Fig. 13B 2 is a cross-sectional view of a manufacturing process of a display panel 10 - 2 according to an exemplary embodiment of the present disclosure, which shows a middle area MA.

[0161] refer to Fig.11 , a partition wall PW and at least one groove G may be provided in the middle area MA to surround the first area OA. Fig.11 The partition wall PW and the groove G in the arrangement are similar to Figure 8 The partition wall PW and the groove G are the same, but the shape of the first metal layer MTL1 is different from that of the first metal layer MTL2. Figure 8The partition wall PW and the groove G are different.

[0162] The first metal layer MTL1 may overlap the groove G in the middle area MA. Fig.11 In the embodiment, the first metal layer MTL1 may overlap the grooves G and the partition walls PW located between the grooves G.

[0163] In addition to the middle area MA, specifically the second middle sub-area SMA2, Fig.12 and Fig. 9 The same, and therefore the following description will focus on the second sub-middle area SMA2.

[0164] refer to Fig.12 In the middle area MA of the second sub-middle area SMA2, one or more grooves G may be located. The organic layer or multiple organic layers (e.g., the first functional layer 222a and / or the second functional layer 222c) included in the middle layer 222 may be disconnected (or separated) by the groove G. Therefore, moisture can be prevented from penetrating into the OLED through the first functional layer 222a and / or the second functional layer 222c. The counter electrode 223 and the cover layer 230 may also be disconnected by the groove G.

[0165] The groove G may be formed and defined in the multilayer film ML between the substrate 100 and the pixel electrode 221. The multilayer film ML may include: a first sublayer including an organic layer and a second sublayer including an inorganic layer. Fig.12 In FIG. 2 , the multilayer film ML includes a first metal layer MTL1 , an inorganic insulating layer 208 , a first organic insulating layer 209 , and a second metal layer MTL2 .

[0166] In the present exemplary embodiment, the first metal layer MTL1 may be positioned corresponding to the grooves G and the partition walls PW located between the grooves G. Fig.12 and Fig.13A , the groove G may include a first groove G1 located on a side of the partition wall PW close to the display area DA and a second groove G2 located on a side of the partition wall PW close to the first area OA. In this case, the first groove G1 and the second groove G2 may be grooves closest to the partition wall PW.

[0167] The first metal layer MTL1 may be located under the first and second grooves G1 and G2, and may extend to be located under the partition wall PW located between the first and second grooves G1 and G2. Since the first metal layer MTL1 is located not only under the first and second grooves G1 and G2, but also under the partition wall PW, Fig.12 The height from the substrate 100 to the top surface of the partition wall PW shown in FIG. 1 may be greater than Fig. 9 The height from the substrate 100 to the top surface of the partition wall PW is .

[0168] Although the first metal layer MTL1 is continuously located under the first groove G1, the partition wall PW, and the second groove G2, the first metal layer MTL1 may not be provided on the edge 10HE of the through portion 10H corresponding to the first area OA. This is because when the metal layer is located on the cutting line portion, in the scribing or cutting process for forming the through portion 10H, cutting is not easy. For example, when a laser cutting method is used and the metal layer is located on the cutting line portion, laser reflection may occur on the metal layer and it may not be easy to perform the cutting process on the film under the metal layer. On the other hand, the first metal layer MTL1 can reduce laser damage to other parts of the display panel 10-2. In an exemplary embodiment of the present disclosure, the first metal layer MTL1 may be provided along the edge 10HE of the through portion 10H corresponding to the first area OA (for example, near the edge 10HE, but not on the edge 10HE), and may overlap with the partition wall PW and a portion of the thin film encapsulation layer 300. Therefore, when the through portion 10H is formed, the first metal layer MTL1 may prevent the partition wall PW and the thin film encapsulation layer 300 from being damaged by laser or the like.

[0169] Will refer to Fig.12 and Fig.13A The groove G is described in detail. Fig.13A and Fig. 10A Similar, but the shape of the first metal layer MTL1 is different from Fig. 10A will no longer be given the same Fig. 10A Explanation of those elements that are the same as those of the preceding elements is repeated, and the following description will mainly focus on the differences between them.

[0170] refer to Fig.12 and Fig.13A , the first groove G1 and the second groove G2 of the multilayer film ML may be formed before the process of forming the intermediate layer 222. Each of the first groove G1 and the second groove G2 may have an undercut structure. Each of the first groove G1 and the second groove G2 may have a first hole 210h formed in the second metal layer MTL2 and a groove or a second hole 209h formed in the first organic insulating layer 209.

[0171] exist Fig.13A In the embodiment, the first hole 210h and the second hole 209h overlap each other to form each of the first groove G1 and the second groove G2. The bottom surface of each of the first groove G1 and the second groove G2 may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209, and in this regard, Fig.13A, the bottom surface of each of the first groove G1 and the second groove G2 is located on the same imaginary surface as the top surface 208a of the inorganic insulating layer 208. Here, the bottom surface of each of the first groove G1 and the second groove G2 has an imaginary surface, and the top surface 208a of the inorganic insulating layer 208 has a real surface. That is, each of the first groove G1 and the second groove G2 may expose at least a portion of the top surface 208a of the inorganic insulating layer 208.

[0172] The first opening 209OD and the second opening 208OD may be formed at both sides of each of the first groove G1 and the second groove G2, and the first metal layer MTL1 and the second metal layer MTL2 directly contacting each other through the first opening 209OD and the second opening 208OD may form an inorganic contact region ICR. Therefore, the inorganic contact region ICR may be formed of a metal-metal contact, thereby providing a better structure in preventing moisture from penetrating into the display area DA than a structure having a lower inorganic film (SiON) as a part of the inorganic contact region ICR.

[0173] The partition wall PW may be located between the first groove G1 and the second groove G2. The partition wall PW may include a plurality of sub-organic insulating layers stacked sequentially. Fig.13A As shown in , the partition wall PW may have a structure in which a portion MP of the first metal layer MTL1, a portion 208P of the inorganic insulating layer 208, a portion 209P of the first organic insulating layer 209, a portion 211P of the second organic insulating layer 211, a portion 215P of the pixel defining film 215, and a portion 217P of the spacer 217 are stacked.

[0174] refer to Fig. 13B , Fig. 13B The display panel 10-2' shown in FIG. Fig.13A The display panel 10 - 2 shown in FIG. 1 is different in that each of the first groove G1 and the second groove G2 is defined as a first hole 210 h , a second hole 209 h , and a third hole 208 h .

[0175] Each of the first groove G1 and the second groove G2 may include a first hole 210h formed in the second metal layer MTL2, a second hole 209h formed in the first organic insulating layer 209, and a third hole 208h formed in the inorganic insulating layer 208. The bottom surface of each of the first groove G1 and the second groove G2 may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209, and in this regard, Fig. 13BIn the embodiment, a bottom surface of each of the first and second grooves G1 and G2 is located on the same imaginary surface as the top surface MTL1a of the first metal layer MTL1. That is, each of the first and second grooves G1 and G2 may expose at least a portion of the top surface MTL1a of the first metal layer MTL1.

[0176] In the present exemplary embodiment, the depth h1′ of each of the first and second grooves G1 and G2 may be the same as the sum of the depths of the second and third holes 209h and 208h. The depth h1′ of each of the first and second grooves G1 and G2 may be greater than the thickness t1 of the first organic insulating layer 209 .

[0177] Fig.14A , Fig. 14B and Fig.15 is a cross-sectional view of a manufacturing process of a display panel according to an exemplary embodiment of the present disclosure, which shows a middle area MA. Fig.14A and 14B Shows Fig. 10A After the process.

[0178] Return to reference Fig. 9 , Fig. 10A and Fig.14A , the intermediate layer 222 may be formed after the groove G is formed. The first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may be integrally formed by using an open mask or the like to be positioned in the display area DA and the intermediate area MA. In this case, the first functional layer 222a and / or the second functional layer 222c may be disconnected or separated by the groove G. In an exemplary embodiment of the present disclosure, the intermediate layer 222 may be formed by a non-conformal deposition process, and therefore, the intermediate layer 222 may not be formed on the sidewalls of the first hole 210h, the second hole 209h, and / or the third hole 208h.

[0179] The layer including the organic material among the layers on the substrate 100 may become a path through which moisture penetrates. Although the first functional layer 222a and / or the second functional layer 222c include an organic layer and may become a penetration path, the first functional layer 222a and / or the second functional layer 222c are disconnected or separated by the groove G, and thus, moisture may be prevented from penetrating into the OLED through the first functional layer 222a and / or the second functional layer 222c. For example, the groove G may be configured to disconnect any organic layer formed above the second metal layer MTL2 to prevent moisture from penetrating into the OLED. Therefore, damage to the OLED disposed in the display area DA may be prevented by cutting off the penetration path of external moisture or oxygen.

[0180] Similar to the first functional layer 222 a and / or the second functional layer 222 c , the counter electrode 223 formed by thermal evaporation may also be disconnected by the groove G. The cap layer 230 including LiF may also be disconnected by the groove G.

[0181] Some of the layers disconnected (or separated) by the groove G may remain as a residual layer GP in the groove G. In an exemplary embodiment of the present disclosure, the residual layer GP in the groove G may include a portion 222aP of the first functional layer 222a, a portion 222cP of the second functional layer 222c, a portion 223P of the counter electrode 223, and a portion 230P of the capping layer 230.

[0182] In an exemplary embodiment of the present disclosure, Fig. 14B As shown in FIG. , when the cap layer 230 includes, for example, SiN x 、SiO x When the inorganic material of SiON or SiO2 is used, the cap layer 230 may be continuously formed without being interrupted by the groove G. In an exemplary embodiment of the present disclosure, the cap layer 230 may be conformally formed in the display area DA and the middle area MA by, for example, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process instead of a thermal evaporation process. In an exemplary embodiment of the present disclosure, the cap layer 230 may be omitted. Fig. 14B As shown in , when the capping layer 230 is continuously formed without being disconnected by the groove G, the residual layer GP may include a portion 222 aP of the first functional layer 222 a , a portion 222 cP of the second functional layer 222 c , and a portion 223P of the counter electrode 223 .

[0183] Fig.14A or Fig. 14B The structure of the intermediate layer 222, the counter electrode 223 and the cap layer 230 can be applied to Figures 11 to 13B An exemplary embodiment of .

[0184] refer to Fig. 9 and Fig.15 , a thin film encapsulation layer 300 may be formed. The thin film encapsulation layer 300 may cover the OLED in the display area DA and may prevent the OLED from being damaged or deteriorated by external impurities.

[0185] The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The first inorganic encapsulation layer 310 formed by a chemical vapor deposition (CVD) process or the like may have better step coverage than the first functional layer 222a, the second functional layer 222c and / or the counter electrode 223, and as Fig. 9 The first inorganic encapsulation layer 310 shown in FIG. 3 may be continuously formed. For example, the first inorganic encapsulation layer 310 may completely cover the inner surface of the groove G.

[0186] The organic encapsulation layer 320 may be formed by applying a monomer or a polymer to the substrate 100 and then curing the monomer or the polymer. The organic encapsulation layer 320 may extend from the display area DA to the middle area MA and may have a relatively flat surface. The end of the organic encapsulation layer 320 facing the first area OA may be positioned adjacent to one side of the partition wall PW. The partition wall PW may be used as a dam to prevent the end of the organic encapsulation layer 320 from overflowing to the edge of the substrate 100 (in the present exemplary embodiment, the boundary between the middle area MA and the first area OA).

[0187] The second inorganic encapsulating layer 330 may be located on the organic encapsulating layer 320 and may directly contact the first inorganic encapsulating layer 310 in a portion of the middle area MA. Fig. 9 and Fig.15 As shown in , in a portion of the middle area MA adjacent to the first area OA, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be in contact with each other. In the present exemplary embodiment, each of the first inorganic encapsulation layer 310, the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 is shown as a single layer, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, at least one of the first inorganic encapsulation layer 310, the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 may be provided in plurality or may be omitted.

[0188] refer to Fig. 9 In the cross-sectional view of the display panel 10-1, the first area OA may be surrounded. For example, when viewed in a direction perpendicular to the top surface of the substrate 100, Fig. 9 The groove G may have an annular shape surrounding the first area OA, such as Figure 8 . Likewise, when viewed in a direction perpendicular to the top surface of the substrate 100, the partition wall PW may have a ring shape surrounding the first area OA. Likewise, when viewed in a direction perpendicular to the top surface of the substrate 100, the inorganic contact region ICR may have a ring shape surrounding the first area OA. Likewise, when viewed in a direction perpendicular to the top surface of the substrate 100, Fig. 9 The element (eg, the element provided in the middle area MA) may have a ring shape surrounding the first area OA.

[0189] Fig.16 is a plan view of a portion of a display panel 10 - 3 according to an exemplary embodiment of the present disclosure, and Fig.17 is along Fig.16 1 is a cross-sectional view of a display panel 10 - 3 according to an exemplary embodiment of the present disclosure, taken along line XVII-XVII′.

[0190] refer to Fig.16, the partition wall PW and at least one groove G may be provided in the middle area MA to surround the first area OA. The at least one groove G may include a first groove G1 located on a side of the partition wall PW close to the display area DA and a second groove G2 and a third groove G3 located on a side of the partition wall PW close to the first area OA. In this case, the second groove G2 may be a groove closest to the partition wall PW among the grooves located on a side of the partition wall PW close to the first area OA.

[0191] The first metal layer MTL1 may overlap some of the grooves G1, G2, G3, and G′ in the middle area MA (see Fig.17 ). Although Fig.16 The first metal layer MTL1 overlaps the first groove G1 and the second groove G2, but the first metal layer MTL1 may not overlap the third groove G3. Fig.16 The first metal layer MTL1 does not overlap the first groove G1 and the second groove G2 continuously, but Fig.11 , Fig.12 , Fig.13A and Fig. 13B As shown in FIG, the first metal layer MTL1 may be integrally formed to also overlap with the partition wall PW. Fig.16 In the embodiment, the first metal layer MTL1 may be discontinuously located below the first groove G1 and the second groove G2, and Fig.11 , Fig.12 , Fig.13A and Fig. 13B As shown in FIG. 1 , the first metal layer MTL1 may be continuously located under the first groove G1 , the partition wall PW, and the second groove G2 .

[0192] The first metal layer MTL1 may include a first sub-metal layer MTL11 corresponding to the first groove G1 and a second sub-metal layer MTL12 corresponding to the second groove G2. The first sub-metal layer MTL11 may be located relatively adjacent to the display area DA, and the second sub-metal layer MTL12 may be located relatively adjacent to the first area OA. Each of the first sub-metal layer MTL11 and the second sub-metal layer MTL12 may have an annular shape surrounding the first area OA, and in this case, a diameter R11 of the first sub-metal layer MTL11 may be greater than a diameter R12 of the second sub-metal layer MTL12.

[0193] refer to Fig.17 , except for the features of the grooves G1, G2, G3 and G' located in the middle area MA, the display panel 10-3 is similar to Fig. 9 The display panel 10-1 is basically the same.

[0194] The display panel 10-3 may include three or more grooves G1, G2, G3, and G' in the middle area MA. The inorganic contact region ICR may be located between adjacent grooves G1, G2, G3, and G', and the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the capping layer 230 may be disconnected by each of the grooves G1, G2, G3, and G'.

[0195] The display panel 10-3 may include a through portion 10H formed in the first area OA, and the through portion 10H may be formed by removing elements located in the first area OA using a scribing or cutting process. The scribing or cutting process may be performed along a cutting line SCL, and Fig.17 The display panel 10 - 3 manufactured by performing a scribing or cutting process or the like along cutting lines SCL is shown.

[0196] The cutting line SCL may pass through one of the grooves G1, G2, G3, and G' (e.g., G'). In this case, a stacked structure including the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and / or the cap layer 230 disconnected by the groove G' may face the through portion 10H. In an exemplary embodiment of the present disclosure, the cutting line SCL may be located between two adjacent grooves G in the groove G, and in this case, the side surface of the display panel 10-3 defining the through portion 10H may be formed as shown in FIG. Fig. 9 as shown in .

[0197] Although the first sub-metal layer MTL11 corresponds to the first groove G1, and the second sub-metal layer MTL12 corresponds to the second groove G2, the first metal layer MTL1 may not be located under the third groove G3. That is, the first metal layer MTL1 may be located under the first groove G1 closest to the partition wall PW and close to the display area DA, may be located under the second groove G2 closest to the partition wall PW and close to the first area OA, and may not be located under other grooves (e.g., G3 and G').

[0198] The first metal layer MTL1 may not be located under the groove G' which is the outermost groove overlapping the cutting line SCL along which the scribing or cutting process is performed. This is because when the metal layer is located on the cutting line portion, it may not be easy to cut in the scribing or cutting process for forming the through portion 10H. For example, when a laser cutting method is used and the metal layer is located on the cutting line portion, laser reflection may occur on the metal layer and it may not be easy to perform the cutting process on the film under the metal layer.

[0199] According to whether the first metal layer MTL1 exists, a depth h2 of the third groove G3 under which the first metal layer MTL1 is not located may be greater than a depth h1 of each of the first and second grooves G1 and G2 under which the first metal layer MTL1 is located.

[0200] Although the bottom surface of the third groove G3 where the first metal layer MTL1 is not located is located at the same Fig.17 The third groove G3 is located on the same imaginary surface as the top surface of the second interlayer insulating layer 207 in the substrate 100, but in an exemplary embodiment of the present disclosure, the bottom surface of the third groove G3 may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of the first organic insulating layer 209. For example, the bottom surface of the third groove G3 may be located on an imaginary surface between the top surface of the substrate 100 and the top surface of at least one lower insulating layer under the first organic insulating layer 209. The at least one lower insulating layer may include an inorganic insulating layer 208.

[0201] Although Figures 8 to 17 Each of the display panels 10-1, 10-2, and 10-3 includes a through portion 10H corresponding to the first area OA, but in an exemplary embodiment of the present disclosure, as described above with reference to FIG. 4B to FIG. 4D As described above, each of the display panels 10 - 1 , 10 - 2 , and 10 - 3 may not have the first opening 10H corresponding to the first area OA.

[0202] The display panel 10 according to the exemplary embodiment of the present disclosure can prevent external impurities such as moisture from damaging the display elements in the display area DA However, this effect is only an example, and the effect according to the exemplary embodiment is described in detail through the description part.

[0203] It should be understood that the exemplary embodiments of the present disclosure described herein should be considered in a descriptive sense only, and not for limiting purposes. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects. Although exemplary embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising: A substrate, comprising a through hole, a display area, and an intermediate area between the through hole and the display area; A pixel circuit and a display element electrically connected to the pixel circuit, located in the display area, wherein the pixel circuit includes a thin film transistor TFT and a second electrode layer, the second electrode layer is a contact metal layer connecting the display element to the TFT, the TFT includes a semiconductor layer, a first gate electrode, a second gate electrode overlapping the semiconductor layer, and a first electrode layer, the first electrode layer includes a source electrode and a drain electrode electrically connected to the semiconductor layer, and the display element includes a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode and including an emission layer and at least one organic layer; a first inorganic insulating layer, located between the first electrode layer and the second electrode layer in the display area; a second metal layer, located in the middle region and disposed on the same layer as the second electrode layer; and a second inorganic insulating layer located in the middle region, wherein the first inorganic insulating layer and the second inorganic insulating layer are the same inorganic insulating layer located in the display region and the middle region respectively; Wherein, the second inorganic insulating layer is in direct contact with the at least one organic layer.

2. The display panel according to claim 1, wherein: The second metal layer has an opening defining an opening region in the middle region.

3. The display panel according to claim 2, wherein: A portion of the second inorganic insulating layer in direct contact with the at least one organic layer is located in the opening region.

4. The display panel according to claim 2, wherein: The opening has a closed curve shape surrounding the through hole.

5. The display panel according to claim 2, further comprising a thin film encapsulation layer covering the display element, the thin film encapsulation layer comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer, in, A side surface of the second metal layer is in direct contact with the first inorganic encapsulation layer.

6. The display panel according to claim 5, wherein: A portion of the organic encapsulation layer is located in the opening area.

7. The display panel according to claim 2, further comprising: A first metal layer is located in the middle region and is arranged on the same layer as the first electrode layer. Wherein, the first metal layer is in direct contact with the second metal layer through the opening area.

8. The display panel according to claim 7, further comprising: an organic insulating layer, located on the first inorganic insulating layer, Wherein, the first inorganic insulating layer is located between the first metal layer and the organic insulating layer.

9. The display panel according to claim 8, wherein: The organic insulating layer has a first hole or a first recess corresponding to the opening.

10. The display panel according to claim 9, wherein: The at least one organic layer is located in the first hole or the first concave portion and includes a portion of the at least one organic layer overlapping the first metal layer.

11. The display panel according to claim 9, wherein: The first hole exposes at least a portion of a top surface of the second inorganic insulating layer.

12. The display panel according to claim 9, wherein: The first hole extends into the second inorganic insulating layer and exposes at least a portion of a top surface of the first metal layer.

13. The display panel according to claim 9, wherein: The second inorganic insulating layer includes a second hole or a second recess corresponding to the first hole and passing through the second inorganic insulating layer.

14. The display panel according to claim 13, wherein: The organic insulating layer has a first contact hole, and the second inorganic insulating layer includes a second contact hole, and The first metal layer and the second metal layer are connected to each other through the first contact hole and the second contact hole.

15. The display panel according to claim 7, further comprising: a data line extending in a first direction and configured to transmit a data signal to the display element, The data line includes a material that is the same as a material of at least one of the first metal layer and the second metal layer.

16. The display panel according to claim 1, wherein: The at least one organic layer includes one or more of a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer.

17. The display panel according to claim 9, wherein: The first metal layer includes a floating metal disconnected from an electrical signal.

18. The display panel according to claim 17, wherein: The first metal layer has a ring shape surrounding the through hole.

19. The display panel according to claim 17, wherein: In a plan view, a width of the first metal layer is greater than a width of the first hole.

20. A display device, comprising: The display panel comprises a substrate, wherein the substrate comprises a through hole, a display area and an intermediate area between the through hole and the display area; as well as A component comprising an electronic component positioned corresponding to the through hole, Wherein, the display panel comprises: A pixel circuit and a display element electrically connected to the pixel circuit, located in the display area, wherein the pixel circuit includes a thin film transistor TFT and a second electrode layer, the second electrode layer is a contact metal layer connecting the display element to the TFT, the TFT includes a semiconductor layer, a first gate electrode, a second gate electrode overlapping the semiconductor layer, and a first electrode layer, the first electrode layer includes a source electrode and a drain electrode electrically connected to the semiconductor layer, and the display element includes a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode and including an emission layer and at least one organic layer; a first inorganic insulating layer, located between the first electrode layer and the second electrode layer in the display area; a second metal layer, located in the middle region and disposed on the same layer as the second electrode layer; and a second inorganic insulating layer located in the middle region, wherein the first inorganic insulating layer and the second inorganic insulating layer are the same inorganic insulating layer located in the display region and the middle region respectively; Wherein, the second inorganic insulating layer is in direct contact with the at least one organic layer.

21. A display panel, comprising: A substrate, comprising a through hole, a display area, and an intermediate area between the through hole and the display area; A thin film transistor TFT is arranged in the display area, and the TFT includes a semiconductor layer and a gate electrode. A display element connected to the TFT, the display element comprising a pixel electrode, a counter electrode, and an intermediate layer comprising at least one organic layer; A first wiring is arranged in the display area, wherein the first wiring and the gate electrode are arranged in the same layer; a first insulating layer covering the gate electrode and the first wiring; a second insulating layer, located on the first insulating layer; A second wiring is arranged on the second insulating layer; an inorganic insulating layer covering the second wiring on the second insulating layer and extending from the display area to the middle area; A third insulating layer, located on the inorganic insulating layer and in the display area; A contact metal layer is located on the third insulating layer and in the display area, and connects the TFT and the pixel electrode of the display element; as well as A second metal layer is located on the inorganic insulating layer and in the middle region, The residual organic layer is in direct contact with the inorganic insulating layer in the middle region, and the residual organic layer includes a material that is the same as that of the at least one organic layer.

22. The display panel according to claim 21, wherein: The second metal layer has an opening in the middle region.

23. The display panel according to claim 22, wherein: A portion of the inorganic insulating layer in direct contact with the residual organic layer is located in the opening.

24. The display panel according to claim 23, wherein: The opening has a closed shape surrounding the through hole.

25. The display panel according to claim 24, further comprising a thin film encapsulation layer covering the display element, the thin film encapsulation layer comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer and an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer, in, A side surface of the second metal layer is in direct contact with the first inorganic encapsulation layer.

26. The display panel according to claim 25, wherein: A portion of the organic encapsulation layer is located in the opening.

27. The display panel according to claim 21, wherein: The at least one organic layer is in direct contact with the upper surface of the second metal layer in the middle region.

28. The display panel according to claim 21, further comprising: A capacitor comprising a lower electrode and an upper electrode, The first insulating layer is disposed between the lower electrode and the upper electrode, and the second insulating layer covers the upper electrode.

29. The display panel according to claim 21, wherein: The inorganic insulating layer is in direct contact with the second wiring.

30. The display panel according to claim 21, wherein: The third insulating layer includes an organic insulating material.

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