Display device

Abstract

A display device is provided. The display device may include a substrate, a driving element layer on the substrate, and a light emitting element layer on the driving element layer. The light emitting element layer may include a pixel defining layer defining sub-pixels, a first electrode of each sub-pixel in an opening of the pixel defining layer, a heating wire disposed on the pixel defining layer to surround the first electrode of each sub-pixel, an intermediate layer covering the first electrode and the pixel defining layer in the opening and partially broken over the heating line; and a second electrode continuously covering the intermediate layer and the heating line between adjacent sub-pixels while covering the intermediate layer in the opening. The heating wire surrounds a pair of first electrodes corresponding to adjacent sub-pixels in the form of Euler traces.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0099318 filed in the Korean Intellectual Property Office on July 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] Wearable devices that form a focal point close to the user's eyes have been developed. For example, the wearable device may take the form of glasses or a helmet that may be a head-mounted display (HMD) device. The wearable device may provide an augmented reality (hereinafter referred to as "AR") screen or a virtual reality (hereinafter referred to as "VR") screen to the user.

[0005] Wearable devices such as HMD devices or AR glasses may require a display specification of at least 2000 PPI (pixels per inch) to avoid dizziness in users after using the wearable device for a long time. To this end, silicon-based organic light-emitting diode (OLEDoS) technology that provides high-resolution small organic light-emitting display devices is emerging. Silicon-based organic light-emitting diode (OLEDoS) technology can provide organic light-emitting diodes (OLEDs) on semiconductor wafer substrates in which or on which complementary metal oxide semiconductor (CMOS) devices can be manufactured.

[0006] When the distance between adjacent pixels is small, a display panel to which OLEDoS technology is applied may experience unexpected leakage current between adjacent pixels. The leakage current may pass through a conductive layer in an intermediate layer arranged between a pixel electrode (e.g., an anode of an OLED) and a common electrode (e.g., a cathode of an OLED), and is known to be the cause of color crosstalk between adjacent pixels. Summary of the invention

[0007] Embodiments of the present disclosure provide a display device for preventing leakage current and color crosstalk by disconnecting at least a portion of an intermediate layer disposed between a pixel electrode and a common electrode between adjacent pixels.

[0008] According to an embodiment of the present disclosure, a display device may include a substrate, a driving element layer arranged on the substrate, and a light-emitting element layer arranged on the driving element layer. The light-emitting element layer may include a pixel defining layer configured to define a plurality of sub-pixels, a first electrode of each sub-pixel arranged in an opening of the pixel defining layer, a heating line arranged on the pixel defining layer to surround the first electrode of each sub-pixel, an intermediate layer configured to cover the first electrode in the opening and the pixel defining layer and configured to be partially disconnected above the heating line, and a second electrode continuously arranged to cover the intermediate layer in the opening while covering the intermediate layer and the heating line between adjacent sub-pixels. The heating line is arranged to surround the pairs of first electrodes corresponding to adjacent sub-pixels in the form of an Euler trace.

[0009] A wiring layer including a power line and a ground line is arranged between the driving element layer and the light emitting element layer, and the power line and the ground line are arranged to cross between the sub-pixels arranged in the odd rows and the sub-pixels arranged in the even rows. The light emitting element layer may also include a first connection electrode configured to connect the starting point of the heating line to the power line through a first contact hole penetrating at least a portion of the pixel defining layer and the wiring layer, and a second connection electrode configured to connect the end point of the heating line to the ground line through a second contact hole penetrating at least a portion of the pixel defining layer and the wiring layer.

[0010] The start and end points of the heating lines are positioned between the sub-pixels arranged in the odd-numbered rows and the sub-pixels arranged in the even-numbered rows.

[0011] The heating line extends from the starting point to surround the second reference sub-pixel among the sub-pixels arranged in the even rows and is connected to the midpoint adjacent to the starting point, and the heating line extends from the midpoint to surround the first reference sub-pixel adjacent to the second reference sub-pixel among the sub-pixels arranged in the odd rows and is connected to the end point.

[0012] The midpoint of the heating line is arranged between the starting point and the end point.

[0013] When viewed in the normal direction of the substrate, the heating line has a shape of the letter "S" as the heating line extends from the start point to the end point via the midpoint.

[0014] The first electrode of each subpixel has an n-gonal shape (n is an integer greater than or equal to 4) when viewed in the normal direction of the substrate, and the heating line has an n-gonal shape spaced apart from the first electrode at a specific interval when viewed in the normal direction of the substrate.

[0015] The first electrode of each sub-pixel has a hexagonal shape when viewed in the normal direction of the substrate, and the heating line has a hexagonal shape spaced apart from the first electrode at a certain interval when viewed in the normal direction of the substrate.

[0016] The power lines are connected to power pads arranged in a non-display area of ​​the substrate, and the power pads may include a main pad to which a Joule heating voltage is applied and a plurality of sub-pads branched from the main pad and provided for respective groups obtained by uniformly dividing the plurality of power lines. The power lines included in the respective groups receive the Joule heating voltage through the sub-pads.

[0017] The power lines are connected to power pads arranged in a non-display area of ​​the substrate, and the power pads may include a plurality of group pads, to which a Joule heating voltage is applied and provided for each group obtained by evenly dividing the plurality of power lines, and the power lines included in each group receive the Joule heating voltage through the group pads.

[0018] According to an embodiment of the present disclosure, a display device may include a substrate, a driving element layer arranged on the substrate, and a light-emitting element layer arranged on the driving element layer. The light-emitting element layer may include a pixel defining layer configured to define a plurality of sub-pixels, a first electrode of each sub-pixel arranged in an opening of the pixel defining layer, a heating line arranged on the pixel defining layer to surround the opening of each sub-pixel, an intermediate layer configured to cover the first electrode in the opening and the pixel defining layer and configured to be partially disconnected above the heating line, and a second electrode continuously arranged to cover the intermediate layer in the opening while covering the intermediate layer and the heating line between adjacent sub-pixels. The heating line is arranged to surround the paired openings corresponding to the adjacent sub-pixels in the form of an Euler trace.

[0019] A wiring layer including a power line and a ground line is arranged between the driving element layer and the light emitting element layer, and the power line and the ground line are arranged to cross between the sub-pixels arranged in the odd rows and the sub-pixels arranged in the even rows. The light emitting element layer may also include a first connection electrode configured to connect the starting point of the heating line to the power line through a first contact hole penetrating at least a portion of the pixel defining layer and the wiring layer, and a second connection electrode configured to connect the end point of the heating line to the ground line through a second contact hole penetrating at least a portion of the pixel defining layer and the wiring layer.

[0020] A pixel may include a first emission region of a first sub-pixel displaying red light, a second emission region of a second sub-pixel displaying green light, and a third emission region of a third sub-pixel displaying blue light, the first emission region and the second emission region are arranged adjacent to each other in a column direction, the first emission region and the third emission region are arranged adjacent to each other in a row direction, and a third length of the third emission region in the column direction is greater than or equal to the sum of a first length of the first emission region in the column direction and a second length of the second emission region in the column direction.

[0021] The heating wire may include a first heating wire arranged to surround the first emission area and the second emission area in the form of an Euler track and a second heating wire arranged to surround the third emission area.

[0022] The first starting point and the first end point of the first heating line are arranged between the second emission area of ​​the pixels arranged in odd rows and the first emission area of ​​the pixels arranged in even rows, and the second starting point and the second end point of the second heating line are arranged between the third emission area of ​​the pixels arranged in odd rows and the third emission area of ​​the pixels arranged in even rows.

[0023] The first heating line extends from the first starting point to a midpoint between the first emission region and the second emission region, and extends from the midpoint to the first end point while surrounding the periphery of the second emission region.

[0024] The midpoint is arranged near a corner of the first emission region adjacent to the third emission region.

[0025] Each of the first to third emission regions has a rectangular shape in a plan view.

[0026] The power lines are connected to power pads arranged in a non-display area of ​​the substrate, and the power pads may include a main pad to which a Joule heating voltage is applied and a plurality of sub-pads branched from the main pad and provided for respective groups obtained by uniformly dividing the plurality of power lines. The power lines included in the respective groups receive the Joule heating voltage through the sub-pads.

[0027] The power lines are connected to power pads arranged in a non-display area of ​​the substrate, and the power pads may include a plurality of group pads, to which a Joule heating voltage is applied and provided for each group obtained by evenly dividing the plurality of power lines, and the power lines included in each group receive the Joule heating voltage through the group pads.

[0028] According to the display device according to the embodiment, leakage current and color crosstalk can be prevented by disconnecting at least a portion of the intermediate layer disposed between the pixel electrode and the common electrode between adjacent pixels.

[0029] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments with reference to the attached drawings.

[0031] Figure 1 is a perspective view showing a head mounted display device according to one embodiment.

[0032] Figure 2 It is shown Figure 1An exploded perspective view of an example of a head-mounted display device.

[0033] Figure 3 is a perspective view showing a head mounted display device according to one embodiment.

[0034] Figure 4 is an exploded perspective view showing a display device according to one embodiment.

[0035] Figure 5 It is shown Figure 4 Layout diagram of an example of a display panel shown in .

[0036] Figure 6 is a block diagram showing a display device according to one embodiment.

[0037] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to one embodiment.

[0038] Figure 8 A cross section of a portion of a display panel according to an embodiment is schematically shown.

[0039] Fig. 9 A power supply line arranged at the same layer as that of the reflective electrode according to one embodiment is shown.

[0040] Fig.10 A power supply line in a wiring layer is shown according to one embodiment.

[0041] Fig.11 A power supply line located in a buffer layer is shown according to one embodiment.

[0042] Fig.12 is a plan view of a heating wire according to one embodiment.

[0043] Fig.13 is a plan view showing a heating wire having a hexagonal shape.

[0044] Fig.14 is a plan view showing a power supply pad according to one embodiment.

[0045] Fig.15 is a plan view showing another shape of a power supply pad according to one embodiment.

[0046] Fig.16 is a plan view showing a heating wire according to one embodiment.

[0047] Fig.17 is a flowchart illustrating a method of manufacturing a display panel according to one embodiment.

[0048] Fig.18 , Fig.19 , Fig. 20 and Fig.21 are cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0049] Hereinafter, some specific embodiments according to the present disclosure are described more fully with reference to the accompanying drawings. The present disclosure should not be construed as being limited to the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey understanding to those skilled in the art.

[0050] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers may also be present.

[0051] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0052] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may interact with each other in various ways, and the corresponding embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0053] In the following, specific embodiments will be described with reference to the accompanying drawings. Features and components in the drawings may not be shown to scale and may be changed in shape or enlarged or reduced in size for clarity of illustration or explanation. The use of the same reference numerals throughout the drawings and description indicates the same or corresponding components.

[0054] Figure 1 is a perspective view showing a head mounted display device according to one embodiment. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted display device.

[0055] Reference Figure 1 and Figure 2 According to one embodiment, a head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0056] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figures 4 to 21 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to. Figures 4 to 21 Description instead.

[0057] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0058] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 may support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0059] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may receive an image source from outside the head mounted display device 1, convert the image source into digital video data DATA (see Figure 6 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0060] The control circuit board 170 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0061] The display device housing 110 may accommodate the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 may cover the open side of the display device housing 110. The housing cover 120 may include a first eyepiece 131 positioned for the user's left eye and a second eyepiece 132 positioned for the user's right eye. Figure 1 and Figure 2It is shown that the first eyepiece 131 and the second eyepiece 132 are separated, but the present disclosure is not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be integrated as a whole.

[0062] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the left eye of the user may observe the image of the first display device 10_1 magnified into a virtual image by the first optical member 151 through the first eyepiece 131, and the right eye of the user may observe the image of the second display device 10_2 magnified into a virtual image by the second optical member 152 through the second eyepiece 132.

[0063] The headband 140 can fix the display device housing 110 to the user's head in a position such that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are adjacent to the left eye and the right eye of the user, respectively. When the display device housing 110 is implemented as a light and small device, the headband 140 may not be required, and the head mounted display device 1 may instead include a headband such as Figure 3 The eyeglass frames shown in .

[0064] The head mounted display device 1 may further include a battery for supplying power, an external memory slot capable of accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) connector, a display port, or a high-definition multimedia interface (HDMI) connector, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0065] Figure 3 is a perspective view showing a head mounted display device according to one embodiment.

[0066] Reference Figure 3 The head mounted display device 1_1 according to one embodiment may be a glasses type display device in which the display device housing 120_1 is implemented as a lightweight and small device. The head mounted display device 1_1 according to one embodiment may include a display device 10_3, a left lens 311, a right lens 312, a support frame 350, temples 341 and 342, an optical member 320, an optical path changing member 330, and a display device housing 120_1.

[0067] Figure 3 The display device 10_3 shown in FIG. 1 can be used with reference to the following Figures 4 to 21 The display device 10 described is substantially the same. Therefore, a detailed description of some specific embodiments of the display device 10_3 is provided below with reference to Figures 4 to 21 provided in the description.

[0068] The display device housing 120_1 may include the display device 10_3, the optical member 320, and the optical path changing member 330. The image displayed on the display device 10_3 may be magnified by the optical member 320, may be observable along the optical path changed by the optical path changing member 330, and may be provided to the right eye of the user through the right lens 312. Therefore, the right eye of the user may observe an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right lens 312 are combined.

[0069] although Figure 3 The display device housing 120_1 at the right end of the support frame 350 is shown, but embodiments of the present disclosure are not limited thereto. For example, the display device housing 120_1 may be arranged at the left end of the support frame 350, in which case the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device housing 120_1 may be arranged at both the left and right ends of the support frame 350, in which case the user may observe the image displayed on the display device 10_3 through both the left and right eyes.

[0070] Figure 4 is an exploded perspective view showing a display device according to one embodiment. Figure 5 It is shown Figure 4 Layout diagram of an example of a display panel shown in . Figure 6 is a block diagram showing a display device according to one embodiment.

[0071] Reference Figure 4 and Figure 5 According to one embodiment, the display device 10 is a device capable of displaying a moving image or a still image. According to one embodiment, the display device 10 may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, and a head mounted display (HMD) for realizing virtual reality or augmented reality.

[0072] The display device 10 according to one embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power circuit 450 .

[0073] The display panel 410 may have a planar shape similar to a quadrilateral shape. For example, the display panel 410 may have a planar shape similar to a quadrilateral shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 at an angle to the first direction DR1. In the display panel 410, the corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be at right angles, or may be rounded with a predetermined curvature. The planar shape of the display panel 410 is not limited to a rectangular shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but embodiments of the present disclosure are not limited thereto.

[0074] like Figure 5 As shown in FIG. 4 , the display panel 410 includes a display area DAA and a non-display area NDA. The display area DAA is used to display an image, and the non-display area NDA does not display an image.

[0075] The display area DAA includes a plurality of pixels PX or sub-pixels SP, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0076] Each of the pixels PX or sub-pixels SP may include a Figure 7 , a light emitting element LE emitting light is shown in FIG. A plurality of pixels PX may be arranged in a matrix or array form having rows extending in a first direction DR1 and columns extending in a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged or spaced apart in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged or spaced apart in the first direction DR1.

[0077] like Figure 6 As shown in , the plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL may include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0078] Each of the plurality of pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3 (see Fig. 9 ). Each of the sub-pixels SP1, SP2 and SP3 may include Figure 7 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 may be formed by a semiconductor process and arranged on a semiconductor substrate SSUB (see FIG. 2 ). Figure 8 For example, a plurality of pixel transistors may be formed as complementary metal oxide semiconductor (CMOS) devices.

[0079] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to one of the plurality of write scan lines GWL, one of the plurality of control scan lines GCL, one of the plurality of bias scan lines EBL, one of the plurality of first emission control lines EL1, one of the plurality of second emission control lines EL2, and one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage from a connected one of the data lines DL in response to a write scan signal of the connected write scan line GWL, and may emit light from its light emitting element LE according to the data voltage.

[0080] like Figure 5 As shown in FIG. 1 , the non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0081] The scan driving area SDA may be an area where the scan driver 510 and the emission driver 520 are arranged. Figure 5 The scan driver 510 on the left side of the display area DAA and the emission driver 520 on the right side of the display area DAA are shown, but the embodiments of the present disclosure are not limited thereto. For example, both the scan driver 510 and the emission driver 520 may be on the left and / or right side of the display area DAA.

[0082] The scan driver 510 includes a plurality of scan transistors, and the emission driver 520 includes a plurality of emission control transistors. The plurality of scan transistors and the plurality of emission control transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 8 For example, the plurality of scan transistors and the plurality of emission control transistors may be CMOS devices.

[0083] like Figure 6As shown in , the scan driver 510 may include a write scan signal output unit 511, a control scan signal output unit 512, and a bias scan signal output unit 513. Each of the write scan signal output unit 511, the control scan signal output unit 512, and the bias scan signal output unit 513 may receive a scan timing control signal SCS from the timing controller 610. The write scan signal output unit 511 may generate a write scan signal in response to the scan timing control signal SCS from the timing controller 610, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 512 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 513 may generate a bias scan signal in response to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0084] The emission driver 520 includes a first emission control driver 521 and a second emission control driver 522. Each of the first emission control driver 521 and the second emission control driver 522 may receive an emission timing control signal ECS from the timing controller 610. The first emission control driver 521 may generate a first emission control signal in response to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 522 may generate a second emission control signal in response to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line EL2.

[0085] The data driving area DDA may be an area where the data driver 530 is arranged. The data driver 530 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 8 For example, the plurality of data transistors may be CMOS devices.

[0086] The data driver 530 may receive digital video data DATA and a data timing control signal DCS from the timing controller 610. The data driver 530 may convert the digital video data DATA into an analog data voltage in response to the data timing control signal DCS, and may output the analog data voltage to the data line DL. In an embodiment where each pixel has three sub-pixels SP1, SP2, and SP3, the sub-pixels SP1, SP2, and SP3 are selected by a write scan signal of the scan driver 510, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0087] The pad area PDA includes a plurality of pads PD that may be linearly distributed along the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover member CV (see Figure 8 ) and polarizer cover.

[0088] like Figure 4 As shown in FIG. 1 , the heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be arranged on one surface (e.g., the rear surface) of the display panel 410. The heat dissipation layer 420 is used to dissipate the heat generated by the display panel 410. The heat dissipation layer 420 may include a layer of a metal such as graphite, silver (Ag), copper (Cu), or aluminum (Al) or other highly thermally conductive material.

[0089] The circuit board 430 may be electrically connected to the plurality of pads PD in the pad area PDA of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film including a flexible material. Figure 4 The circuit board 430 is shown as being unfolded or flat, but the circuit board 430 may be bent. For example, one end of the circuit board 430 may be located on or adjacent to the rear surface of the display panel 410. The end of the circuit board 430 bent behind the display panel 410 may be opposite to the end of the circuit board 430 connected to the plurality of pads PD of the pad area PDA of the display panel 410 by the conductive adhesive member.

[0090] The timing controller 610 may receive digital video data DATA and a timing signal from outside the display device 10. The timing controller 610 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 410 in response to the timing signal. The timing controller 610 may output the scan timing control signal SCS to the scan driver 510, and output the emission timing control signal ECS to the emission driver 520. The timing controller 610 may output the digital video data DATA and the data timing control signal DCS to the data driver 530.

[0091] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a power supply voltage from outside the display device 10. For example, the power supply circuit 450 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 410. Figure 7 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are further described.

[0092] Each of the timing controller 610 and the power supply circuit 450 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 430. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS from the timing controller 610 may be supplied to the display panel 410 through the circuit board 430. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT from the power supply circuit 450 may be supplied to the display panel 410 through the circuit board 430.

[0093] Figure 7 is an equivalent circuit diagram of a sub-pixel according to one embodiment. The equivalent circuit diagram can be applied to any sub-pixel SP1, SP2 or SP3 (see Fig. 9 ),but Figure 7 The first sub-pixel SP1 is shown to provide a specific example.

[0094] Reference Figure 7 , the first sub-pixel SP1 may be connected to a write scan line GWL, a control scan line GCL, a bias scan line EBL, a first emission control line EL1, a second emission control line EL2, and a data line DL associated with the first sub-pixel SP1. In addition, the first sub-pixel SP1 may be connected to a first drive voltage VSS (see Figure 6 ) and a first driving voltage line VSL to which a second driving voltage VDD corresponding to a high potential voltage is applied (see Figure 6 ) and a second driving voltage line VDL to which a third driving voltage VINT corresponding to an initialization voltage is applied (see Figure 6 ). That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be a voltage lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0095] The first sub-pixel SP1 includes a light emitting element LE and a pixel driving circuit PC connected to the light emitting element LE. The pixel driving circuit PC includes a plurality of transistors T1 to T6, a first capacitor C1, and a second capacitor C2.

[0096] The light emitting element LE emits light in response to a driving current flowing through the channel of the first transistor T1. The emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode, but the embodiments of the present disclosure are not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode, and in this case, the light emitting element LE may be a micro light emitting diode. The light emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode (or a pixel electrode), and the second electrode of the light emitting element LE may be a cathode (or a common electrode).

[0097] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode in response to a voltage applied to a gate electrode. The first transistor T1 has a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0098] The second transistor T2 may be arranged between the data line DL and one electrode of the first capacitor C1. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0099] The third transistor T3 may be arranged between the first node N1 and the second node N2. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1. The control scan signal of the control scan line GCL can turn on the third transistor T3 to connect the first node N1 to the second node N2. Therefore, the gate electrode and the drain electrode of the first transistor T1 may be connected so that the first transistor T1 operates as a diode.

[0100] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3. The fourth transistor T4 may be turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current of the first transistor T1 may be supplied to the light emitting element LE.

[0101] The fifth transistor T5 may be arranged between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL. The fifth transistor T5 may be turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE.

[0102] The sixth transistor T6 may be arranged between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1. The sixth transistor T6 may be turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1.

[0103] The first capacitor C1 is located between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0104] The second capacitor C2 is located between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0105] The first node N1 is a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0106] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of the present disclosure are not limited thereto. For example, each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, among the first transistor T1 to the sixth transistor T6, some transistors may be P-type MOSFETs, and other transistors may be N-type MOSFETs.

[0107] although Figure 7 The first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors C1 and C2, but the first sub-pixel SP1 is not limited to Figure 7 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 7 Those shown in .

[0108] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 7 The described equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 will be redundant and omitted in the present disclosure.

[0109] Figure 8 Schematically shows a cross section of a portion of a display panel according to an embodiment. For example, Figure 8 4 is a diagram schematically illustrating a stack structure suitable for each of the non-display area NDA and the display area DAA of the display panel 410 according to one embodiment.

[0110] In reference Figure 8 In the description of , the term “on” may refer to a third direction DR3 in which the front surface of the substrate SSUB faces. The front surface of the substrate SSUB may refer to a direction in which the light emitting elements LE arranged in the display area DAA emit light for displaying an image.

[0111] Reference Figure 8 , the display panel 410 according to one embodiment may include a substrate SSUB, and the substrate SSUB may be a semiconductor wafer substrate.

[0112] A driving element layer 801, at least one wiring layer 802, a light emitting element layer 803 including a light emitting element LE, an encapsulation layer 804 covering the light emitting element LE, a color filter layer 805 including a color filter CF, a light control layer 806 including a refractive layer MLA, and a covering layer 807 including a covering member CV may be sequentially stacked on the front surface of the substrate SSUB. At least some of the light emitting element layer 803, the encapsulation layer 804, the color filter layer 805, the light control layer 806, and the covering layer 807 may be located in the display area DAA, but may not exist in the non-display area NDA.

[0113] The substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The substrate SSUB may be a substrate doped with a first type impurity. The first type impurity may be a P type impurity, and the second type impurity may be an N type impurity. Alternatively, the first type impurity may be an N type impurity, and the second type impurity may be a P type impurity.

[0114] The driving element layer 801 including N-type MOSFET and / or P-type MOSFET is arranged on the substrate SSUB. The scanning driver 510 (see Figure 6 ) can be arranged in the driving element layer 801. The emission driver 520 (see Figure 6 ) can be arranged in the driving element layer 801. Figure 7 The plurality of pixel transistors T1 to T6 described (see Figure 7 ) may be arranged in the driving element layer 801. The data driver 530 (see Figure 6 ) may be arranged in the driving element layer 801. Therefore, the driving element layer 801 may include a scan transistor of the scan driver 510, an emission control transistor of the emission driver 520, a pixel transistor of the pixel circuit, and a data transistor of the data driver 530.

[0115] For simplicity of description, Figure 8 4 shows a plurality of pixel transistors T1 to T6 arranged in a display area DAA of a display panel 410 (see Figure 7 ) as an example. In addition, as an example, Figure 8 An N-type MOSFET MOS is shown among the transistors included in the driving element layer 801 .

[0116] The N-type MOSFET MOS may include a well region W1 doped with N-type impurities in a substrate SSUB doped with P-type impurities. The well region W1 may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having a relatively low impurity concentration compared to other portions. The first low-concentration impurity region LDD1 may define a source region S1, and the second low-concentration impurity region LDD2 may define a drain region D1. A source electrode SE of the MOSFET MOS may be connected to the source region S1, and a drain electrode DE of the MOSFET MOS may be connected to the drain region D1.

[0117] The channel CH arranged to overlap the gate G1 is located between the first low concentration impurity region LDD1 and the second low concentration impurity region LDD2 in the well region W1. An insulating layer (not shown) which may be an oxide layer may be arranged between the gate G1 and the well region W1.

[0118] At least one wiring layer 802 is arranged on the driving element layer 801. The at least one wiring layer 802 includes a plurality of insulating layers VIA sequentially stacked on the driving element layer 801, and a connection electrode CE and a line (not shown) connected to the MOSFET MOS through a contact hole CT1 penetrating at least a portion of the plurality of insulating layers VIA. That is, the wiring layer 802 includes a connection electrode CE and a connection line that connect the MOSFET MOS of the driving element layer 801 to each other, and an insulating layer VIA for insulating the connection electrode CE and the connection line from each other. In addition, the wiring layer 802 may include a plurality of power supply lines 910 (see Fig.14 ) and a plurality of signal lines for driving the display panel 410.

[0119] Figure 8 The connection electrode CE shown in FIG. 8 is connected to a plurality of pixel transistors T1 to T6 (see FIG. 8 ) arranged in the driving element layer 801. Figure 7 ) are connected in a vertical direction to the light emitting elements LE arranged on the wiring layer 802. Here, the vertical direction refers to the normal direction of the display panel 410 (ie, the third direction DR3).

[0120] The wires (not shown) arranged in the wiring layer 802 may include, for example, wires GWL, GCL, EBL, EL1, EL2, VIL, VSL, and VDL (see FIG. 1 ) connected to the pixel driving circuit PC. Figure 7 ).

[0121] The wiring layer 802 may include pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 located in the non-display area NDA. The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 may include a first gate pad PD1 connected to the write scan line GWL, a second gate pad PD2 connected to the control scan line GCL, a third gate pad PD3 connected to the bias scan line EBL, a first emission control pad PD4 connected to the first emission control line EL1, a second emission control pad PD5 connected to the second emission control line EL2, a first drive voltage pad PD6 connected to the first drive voltage line VSL, and a second drive voltage pad PD7 connected to the second drive voltage line VDL. However, Figure 8 The pad electrodes PD1 , PD2 , PD3 , PD4 , PD5 , PD6 , and PD7 shown in FIG. 1 are merely examples, and the present disclosure is not limited thereto.

[0122] A planarization layer FL including an organic layer may be disposed on the uppermost layer among the insulating layers VIA included in the wiring layer 802 , but the present disclosure is not limited thereto.

[0123] The plurality of sub-pixels SP are defined (see Figure 6 ) and a light emitting element layer 803 of the light emitting element LE may be arranged on the wiring layer 802. The light emitting element LE includes a first electrode ANE connected to a MOSFET MOS included in the pixel driving circuit PC through a contact hole CT2 and a connection electrode CE, an intermediate layer ML arranged on the first electrode ANE, and a second electrode CAE arranged on the intermediate layer ML. The pixel defining layer PDL may include openings OP (see Fig. 9 ), and the first electrode ANE of the light emitting element LE may be exposed through each opening OP during the process.

[0124] The middle layer ML may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer, but the present disclosure is not limited thereto. For example, the light emitting element LE may be a light emitting element 200 from the first sub-pixel SP1 (see Fig. 9 ) (eg, a red pixel) emits a first color light (eg, red light), and a second sub-pixel SP2 (eg, a red pixel) emits a first color light (eg, red light). Fig. 9 ) (eg, a green pixel) emits a second color light (eg, green light), and a third sub-pixel SP3 (see Fig. 9 )(e.g., blue pixel) emits a third color light (e.g., blue light). Alternatively, the light emitting element LE may be a WOLED type light emitting element in which white light is emitted from the first sub-pixel SP1 (e.g., red pixel), the second sub-pixel SP2 (e.g., green pixel) and the third sub-pixel SP3 (e.g., blue pixel).

[0125] The stack structure of the organic material included in the middle layer ML may include a different structure depending on whether the light emitting element LE is an RGB type or a WOLED (white OLED) type, but the present disclosure is not limited thereto.

[0126] A heating line 810 is disposed on the pixel defining layer PDL, and the heating line 810 disconnects the middle layer ML of the light emitting element LE between adjacent sub-pixels SP during the process. The disconnection of the middle layer ML occurs during the process of applying the Joule heating voltage to the heating line 810. The process of applying the Joule heating voltage to the heating line 810 may be performed after depositing the middle layer ML.

[0127] According to one embodiment, the heating line 810 is electrically connected to the power line 910 through the first connection electrode 821 arranged to vertically penetrate the pixel defining layer PDL (see Figures 9 to 11 ). The heating line 810 is configured to receive a Joule heating voltage through the power line 910 and the first connection electrode 821, and generate heat based on the input Joule heating voltage. The Joule heating voltage and the current generated thereby cause the temperature of the heating line 810 to rise to a high temperature, for example, about 400° C. or higher, and the intermediate layer ML deposited on and around the heating line 810 can be removed by the high temperature.

[0128] In one embodiment, leakage current and color crosstalk between adjacent sub-pixels SP can be prevented by disconnecting the intermediate layer ML of the light-emitting element LE between adjacent sub-pixels SP. The color crosstalk phenomenon refers to, for example, a phenomenon in which a red pixel (e.g., a first sub-pixel SP1) adjacent to a blue pixel (e.g., a third sub-pixel SP3) is accidentally turned on while the blue pixel is emitting blue light. The color crosstalk phenomenon due to leakage current may occur when the blue pixel and the red pixel adjacent to each other have a large difference in driving voltage. For example, leakage current is a phenomenon in which a portion of the driving current is sent to the red pixel (e.g., the first sub-pixel SP1) through at least some conductive layers of the intermediate layer ML while the driving current is being supplied to the light-emitting element LE of the blue pixel so as to turn on the blue pixel. If leakage current occurs, the red pixel may be accidentally turned on while the blue pixel is being turned on.

[0129] The encapsulation layer 804, which may include at least one organic encapsulation layer and at least one inorganic encapsulation layer, may be located on the light emitting element layer 803. For example, the encapsulation layer 804 may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3, but the present disclosure is not limited thereto.

[0130] A color filter layer 805 including a color filter CF may be disposed on the encapsulation layer 804. The color filter CF may include a first color filter that transmits red light, a second color filter that transmits green light, and a third color filter that transmits blue light, but the present disclosure is not limited thereto. When the light-emitting element LE of the light-emitting element layer 803 is a WOLED type light-emitting element, the color filter layer 805 may be provided. If the light-emitting element LE of the light-emitting element layer 803 is an RGB type light-emitting element that directly emits red light, green light, and blue light, the color filter layer 805 may be omitted.

[0131] The light control layer 806 including the refraction layer MLA is disposed on the color filter layer 805. The refraction layer MLA may refract light emitted from the light emitting element layer 803 toward a normal direction (ie, a third direction DR3) of the display panel 410. The refraction layer MLA may include a micro lens array.

[0132] A cover layer 807 serving as a cover of the display panel 410 may be disposed on the light control layer 806. The cover layer 807 may include a cover member CV made of glass, but the present disclosure is not limited thereto. The cover layer 807 may include, for example, a protective film.

[0133] Fig. 9 is a cross-sectional view showing a power supply line arranged at the same layer as that of a reflective electrode according to one embodiment.

[0134] Reference Fig. 9 The reflective electrode RL is located on the insulating layer VIA included in the wiring layer 802 and is patterned to form a region corresponding to each of the sub-pixels SP1, SP2, and SP3. According to one embodiment, the reflective electrode RL may include a first reflective electrode RL1, a second reflective electrode RL2, and a third reflective electrode RL3 sequentially stacked on the insulating layer VIA.

[0135] The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0136] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0137] The third reflective electrode RL3 may be arranged on the second reflective electrode RL2. The third reflective electrode RL3 may include a metal having a high reflectivity to facilitate reflection of light. The third reflective electrode RL3 may be formed of aluminum (Al); a stacked structure of aluminum and titanium (Ti / Al / Ti); a stacked structure of aluminum and ITO (ITO / Al / ITO); an APC alloy which is an alloy of silver (Ag), palladium (Pd), and copper (Cu); and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present disclosure is not limited thereto.

[0138] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0139] According to one embodiment, the power line 910 may be arranged to correspond to between adjacent sub-pixels SP1, SP2, and SP3. The power line 910 may be arranged at the same layer as the reflective electrode RL. For example, the power line 910 and the reflective electrode RL may be formed of the same material through the same process.

[0140] According to one embodiment, a difference layer IL may be disposed on the reflective electrode RL. The difference layer IL may include a first difference layer IL1 and a second difference layer IL2 disposed on the first difference layer IL1. The difference layer IL may be commonly stacked in the first sub-pixel SP1 and the second sub-pixel SP2, but may not be stacked or exist in the third sub-pixel SP3.

[0141] The difference layer IL may be used to change the first electrode ANE (see FIG. 1 ) for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Figure 8 ) and the reflective electrode RL. In the first sub-pixel SP1, the first difference layer IL1, the second difference layer IL2, and the first electrode ANE1 of the first sub-pixel SP1 may be sequentially stacked on the reflective electrode RL. In the second sub-pixel SP2, the second difference layer IL2 and the first electrode ANE2 of the second sub-pixel SP2 may be sequentially stacked on the reflective electrode RL. In the third sub-pixel SP3, the first electrode ANE3 of the third sub-pixel SP3 may be arranged on the reflective electrode RL. Therefore, for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode ANE and the reflective electrode RL may be different. For example, due to the difference in the thickness of the difference layer IL, the distance between the first electrode ANE and the reflective electrode RL may be the longest in the first sub-pixel SP1 and the shortest in the third sub-pixel SP3.

[0142] According to one embodiment, a pixel defining layer PDL defining the sub-pixels SP1, SP2, and SP3 is disposed on the first electrodes ANE1, ANE2, and ANE3 and the difference layer IL. The pixel defining layer PDL may cover both ends of each of the first electrodes ANE1, ANE2, and ANE3 of the corresponding sub-pixels SP1, SP2, and SP3. In an opening OP passing through the pixel defining layer PDL, each of the first electrodes ANE1, ANE2, and ANE3 is disposed to be partially exposed during a process.

[0143] The heating line 810 is arranged on the pixel defining layer PDL between adjacent sub-pixels SP1, SP2, and SP3. The heating line 810 may surround each of the first electrodes ANE1, ANE2, and ANE3 of the corresponding sub-pixels SP1, SP2, and SP3. The heating line 810 may be electrically connected to the power line 910 via the first connection electrode 821. The first connection electrode 821 connects the heating line 810 to the power line 910 through a first contact hole CT821 that penetrates the pixel defining layer PDL and a portion of the wiring layer (e.g., the difference layer IL).

[0144] In the display panel 410 according to one embodiment, the heating line 810 is arranged in the area between the sub-pixels SP1, SP2 and SP3 to prevent leakage current. When the heating line 810 arranged between the adjacent sub-pixels SP1, SP2 and SP3 is electrically driven, heat and high temperature are generated. The generated high temperature disconnects at least some of the conductive layers included in the middle layer ML. According to the present disclosure, leakage current and color interference can be prevented by disconnecting at least some of the conductive layers included in the middle layer ML around the heating line 810. In the present disclosure, at least some of the conductive layers of the middle layer ML disconnected around the heating line 810 may include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.

[0145] According to one embodiment, the middle layer ML of the light emitting element LE is arranged on the first electrodes ANE1, ANE2 and ANE3. The middle layer ML covers the first electrodes ANE1, ANE2 and ANE3 in the opening OP of the pixel defining layer PDL, and covers the pixel defining layer PDL around the adjacent sub-pixels SP1, SP2 and SP3. However, in the case where the middle layer ML covers the pixel defining layer PDL, the middle layer ML is partially disconnected above the heating line 810. Therefore, the middle layer ML is commonly arranged in the sub-pixels SP1, SP2 and SP3, but the middle layer ML is partially disconnected above the heating line 810 arranged between the adjacent sub-pixels SP1, SP2 and SP3.

[0146] According to one embodiment, the second electrode CAE is arranged on the intermediate layer ML. The second electrode CAE may be commonly arranged in the sub-pixels SP1, SP2, and SP3. The second electrode CAE may be a common layer in which a plurality of sub-pixels SP1, SP2, and SP3 are connected to each other. Specifically, the second electrode CAE may continuously cover the intermediate layer ML and the heating line 810 between adjacent sub-pixels SP1, SP2, and SP3 while covering the intermediate layer ML in the opening OP of the pixel defining layer PDL.

[0147] Fig.10 is a cross-sectional view showing a power supply line located in a wiring layer according to one embodiment.

[0148] Fig.10 The implementation method and Fig. 9 The difference in the implementation method is that Fig.10 The power supply line 910 in the embodiment of FIG. 8 is arranged in the wiring layer 802. Fig.10 The description of the implementation method will be omitted Fig. 9 redundant description of the implementation methods of Fig.10 differences in the implementation of the

[0149] Reference Fig.10 , the power supply line 910 may be arranged in the wiring layer 802 (see Figure 8 ) on any one of the insulating layers VIA. For example, the power line 910 may be connected to the reference Figure 8 Any of the described lines and the connection electrode CE are arranged in the same layer.

[0150] According to one embodiment, the power line 910 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or an alloy containing any one of them.

[0151] Fig.11 is a diagram showing an arrangement of power lines in a buffer layer according to one embodiment.

[0152] Fig.11 The implementation method and Fig. 9 The difference in the implementation method is that Fig.11 The power line 910 in the embodiment of the present invention is arranged in the buffer layer BFL. Fig.11 The description of the implementation method will be omitted Fig. 9 redundant description of the implementation methods of Fig.11 differences in the implementation of the

[0153] Reference Fig.11The display panel 410 may further include a buffer layer BFL between the wiring layer 802 and the reflective electrode RL. The power line 910 may be arranged in the buffer layer BFL. The buffer layer BFL may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0154] According to one embodiment, the power line 910 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or an alloy containing any one of them.

[0155] Fig.12 is a plan view for describing an S-shaped pattern of a heating line according to one embodiment. Fig.13 is a plan view showing heating lines in a hexagonal shape pattern.

[0156] Reference Fig.12 , each of the sub-pixels SP may include a first electrode ANE. Figure 8 ), the first electrode ANE of each sub-pixel SP may have a hexagonal structure having a hexagonal shape in a plan view.

[0157] According to one embodiment, each heating line 810 is arranged to surround the pair of first electrodes ANE_A and ANE_B corresponding to the adjacently arranged sub-pixels SP in the form of an Euler track. The Euler track form means that the lines are arranged in a form such that the line or path passes once and does not pass again. Therefore, each heating line 810 surrounding the pair of adjacent first electrodes ANE_A and ANE_B is arranged to pass only once through the starting point P1, the midpoint P2, and the end point P3. According to one embodiment, when viewed in the normal direction of the substrate SSUB, as the heating line 810 extends from the starting point P1 via the midpoint P2 to the end point P3, the heating line 810 may have the shape of the letter "S".

[0158] In the present disclosure, the starting point P1, the midpoint P2, and the end point P3 are preferably understood as virtual points representing some points on each heating line 810. For example, the starting point P1 may be a point where the heating line 810 is connected to the power line 910, and may be one end of the heating line 810. The end point P3 may be a point where the heating line 810 is connected to the ground line 920, and may be the other end of the heating line 810. The midpoint P2 may be a point that divides the entire length of the heating line 810 into two. The distance from the midpoint P2 to the starting point P1 may be substantially equal to the distance from the midpoint P2 to the end point P3.

[0159] According to one embodiment, the wiring layer 802 includes a power line 910 and a ground line 920. The power line 910 and the ground line 920 may be arranged to cross between the sub-pixels SP_ODD arranged in the odd rows and the sub-pixels SP_EVEN arranged in the even rows. The starting point P1 of the heating line 810 is connected to the power line 910 through the first connection electrode 821 arranged in the first contact hole CT821. The end point P3 of the heating line 810 is connected to the ground line 920 through the second connection electrode 822 arranged in the second contact hole CT822. Therefore, the starting point P1 and the end point P3 of each heating line 810 may be arranged between the sub-pixels SP_ODD arranged in the odd rows and the sub-pixels SP_EVEN arranged in the even rows.

[0160] According to one embodiment, the heating line 810 extends from the starting point P1 to surround the second reference sub-pixel (or the first electrode ANE_A of the second reference sub-pixel) among the sub-pixels SP_EVEN arranged in the even-numbered rows and is connected to the midpoint P2 adjacent to the starting point P1. The heating line 810 extends from the midpoint P2 to surround the first reference sub-pixel (or the first electrode ANE_B of the first reference sub-pixel) adjacent to the second reference sub-pixel among the sub-pixels SP_ODD arranged in the odd-numbered rows and is connected to the end point P3. In this case, the midpoint P2 of the heating line 810 is arranged between the starting point P1 and the end point P3. Therefore, when viewed in the normal direction of the substrate SSUB, as the heating line 810 extends from the starting point P1 to the end point P3 via the midpoint P2, the heating line 810 may have the shape of the letter "S".

[0161] In one embodiment of the present disclosure, each heating line 810 is arranged to surround the paired first electrodes ANE_A and ANE_B corresponding to the adjacently arranged sub-pixels SP in the form of an Euler trace. Therefore, the length of each heating line 810 can be reduced. In addition, because the length of the heating line 810 is reduced, the Joule heating voltage can be reduced. For example, when the heating line 810 surrounds a plurality of sub-pixels SP in a grid form, its resistance and length increase. Therefore, a Joule heating voltage of about 3300V may be required. On the other hand, in one embodiment of the present disclosure, each heating line 810 is driven with a Joule heating voltage of about 6V, and the driven heating line 810 can be used to disconnect the middle layer ML.

[0162] According to the example shown, each heating line 810 surrounds the periphery of the first electrode ANE in a circular shape, but the present disclosure is not limited thereto. For example, the shape in which each heating line 810 surrounds the first electrode ANE may depend on the structure or shape of the first electrode ANE. For example, when viewed in the normal direction of the substrate SSUB, the first electrode ANE of each sub-pixel SP may have an n-gon shape (n is an integer greater than or equal to 4). The heating line 810 may have an n-gon shape spaced apart from the first electrode ANE at a specific interval. Therefore, as Fig.13 As shown in , when the first electrode ANE of each sub-pixel SP has a hexagonal structure, the heating line 810 may have a hexagonal shape spaced apart from the first electrode ANE at a certain interval.

[0163] According to one embodiment, the power supply line 910 may be connected to the power supply pad JPD arranged in the non-display area of ​​the substrate SSUB. In order to reduce the current when the Joule heating voltage is applied, the power supply pad JPD may be divided into a plurality of parts instead of being provided as a single part. Fig.14 and Fig.15 Detailed Description Division of a power supply pad JPD into a plurality of power supply pads according to one embodiment is described.

[0164] Fig.14 is a plan view showing a power supply pad according to one embodiment.

[0165] Reference Fig.14 , a power pad JPD according to an embodiment is arranged in a non-display area of ​​the substrate SSUB, and a Joule heating voltage is applied to the power pad JPD. The power pad JPD is connected to a plurality of power lines 910 extending to and in the display area, and thus the Joule heating voltage applied to the power pad JPD can be transmitted to the heating line 810 via the power line 910.

[0166] The power supply pad JPD according to one embodiment may include a main pad MPD to which a Joule heating voltage is applied and a sub pad SPD branched from the main pad MPD.

[0167] The main pad MPD may be a pad to which a Joule heating voltage is applied, and may be provided as a single component. A sub-pad SPD may be provided for each group of a plurality of power lines 910. For example, as shown in the accompanying drawings, when the number of power lines 910 is N*M in total (here, * is a multiplication symbol, and each of N and M is an integer greater than 2), the power lines 910 may be divided into N groups 910_G1 to 910_GN, and each of the N groups 910_G1 to 910_GN includes M power lines 910. In this case, the main pad MPD is provided as a single component, but the sub-pad SPD may include N sub-pads SPD_1 to SPD_N corresponding to the N groups 910_G1 to 910_GN. For example, the first sub pad SPD_1 may receive a Joule heating voltage from the main pad MPD, and may supply the received Joule heating voltage to the first to M-th power lines 910_1 to 910_M included in the first group 910_G1. Similarly, the second sub pad SPD_2 may receive a Joule heating voltage from the main pad MPD, and may supply the received Joule heating voltage to the first to M-th power lines 910_1 to 910_M included in the second group 910_G2.

[0168] In this embodiment of the present disclosure, by dividing the power supply pad JPD into a plurality of power supply pads, the current when the Joule heating voltage is supplied can be reduced.

[0169] On the other hand, in the display panel 410 according to one embodiment, the power pad JPD may not be provided in the non-display area. For example, the power pad JPD may be a dummy pad that is not substantially used after the process of disconnecting the middle layer ML by supplying the Joule heating voltage to the heating line 810. Therefore, after this process, a partial area of ​​the substrate SSUB on which the power pad JPD is arranged may be removed by a cutting process of cutting the periphery of the display panel 410.

[0170] Fig.15 is a plan view showing another shape of a power supply pad according to one embodiment.

[0171] Fig.15 The implementation method and Fig.14 The embodiment of FIG. 1 is different in that the power supply pad JPD is not divided into the main pad MPD and the sub pad SPD.

[0172] Reference Fig.15, the power pad JPD may be provided for each of the groups 910_G1 to 910_GN of the power line 910 without being divided into the main pad MPD to which the Joule heating voltage is applied and the sub pad SPD branched therefrom. For example, as shown in the drawings, when the number of power lines 910 is N*M in total (here, * is a multiplication symbol, and each of N and M is an integer greater than 2), the power line 910 may be divided into N groups 910_G1 to 910_GN, each of the N groups 910_G1 to 910_GN including M power lines 910. In this case, the power pad JPD may include group pads GPD_1 to GPD_N provided for the groups 910_G1 to 910_GN, respectively.

[0173] Specifically, the power supply pad JPD may include N group pads GPD_1 to GPD_N corresponding to the N groups 910_G1 to 910_GN of the power supply line 910. The Joule heating voltage may be directly applied to each of the group pads GPD_1 to GPD_N. For example, the first group pad GPD_1 may receive the Joule heating voltage, and supply the received Joule heating voltage to the first power supply line 910_1 to the Mth power supply line 910_M included in the first group 910_G1. Similarly, the second group pad GPD_2 may receive the Joule heating voltage independently of the first group pad GPD_1, and may supply the received Joule heating voltage to the first power supply line 910_1 to the Mth power supply line 910_M included in the second group 910_G2.

[0174] On the other hand, in the display panel 410 according to one embodiment, the power pad JPD may not be provided in the non-display area. For example, the power pad JPD is a dummy pad that is not substantially used after the process of disconnecting the middle layer ML by supplying the Joule heating voltage to the heating line 810. Therefore, after this process, a partial area of ​​the substrate SSUB on which the power pad JPD is arranged may be removed by a cutting process of cutting the periphery of the display panel 410.

[0175] Fig.16 is a plan view showing a heating wire according to one embodiment.

[0176] Fig.16 The implementation method and Fig.12 The difference in the implementation method is that Fig.16 The heating line 810 in the embodiment of FIG. 8 is arranged to surround the sub-pixel SP (see Figure 6 ) opening OP (see Fig. 9 ) (i.e., the periphery of the emission area of ​​the sub-pixel SP). Fig.16 The description of the implementation method will be omitted Fig.12 redundant description of the implementation methods of Fig.16differences in the implementation of the

[0177] Reference Fig.16 The display panel 410 according to one embodiment may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form, and the emission areas EA1, EA2, and EA3 may have a stripe structure.

[0178] According to one embodiment, each of the pixels PX may include a first subpixel SP1 displaying light of a first color, a second subpixel SP2 displaying light of a second color, and a third subpixel SP3 displaying light of a third color. Here, the light of the first color may be light of a red wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a blue wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 370nm to 460nm, the green wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 480nm to 560nm, and the red wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 600nm to 750nm.

[0179] According to one embodiment, each of the pixels PX includes a first emission area EA1 as an emission area of ​​the first sub-pixel SP1, a second emission area EA2 as an emission area of ​​the second sub-pixel SP2, and a third emission area EA3 as an emission area of ​​the third sub-pixel SP3. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be connected to the pixel defining layer PDL (see Fig. 9 ) are substantially the same.

[0180] Each of the first, second, and third emission areas EA1, EA2, and EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in a plan view.

[0181] The first emission area EA1 and the second emission area EA2 may be arranged adjacent to each other in a column direction. Here, the column direction may be a direction in which the data line DL (see Figure 6 ) extends in a second direction DR2.

[0182] The first emission area EA1 (or the second emission area EA2) and the third emission area EA3 may be arranged adjacent to each other in a row direction. Here, the row direction may be a direction in which the scan line SL (see Figure 5 ) and a first direction DR1 in which the plurality of power lines 910 extend.

[0183] The third length of the third emission area EA3 in the column direction may be equal to or greater than the sum of the first length of the first emission area EA1 in the column direction and the second length of the second emission area EA2 in the column direction. For example, the size of the third emission area EA3 may be greater than the size of the first emission area EA1, and the size of the third emission area EA3 may be greater than the size of the second emission area EA2. For example, the size of the first emission area EA1 may be different from the size of the second emission area EA2.

[0184] According to one embodiment, the heating line 810 is arranged to surround the paired openings OP in the pixel defining layer PDL corresponding to the adjacently arranged sub-pixels SP in the form of an Euler track. The openings OP of the pixel defining layer PDL substantially indicate the emission areas EA1, EA2, EA3 of the corresponding sub-pixels SP. Therefore, the heating line 810 may be arranged to surround the paired emission areas (e.g., emission areas EA1 and EA2) corresponding to the adjacently arranged sub-pixels SP in the form of an Euler track.

[0185] According to one embodiment, each heating line 810 is connected to a power line 910 and a ground line 920. For example, the starting point P1 of the heating line 810 is connected to the ground line 920 through the first connection electrode 821 (see Fig.12 ) is connected to the power line 910, and the end point P3 of the heating line 810 is connected to the power line 910 through the second connection electrode 822 (see Fig.12 ) is connected to the ground line 920. The first connection electrode 821 penetrates the pixel definition layer PDL and the wiring layer 802 (see Figure 8 The first contact hole CT821 of the first connection electrode 822 connects the starting point P1 of the heating line 810 to the power line 910. The second connection electrode 822 connects the end point P3 of the heating line 810 to the ground line 920 through the second contact hole CT822 penetrating the pixel definition layer PDL and the wiring layer 802.

[0186] According to one embodiment, the power line 910 and the ground line 920 are arranged to cross between the pixels PX_ODD arranged in odd rows and the pixels PX_EVEN arranged in even rows. For example, the power line 910 and the ground line 920 may extend parallel to the plurality of scan lines SL in the first direction DR1.

[0187] The heating line 810 may include a first heating line 811 and a second heating line 812 provided for each pixel PX. The first heating line 811 is arranged to surround the first emission area EA1 and the second emission area EA2 in the form of an Euler track. The second heating line 812 is arranged to surround the third emission area EA3.

[0188] The first starting point P1_1 and the first end point P3_1 of the first heating line 811 may be disposed between the second emission area EA2 of the pixels PX_ODD arranged in odd rows and the first emission area EA1 of the pixels PX_EVEN arranged in even rows. The second starting point P1_2 and the second end point P3_2 of the second heating line 812 may be disposed between the third emission area EA3 of the pixels PX_ODD arranged in odd rows and the third emission area EA3 of the pixels PX_EVEN arranged in even rows.

[0189] The first heating line 811 may extend as follows so as to surround the first emission area EA1 and the second emission area EA2 which are adjacently arranged in the form of an Euler track. For example, the first heating line 811 may extend from the first starting point P1_1 to the midpoint P2 located between the first emission area EA1 and the second emission area EA2, and may extend from the midpoint P2 to the first end point P3_1 while surrounding the periphery of the second emission area EA2. Here, the midpoint P2 may be arranged near a corner of the first emission area EA1 adjacent to the third emission area EA3.

[0190] Fig.17 is a flowchart illustrating a method of manufacturing a display panel according to one embodiment. Figures 18 to 21 are cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment.

[0191] In the following, reference will be made to Figures 17 to 21 A display panel 410 according to an embodiment is described (see Figure 4 The following description is only a part of the manufacturing process of the display panel 410, and the process for forming the components described with reference to the present disclosure may be additionally performed before or after each step described below. In addition, the manufacturing process of the display panel 410 known to those skilled in the art may be additionally performed before or after each step described below.

[0192] Reference Fig.17 In step 1710, the substrate SSUB (see Figure 8 ) is formed on the driving element layer 801 (see Figure 8 ). The driving element layer 801 may include a reference Figure 8 Description of MOSFET MOS.

[0193] Reference Fig.17 In step 1720, a wiring layer 802 may be formed on the driving element layer 801. The wiring layer 802 may include an insulating layer VIA sequentially stacked on the driving element layer 801, a connecting electrode CE (see Figure 8) and a plurality of lines. According to one embodiment, the wiring layer 802 may further include a power line 910 to which a Joule heating voltage is applied and a ground line 920 connected to ground. In the illustrated example, the power line 910 and the ground line 920 are arranged in the same layer, but the present disclosure is not limited thereto. For example, the power line 910 and the ground line 920 may be arranged in different layers.

[0194] Reference Fig.17 In step 1730, each sub-pixel SP may be formed on the wiring layer 802 (see Figure 6 ) and a pixel defining layer PDL defining the sub-pixel SP. During the process, the first electrode ANE may be formed through an opening OP (see FIG. Fig. 9 ) is partially exposed. An edge of each first electrode ANE may be covered by a pixel defining layer PDL.

[0195] Reference Fig.17 and Fig.18 In step 1740, a first contact hole CT821 and a second contact hole CT822 penetrating at least a portion of the pixel defining layer PDL and the insulating layer VIA are formed. Subsequently, a first connection electrode 821 connected to the power line 910 is formed by covering the first contact hole CT821. In addition, a second connection electrode 822 connected to the ground line 920 is formed by covering the second contact hole CT822. Next, a heating line 810 is formed on the pixel defining layer PDL positioned between adjacent sub-pixels (e.g., sub-pixels SP1 and SP2).

[0196] According to one embodiment, as referenced Fig.12 and Fig.13 As described above, the heating line 810 may be arranged to surround the pair of first electrodes ANE_A and ANE_B corresponding to the adjacently arranged sub-pixels SP in the form of an Euler track. The starting point P1 of the heating line 810 is connected to the power line 910 through the first connection electrode 821 arranged in the first contact hole CT821. The end point P3 of the heating line 810 is connected to the ground line 920 through the second connection electrode 822 arranged in the second contact hole CT822.

[0197] According to one embodiment, as referenced Fig.16 As described above, the heating line 810 may include a first heating line 811 surrounding the first emission area EA1 and the second emission area EA2 in the form of an Euler track, and a second heating line 812 surrounding the third emission area EA3.

[0198] According to one embodiment, the first metal forming the heating line 810, the second metal forming the connection electrodes 821 and 822, and the third metal forming the power line 910 may be different from each other. The resistance of the first metal may be greater than the resistance of the second metal. The resistance of the second metal may be greater than the resistance of the third metal.

[0199] Reference Fig.17 and Fig.19 In step 1750, the middle layer ML may be deposited. For example, the middle layer ML may be disposed not only above the opening OP of the pixel defining layer PDL but also on the pixel defining layer PDL disposed between adjacent sub-pixels (e.g., sub-pixels SP1 and SP2) using an opening mask (not shown). Therefore, the middle layer ML may cover the first electrode ANE in each opening OP of the pixel defining layer PDL and also cover the heating line 810 disposed on the pixel defining layer PDL.

[0200] Reference Fig.17 and Fig. 20 In step 1760, the heating line 810 may be used to remove all or part of the intermediate layer ML disposed between adjacent sub-pixels (eg, sub-pixels SP1 and SP2). To this end, a Joule heating voltage is applied to the power supply pad JPD (see Fig.12 ), and the Joule heating voltage applied to the power supply pad JPD may be transmitted to the heating line 810 via the power supply line 910. The heating line 810 is configured to receive the Joule heating voltage through the power supply line 910 and the first connection electrode 821, and generate heat 1501 based on the input Joule heating voltage. The temperature of the heating line 810 is increased to a high temperature of about 400° C. or more by the input Joule heating voltage, and the intermediate layer ML deposited on and around the heating line 810 may be removed due to the high temperature.

[0201] Reference Fig.17 and Fig.21 In step 1770, the second electrode CAE may be deposited. For example, the second electrode CAE may be arranged not only on the opening OP of the pixel defining layer PDL, but also on the pixel defining layer PDL arranged between adjacent sub-pixels (e.g., sub-pixels SP1 and SP2) using an opening mask. Therefore, the second electrode CAE may cover the middle layer ML in each opening OP of the pixel defining layer PDL, and also cover the middle layer ML and the heating line 810 arranged on the pixel defining layer PDL.

[0202] In reference Figures 17 to 21In the manufacturing method of the display panel 410 described above, the process of removing all or part of the middle layer ML using the heating line 810 is performed before the step of depositing the second electrode CAE, but the present disclosure is not limited thereto. For example, the process of removing part of the middle layer ML using the heating line 810 may be performed after the step of depositing the second electrode CAE.

[0203] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the exemplary embodiments without departing substantially from the principles of the present disclosure. Therefore, the specific embodiments described herein are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; a driving element layer, wherein the driving element layer is arranged on the substrate; as well as a light emitting element layer, the light emitting element layer being arranged on the driving element layer, Wherein, the light emitting element layer comprises: a pixel defining layer, the pixel defining layer being configured to define a plurality of sub-pixels; a first electrode of each sub-pixel of the plurality of sub-pixels, the first electrode being arranged in an opening of the pixel defining layer; a heating line arranged on the pixel defining layer to surround the first electrode of each sub-pixel; an intermediate layer, the intermediate layer being configured to cover the first electrode in the opening and to cover the pixel defining layer, and the intermediate layer being configured to be partially disconnected above the heating line; and a second electrode continuously arranged to cover the intermediate layer and the heating line between adjacent sub-pixels while covering the intermediate layer in the opening, The heating lines are arranged in the form of Euler traces to surround the pairs of first electrodes corresponding to the adjacent sub-pixels.

2. The display device according to claim 1, wherein: a wiring layer including a power supply line and a ground line is arranged between the driving element layer and the light emitting element layer, and The power supply line and the ground line are arranged to cross between the sub-pixels arranged in the odd-numbered rows and the sub-pixels arranged in the even-numbered rows, Wherein, the light emitting element layer further comprises: a first connection electrode configured to connect a starting point of the heating line to the power line through a first contact hole penetrating the pixel defining layer and at least a portion of the wiring layer; and A second connection electrode configured to connect an end point of the heating line to the ground line through a second contact hole penetrating the pixel defining layer and at least a portion of the wiring layer.

3. The display device according to claim 2, wherein: The start point and the end point of the heating line are positioned between the sub-pixels arranged in the odd-numbered rows and the sub-pixels arranged in the even-numbered rows.

4. The display device according to claim 3, wherein: The heating line extends from the starting point to surround a second reference sub-pixel among the sub-pixels arranged in the even-numbered rows and is connected to a midpoint adjacent to the starting point, and The heating line extends from the midpoint to surround a first reference sub-pixel adjacent to the second reference sub-pixel among the sub-pixels arranged in the odd-numbered rows, and is connected to the end point.

5. The display device according to claim 4, wherein: The midpoint of the heating line is arranged between the start point and the end point.

6. The display device according to claim 5, wherein: When viewed in the normal direction of the substrate, the heating line has a shape of a letter S as the heating line extends from the start point via the midpoint to the end point.

7. The display device according to claim 5, wherein: When viewed in the normal direction of the substrate, the first electrode of each sub-pixel has an n-gonal shape, where n is an integer greater than or equal to 4, and The heating line has the n-gonal shape spaced apart from the first electrode at a certain interval when viewed in the normal direction of the substrate.

8. The display device according to claim 7, wherein: When viewed in the normal direction of the substrate, the first electrode of each sub-pixel has a hexagonal shape, and The heating wire has the hexagonal shape spaced apart from the first electrode at the specific interval when viewed in the normal direction of the substrate.

9. The display device according to claim 2, wherein: The power supply line is connected to a power supply pad arranged in a non-display area of ​​the substrate, and The power pad comprises: a main pad to which a Joule heating voltage is applied; and a plurality of sub pads branched from the main pad and provided for respective groups obtained by evenly dividing a plurality of the power supply lines, The power lines included in each group receive the Joule heating voltage through the sub-pad.

10. The display device according to claim 2, wherein: The power supply line is connected to a power supply pad arranged in a non-display area of ​​the substrate, The power supply pads include a plurality of group pads to which a Joule heating voltage is applied and provided for respective groups obtained by uniformly dividing a plurality of the power supply lines, and The power lines included in each group receive the Joule heating voltage through the group pad.

11. A display device, comprising: substrate; a driving element layer, wherein the driving element layer is arranged on the substrate; as well as a light emitting element layer, the light emitting element layer being arranged on the driving element layer, Wherein, the light emitting element layer comprises: a pixel defining layer, the pixel defining layer being configured to define a plurality of sub-pixels; a first electrode of each sub-pixel of the plurality of sub-pixels, the first electrode being arranged in an opening of the pixel defining layer; a heating line arranged on the pixel defining layer to surround the opening of each sub-pixel; an intermediate layer, the intermediate layer being configured to cover the first electrode in the opening and to cover the pixel defining layer, and the intermediate layer being configured to be partially disconnected above the heating line; and a second electrode continuously arranged to cover the intermediate layer and the heating line between adjacent sub-pixels while covering the intermediate layer in the opening, The heating lines are arranged in the form of Euler traces to surround the pairs of openings corresponding to the adjacent sub-pixels.

12. The display device according to claim 11, wherein: a wiring layer including a power supply line and a ground line is arranged between the driving element layer and the light emitting element layer, and The power supply line and the ground line are arranged to cross between the sub-pixels arranged in the odd-numbered rows and the sub-pixels arranged in the even-numbered rows, Wherein, the light emitting element layer further comprises: a first connection electrode configured to connect a starting point of the heating line to the power line through a first contact hole penetrating the pixel defining layer and at least a portion of the wiring layer; and A second connection electrode configured to connect an end point of the heating line to the ground line through a second contact hole penetrating the pixel defining layer and at least a portion of the wiring layer.

13. The display device according to claim 12, wherein: One pixel includes a first emission region of a first sub-pixel displaying red light, a second emission region of a second sub-pixel displaying green light, and a third emission region of a third sub-pixel displaying blue light. The first emission region and the second emission region are arranged adjacent to each other in a column direction, The first emission region and the third emission region are arranged adjacent to each other in a row direction, and A third length of the third emission region in the column direction is greater than or equal to a sum of a first length of the first emission region in the column direction and a second length of the second emission region in the column direction.

14. The display device according to claim 13, wherein: The heating wire comprises: a first heating line arranged to surround the first emission area and the second emission area in the form of the Euler track; and A second heating line is arranged to surround the third emission area.

15. The display device according to claim 14, wherein: The first starting point and the first end point of the first heating line are arranged between the second emission regions of the pixels arranged in the odd-numbered rows and the first emission regions of the pixels arranged in the even-numbered rows, and The second start point and the second end point of the second heating line are arranged between the third emission regions of the pixels arranged in the odd-numbered rows and the third emission regions of the pixels arranged in the even-numbered rows.

16. The display device according to claim 15, wherein: The first heating line extends from the first starting point to a midpoint between the first emission area and the second emission area, and extends from the midpoint to the first end point while surrounding the periphery of the second emission area.

17. The display device according to claim 16, wherein: The midpoint is arranged near a corner of the first emission area adjacent to the third emission area.

18. The display device according to claim 13, wherein: Each of the first to third emission regions has a rectangular shape in a plan view.

19. The display device according to claim 12, wherein: The power supply line is connected to a power supply pad arranged in a non-display area of ​​the substrate, and The power pad comprises: a main pad to which a Joule heating voltage is applied; and a plurality of sub pads branched from the main pad and provided for respective groups obtained by evenly dividing a plurality of the power supply lines, The power lines included in each group receive the Joule heating voltage through the sub-pad.

20. The display device according to claim 12, wherein: The power supply line is connected to a power supply pad arranged in a non-display area of ​​the substrate, The power supply pads include a plurality of group pads to which a Joule heating voltage is applied and provided for respective groups obtained by uniformly dividing a plurality of the power supply lines, and The power lines included in each group receive the Joule heating voltage through the group pad.

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