Display substrate, preparation method thereof and display device

Abstract

A display substrate and a preparation method thereof, and a display device, relating to but not limited to the technical field of display, the display substrate comprising: an active layer (12) disposed on one side of a substrate (101), the active layer (12) comprising a channel region; the grid electrode (13) is arranged on one side, far away from the substrate (101), of the active layer (12), and at least part of the grid electrode (13) is overlapped with the orthographic projection of the channel region on the substrate (101); the shading layer (11) is arranged on the side, close to the substrate (101), of the active layer (12), and at least part of the shading layer (11) is overlapped with the orthographic projection of the channel region on the substrate (101).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] As users' demands for products such as narrow bezels and high PPI continue to increase, higher requirements are placed on the performance of thin film transistor (TFT) devices. At present, semiconductor materials in TFT devices generally use amorphous silicon (a-Si), metal oxides (such as IGZO) and low-temperature polycrystalline silicon (LTPS). The effective mobility of metal oxides is low compared to that of low-temperature polycrystalline silicon. In order to improve the mobility of metal oxide materials, it is generally adopted to increase the indium (In) content in metal oxides, remove zinc (Zn) from metal oxides, or add tin (Sn) elements to metal oxides to improve the mobility of metal oxide materials. However, high-mobility metal oxide materials have a small bandgap and are highly sensitive to light. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] An active layer is disposed on one side of the substrate, wherein the active layer includes a channel region;

[0007] A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0008] A light shielding layer is arranged on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

[0009] In an exemplary embodiment, the gate includes a main body portion and a protrusion disposed on the main body portion, the protrusion overlaps an orthographic projection of the channel region on the substrate, and the main body portion does not overlap an orthographic projection of the channel region on the substrate.

[0010] In an exemplary embodiment, a space is provided between an edge of the body portion on a side close to the channel region and an edge of the channel region on a side close to the body portion.

[0011] In an exemplary embodiment, the main body portion is in a strip shape, the active layer is in a strip shape, and an extending direction of the main body portion is substantially the same as an extending direction of the active layer.

[0012] In an exemplary embodiment, the shape of the protrusion includes a block shape or a strip shape.

[0013] In an exemplary embodiment, the shape of the active layer includes a stripe shape, the active layer extends along the second direction, the shape of the gate includes a stripe shape, the gate extends along a first direction, and the first direction intersects the second direction.

[0014] In an exemplary embodiment, the active layer further includes a first doping region and a second doping region, and the first doping region and the second doping region are connected through the channel region.

[0015] In an exemplary embodiment, a first electrode and a second electrode are further included, wherein the first electrode and the second electrode are both arranged on a side of the active layer away from the substrate, the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the second doped region through a second via hole.

[0016] In an exemplary embodiment, a pixel electrode is further included. The pixel electrode is disposed on a side of the first electrode and the second electrode away from the substrate, and the pixel electrode is connected to the second electrode through a third via hole.

[0017] In an exemplary embodiment, the orthographic projections of the second via hole and the third via hole on the substrate overlap.

[0018] In an exemplary embodiment, an organic medium layer is further included, the organic medium layer is disposed between the pixel electrode and the second electrode, a fourth via hole is disposed in the organic medium layer, and the orthographic projection of the third via hole on the substrate is located within the orthographic projection of the fourth via hole on the substrate.

[0019] In an exemplary embodiment, a common electrode is further included. The common electrode is disposed on a side of the pixel electrode close to the substrate, and the common electrode is connected to the pixel electrode through a fifth via hole.

[0020] In an exemplary embodiment, a touch electrode is further included, wherein the touch electrode is disposed between the common electrode and the pixel electrode, and the touch electrode is connected to the pixel electrode through the fifth via hole.

[0021] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described above.

[0022] In a third aspect, the present disclosure also provides a method for preparing a display substrate, comprising:

[0023] forming a light shielding layer on the substrate;

[0024] An active layer is formed on a side of the light shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate;

[0025] A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

[0026] In an exemplary embodiment, further comprising:

[0027] forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole;

[0028] A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the second via hole and the third via hole overlap in their orthographic projections on the substrate.

[0029] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0031] Figure 1 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 2 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 3aThis is a schematic diagram of an exemplary embodiment of the present disclosure after a light shielding layer is formed in a display substrate preparation process;

[0034] Figure 3b It is a schematic diagram of an exemplary embodiment of the present disclosure after an active layer is formed in a process of preparing a display substrate;

[0035] Figure 3c This is a schematic diagram of an exemplary embodiment of the present disclosure after a gate is formed in a process of preparing a display substrate;

[0036] Figure 3d It is a schematic diagram of a first electrode and a second electrode in a process of preparing a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 3e This is a schematic diagram of an exemplary embodiment of the present disclosure after a third inorganic dielectric layer, an organic dielectric layer and a fourth via hole are formed in a display substrate preparation process;

[0038] Figure 3f It is a schematic diagram of an exemplary embodiment of the present disclosure after a common electrode is formed in a process of preparing a display substrate;

[0039] Figure 3g It is a schematic diagram of an exemplary embodiment of the present disclosure after a touch electrode is formed in a display substrate preparation process;

[0040] Figure 3h It is a schematic diagram of an exemplary embodiment of the present disclosure after a third via hole and a fifth via hole are formed in a process of preparing a display substrate;

[0041] Figure 4 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 5 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] Figure 6 for Figure 5 Schematic diagram of the planar structure of the middle gate;

[0044] Figure 7 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 8 The figure is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0047] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0048] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0049] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0050] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0051] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0052] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0053] In this specification, "connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0054] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0055] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0056] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0057] The inventors of the present disclosure have found that the active layer in the metal oxide thin film transistor generally uses indium gallium zinc oxide (IGZO), which has the characteristics of good uniformity and high mobility. However, for the metal oxide thin film transistor with a top gate structure, since the backlight source is on the lower side of the TFT substrate, the light emitted by the backlight source will irradiate the metal oxide thin film transistor, causing the gate threshold voltage (Vth) of the metal oxide thin film transistor to be negatively biased, causing the metal oxide thin film transistor to be turned on early, leakage problems, and poor display problems such as sand Mura bright spots; and light exposure will increase the new defects of the metal oxide thin film transistor, reduce the negative bias temperature illumination stress (negative bias temperature illumination stress, nbtis) of the metal oxide thin film transistor, and reduce the life of the display substrate.

[0058] An exemplary embodiment of the present disclosure provides a display substrate, including:

[0059] An active layer is disposed on one side of the substrate, wherein the active layer includes a channel region;

[0060] A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0061] A light shielding layer is arranged on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

[0062] The solution of this embodiment is described below by means of some examples.

[0063] Figure 1 The schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure illustrates the structure of a thin film transistor in the display substrate. In the exemplary embodiment, the display substrate at least includes a light shielding layer 11 sequentially disposed on a substrate, an active layer 12 disposed on a side of the light shielding layer 11 away from the substrate, a gate 13 disposed on a side of the active layer 12 away from the substrate, and a first electrode 14 and a second electrode 15 disposed on a side of the gate 13 away from the substrate.

[0064] In an exemplary embodiment, the active layer 12 may be in a strip shape, and the active layer 12 extends along the second direction Y. The active layer 12 includes a channel region and a first doping region and a second doping region located on opposite sides of the channel region in the second direction Y. The first doping region and the second doping region may be connected through the channel region. The first doping region and the second doping region are both regions of the active layer 12 after being conductorized.

[0065] In an exemplary embodiment, the gate 13 may be in a strip shape, the gate 13 extends along a first direction X, and at least a portion of the gate 13 overlaps with the orthographic projection of the channel region of the active layer 12 on the substrate. The first direction X and the second direction Y are both parallel to the substrate, and the first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0066] In an exemplary embodiment, the light-shielding layer 11 can be shaped like a rectangular block. The light-shielding layer 11 is located on the side of the active layer 12 close to the substrate. At least part of the light-shielding layer 11 overlaps with the orthographic projection of the channel region of the active layer 12 on the substrate, so that the light-shielding layer 11 can block the light emitted toward the channel region and prevent the light from directly irradiating the channel region.

[0067] In an exemplary embodiment, the orthographic projection of the channel region of the active layer 12 on the substrate is located within the orthographic projection of the light shielding layer 11 on the substrate, so that the light shielding layer 11 can completely shield the channel region.

[0068] The disclosed embodiment displays a substrate that shields the channel region of the active layer through a shielding layer to prevent light from directly irradiating the channel region, thereby reducing the negative bias of the transistor gate threshold voltage (Vth) caused by light, solving the leakage problem of the display substrate, and ensuring the negative bias temperature illumination stress (nbtis) stability, thereby increasing the life of the display substrate.

[0069] In an exemplary embodiment, at least a portion of the light shielding layer 11 overlaps with an orthographic projection of the gate 13 on the substrate.

[0070] In an exemplary embodiment, the first electrode 14 may be block-shaped, and the first electrode 14 is located on one side of the gate 13 in the second direction Y, and does not overlap with the orthographic projection of the gate 13 on the substrate. The first electrode 14 overlaps with the orthographic projection of the first doping region of the active layer 12 on the substrate, and the first electrode 14 is connected to the first doping region of the active layer 12 through the first via 21.

[0071] In an exemplary embodiment, the second electrode 15 may be in the shape of a strip, and the second electrode 15 extends along the first direction X. The second electrode 15 is located on the side of the gate 13 in the opposite direction of the second direction Y, and does not overlap with the orthographic projection of the gate 13 on the substrate. The first end of the second electrode 15 overlaps with the orthographic projection of the second doping region of the active layer 12 on the substrate, and the first end of the second electrode 15 is connected to the second doping region of the active layer 12 through the second via 22. The second end of the second electrode 15 extends in the opposite direction of the first direction X, and the second end of the second electrode 15 may be connected to the pixel electrode (not shown) through the third via 23.

[0072] Figure 2FIG. 1 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 2 As shown, the display substrate at least includes a light shielding layer 11 disposed on a substrate 101, a first inorganic dielectric layer 41 disposed on a side of the light shielding layer 11 away from the substrate 101, an active layer 12 disposed on a side of the first inorganic dielectric layer 41 away from the substrate 101, a gate insulating layer disposed on a side of the active layer 12 away from the substrate 101, a gate 13 disposed on a side of the gate insulating layer away from the substrate 101, a second inorganic dielectric layer 42 disposed on a side of the gate 13 away from the substrate 101, a first electrode 14 and a second electrode 15 disposed on a side of the second inorganic dielectric layer 42 away from the substrate 101, and a first electrode 14 disposed on a side of the first electrode 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the second inorganic dielectric layer 14 disposed on a side of the first ... 4 and the second electrode 15 are away from the substrate 101, the third inorganic dielectric layer 43 is arranged on the side of the third inorganic dielectric layer 43 away from the substrate 101, the organic dielectric layer 46 is arranged on the side of the third inorganic dielectric layer 43 away from the substrate 101, the common electrode 16 is arranged on the side of the organic dielectric layer 46 away from the substrate 101, the fourth inorganic dielectric layer 44 is arranged on the side of the common electrode 16 away from the substrate 101, the touch electrode 17 is arranged on the side of the fourth inorganic dielectric layer 44 away from the substrate 101, the fifth inorganic dielectric layer 45 is arranged on the side of the touch electrode 17 away from the substrate 101, and the pixel electrode 18 is arranged on the side of the fifth inorganic dielectric layer 45 away from the substrate 101.

[0073] In an exemplary embodiment, the display substrate further includes a first via hole 21 , a second via hole 22 , a third via hole 23 , a fourth via hole 24 , and a fifth via hole 25 disposed on one side of the base 101 .

[0074] In an exemplary embodiment, the first via hole 21 is disposed in the second inorganic dielectric layer 42 , and the first via hole 21 extends from the surface of the second inorganic dielectric layer 42 away from the substrate 101 to the surface of the first doping region of the active layer 12 , and the first via hole 21 exposes at least a portion of the surface of the first doping region, and the first electrode 14 is connected to the first doping region of the active layer 12 through the first via hole 21 .

[0075] In an exemplary embodiment, the second via 22 is disposed in the second inorganic dielectric layer 42 , and the second via 22 extends from the surface of the second inorganic dielectric layer 42 away from the substrate 101 to the surface of the second doping region of the active layer 12 , and the second via 22 exposes at least a portion of the surface of the second doping region, and the second electrode 15 is connected to the second doping region of the active layer 12 through the second via 22 .

[0076] In an exemplary embodiment, the third via hole 23 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially penetrates the fifth inorganic dielectric layer 45, the fourth inorganic dielectric layer 44, the organic dielectric layer 46, and the third inorganic dielectric layer 43, and extends to the surface of the second electrode 15. The third via hole 23 exposes at least a portion of the surface of the second electrode 15, and the pixel electrode 18 is connected to the second electrode 15 through the third via hole 23.

[0077] In an exemplary embodiment, the fourth via hole 24 is disposed in the organic medium layer 46, and the fourth via hole 24 penetrates the organic medium layer 46. The area of ​​the orthographic projection of the fourth via hole 24 on the substrate is greater than the area of ​​the orthographic projection of the third via hole 23 on the substrate, and the orthographic projection of the third via hole 23 on the substrate is located within the orthographic projection of the fourth via hole 24 on the substrate.

[0078] The disclosed embodiment shows that the substrate forms a fourth via hole 24 in the organic dielectric layer 46 first, and then fills the fourth inorganic dielectric layer 44 in the fourth via hole 24, so that the third via hole 23 passes through the organic dielectric layer 46 through the fourth inorganic dielectric layer 44 in the fourth via hole 24, so that the third via hole 23 can be formed by a single dry etching process, thereby simplifying the process steps.

[0079] In an exemplary embodiment, the fifth via hole 25 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially penetrates the fifth inorganic dielectric layer 45 and the fourth inorganic dielectric layer 44, and extends to the common electrode 16. The fifth via hole 25 exposes at least a portion of the surface of the touch electrode 17 and at least a portion of the surface of the common electrode 16. The touch electrode 17 and the common electrode 16 are connected to the pixel electrode 18 through the fifth via hole 25.

[0080] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0081] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0082] (11) Forming a light shielding layer. In an exemplary embodiment, forming the light shielding layer may include: depositing a metal film on the substrate 101, and patterning the metal film through a patterning process to form the light shielding layer 11, such as Figure 3a shown.

[0083] In an exemplary embodiment, the light shielding layer 11 may be made of molybdenum and its alloys, composite metal of aluminum and copper, and the like.

[0084] (12) Forming an active layer. In an exemplary embodiment, forming the active layer may include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a first inorganic insulating film and a semiconductor film on the substrate 101, patterning the first inorganic insulating film and the semiconductor film by a patterning process to form a first inorganic dielectric layer 41 covering the light shielding layer 11, and an active layer 12 disposed on the first inorganic dielectric layer 41, such as Figure 3b shown.

[0085] In an exemplary embodiment, the first inorganic dielectric layer 41 may be made of silicon oxide (SiO), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 200 nm to 500 nm.

[0086] In an exemplary embodiment, the active layer 12 may be made of a high-mobility oxide material, such as metal oxides such as IGZTO and IGO.

[0087] (13) Forming a gate. In an exemplary embodiment, forming the gate may include: depositing a gate insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming a gate 13 disposed on the gate insulating film, wherein the gate 13 overlaps with the orthographic projection of the active layer 12 on the substrate 101;

[0088] Subsequently, the gate insulating film is pattern-etched using the gate 13 as a mask, so that the gate insulating film forms a gate insulating layer 47 disposed on the active layer 12, and the gate insulating layer 47 exposes both ends of the active layer;

[0089] Subsequently, the two ends of the exposed active layer are conductively connected to form a first doping region and a second doping region, and the portion of the active layer 12 covered by the gate 13 forms a channel region. Figure 3c shown.

[0090] In an exemplary embodiment, the orthographic projection of the channel region of the active layer 12 on the substrate 101 is located in the orthographic projection of the light shielding layer 11 on the substrate 101 , so that the light shielding layer 11 can completely shield the channel region of the active layer 12 .

[0091] In an exemplary embodiment, the first doping region and the second doping region may be formed by a plasma process using one or a mixture of helium (He), argon (Ar), hydrogen, and methane.

[0092] In an exemplary embodiment, the gate insulating layer 47 may use silicon oxide, and the thickness of the gate insulating layer 47 may be 10 nm to 30 nm.

[0093] In an exemplary embodiment, the gate electrode 13 may be made of molybdenum and its alloys, composite metal of aluminum and copper, and the like.

[0094] (14) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode may include: depositing a second inorganic insulating film on the substrate on which the aforementioned pattern is formed to form a second inorganic dielectric layer 42 covering the gate 13; then, forming a first via hole 21 and a second via hole 22 in the second inorganic dielectric layer 42 by an etching process, wherein the first via hole 21 and the second via hole 22 both penetrate the second inorganic dielectric layer 42, the first via hole 21 exposes the surface of the first doped region of the active layer 12, and the second via hole 22 exposes the surface of the second doped region of the active layer 12; then, depositing a second conductive film on the second inorganic dielectric layer 42, and patterning the second conductive film by a patterning process to form a first electrode 14 and a second electrode 15 disposed on the second inorganic dielectric layer 42, wherein the first electrode 14 is connected to the first doped region of the active layer 12 through the first via hole 21, and the second electrode 15 is connected to the second doped region of the active layer 12 through the second via hole 22, as shown in FIG. Figure 3d shown.

[0095] In an exemplary embodiment, the second inorganic dielectric layer 42 may be made of silicon oxide (SiO), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 300 nm to 600 nm.

[0096] In an exemplary embodiment, the first electrode 14 and the second electrode 15 may both be made of materials such as molybdenum and its alloys, and composite metals of aluminum and copper.

[0097] (15) Forming a third inorganic dielectric layer, an organic dielectric layer, and a fourth via hole. In an exemplary embodiment, forming the third inorganic dielectric layer, the organic dielectric layer, and the fourth via hole includes: on the substrate formed with the aforementioned pattern, sequentially depositing a third inorganic insulating film and an organic film on the first electrode 14 and the second electrode 15 to form a third inorganic dielectric layer 43 covering the first electrode 14 and the second electrode 15, and forming an organic dielectric layer 46 disposed on the third inorganic dielectric layer 43; then, by a photolithography process, forming a fourth via hole 24 in the organic dielectric layer 46, the fourth via hole 24 penetrating the organic dielectric layer 46, and the fourth via hole 24 exposing the surface of the third inorganic dielectric layer 43, as shown in FIG. Figure 3e shown.

[0098] (16) Forming a common electrode. In an exemplary embodiment, forming the common electrode includes: depositing a third conductive film on the organic dielectric layer 46 on the substrate formed with the aforementioned pattern, patterning the third conductive film by a patterning process, and forming a common electrode 16 disposed on the organic dielectric layer 46, such as Figure 3f shown.

[0099] In an exemplary embodiment, the common electrode 16 may be made of a transparent conductive material such as indium tin oxide (ITO).

[0100] In an exemplary embodiment, the common electrode 16 does not overlap with the orthographic projection of the fourth via hole 24 on the substrate 101 .

[0101] (17) Forming a touch electrode. In an exemplary embodiment, forming the touch electrode includes: depositing a fourth inorganic insulating film and a fourth conductive film in sequence on the substrate having the aforementioned pattern, patterning the fourth inorganic insulating film and the fourth conductive film by a patterning process to form a fourth inorganic dielectric layer 44 covering the common electrode 16, and forming the touch electrode 17 disposed on the fourth inorganic dielectric layer 44, such as Figure 3g shown.

[0102] In an exemplary embodiment, the touch electrode 17 may be made of molybdenum and its alloys, or a composite metal of aluminum and copper.

[0103] (18) Forming the third via hole and the fifth via hole. The forming of the third via hole and the fifth via hole comprises: depositing a fifth inorganic insulating film on the substrate formed with the aforementioned pattern to form a fourth fifth organic dielectric layer 45 covering the touch electrode 17; then, forming the third via hole 23 and the fifth via hole 25 in the fourth fifth organic dielectric layer 45 by dry etching process, as shown in FIG. Figure 3h shown.

[0104] In an exemplary embodiment, the third via hole 23 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially penetrates the fifth inorganic dielectric layer 45, the fourth inorganic dielectric layer 44, the organic dielectric layer 46, and the third inorganic dielectric layer 43, and extends to the surface of the second electrode 15. The third via hole 23 exposes at least part of the surface of the second electrode 15. The orthographic projection of the third via hole 23 on the substrate is located within the orthographic projection of the fourth via hole 24 on the substrate.

[0105] In an exemplary embodiment, the fifth via 25 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially penetrates the fifth inorganic dielectric layer 45 and the fourth inorganic dielectric layer 44, and extends to the common electrode 16. The fifth via 25 exposes at least a portion of the surface of the touch electrode 17 and at least a portion of the surface of the common electrode 16.

[0106] (19) Forming a pixel electrode. The pixel electrode is formed by depositing a fifth conductive film on the substrate formed with the aforementioned pattern, patterning the fifth conductive film by a patterning process, and forming a pixel electrode 18 disposed on the fifth inorganic dielectric layer 45, wherein the pixel electrode 18 is connected to the second electrode 15 through the third via hole 23, and the pixel electrode 18 is respectively connected to the touch electrode 17 and the common electrode 16 through the fifth via hole 25. Figure 2 shown.

[0107] In an exemplary embodiment, a slit is disposed in the pixel electrode 18 , and the pixel electrode 18 overlaps with the common electrode 16 in their orthographic projections on the substrate, thereby forming an electric field.

[0108] In some embodiments, the preparation process of the substrate shown in this embodiment may not form a touch layer and a fourth inorganic dielectric layer, and the embodiments of the present disclosure will not be described in detail herein.

[0109] Figure 4 FIG. 2 is a schematic cross-sectional structure diagram of another display substrate of the exemplary embodiment of the present disclosure. The inventors of the present disclosure have found that Figure 4 As shown, the light A is reflected from the lower surface of the gate 13 to the upper surface of the shielding layer 11, and then reflected from the upper surface of the shielding layer 11 to the channel region of the active layer 12, affecting the performance of the thin film transistor.

[0110] Figure 5 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 6 for Figure 5 Schematic diagram of the planar structure of the middle gate. Figure 5 and Figure 6 As shown, this exemplary embodiment shows the structure of the substrate and Figure 1 The structures of the display substrates shown are basically the same, except that, in the display substrate of this exemplary embodiment, the gate 13 includes a main body portion 131 and an extension portion 132 arranged on the main body portion 131, and the extension portion 132 overlaps with the orthographic projection of the channel region of the active layer 12 on the substrate, and the main body portion 131 does not overlap with the orthographic projection of the channel region of the active layer 12 on the substrate.

[0111] In an exemplary embodiment, the active layer 12 may be in a strip shape, and the active layer 12 extends along the first direction X.

[0112] In an exemplary embodiment, the main body portion 131 of the gate 13 may be in a strip shape, and the main body portion 131 extends along the first direction X. The extending direction of the main body portion 131 is substantially the same as the extending direction of the active layer 12 .

[0113] In an exemplary embodiment, a space is provided between an edge of the main body portion 131 of the gate 13 on a side close to the channel region and an edge of the channel region on a side close to the main body portion 131 .

[0114] In an exemplary embodiment, the extension portion 132 of the gate 13 is strip-shaped, the extension portion 132 extends along the second direction Y, the first end of the extension portion 132 is vertically connected to the main portion 131, and the second end of the extension portion 132 extends in the opposite direction of the second direction Y, overlapping with the positive projection of the channel region of the active layer 12 on the substrate.

[0115] In some embodiments, the extension portion 132 of the gate 13 may be in a block shape.

[0116] In an exemplary embodiment, the first electrode 14 and the second electrode 15 are located at opposite sides of the protruding portion 132 of the gate 13 in the first direction X.

[0117] The disclosed embodiment shows that the substrate overlaps with the channel region through the extension portion 132 of the gate 13, so that the main portion 131 of the gate 13 is away from the channel region, thereby preventing light from being reflected through the main portion 131 of the gate 13 and the shielding layer 11 to the channel region of the active layer 12, thereby reducing the reflected light irradiating the channel region of the active layer 12.

[0118] Figure 7 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 8 FIG. 2 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 7 and Figure 8 As shown, this exemplary embodiment shows the structure of the substrate and Figure 5 The structures of the display substrates shown are substantially the same, except that in the exemplary embodiment, the second via hole 22 and the third via hole 23 in the display substrate overlap in their orthographic projections on the base.

[0119] In an exemplary embodiment, the third via hole 23 overlaps the second via hole 22 at an orthographic projection portion of the substrate.

[0120] The display substrate of the embodiment of the present disclosure reduces the space occupied by the second via hole 22 and the third via hole 23 by overlapping the orthographic projections of the second via hole 22 and the third via hole 23 on the substrate, thereby improving the space utilization of the display substrate.

[0121] The present disclosure also provides a method for preparing a display substrate, comprising:

[0122] forming a light shielding layer on the substrate;

[0123] An active layer is formed on a side of the light shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate;

[0124] A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

[0125] In an exemplary embodiment, the method for preparing a display substrate further includes:

[0126] forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole;

[0127] A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the second via hole and the third via hole overlap in their orthographic projections on the substrate.

[0128] The embodiment of the present invention further provides a display device, comprising any of the above-mentioned display substrates. The display device includes a mobile phone, a tablet computer, a smart wearable product (such as a smart watch, a bracelet, etc.), a personal digital assistant (PDA), a car computer, etc. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above-mentioned foldable display device.

[0129] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0130] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: An active layer is disposed on one side of the substrate, wherein the active layer includes a channel region; A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate; A light shielding layer is arranged on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

2. The display substrate according to claim 1, characterized in that: The gate includes a main body portion and a protruding portion disposed on the main body portion, the protruding portion overlaps with an orthographic projection of the channel region on the substrate, and the main body portion does not overlap with an orthographic projection of the channel region on the substrate.

3. The display substrate according to claim 2, characterized in that: A gap is arranged between an edge of the main body portion close to the channel region and an edge of the channel region close to the main body portion.

4. The display substrate according to claim 2, characterized in that: The main body portion is in a strip shape, the active layer is in a strip shape, and an extension direction of the main body portion is substantially the same as an extension direction of the active layer.

5. The display substrate according to claim 2, characterized in that: The shape of the protruding portion includes a block shape or a strip shape.

6. The display substrate according to claim 1, characterized in that: The active layer has a strip shape and extends along a second direction. The gate has a strip shape and extends along a first direction, and the first direction intersects with the second direction.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The active layer further includes a first doping region and a second doping region, and the first doping region and the second doping region are connected through the channel region.

8. The display substrate according to claim 7, characterized in that: It also includes a first electrode and a second electrode, both of which are arranged on a side of the active layer away from the substrate, the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the second doped region through a second via hole.

9. The display substrate according to claim 8, characterized in that: It also includes a pixel electrode, which is arranged on a side of the first electrode and the second electrode away from the substrate, and the pixel electrode is connected to the second electrode through a third via hole.

10. The display substrate according to claim 9, characterized in that: The orthographic projections of the second via hole and the third via hole on the substrate overlap.

11. The display substrate according to claim 9, characterized in that: It also includes an organic medium layer, which is arranged between the pixel electrode and the second electrode. A fourth via hole is arranged in the organic medium layer, and the orthographic projection of the third via hole on the substrate is located within the orthographic projection of the fourth via hole on the substrate.

12. The display substrate according to claim 9, characterized in that: It also includes a common electrode, which is arranged on a side of the pixel electrode close to the substrate, and is connected to the pixel electrode through a fifth via hole.

13. The display substrate according to claim 12, characterized in that: It also includes a touch electrode, which is arranged between the common electrode and the pixel electrode, and the touch electrode is connected to the pixel electrode through the fifth via hole.

14. A display device, characterized in that: The display substrate comprises any one of claims 1 to 13.

15. A method for preparing a display substrate, characterized in that: include: forming a light shielding layer on the substrate; An active layer is formed on a side of the light shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate; A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

16. The method for preparing a display substrate according to claim 15, characterized in that: Also includes: forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole; A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the second via hole and the third via hole overlap in their orthographic projections on the substrate.

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