Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device comprises a base substrate, a transistor layer, an insulating layer, a first pixel electrode, a second pixel electrode and a pixel defining layer, and the base substrate comprises a display area comprising a first pixel area and a second pixel area. A transistor layer on the base substrate and including a first pixel circuit portion corresponding to the first pixel region and a second pixel circuit portion corresponding to the second pixel region, and an insulating layer on the transistor layer and having a first trench positioned between the first pixel region and the second pixel region, a first pixel electrode is on the insulating layer and electrically connected to the first pixel circuit portion, a second pixel electrode is on the insulating layer and electrically connected to the second pixel circuit portion, and a pixel defining layer is on the insulating layer, the first pixel electrode, and the second pixel electrode, extends into the first trench, and covers an inner surface of the first trench.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. More particularly, the present disclosure relates to a display device providing visual information and a method of manufacturing the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs) and / or quantum dot display devices is increasing.

[0003] The display device includes red pixels, green pixels and blue pixels, and each pixel includes a light-emitting element that emits light. In addition, in order to improve the light-emitting efficiency of the light-emitting element, the light-emitting element includes at least one common layer (e.g., a hole transport layer, an electron transport layer, etc.). Summary of the invention

[0004] One or more embodiments of the present disclosure provide a display device.

[0005] One or more embodiments of the present disclosure provide a method for manufacturing a display device.

[0006] According to one or more embodiments, a display device includes a base substrate, a transistor layer, an insulating layer, a first pixel electrode, a second pixel electrode and a pixel defining layer, the base substrate includes a display area including a first pixel area and a second pixel area and a peripheral area around the display area, the transistor layer is located on the base substrate and includes a first pixel circuit portion corresponding to the first pixel area and a second pixel circuit portion corresponding to the second pixel area, the insulating layer is located on the transistor layer and has a contact hole exposing the first pixel circuit portion and the second pixel circuit portion and a first groove positioned between the first pixel area and the second pixel area, the first pixel electrode is positioned at the first pixel area on the insulating layer and is electrically connected to the first pixel circuit portion, the second pixel electrode is positioned at the second pixel area of ​​the insulating layer and is electrically connected to the second pixel circuit portion, the pixel defining layer is located on the insulating layer, the first pixel electrode and the second pixel electrode, the pixel defining layer exposes a portion of each of the first pixel electrode and the second pixel electrode, the pixel defining layer extends into the first groove, and the pixel defining layer covers the inner surface of the first groove.

[0007] In one or more embodiments, the pixel defining layer may include a first defining layer located on the insulating layer and spaced apart from the first groove in a plan view; a second defining layer located on the first defining layer and spaced apart from the first groove in a plan view; and a third defining layer located on the second defining layer, extending into the first groove and covering an inner surface of the first groove.

[0008] In one or more embodiments, the insulating layer may include an organic material, and each of the first, second, and third defining layers may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0009] In one or more embodiments, in a cross-sectional view, a width of the first trench may be smaller than a separation distance between the first pixel electrode and the second pixel electrode, and a thickness of the third defining layer may be smaller than the width of the first trench.

[0010] In one or more embodiments, a side surface of the pixel defining layer may have a stepped step.

[0011] In one or more embodiments, the display device may further include a common layer on the insulating layer and the pixel defining layer and disconnected by the first trench, and a common electrode on the common layer and not disconnected by the first trench.

[0012] In one or more embodiments, the common layer may include a first hole transport layer, a first light-emitting layer located on the first hole transport layer, a first electron transport layer located on the first light-emitting layer, a first charge generation layer located on the first electron transport layer, a second hole transport layer located on the first charge generation layer, a second light-emitting layer located on the second hole transport layer, a second electron transport layer located on the second light-emitting layer, a second charge generation layer located on the second electron transport layer, a third hole transport layer located on the second charge generation layer, a third light-emitting layer located on the third hole transport layer, and a third electron transport layer located on the third light-emitting layer.

[0013] In one or more embodiments, the display device may further include a first dam located in the peripheral area and surrounding the display area and a second dam located in the peripheral area and surrounding the first dam, and the first dam may include: a first lower dam including a material the same as that of the insulating layer and having a second groove surrounding the display area; a first upper dam located on the first lower dam and spaced apart from the second groove in a plan view; a second upper dam located on the first upper dam and spaced apart from the second groove in a plan view; and a third upper dam located on the second upper dam, extending into the second groove and covering an inner surface of the second groove.

[0014] In one or more embodiments, the first lower dam may include an organic material, and each of the first upper dam, the second upper dam, and the third upper dam may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0015] In one or more embodiments, the second dam may include: a second lower dam including a material the same as that of the insulating layer and having a third groove surrounding the display area; a fourth upper dam located on the second lower dam and spaced apart from the third groove in a plan view; a fifth upper dam located on the fourth upper dam and spaced apart from the third groove in a plan view; and a sixth upper dam located on the fifth upper dam, extending into the third groove and covering an inner surface of the third groove.

[0016] In one or more embodiments, the second lower dam may include an organic material, and each of the fourth upper dam, the fifth upper dam, and the sixth upper dam may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0017] In one or more embodiments, each of the second trench and the third trench may have a closed loop shape.

[0018] In one or more embodiments, the base substrate may include a silicon wafer.

[0019] In one or more embodiments, the display device may further include a connection pattern in the contact hole of the insulating layer, and the connection pattern may electrically connect the first pixel electrode and the first pixel circuit portion and may electrically connect the second pixel electrode and the second pixel circuit portion.

[0020] According to one or more embodiments, a method for manufacturing a display device includes: forming a transistor layer including a first pixel circuit portion corresponding to the first pixel area and a second pixel circuit portion corresponding to the second pixel area on a base substrate including a display area including a first pixel area and a second pixel area and a peripheral area located around the display area, forming an insulating layer on the transistor layer, forming a first pixel electrode located in the first pixel area and a second pixel electrode located in the second pixel area on the insulating layer, forming a first preliminary defining layer covering the first pixel electrode and the second pixel electrode and exposing a portion of the insulating layer on the insulating layer, forming a second preliminary defining layer exposing a portion of the insulating layer on the first preliminary defining layer, forming a first groove positioned between the first pixel area and the second pixel area by removing a portion of the insulating layer exposed from the first preliminary defining layer and the second preliminary defining layer, forming a third preliminary defining layer on the insulating layer and the second preliminary defining layer to extend into the first groove and cover an inner surface of the first groove, and forming a pixel defining layer exposing a portion of each of the first pixel electrode and the second pixel electrode, extending into the first groove and covering the inner surface of the first groove by removing a portion of the first preliminary defining layer, a portion of the second preliminary defining layer, and a portion of the third preliminary defining layer.

[0021] In one or more embodiments, each of the first preliminary defining layer, the second preliminary defining layer, and the third preliminary defining layer may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0022] In one or more embodiments, in a cross-sectional view, a width of the first trench may be smaller than a separation distance between the first pixel electrode and the second pixel electrode, and a thickness of the third preliminary defining layer may be smaller than the width of the first trench.

[0023] In one or more embodiments, the pixel defining layer may include a first defining layer formed on the insulating layer by removing a portion of the first preliminary defining layer, a second defining layer formed on the first defining layer by removing a portion of the second preliminary defining layer, and a third defining layer formed on the second defining layer by removing a portion of the third preliminary defining layer, the first defining layer and the second defining layer may be spaced apart from the first groove, and the third defining layer may extend into the first groove and cover an inner surface of the first groove.

[0024] In one or more embodiments, the method may further include forming a common layer disconnected by the first groove on the insulating layer and the pixel defining layer and forming a common electrode not disconnected by the first groove on the common layer, and forming the common layer and forming the common electrode may be performed after forming the pixel defining layer.

[0025] In one or more embodiments, in forming the insulating layer, a first lower dam in the peripheral area and surrounding the display area and a second lower dam in the peripheral area and surrounding the first lower dam may be formed, and in forming the first groove, a second groove surrounding the display area is formed in the first lower dam and a third groove surrounding the second groove may be formed in the second lower dam.

[0026] In one or more embodiments, the second trench and the third trench may be formed to have a closed loop shape.

[0027] In one or more embodiments, in forming a pixel defining layer, a first upper dam separated from the second groove may be formed on the first lower dam by removing a portion of the first preliminary defining layer, a second upper dam separated from the second groove may be formed on the first upper dam by removing a portion of the second preliminary defining layer, and a third upper dam extending into the second groove and covering the inner surface of the second groove may be formed on the second upper dam by removing a portion of the third preliminary defining layer.

[0028] In one or more embodiments, the first lower dam may include an organic material, and each of the first upper dam, the second upper dam, and the third upper dam may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0029] In one or more embodiments, in forming the pixel defining layer, a fourth upper dam separated from the third groove may be formed on the second lower dam by removing a portion of the first preliminary defining layer, a fifth upper dam separated from the third groove may be formed on the fourth upper dam by removing a portion of the second preliminary defining layer, and a sixth upper dam extending into the third groove and covering the inner surface of the third groove may be formed on the fifth upper dam by removing a portion of the third preliminary defining layer.

[0030] In one or more embodiments, the second lower dam may include an organic material, and each of the fourth upper dam, the fifth upper dam, and the sixth upper dam may include at least one of silicon oxide, silicon nitride, and silicon carbonitride.

[0031] The display device according to the embodiment may be divided into a display area and a peripheral area, and the display area may include a first pixel area and a second pixel area. In addition, the display device may include a transistor layer and an insulating layer located on the transistor layer, the transistor layer including a first pixel circuit portion corresponding to the first pixel area and a second pixel circuit portion corresponding to the second pixel area. In addition, the insulating layer may define a groove positioned between the first pixel area and the second pixel area. In addition, the pixel defining layer located on the insulating layer may have a structure in which a plurality of layers are stacked, and the uppermost layer among the plurality of layers of the pixel defining layer may extend into the groove and may cover the inner surface of the groove.

[0032] Therefore, by adjusting the width of the groove and the thickness of the uppermost layer of the pixel defining layer, the size of the remaining space in the groove can be changed in various ways. Therefore, the size of the remaining space in the groove required to disconnect the common layer on the insulating layer and the pixel defining layer and avoid disconnecting the common electrode on the common layer can be easily achieved. In other words, the common layer can be disconnected by the groove, and the common electrode may not be disconnected by the groove.

[0033] Therefore, when the common layer is disconnected by the groove, the current applied to the common layer from the first pixel electrode in the first pixel area may not leak into the common layer on the second pixel electrode in the second pixel area. That is, the current leakage through the common layer between adjacent pixel areas can be reduced or prevented. At the same time, the common electrode may not be disconnected by the groove. For example, the common electrode may be integrally located on the entire surface of the display area without being disconnected. Therefore, the voltage drop (IR drop) phenomenon of the common electrode can be reduced or prevented.

[0034] In addition, the display device may include a dam located in the peripheral area, and the dam may define a groove formed together with the groove of the insulating layer. Since the dam defines the groove, the phenomenon that the organic material of the organic encapsulation layer of the thin film encapsulation layer sealing the display area flows outward from the dam can be further reduced or prevented.

[0035] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0037] Figure 1 is a plan view showing a display device according to one or more embodiments.

[0038] Figure 2 It is shown Figure 1 A cross-sectional view of a display device.

[0039] Figure 3 It is shown that the Figure 2 A cross-sectional view of a thin film encapsulation layer, a color conversion layer, and a glass encapsulation layer in a display device.

[0040] Figure 4 It is shown that the Figure 2 A plan view of a stacked structure of a base substrate, a transistor layer, and a light-emitting element layer in a display device.

[0041] Figure 5 It is shown that the Figure 4 A cross-sectional view of the stacked structure of the first pixel region in the light-emitting element layer.

[0042] Figure 6 According to one or more embodiments Figure 4 A cross-sectional view taken along line II'.

[0043] Figure 7 According to one or more embodiments Figure 1 A cross-sectional view taken along line II-II'.

[0044] Figures 8 to 27 It shows the manufacturing Figure 6 and Figure 7 A view of a method of displaying an apparatus.

[0045] Fig.28 According to one or more embodiments Figure 4 A cross-sectional view taken along line II'.

[0046] Fig.29 According to one or more embodiments Figure 1 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0047] The present disclosure will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals indicate the same elements throughout the text.

[0048] For the purposes of the present disclosure, expressions such as "at least one of," "one of," and "selected from," when following a list of elements, modify the entire list of elements rather than the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as XYZ, XYY, XZ, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure."

[0049] Figure 1 is a plan view showing a display device according to one or more embodiments, and Figure 2 It is shown Figure 1 A cross-sectional view of a display device.

[0050] Reference Figure 1 , a display device DD according to one or more embodiments (eg, Figure 2 The base substrate SUB in the display device may include a display area DA and a peripheral area PA. The display area DA may be an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area PA may be an area where an image is not displayed. The peripheral area PA may be positioned around the display area DA. For example, the peripheral area PA may be around the display area DA (e.g., may completely surround the display area DA).

[0051] The display area DA may include a plurality of pixel areas. The pixel areas may be arranged in a matrix along a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the pixel areas may be arranged along rows and columns of a matrix along the first direction D1 and the second direction D2. For example, the pixel areas may include a first pixel area PX1, a second pixel area PX2, and a third pixel area PX3.

[0052] Each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may mean an area where light emitted from the light emitting element is emitted to the outside of the display device DD. For example, the first pixel region PX1 may emit a first color light, the second pixel region PX2 may emit a second color light, and the third pixel region PX3 may emit a third color light. In one or more embodiments, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the present disclosure is not limited thereto. For example, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may be combined to emit yellow light, cyan light, and magenta light.

[0053] Each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may have a triangular planar shape, a square planar shape, a circular planar shape, an elliptical planar shape, etc. In one or more embodiments, each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may have a rectangular planar shape. However, the present disclosure is not limited thereto, and each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may have a planar shape other than a rectangle.

[0054] also, Figure 1 It is shown that the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 have the same size, but the present disclosure is not necessarily limited thereto. The first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 may have different sizes.

[0055] A first dam DAM1 and a second dam DAM2 may be positioned in the peripheral area PA. The first dam DAM1 may be around the display area DA (e.g., may surround the display area DA). The second dam DAM2 may be spaced apart from the first dam DAM1 and may be around the first dam DAM1 (e.g., may surround the first dam DAM1). In one or more embodiments, the first dam DAM1 and the second dam DAM2 may reduce or block the organic material of the organic encapsulation layer of the thin film encapsulation layer that seals the display area DA from flowing outward from each of the first dam DAM1 and the second dam DAM2.

[0056] In the present disclosure, a plane may be defined as extending in a first direction D1 and a second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. The third direction D3 may be a normal direction of the plane.

[0057] Reference Figure 2, the display device DD may include a base substrate SUB, a transistor layer TL, a light emitting element layer EL, a thin film encapsulation layer TFE, a color conversion layer CCL, and a glass encapsulation layer ENC. The transistor layer TL, the light emitting element layer EL, the thin film encapsulation layer TFE, the color conversion layer CCL, and the glass encapsulation layer ENC may be sequentially stacked on the base substrate SUB.

[0058] The base substrate SUB may include a silicon wafer. The base substrate SUB may be a supporting member for supporting other components of the display device DD.

[0059] The transistor layer TL may generate a driving current. For example, the transistor layer TL may include a pixel circuit portion. Each of the pixel circuit portions may include various driving elements, wirings, etc. for driving a light emitting element.

[0060] The light emitting element layer EL may emit light corresponding to the driving current. The thin film encapsulation layer TFE may prevent moisture and external air from penetrating into the light emitting element layer EL. The color conversion layer CCL may convert the color of light emitted from the light emitting element layer EL, and the glass encapsulation layer ENC may protect the light emitting element layer EL and the color conversion layer CCL from impact.

[0061] Figure 3 It is shown that the Figure 2 A cross-sectional view of a thin film encapsulation layer, a color conversion layer, and a glass encapsulation layer in a display device.

[0062] Reference Figure 3 The thin film encapsulation layer TFE may include a first inorganic encapsulation layer IEL1, an organic encapsulation layer OEL, and a second inorganic encapsulation layer IEL2. The color conversion layer CCL may include a color filter layer CF, a micro lens array MLA, and a filler FM.

[0063] The first inorganic encapsulation layer IEL1 may be arranged on the light emitting element layer EL. In one or more embodiments, the first inorganic encapsulation layer IEL1 may be formed of an inorganic material. Examples of inorganic materials that can be used as the first inorganic encapsulation layer IEL1 may include silicon oxide, silicon nitride and / or silicon oxynitride. These can be used alone or in combination with each other.

[0064] The organic encapsulation layer OEL may be arranged on the first inorganic encapsulation layer IEL1. In one or more embodiments, the organic encapsulation layer OEL may be formed of an organic material. Examples of organic materials that can be used as the organic encapsulation layer OEL may include photoresists, polyacrylic resins, polyimide resins, and / or acrylic resins. These can be used alone or in combination with each other.

[0065] The second inorganic encapsulating layer IEL2 may be disposed on the organic encapsulating layer OEL, and may be formed of substantially the same material as that of the first inorganic encapsulating layer IEL1.

[0066] The color filter layer CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. In one or more embodiments, the first color filter CF1 may convert the color of light emitted from the light emitting element layer EL into red, the second color filter CF2 may convert the color of light emitted from the light emitting element layer EL into green, and the third color filter CF3 may convert the color of light emitted from the light emitting element layer EL into blue. In other words, the first color filter CF1 may correspond to the first pixel region PX1, the second color filter CF2 may correspond to the second pixel region PX2, and the third color filter CF3 may correspond to the third pixel region PX3.

[0067] The microlens array MLA may include a plurality of microlenses. The microlens array MLA may create a virtual image from an image provided by the light emitting element layer EL and the color filter layer CF, and may project the virtual image to the user's eyes.

[0068] The filler FM may protect the color filter layer CF and the microlens array MLA from impact, and may include a liquid polymer.

[0069] The glass encapsulation layer ENC may be formed of glass and may protect underlying components from impact.

[0070] Figure 4 It is shown that the Figure 2 A plan view of a stacked structure of a base substrate, a transistor layer, and a light-emitting element layer in a display device of Figure 5 It is shown that the Figure 4 A cross-sectional view of a stacked structure of a first pixel region in a light-emitting element layer, and Figure 6 According to one or more embodiments Figure 4 A cross-sectional view taken along line II'.

[0071] In one or more embodiments, the stack structure of each of the second pixel region PX2 and the third pixel region PX3 may be similar to Figure 5 The stacking structure of the first pixel region PX1 shown in FIG. 1 is substantially the same. Therefore, the corresponding description is omitted.

[0072] In addition, the cross-sectional structure between the second pixel region PX2 and the third pixel region PX3 may be similar to Figure 6 The cross-sectional structures between the first pixel region PX1 and the second pixel region PX2 shown in FIG. 1 are substantially the same. Therefore, the corresponding description is omitted.

[0073] Reference Figure 4 and Figure 5 , a first pixel electrode PE1 , a common layer CL, a common electrode CE, and a cover layer CPL may be disposed in the first pixel region PX1 .

[0074] The common layer CL may be formed in all of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. The common layer CL may include a first hole transport layer HTL1, a first auxiliary layer BIL, a first light emitting layer BEML, a first electron transport layer ETL1, a first charge generation layer CGL1, a second hole transport layer HTL2, a second auxiliary layer RIL, a second light emitting layer REML, a second electron transport layer ETL2, a second charge generation layer CGL2, a third hole transport layer HTL3, a third auxiliary layer GIL, a third light emitting layer GEML, and a third electron transport layer ETL3. The first charge generation layer CGL1 may include a first n-type charge generation layer nCGL1 and a first p-type charge generation layer pCGL1, and the second charge generation layer CGL2 may include a second n-type charge generation layer nCGL2 and a second p-type charge generation layer pCGL2.

[0075] The first pixel electrode PE1 may be arranged on the transistor layer TL. In one or more embodiments, the first pixel electrode PE1 may be electrically connected to the transistor layer TL. For example, the first pixel electrode PE1 may be electrically connected to a first pixel circuit portion PXC1 (in Figure 6 The first pixel electrode PE1 may be formed of a metal, an alloy, a metal oxide, a reflective conductive material, etc. Examples of materials that can be used as the first pixel electrode PE1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0076] The first hole transport layer HTL1 may be arranged on the first pixel electrode PE1. The first hole transport layer HTL1 may increase the mobility of holes. In one or more embodiments, the first hole transport layer HTL1 may include a hole transport material. Examples of materials that can be used as the first hole transport layer HTL1 may include HATCN (1,4,5,8,9,11-hexaazatriphenylene-hexanitrile), CuPc (copper phthalocyanine), PEDOT (poly (3,4-ethylenedioxythiophene)), PANI (polyaniline), NPD (N,N'-dinaphthyl-N,N'-diphenylbenzidine), etc. These can be used alone or in combination with each other.

[0077] The first auxiliary layer BIL may be disposed on the first hole transport layer HTL1. The first auxiliary layer BIL may enhance the resonance of light emitted from the first light emitting layer BEML. In one or more embodiments, the first auxiliary layer BIL may be formed of an amine-based organic compound, and the resonance may be enhanced by adjusting the thickness of the first auxiliary layer BIL. In one or more embodiments, the first auxiliary layer BIL may include a highly reflective metal such as Ag and / or MgAg, and a highly reflective metal such as SiN, SiO 2 、TiO 2 、 2 O 5 , ITO and / or IZO materials for optical path adjustment.

[0078] The first light emitting layer BEML may be disposed on the first auxiliary layer BIL. When electrons and holes are injected into the first light emitting layer BEML, the first light emitting layer BEML may emit light of a preset color. For example, the first light emitting layer BEML may be formed of an organic material emitting blue light and may emit blue light. However, the present disclosure is not necessarily limited thereto.

[0079] The first electron transport layer ETL1 may be disposed on the first light emitting layer BEML. The first electron transport layer ETL1 may increase electron mobility. In one or more embodiments, the first electron transport layer ETL1 may include an electron transport material. Examples of materials that can be used as the first electron transport layer ETL1 may include 8-hydroxyquinoline lithium (LiQ), Alq 3 (tris(8-hydroxyquinoline)aluminum), PBD(2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ, spiro-PBD, etc. These can be used alone or in combination with each other.

[0080] The first n-type charge generation layer nCGL1 may be disposed on the first electron transport layer ETL1. The first n-type charge generation layer nCGL1 may supply electrons to the first light emitting layer BEML. Examples of materials that can be used as the first n-type charge generation layer nCGL1 may include metals, alloys, metal oxides, reflective conductive materials, and / or organic materials doped with n-type materials.

[0081] The first p-type charge generation layer pCGL1 may be disposed on the first n-type charge generation layer nCGL1. The first p-type charge generation layer pCGL1 may supply holes to the second light emitting layer REML. Examples of materials that can be used as the first p-type charge generation layer pCGL1 may include metals, alloys, metal oxides, reflective conductive materials, and / or organic materials doped with p-type materials.

[0082] The second hole transport layer HTL2 may be disposed on the first p-type charge generation layer pCGL1. The second hole transport layer HTL2 may increase the mobility of holes. In one or more embodiments, the second hole transport layer HTL2 may include a hole transport material.

[0083] The second auxiliary layer RIL may be disposed on the second hole transport layer HTL2. The second auxiliary layer RIL may enhance resonance of light emitted from the second light emitting layer REML.

[0084] The second light emitting layer REML may be disposed on the second auxiliary layer RIL. When electrons and holes are injected into the second light emitting layer REML, the second light emitting layer REML may emit light of a preset color. For example, the second light emitting layer REML may be formed of an organic material emitting red light and may emit red light. However, the present disclosure is not necessarily limited thereto.

[0085] The second electron transport layer ETL2 may be disposed on the second light emitting layer REML. The second electron transport layer ETL2 may increase electron mobility. In one or more embodiments, the second electron transport layer ETL2 may include an electron transport material.

[0086] The second n-type charge generation layer nCGL2 may be disposed on the second electron transport layer ETL2. The second n-type charge generation layer nCGL2 may supply electrons to the second light emitting layer REML. Examples of materials that can be used as the second n-type charge generation layer nCGL2 may include metals, alloys, metal oxides, reflective conductive materials, and / or organic materials doped with n-type materials.

[0087] The second p-type charge generation layer pCGL2 may be disposed on the second n-type charge generation layer nCGL2. The second p-type charge generation layer pCGL2 may supply holes to the third light emitting layer GEML. Examples of materials that can be used as the second p-type charge generation layer pCGL2 may include metals, alloys, metal oxides, reflective conductive materials, and / or organic materials doped with p-type materials.

[0088] The third hole transport layer HTL3 may be disposed on the second p-type charge generation layer pCGL2. The third hole transport layer HTL3 may increase the mobility of holes. In one or more embodiments, the third hole transport layer HTL3 may include a hole transport material.

[0089] The third auxiliary layer GIL may be disposed on the third hole transport layer HTL3. The third auxiliary layer GIL may enhance resonance of light emitted from the third light emitting layer GEML.

[0090] The third light emitting layer GEML may be disposed on the third auxiliary layer GIL. When electrons and holes are injected into the third light emitting layer GEML, the third light emitting layer GEML may emit light of a preset color. For example, the third light emitting layer GEML may be formed of an organic material emitting green light and may emit green light. However, the present disclosure is not necessarily limited thereto.

[0091] The third electron transport layer ETL3 may be disposed on the third light emitting layer GEML. The third electron transport layer ETL3 may increase electron mobility. In one or more embodiments, the third electron transport layer ETL3 may include an electron transport material.

[0092] In one or more embodiments, Figure 5 The structure of the common layer CL shown in FIG. 1 is an example and may be changed in various ways according to the embodiment. For example, the common layer CL may have a structure in which the Figure 5 The structure of at least one of the components shown in Figure 5 The structure of the components not shown in the figure.

[0093] The common electrode CE may be arranged on the third electron transport layer ETL3. In one or more embodiments, the common electrode CE may include a metal, an alloy, a metal oxide, a reflective conductive material, etc. Examples of materials that can be used as the common electrode CE may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0094] The cover layer CPL may be disposed on the common electrode CE. The refractive index of the cover layer CPL may resonate the light emitted from the first light emitting layer BEML, the second light emitting layer REML, and the third light emitting layer GEML, and the light extraction efficiency of the first light emitting layer BEML, the second light emitting layer REML, and the third light emitting layer GEML may be improved. For example, the cover layer CPL may include an organic material and / or an inorganic material.

[0095] Further references Figure 6 , the transistor layer TL may include a first pixel circuit portion PXC1 and a second pixel circuit portion PXC2. The first pixel circuit portion PXC1 may correspond to the first pixel region PX1, and the second pixel circuit portion PXC2 may correspond to the second pixel region PX2. As described above, the first pixel circuit portion PXC1 and the second pixel circuit portion PXC2 may include various driving elements, wirings, etc. for driving the light emitting element.

[0096] An insulating layer IL may be arranged on the transistor layer TL. The insulating layer IL may be arranged in the display area DA. The insulating layer IL may prevent contact between the pixel electrode and the pixel circuit portion. The insulating layer IL may include an organic material. Examples of organic materials that can be used as the insulating layer IL may include photoresists, polyacrylic resins, polyimide resins, and / or acrylic resins. These can be used alone or in combination with each other.

[0097] The insulating layer IL may define a contact hole that penetrates the insulating layer IL and exposes the first pixel circuit portion PXC1 and the second pixel circuit portion PXC2. Each of the contact holes may be filled with a connection pattern CP. The connection pattern CP may be electrically connected to the first pixel circuit portion PXC1 and the second pixel circuit portion PXC2. For example, the connection pattern CP positioned in the first pixel area PX1 may be electrically connected to the first pixel circuit portion PXC1, and the connection pattern CP positioned in the second pixel area PX2 may be electrically connected to the second pixel circuit portion PXC2. In one or more embodiments, the connection pattern CP may include a conductive material. For example, the connection pattern CP may include tungsten (W).

[0098] The insulating layer IL may have a first trench TRC1 positioned between the first pixel region PX1 and the second pixel region PX2 . Figure 6 The first trench TRC1 is shown to expose the upper surface of the transistor layer TL, but the present disclosure is not necessarily limited thereto. In one or more embodiments, the first trench TRC1 may not expose the upper surface of the transistor layer TL, but may extend from the upper surface of the insulating layer IL only to the inside of the insulating layer IL. In one or more embodiments, the first trench TRC1 may extend from the upper surface of the insulating layer IL through the upper surface of the transistor layer TL to the inside of the transistor layer TL.

[0099] The pixel electrodes may be arranged on the insulating layer IL. For example, the first pixel electrode PE1 may be arranged on the insulating layer IL to correspond to the first pixel region PX1, and the second pixel electrode PE2 may be arranged on the insulating layer IL to correspond to the second pixel region PX2. The first pixel electrode PE1 may be electrically connected to the first pixel circuit portion PXC1 through the connection pattern CP, and the second pixel electrode PE2 may be electrically connected to the second pixel circuit portion PXC2 through the connection pattern CP.

[0100] The first pixel electrode PE1 and the second pixel electrode PE2 may be spaced apart from the first trench TRC1. That is, the first pixel electrode PE1 and the second pixel electrode PE2 may be arranged across the first trench TRC1. In other words, the first trench TRC1 may be positioned between the first pixel electrode PE1 and the second pixel electrode PE2. For example, the width WD of the first trench TRC1 may be less than the separation distance SD between the first pixel electrode PE1 and the second pixel electrode PE2.

[0101] A pixel defining layer PDL may be disposed on the insulating layer IL, the first pixel electrode PE1, and the second pixel electrode PE2.

[0102] The pixel defining layer PDL may cover a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2. That is, the pixel defining layer PDL may expose a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2. For example, the pixel defining layer PDL may cover a side portion of each of the first pixel electrode PE1 and the second pixel electrode PE2, and expose a central portion of each of the first pixel electrode PE1 and the second pixel electrode PE2.

[0103] The pixel defining layer PDL may extend into the first trench TRC1 and cover the inner surface of the first trench TRC1. Figure 6 As shown in , the pixel defining layer PDL may extend into the first trench TRC1 and cover all surfaces defining the first trench TRC1.

[0104] In one or more embodiments, the pixel defining layer PDL may include a first defining layer DL1, a second defining layer DL2, and a third defining layer DL3. The first defining layer DL1, the second defining layer DL2, and the third defining layer DL3 may be sequentially stacked on the insulating layer IL.

[0105] The first defining layer DL1 may be arranged on the insulating layer IL and on a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2, and may be spaced apart from the first trench TRC1 in a plan view. That is, the first defining layer DL1 may not be arranged inside the first trench TRC1. In one or more embodiments, the first defining layer DL1 may include an inorganic material. For example, the first defining layer DL1 may include silicon oxide, silicon nitride, and / or silicon carbonitride.

[0106] The second defining layer DL2 may be arranged on the first defining layer DL1 and may be spaced apart from the first trench TRC1 in a plan view. That is, the second defining layer DL2 may not be arranged inside the first trench TRC1. In one or more embodiments, the second defining layer DL2 may include an inorganic material. For example, the second defining layer DL2 may include silicon oxide, silicon nitride, and / or silicon carbonitride.

[0107] In one or more embodiments, the second defining layer DL2 may expose a portion of the first defining layer DL1. That is, an end portion of the first defining layer DL1 and an end portion of the second defining layer DL2 may define a stair-shaped step.

[0108] The third definition layer DL3 may be disposed on the second definition layer DL2, extend into the first trench TRC1, and cover the inner surface of the first trench TRC1. Figure 6 As shown in , the third defining layer DL3 may extend into the first trench TRC1 and cover all surfaces defining the first trench TRC1. In other words, when the third defining layer DL3 extends into the first trench TRC1 and covers the inner surface of the first trench TRC1, the pixel defining layer PDL may extend into the first trench TRC1 and cover the inner surface of the first trench TRC1.

[0109] In one or more embodiments, the third defining layer DL3 may expose a portion of the second defining layer DL2. That is, the end of the second defining layer DL2 and the end of the third defining layer DL3 may define a stair-shaped step. Therefore, the side surface of the pixel defining layer PDL may have a stair-shaped step. Therefore, the step coverage of the common layer CL and the common electrode CE formed on the pixel defining layer PDL may be improved. Therefore, the durability of the display device DD may be improved.

[0110] The thickness TH of the third definition layer DL3 may be smaller than the width WD of the first trench TRC1. That is, even when the third definition layer DL3 covers the inner surface of the first trench TRC1, a remaining space may remain in the first trench TRC1.

[0111] In one or more embodiments, Figure 6 As shown in , the pixel defining layer PDL may have a structure in which a first defining layer DL1, a second defining layer DL2, and a third defining layer DL3 are sequentially stacked. For example, the pixel defining layer PDL may have a three-layer structure in which a first defining layer DL1 including silicon nitride, a second defining layer DL2 including silicon oxide, and a third defining layer DL3 including silicon nitride are sequentially stacked. In addition, the pixel defining layer PDL may have a three-layer structure in which a first defining layer DL1 including silicon carbonitride, a second defining layer DL2 including silicon oxide, and a third defining layer DL3 including silicon carbonitride are sequentially stacked. In addition, the pixel defining layer PDL may have a three-layer structure in which a first defining layer DL1 including silicon oxide, a second defining layer DL2 including silicon nitride, and a third defining layer DL3 including silicon oxide are sequentially stacked. In addition, the pixel defining layer PDL may have a three-layer structure in which a first defining layer DL1 including silicon oxide, a second defining layer DL2 including silicon carbonitride, and a third defining layer DL3 including silicon oxide are sequentially stacked. However, this is merely an example, and a stack structure of the pixel defining layer PDL and a material of each layer constituting the pixel defining layer PDL may be variously changed according to one or more embodiments.

[0112] The common layer CL may be disposed on the insulating layer IL, the first pixel electrode PE1, the second pixel electrode PE2, and the pixel defining layer PDL, and may be disconnected by the first trench TRC1. Therefore, the common layer CL disposed on the first pixel electrode PE1 and the common layer CL disposed on the second pixel electrode PE2 may not be electrically connected to each other.

[0113] For example, by adjusting the width WD of the first trench TRC1 and the thickness TH of the third definition layer DL3 , the size of the remaining space in the first trench TRC1 required to disconnect the common layer CL may be achieved. Therefore, the common layer CL may be disconnected by the first trench TRC1 .

[0114] Therefore, current applied to the common layer CL from the first pixel electrode PE1 corresponding to the first pixel region PX1 may not leak into the common layer CL disposed on the second pixel electrode PE2. That is, current leakage through the common layer CL between adjacent pixel regions may be reduced or prevented.

[0115] The common electrode CE may be disposed on the common layer CL and may not be disconnected by the first trench TRC1. For example, the common electrode CE may be integrally disposed on the entire surface of the display area DA without being disconnected.

[0116] For example, by adjusting the width WD of the first groove TRC1 and the thickness TH of the third limiting layer DL3, the size of the remaining space in the first groove TRC1 required to avoid disconnecting the common electrode CE can be easily achieved. Therefore, the common electrode CE may not be disconnected by the first groove TRC1. Therefore, the voltage drop (IR drop) phenomenon of the common electrode CE can be prevented.

[0117] As a result, according to one or more embodiments, the insulating layer IL disposed on the transistor layer TL may define the first trench TRC1 positioned between the first pixel region PX1 and the second pixel region PX2. In addition, the pixel defining layer PDL on the insulating layer IL may have a structure in which a plurality of layers are stacked, and the uppermost layer (e.g., the third defining layer DL3) among the plurality of layers of the pixel defining layer PDL may extend into the first trench TRC1 and may cover the inner surface of the first trench TRC1.

[0118] Therefore, by adjusting the width WD of the first groove TRC1 and the thickness of the uppermost layer of the pixel defining layer PDL, the size of the remaining space in the first groove TRC1 can be changed in various ways. Therefore, the size of the remaining space in the first groove TRC1 required to disconnect the common layer CL on the insulating layer IL and the pixel defining layer PDL and avoid disconnecting the common electrode CE on the common layer CL can be achieved. In other words, the common layer CL can be disconnected by the first groove TRC1, and the common electrode CE may not be disconnected by the first groove TRC1.

[0119] Since the common layer CL is disconnected by the first groove TRC1, the current applied to the common layer CL from the first pixel electrode PE1 corresponding to the first pixel area PX1 may not leak into the common layer CL arranged on the second pixel electrode PE2. That is, the current leakage through the common layer CL between adjacent pixel areas can be reduced or prevented. At the same time, the common electrode CE may not be disconnected by the first groove TRC1. For example, the common electrode CE may be arranged integrally on the entire surface of the display area DA without being disconnected. Therefore, the voltage drop (IR drop) phenomenon of the common electrode CE can be reduced or prevented.

[0120] Figure 7 According to one or more embodiments Figure 1 A cross-sectional view taken along line II-II'.

[0121] In one or more embodiments, for the convenience of description, Figure 7 The structures on the first dam DAM1 and the second dam DAM2 (eg, the thin film encapsulation layer TFE, etc.) are omitted.

[0122] Reference Figure 1 , Figure 6 and Figure 7 , the first dam DAM1 and the second dam DAM2 may be disposed in the peripheral area PA on the base substrate SUB. For example, the first dam DAM1 and the second dam DAM2 may be disposed on the transistor layer TL.

[0123] In one or more embodiments, the first dam DAM1 may include a first lower dam LDAM1, a first upper dam UDAM1, a second upper dam UDAM2, and a third upper dam UDAM3.

[0124] The first lower dam LDAM1 may be arranged on the transistor layer TL. The first lower dam LDAM1 may include the same material as that of the insulating layer IL. In other words, the first lower dam LDAM1 may be arranged at the same layer (e.g., at the same layer) as the insulating layer IL. In other words, the first lower dam LDAM1 may be formed together with the insulating layer IL in the same process. For example, the first lower dam LDAM1 may include an organic material. Examples of organic materials that can be used as the first lower dam LDAM1 may include photoresists, polyacrylic resins, polyimide resins, and / or acrylic resins. These can be used alone or in combination with each other.

[0125] In one or more embodiments, the first lower dam LDAM1 may define the second trench TRC2 around the display area DA (e.g., surrounding the display area DA). That is, the first lower dam LDAM1 may surround the display area DA, and the second trench TRC2 may penetrate the upper surface of the first lower dam LDAM1, so that the second trench TRC2 may surround the display area DA. In other words, the second trench TRC2 may have a closed loop shape. The second trench TRC2 may be formed together with the first trench TRC1 of the insulating layer IL.

[0126] Figure 7 The second trench TRC2 is shown to expose the upper surface of the transistor layer TL, but the present disclosure is not necessarily limited thereto. In one or more embodiments, the second trench TRC2 may not expose the upper surface of the transistor layer TL, but may extend from the upper surface of the first lower dam LDAM1 only to the inside of the first lower dam LDAM1. In one or more embodiments, the second trench TRC2 may extend from the upper surface of the first lower dam LDAM1 through the upper surface of the transistor layer TL to the inside of the transistor layer TL.

[0127] The first upper dam UDAM1 may be arranged on the first lower dam LDAM1 and may be spaced apart from the second trench TRC2 in a plan view. That is, the first upper dam UDAM1 may not be arranged in the second trench TRC2. The first upper dam UDAM1 may include the same material as that of the first definition layer DL1. In other words, the first upper dam UDAM1 may be arranged at the same layer (e.g., at the same layer) as the first definition layer DL1. In other words, the first upper dam UDAM1 may be formed together with the first definition layer DL1 in the same process. For example, the first upper dam UDAM1 may include an inorganic material. For example, the first upper dam UDAM1 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0128] The second upper dam UDAM2 may be arranged on the first upper dam UDAM1 and may be spaced apart from the second trench TRC2 in a plan view. That is, the second upper dam UDAM2 may not be arranged in the second trench TRC2. The second upper dam UDAM2 may include the same material as the material of the second definition layer DL2. In other words, the second upper dam UDAM2 may be arranged at the same layer (e.g., at the same layer) as the second definition layer DL2. In other words, the second upper dam UDAM2 may be formed together with the second definition layer DL2 in the same process. For example, the second upper dam UDAM2 may include an inorganic material. In one or more embodiments, the second upper dam UDAM2 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0129] The third upper dam UDAM3 may be disposed on the second upper dam UDAM2, extend into the second trench TRC2, and cover the inner surface of the second trench TRC2. Figure 7As shown in , the third upper dam UDAM3 may extend into the second trench TRC2 and cover all surfaces defining the second trench TRC2. The third upper dam UDAM3 may include the same material as the material of the third definition layer DL3. In other words, the third upper dam UDAM3 may be arranged at the same layer (e.g., at the same layer) as the third definition layer DL3. In other words, the third upper dam UDAM3 may be formed together with the third definition layer DL3 in the same process. For example, the third upper dam UDAM3 may include an inorganic material. In one or more embodiments, the third upper dam UDAM3 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0130] In one or more embodiments, the second dam DAM2 may include a second lower dam LDAM2 , a fourth upper dam UDAM4 , a fifth upper dam UDAM5 , and a sixth upper dam UDAM6 .

[0131] The second lower dam LDAM2 may be arranged on the transistor layer TL. The second lower dam LDAM2 may include the same material as the insulating layer IL and the first lower dam LDAM1. In other words, the second lower dam LDAM2 may be arranged at the same layer (e.g., at the same layer) as the insulating layer IL and the first lower dam LDAM1. In other words, the second lower dam LDAM2 may be formed together with the insulating layer IL and the first lower dam LDAM1 in the same process. For example, the second lower dam LDAM2 may include an organic material. Examples of organic materials that can be used as the second lower dam LDAM2 may include photoresists, polyacrylic resins, polyimide resins, and / or acrylic resins. These can be used alone or in combination with each other.

[0132] In one or more embodiments, the second lower dam LDAM2 may be defined as a third trench TRC3 around (e.g., surrounding) the second trench TRC2. That is, the second lower dam LDAM2 may surround the first lower dam LDAM1, and the third trench TRC3 may penetrate the upper surface of the second lower dam LDAM2, so that the third trench TRC3 may surround the second trench TRC2. In other words, the third trench TRC3 may have a closed loop shape. The third trench TRC3 may be formed together with the first trench TRC1 of the insulating layer IL and the second trench TRC2 of the first lower dam LDAM1.

[0133] Figure 7 The third trench TRC3 is shown to expose the upper surface of the transistor layer TL, but the present disclosure is not necessarily limited thereto. In one or more embodiments, the third trench TRC3 may not expose the upper surface of the transistor layer TL, but may extend from the upper surface of the second lower dam LDAM2 only to the inside of the second lower dam LDAM2. In one or more embodiments, the third trench TRC3 may extend from the upper surface of the second lower dam LDAM2 through the upper surface of the transistor layer TL to the inside of the transistor layer TL.

[0134] The fourth upper dam UDAM4 may be arranged on the second lower dam LDAM2 and may be spaced apart from the third trench TRC3 in a plan view. That is, the fourth upper dam UDAM4 may not be arranged in the third trench TRC3. The fourth upper dam UDAM4 may include the same material as the first limit layer DL1 and the first upper dam UDAM1. In other words, the fourth upper dam UDAM4 may be arranged at the same layer (e.g., at the same layer) as the first limit layer DL1 and the first upper dam UDAM1. In other words, the fourth upper dam UDAM4 may be formed together with the first limit layer DL1 and the first upper dam UDAM1 in the same process. For example, the fourth upper dam UDAM4 may include an inorganic material. For example, the fourth upper dam UDAM4 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0135] The fifth upper dam UDAM5 may be arranged on the fourth upper dam UDAM4 and may be spaced apart from the third trench TRC3 in a plan view. That is, the fifth upper dam UDAM5 may not be arranged in the third trench TRC3. The fifth upper dam UDAM5 may include the same material as the second limit layer DL2 and the second upper dam UDAM2. In other words, the fifth upper dam UDAM5 may be arranged at the same layer (e.g., at the same layer) as the second limit layer DL2 and the second upper dam UDAM2. In other words, the fifth upper dam UDAM5 may be formed together with the second limit layer DL2 and the second upper dam UDAM2 in the same process. For example, the fifth upper dam UDAM5 may include an inorganic material. For example, the fifth upper dam UDAM5 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0136] The sixth upper dam UDAM6 may be disposed on the fifth upper dam UDAM5, extend into the third trench TRC3, and cover the inner surface of the third trench TRC3. Figure 7 As shown in , the sixth upper dam UDAM6 may extend into the third trench TRC3 and cover all surfaces defining the third trench TRC3. The sixth upper dam UDAM6 may include the same material as the third defining layer DL3 and the third upper dam UDAM3. In other words, the sixth upper dam UDAM6 may be arranged at the same layer (e.g., at the same layer) as the third defining layer DL3 and the third upper dam UDAM3. In other words, the sixth upper dam UDAM6 may be formed together with the third defining layer DL3 and the third upper dam UDAM3 in the same process. For example, the sixth upper dam UDAM6 may include an inorganic material. For example, the sixth upper dam UDAM6 may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0137] According to one or more embodiments, each of the first dam DAM1 and the second dam DAM2 arranged in the peripheral area PA may define a groove. In addition, the groove may be formed together with the first groove TRC1 of the insulating layer IL. For example, the first lower dam LDAM1 of the first dam DAM1 may define a second groove TRC2 formed together with the first groove TRC1, and the second lower dam LDAM2 of the second dam DAM2 may define a third groove TRC3 formed together with the first groove TRC1. Therefore, the phenomenon in which the organic material of the thin film encapsulation layer sealing the display area DA flows outward from each of the first dam DAM1 and the second dam DAM2 may be further reduced or prevented.

[0138] The display device DD according to one or more embodiments may be a display device that displays an image. For example, the display device DD may be a display device such as an organic light-emitting display device, a liquid crystal display device, an organic light-emitting diode on silicon substrate (OLEDos), a liquid crystal on silicon substrate (LCos), a light-emitting diode on silicon substrate (LEDos), etc. In one or more embodiments, the display device DD may be a display device such as OLEDos.

[0139] For example, if the display device DD is a display device such as OLEDos, the display device DD may be a head-mounted display. The head-mounted display may be worn in the form of glasses, a helmet, etc., and may be a glasses-type monitor device for virtual reality or augmented reality that focuses at a distance close to the user's eyes. However, the present disclosure is not necessarily limited thereto, and the display device DD may be configured with various displays.

[0140] The display device DD according to one or more embodiments may be divided into a display area DA and a peripheral area PA, and the display area DA may include a first pixel area PX1 and a second pixel area PX2. In addition, the display device DD may include a transistor layer TL and an insulating layer IL arranged on the transistor layer TL, the transistor layer TL including a first pixel circuit portion PXC1 corresponding to the first pixel area PX1 and a second pixel circuit portion PXC2 corresponding to the second pixel area PX2. In addition, the insulating layer IL may define a first trench TRC1 positioned between the first pixel area PX1 and the second pixel area PX2. In addition, the pixel defining layer PDL on the insulating layer IL may have a structure in which a plurality of layers are stacked, and the uppermost layer among the plurality of layers of the pixel defining layer PDL may extend into the first trench TRC1 and may cover the inner surface of the first trench TRC1.

[0141] Therefore, by adjusting the width WD of the first groove TRC1 and the thickness of the uppermost layer of the pixel defining layer PDL, the size of the remaining space in the first groove TRC1 can be changed in various ways. Therefore, the size of the remaining space in the first groove TRC1 required to disconnect the common layer CL on the insulating layer IL and the pixel defining layer PDL and avoid disconnecting the common electrode CE on the common layer CL can be achieved. In other words, the common layer CL can be disconnected by the first groove TRC1, and the common electrode CE may not be disconnected by the first groove TRC1.

[0142] Therefore, when the common layer CL is disconnected by the first groove TRC1, the current applied to the common layer CL from the first pixel electrode PE1 corresponding to the first pixel region PX1 may not leak into the common layer CL arranged on the second pixel electrode PE2. That is, the current leakage through the common layer CL between adjacent pixel regions can be reduced or prevented. At the same time, the common electrode CE may not be disconnected by the first groove TRC1. For example, the common electrode CE may be arranged integrally on the entire surface of the display area DA without being disconnected. Therefore, the voltage drop (IR drop) phenomenon of the common electrode CE can be reduced or prevented.

[0143] In addition, the display device DD may include a first dam DAM1 and a second dam DAM2 arranged in the peripheral area PA, and each of the first dam DAM1 and the second dam DAM2 may define a groove formed together with the first groove TRC1 of the insulating layer IL. Since each of the first dam DAM1 and the second dam DAM2 defines the groove, a phenomenon in which an organic material of an organic encapsulation layer of a thin film encapsulation layer sealing the display area DA flows outward from each of the first dam DAM1 and the second dam DAM2 may be further reduced or prevented.

[0144] Figures 8 to 27 It shows the manufacturing Figure 6 and Figure 7 A view of a method of displaying an apparatus.

[0145] For example, Figure 8 , Fig.10 , Fig.11 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 and Fig. 27 It is shown Figure 6 , which is a cross-sectional view of a manufacturing process of a display device DD in a display area DA shown in FIG. Fig. 9 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 and Fig.25 It is shown Figure 7 0 is a cross-sectional view of a manufacturing process of a display device DD in a peripheral area PA shown in FIG.

[0146] Reference Figure 8 and Fig. 9 , a transistor layer TL may be formed on a base substrate SUB. The transistor layer TL may include a first pixel circuit portion PXC1 corresponding to the first pixel region PX1 and a second pixel circuit portion PXC2 corresponding to the second pixel region PX2. The base substrate SUB may be formed of a silicon wafer.

[0147] The insulating layer IL, the first lower dam LDAM1 and the second lower dam LDAM2 may be formed on the transistor layer TL. That is, the insulating layer IL, the first lower dam LDAM1 and the second lower dam LDAM2 may be formed together in the same process. The insulating layer IL, the first lower dam LDAM1 and the second lower dam LDAM2 may be formed of an organic material.

[0148] The contact hole CNT may be formed by removing a portion of the insulating layer IL in each of the first and second pixel regions PX1 and PX2 . The contact hole CNT may expose a portion of each of the first and second pixel circuit portions PXC1 and PXC2 .

[0149] Further references Fig.10 , the contact hole CNT may be filled with the connection pattern CP. For example, the connection pattern CP may be formed of tungsten (W). The connection pattern CP may be electrically connected to the first pixel circuit portion PXC1 and the second pixel circuit portion PXC2.

[0150] Further references Fig.11 , a first pixel electrode PE1 and a second pixel electrode PE2 may be formed in the display area DA on the insulating layer IL. For example, the first pixel electrode PE1 may correspond to the first pixel area PX1, and the second pixel electrode PE2 may correspond to the second pixel area PX2. The first pixel electrode PE1 and the second pixel electrode PE2 may be electrically connected to the connection pattern CP. Therefore, the first pixel electrode PE1 may be electrically connected to the first pixel circuit portion PXC1, and the second pixel electrode PE2 may be electrically connected to the second pixel circuit portion PXC2.

[0151] Further references Fig.12 and Fig.13, a first preliminary defining layer DL-A1 may be formed on the insulating layer IL, the first lower dam LDAM1, and the second lower dam LDAM2. The first preliminary defining layer DL-A1 may cover the first pixel electrode PE1 and the second pixel electrode PE2. The first preliminary defining layer DL-A1 may expose a portion of the insulating layer IL, a portion of the first lower dam LDAM1, and a portion of the second lower dam LDAM2. The first preliminary defining layer DL-A1 may be formed of an inorganic material. For example, the first preliminary defining layer DL-A1 may be formed of silicon oxide, silicon nitride, and / or silicon carbonitride.

[0152] Further references Fig.14 and Fig.15 , a second preliminary defining layer DL-A2 may be formed on the first preliminary defining layer DL-A1. The second preliminary defining layer DL-A2 may cover the first preliminary defining layer DL-A1. The second preliminary defining layer DL-A2 may expose a portion of the insulating layer IL, a portion of the first lower dam LDAM1, and a portion of the second lower dam LDAM2. The second preliminary defining layer DL-A2 may be formed of an inorganic material. For example, the second preliminary defining layer DL-A2 may be formed of silicon oxide, silicon nitride, and / or silicon carbonitride.

[0153] Further references Fig.16 and Fig.17 , a portion of the insulating layer IL may be removed to form the first trench TRC1. That is, the first trench TRC1 may be formed by removing a portion of the insulating layer IL exposed from the first preliminary defining layer DL-A1 and the second preliminary defining layer DL-A2. In addition, a portion of the first lower dam LDAM1 may be removed to form the second trench TRC2. That is, the second trench TRC2 may be formed by removing a portion of the first lower dam LDAM1 exposed from the first preliminary defining layer DL-A1 and the second preliminary defining layer DL-A2. In addition, a portion of the second lower dam LDAM2 may be removed to form the third trench TRC3. That is, the third trench TRC3 may be formed by removing a portion of the second lower dam LDAM2 exposed from the first preliminary defining layer DL-A1 and the second preliminary defining layer DL-A2. That is, the first trench TRC1, the second trench TRC2, and the third trench TRC3 may be formed together in the same process.

[0154] Further references Fig.18 and Fig.19, a third preliminary defining layer DL-A3 may be formed on the insulating layer IL, the first lower dam LDAM1, the second lower dam LDAM2, and the second preliminary defining layer DL-A2. The third preliminary defining layer DL-A3 may cover the insulating layer IL, the first lower dam LDAM1, the second lower dam LDAM2, and the second preliminary defining layer DL-A2. The third preliminary defining layer DL-A3 may be formed of an inorganic material. For example, the third preliminary defining layer DL-A3 may be formed of silicon oxide, silicon nitride, and / or silicon carbonitride.

[0155] Further references Fig. 20 and Fig.21 , the third defining layer DL3, the third upper dam UDAM3, and the sixth upper dam UDAM6 may be formed by removing part of the third preliminary defining layer DL-A3. That is, the third defining layer DL3, the third upper dam UDAM3, and the sixth upper dam UDAM6 may be formed together in the same process. The third defining layer DL3 may extend into the first trench TRC1 and may cover the inner surface of the first trench TRC1. The third upper dam UDAM3 may extend into the second trench TRC2 and may cover the inner surface of the second trench TRC2. The sixth upper dam UDAM6 may extend into the third trench TRC3 and may cover the inner surface of the third trench TRC3.

[0156] Further references Fig. 22 and Fig.23 , the second defining layer DL2, the second upper dam UDAM2, and the fifth upper dam UDAM5 may be formed by removing part of the second preliminary defining layer DL-A2. That is, the second defining layer DL2, the second upper dam UDAM2, and the fifth upper dam UDAM5 may be formed together in the same process. In a plan view, the second defining layer DL2 may be spaced apart from the first trench TRC1. In a plan view, the second upper dam UDAM2 may be spaced apart from the second trench TRC2. In a plan view, the fifth upper dam UDAM5 may be spaced apart from the third trench TRC3.

[0157] In one or more embodiments, the second defining layer DL2 may be formed such that a portion of the second defining layer DL2 is exposed from the third defining layer DL3. That is, an end portion of the second defining layer DL2 and an end portion of the third defining layer DL3 may define a stair-shaped step.

[0158] Further references Fig.24 and Fig.25, the first definition layer DL1, the first upper dam UDAM1, and the fourth upper dam UDAM4 may be formed by removing part of the first preliminary definition layer DL-A1. That is, the first definition layer DL1, the first upper dam UDAM1, and the fourth upper dam UDAM4 may be formed together in the same process. In a plan view, the first definition layer DL1 may be spaced apart from the first trench TRC1. In a plan view, the first upper dam UDAM1 may be spaced apart from the second trench TRC2. In a plan view, the fourth upper dam UDAM4 may be spaced apart from the third trench TRC3.

[0159] In one or more embodiments, the first definition layer DL1 may be formed such that a portion of the first definition layer DL1 is exposed from the second definition layer DL2. That is, ends of the first definition layer DL1 and ends of the second definition layer DL2 may define a stair-shaped step.

[0160] As a result, the first defining layer DL1, the second defining layer DL2, and the third defining layer DL3 may be sequentially stacked on the insulating layer IL to form a pixel defining layer PDL. That is, a pixel defining layer PDL covering the side portion of each of the first pixel electrode PE1 and the second pixel electrode PE2 and exposing the center portion of each of the first pixel electrode PE1 and the second pixel electrode PE2 may be formed. The pixel defining layer PDL may extend into the first trench TRC1 and may cover the inner surface of the first trench TRC1. In addition, the first lower dam LDAM1, the first upper dam UDAM1, the second upper dam UDAM2, and the third upper dam UDAM3 may be sequentially stacked in the peripheral area PA to form the first dam DAM1. In addition, the second lower dam LDAM2, the fourth upper dam UDAM4, the fifth upper dam UDAM5, and the sixth upper dam UDAM6 may be sequentially stacked in the peripheral area PA to form the second dam DAM2.

[0161] Further references Fig.26 , a common layer CL may be formed on the insulating layer IL and the pixel defining layer PDL. Fig.26 As shown in , the common layer CL can be disconnected by the first trench TRC1. For example, by adjusting the width of the first trench TRC1 in the process of forming the first trench TRC1, and adjusting the thickness of the third defining layer DL3 in the process of forming the third defining layer DL3, the size of the remaining space in the first trench TRC1 required to disconnect the common layer CL can be achieved. Therefore, the common layer CL can be disconnected by the first trench TRC1. When the common layer CL is disconnected, current leakage caused by the common layer CL can be reduced or prevented.

[0162] Further references Fig. 27 , a common electrode CE may be formed on the common layer CL. Fig.26As shown in , the common electrode CE may not be disconnected by the first groove TRC1. For example, by adjusting the width of the first groove TRC1 in the process of forming the first groove TRC1, and adjusting the thickness of the third defining layer DL3 in the process of forming the third defining layer DL3, the size of the remaining space in the first groove TRC1 required to avoid disconnecting the common electrode CE can be achieved. Therefore, the common electrode CE may not be disconnected by the first groove TRC1. By forming the common electrode CE as a plate electrode, the voltage drop phenomenon of the common electrode CE can be reduced or prevented.

[0163] As a result, according to the manufacturing method of the display device DD according to one or more embodiments, by adjusting the width of the first groove TRC1 and the thickness of the uppermost layer of the pixel defining layer PDL, the size of the remaining space in the first groove TRC1 can be changed in various ways. Therefore, the size of the remaining space in the first groove TRC1 required to disconnect the common layer CL on the insulating layer IL and the pixel defining layer PDL and avoid disconnecting the common electrode CE on the common layer CL can be achieved. In other words, the common layer CL can be formed to be disconnected by the first groove TRC1, and the common electrode CE can be formed not to be disconnected by the first groove TRC1. Therefore, the current leakage through the common layer CL can be reduced or prevented, and at the same time, the voltage drop phenomenon of the common electrode CE can be reduced or prevented.

[0164] Fig.28 According to one or more embodiments Figure 4 A cross-sectional view taken along line II' of Fig.29 According to one or more embodiments Figure 1 A cross-sectional view taken along line II-II'.

[0165] That is to say, Fig.28 Corresponds to Figure 6 , and Fig.29 Corresponds to Figure 7 Cross-sectional view of .

[0166] In addition to the pixel defining layer PDL', the first dam DAM1' and the second dam DAM2', Fig.28 and Fig.29 The display device DD' described can be used with Figure 6 and Figure 7 That is, the display device DD' may include a pixel defining layer PDL', a first dam DAM1', and a second dam DAM2' instead of a pixel defining layer PDL, a first dam DAM1, and a second dam DAM2. In addition, except for the layer structure, the pixel defining layer PDL', the first dam DAM1', and the second dam DAM2' may be the same as the reference 1. Figure 6 and Figure 7The described pixel defining layer PDL, the first dam DAM1, and the second dam DAM2 are substantially the same. Therefore, hereinafter, descriptions overlapping with those of the display device DD will be omitted or simplified.

[0167] Reference Fig.28 , the pixel defining layer PDL' may have a four-layer structure in which a first defining layer DL1', a second defining layer DL2', a third defining layer DL3', and a fourth defining layer DL4' are sequentially stacked.

[0168] The first defining layer DL1' may be arranged on the insulating layer IL, the first pixel electrode PE1 and the second pixel electrode PE2, and spaced apart from the first trench TRC1 in a plan view. That is, the first defining layer DL1' may not be arranged inside the first trench TRC1. In one or more embodiments, the first defining layer DL1' may include an inorganic material. For example, the first defining layer DL1' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0169] The second defining layer DL2' may be arranged on the first defining layer DL1' and may be spaced apart from the first trench TRC1 in a plan view. That is, the second defining layer DL2' may not be arranged inside the first trench TRC1. In one or more embodiments, the second defining layer DL2' may include an inorganic material. For example, the second defining layer DL2' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0170] In one or more embodiments, the second definition layer DL2' may expose a portion of the first definition layer DL1'. That is, an end portion of the first definition layer DL1' and an end portion of the second definition layer DL2' may define a stair-shaped step.

[0171] The third defining layer DL3' may be arranged on the second defining layer DL2' and may be spaced apart from the first trench TRC1 in a plan view. That is, the third defining layer DL3' may not be arranged inside the first trench TRC1. In one or more embodiments, the third defining layer DL3' may include an inorganic material. For example, the third defining layer DL3' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0172] In one or more embodiments, the third definition layer DL3' may expose a portion of the second definition layer DL2'. That is, an end portion of the second definition layer DL2' and an end portion of the third definition layer DL3' may define a stair-shaped step.

[0173] The fourth definition layer DL4' may be disposed on the third definition layer DL3', extend into the first trench TRC1, and cover the inner surface of the first trench TRC1. Fig.28As shown in , the fourth defining layer DL4' may extend into the first trench TRC1 and cover all surfaces defining the first trench TRC1. In other words, when the fourth defining layer DL4' extends into the first trench TRC1 and covers the inner surface of the first trench TRC1, the pixel defining layer PDL' may extend into the first trench TRC1 and cover the inner surface of the first trench TRC1.

[0174] In one or more embodiments, the fourth defining layer DL4' may expose a portion of the third defining layer DL3'. That is, the end of the third defining layer DL3' and the end of the fourth defining layer DL4' may define a stair-shaped step. Therefore, the side surface of the pixel defining layer PDL' may have a stair-shaped step. Therefore, the step coverage of the common layer CL and the common electrode CE formed on the pixel defining layer PDL' may be improved. Therefore, the durability of the display device DD' may be improved.

[0175] The thickness TH' of the fourth definition layer DL4' may be smaller than the width WD of the first trench TRC1. That is, even when the fourth definition layer DL4' covers the inner surface of the first trench TRC1, a remaining space may still remain in the first trench TRC1.

[0176] In one or more embodiments, Fig.28 As shown in , the pixel defining layer PDL' may have a structure in which a first defining layer DL1', a second defining layer DL2', a third defining layer DL3', and a fourth defining layer DL4' are sequentially stacked. For example, the pixel defining layer PDL' may have a four-layer structure in which a first defining layer DL1' including silicon oxide, a second defining layer DL2' including silicon nitride, a third defining layer DL3' including silicon oxide, and a fourth defining layer DL4' including silicon nitride are sequentially stacked. In addition, the pixel defining layer PDL' may have a four-layer structure in which a first defining layer DL1' including silicon oxide, a second defining layer DL2' including silicon carbonitride, a third defining layer DL3' including silicon oxide, and a fourth defining layer DL4' including silicon carbonitride are sequentially stacked. In addition, the pixel defining layer PDL' may have a four-layer structure in which a first defining layer DL1' including silicon nitride, a second defining layer DL2' including silicon oxide, a third defining layer DL3' including silicon oxide, and a fourth defining layer DL4' including silicon nitride are sequentially stacked. However, this is merely an example, and a stack structure of the pixel defining layer PDL′ and a material of each layer constituting the pixel defining layer PDL′ may be variously changed according to one or more embodiments.

[0177] Reference Fig.29In one or more embodiments, the first dam DAM1' may include a first lower dam LDAM1, a first upper dam UDAM1', a second upper dam UDAM2', a third upper dam UDAM3', and a fourth upper dam UDAM4'. Hereinafter, the description of the first lower dam LDAM1 is omitted because it is similar to the description of the first lower dam LDAM1. Figure 7 The description is repeated.

[0178] The first upper dam UDAM1' may be arranged on the first lower dam LDAM1, and may be spaced apart from the second trench TRC2 in a plan view. That is, the first upper dam UDAM1' may not be arranged in the second trench TRC2. The first upper dam UDAM1' may include the same material as that of the first definition layer DL1'. In other words, the first upper dam UDAM1' may be arranged at the same layer (e.g., at the same layer) as the first definition layer DL1'. In other words, the first upper dam UDAM1' may be formed together with the first definition layer DL1' in the same process. For example, the first upper dam UDAM1' may include an inorganic material. For example, the first upper dam UDAM1' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0179] The second upper dam UDAM2' may be arranged on the first upper dam UDAM1' and may be spaced apart from the second trench TRC2 in a plan view. That is, the second upper dam UDAM2' may not be arranged in the second trench TRC2. The second upper dam UDAM2' may include the same material as that of the second definition layer DL2'. In other words, the second upper dam UDAM2' may be arranged at the same layer (e.g., at the same layer) as the second definition layer DL2'. In other words, the second upper dam UDAM2' may be formed together with the second definition layer DL2' in the same process. For example, the second upper dam UDAM2' may include an inorganic material. For example, the second upper dam UDAM2' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0180] The third upper dam UDAM3' may be arranged on the second upper dam UDAM2' and may be spaced apart from the second trench TRC2 in a plan view. That is, the third upper dam UDAM3' may not be arranged in the second trench TRC2. The third upper dam UDAM3' may include the same material as that of the third definition layer DL3'. In other words, the third upper dam UDAM3' may be arranged at the same layer (e.g., at the same layer) as the third definition layer DL3'. In other words, the third upper dam UDAM3' may be formed together with the third definition layer DL3' in the same process. For example, the third upper dam UDAM3' may include an inorganic material. For example, the third upper dam UDAM3' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0181] The fourth upper dam UDAM4' may be disposed on the third upper dam UDAM3', extend into the second trench TRC2, and cover the inner surface of the second trench TRC2. Fig.29 As shown in , the fourth upper dam UDAM4' may extend into the second trench TRC2 and cover all surfaces defining the second trench TRC2. The fourth upper dam UDAM4' may include the same material as the material of the fourth definition layer DL4'. In other words, the fourth upper dam UDAM4' may be arranged at the same layer (e.g., at the same layer) as the fourth definition layer DL4'. In other words, the fourth upper dam UDAM4' may be formed together with the fourth definition layer DL4' in the same process. For example, the fourth upper dam UDAM4' may include an inorganic material. For example, the fourth upper dam UDAM4' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0182] In one or more embodiments, the second dam DAM2' may include a second lower dam LDAM2, a fifth upper dam UDAM5', a sixth upper dam UDAM6', a seventh upper dam UDAM7', and an eighth upper dam UDAM8'. Hereinafter, the description of the second lower dam LDAM2 is omitted because it is similar to the reference numeral 2. Figure 7 The description is repeated.

[0183] The fifth upper dam UDAM5' may be arranged on the second lower dam LDAM2 and may be spaced apart from the third trench TRC3 in a plan view. That is, the fifth upper dam UDAM5' may not be arranged in the third trench TRC3. The fifth upper dam UDAM5' may include the same material as the first definition layer DL1' and the first upper dam UDAM1'. In other words, the fifth upper dam UDAM5' may be arranged at the same layer (e.g., at the same layer) as the first definition layer DL1' and the first upper dam UDAM1'. In other words, the fifth upper dam UDAM5' may be formed together with the first definition layer DL1' and the first upper dam UDAM1' in the same process. For example, the fifth upper dam UDAM5' may include an inorganic material. For example, the fifth upper dam UDAM5' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0184] The sixth upper dam UDAM6' may be arranged on the fifth upper dam UDAM5' and may be spaced apart from the third trench TRC3 in a plan view. That is, the sixth upper dam UDAM6' may not be arranged in the third trench TRC3. The sixth upper dam UDAM6' may include the same material as the second limit layer DL2' and the second upper dam UDAM2'. In other words, the sixth upper dam UDAM6' may be arranged at the same layer (e.g., at the same layer) as the second limit layer DL2' and the second upper dam UDAM2'. In other words, the sixth upper dam UDAM6' may be formed together with the second limit layer DL2' and the second upper dam UDAM2' in the same process. For example, the sixth upper dam UDAM6' may include an inorganic material. Specifically, the sixth upper dam UDAM6' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0185] The seventh upper dam UDAM7' may be arranged on the sixth upper dam UDAM6' and may be spaced apart from the third trench TRC3 in a plan view. That is, the seventh upper dam UDAM7' may not be arranged in the third trench TRC3. The seventh upper dam UDAM7' may include the same material as the third limit layer DL3' and the third upper dam UDAM3'. In other words, the seventh upper dam UDAM7' may be arranged at the same layer (e.g., at the same layer) as the third limit layer DL3' and the third upper dam UDAM3'. In other words, the seventh upper dam UDAM7' may be formed together with the third limit layer DL3' and the third upper dam UDAM3' in the same process. For example, the seventh upper dam UDAM7' may include an inorganic material. For example, the seventh upper dam UDAM7' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0186] The eighth upper dam UDAM8' may be disposed on the seventh upper dam UDAM7', extend into the third trench TRC3, and cover the inner surface of the third trench TRC3. Fig.29 As shown in , the eighth upper dam UDAM8' may extend into the third trench TRC3 and cover all surfaces defining the third trench TRC3. The eighth upper dam UDAM8' may include the same material as the fourth defining layer DL4' and the fourth upper dam UDAM4'. In other words, the eighth upper dam UDAM8' may be arranged at the same layer (e.g., at the same layer) as the fourth defining layer DL4' and the fourth upper dam UDAM4'. In other words, the eighth upper dam UDAM8' may be formed together with the fourth defining layer DL4' and the fourth upper dam UDAM4' in the same process. For example, the eighth upper dam UDAM8' may include an inorganic material. For example, the eighth upper dam UDAM8' may include silicon oxide, silicon nitride and / or silicon carbonitride.

[0187] The present disclosure should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0188] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A base substrate, the base substrate comprising a display area including a first pixel area and a second pixel area and a peripheral area located around the display area; a transistor layer, the transistor layer being located on the base substrate and comprising a first pixel circuit portion corresponding to the first pixel area and a second pixel circuit portion corresponding to the second pixel area; an insulating layer disposed on the transistor layer and having a contact hole exposing the first pixel circuit portion and the second pixel circuit portion and a first trench positioned between the first pixel region and the second pixel region; a first pixel electrode positioned at the first pixel region on the insulating layer and electrically connected to the first pixel circuit portion; a second pixel electrode positioned at the second pixel region on the insulating layer and electrically connected to the second pixel circuit portion; as well as A pixel defining layer is located on the insulating layer, the first pixel electrode and the second pixel electrode, exposes a portion of each of the first pixel electrode and the second pixel electrode, extends into the first groove, and covers an inner surface of the first groove.

2. The display device according to claim 1, wherein: The pixel defining layer comprises: a first defining layer, the first defining layer being on the insulating layer and spaced apart from the first trench in a plan view; a second defining layer on the first defining layer and spaced apart from the first trench in a plan view; and A third defining layer is located on the second defining layer, extends into the first trench, and covers the inner surface of the first trench.

3. The display device according to claim 2, wherein: The insulating layer includes an organic material, and Wherein, each of the first defining layer, the second defining layer and the third defining layer includes at least one of silicon oxide, silicon nitride and silicon carbonitride.

4. The display device according to claim 2, wherein: In the cross-sectional view, the width of the first groove is smaller than the separation distance between the first pixel electrode and the second pixel electrode, and Wherein, the thickness of the third limiting layer is smaller than the width of the first groove.

5. The display device according to claim 2, wherein: A side surface of the pixel defining layer has a stepped step.

6. The display device according to claim 1, further comprising: a common layer, the common layer being located on the insulating layer and the pixel defining layer and being disconnected by the first groove; as well as A common electrode is located on the common layer and is not disconnected by the first trench.

7. The display device according to claim 6, wherein: The common layer includes: a first hole transport layer; a first light-emitting layer, wherein the first light-emitting layer is located on the first hole transport layer; A first electron transport layer, wherein the first electron transport layer is located on the first light-emitting layer; a first charge generation layer, the first charge generation layer being located on the first electron transport layer; a second hole transport layer, the second hole transport layer being located on the first charge generation layer; a second light-emitting layer, the second light-emitting layer being located on the second hole transport layer; a second electron transport layer, wherein the second electron transport layer is located on the second light-emitting layer; a second charge generation layer, the second charge generation layer being located on the second electron transport layer; a third hole transport layer, the third hole transport layer being located on the second charge generation layer; a third light-emitting layer, the third light-emitting layer being located on the third hole transport layer; and A third electron transport layer is located on the third light emitting layer.

8. The display device according to claim 1, further comprising: a first dam located in the peripheral area and surrounding the display area; as well as a second dam located in the peripheral region and surrounding the first dam, and Wherein, the first dam comprises: a first lower dam including a material that is the same as that of the insulating layer and having a second groove surrounding the display area; a first upper dam located on the first lower dam and spaced apart from the second groove in a plan view; a second upper dam located on the first upper dam and spaced apart from the second groove in a plan view; and The third upper dam is located on the second upper dam, extends into the second trench, and covers an inner surface of the second trench.

9. The display device according to claim 8, wherein: The first lower dam comprises an organic material, and Wherein, each of the first upper dam, the second upper dam and the third upper dam includes at least one of silicon oxide, silicon nitride and silicon carbonitride.

10. The display device according to claim 8, wherein: The second dam comprises: a second lower dam including a material that is the same as the material of the insulating layer and having a third groove surrounding the display area; a fourth upper dam, the fourth upper dam being located on the second lower dam and spaced apart from the third groove in a plan view; a fifth upper dam located on the fourth upper dam and spaced apart from the third trench in a plan view; and A sixth upper dam is located on the fifth upper dam, extends into the third trench, and covers an inner surface of the third trench.

11. The display device according to claim 10, wherein: The second lower dam comprises an organic material, and Wherein, each of the fourth upper dam, the fifth upper dam and the sixth upper dam includes at least one of silicon oxide, silicon nitride and silicon carbonitride.

12. The display device according to claim 10, wherein: Each of the second groove and the third groove has a closed loop shape.

13. The display device according to claim 1, wherein: The base substrate includes a silicon wafer.

14. The display device according to claim 1, further comprising: a connection pattern, the connection pattern being located in the contact hole of the insulating layer, and The connection pattern electrically connects the first pixel electrode and the first pixel circuit portion, and electrically connects the second pixel electrode and the second pixel circuit portion.

15. A method for manufacturing a display device, the method comprising: On a base substrate including a display area including a first pixel area and a second pixel area and a peripheral area around the display area, a transistor layer including a first pixel circuit portion corresponding to the first pixel area and a second pixel circuit portion corresponding to the second pixel area is formed; forming an insulating layer on the transistor layer; forming a first pixel electrode located in the first pixel area and a second pixel electrode located in the second pixel area on the insulating layer; forming a first preliminary defining layer on the insulating layer, covering the first pixel electrode and the second pixel electrode and exposing a portion of the insulating layer; forming a second preliminary defining layer on the first preliminary defining layer exposing a portion of the insulating layer; forming a first trench positioned between the first pixel region and the second pixel region by removing a portion of the insulating layer exposed from the first preliminary defining layer and the second preliminary defining layer; forming a third preliminary definition layer on the insulating layer and the second preliminary definition layer to extend into the first trench and cover an inner surface of the first trench; as well as A pixel defining layer is formed by removing portions of the first preliminary defining layer, the second preliminary defining layer, and the third preliminary defining layer, the pixel defining layer exposing portions of each of the first pixel electrode and the second pixel electrode, extending into the first groove and covering the inner surface of the first groove.

16. The method according to claim 15, wherein: Each of the first preliminary defining layer, the second preliminary defining layer, and the third preliminary defining layer includes at least one of silicon oxide, silicon nitride, and silicon carbonitride.

17. The method according to claim 15, wherein: In the cross-sectional view, the width of the first groove is smaller than the separation distance between the first pixel electrode and the second pixel electrode, and Wherein, the thickness of the third preliminary limiting layer is smaller than the width of the first groove.

18. The method according to claim 15, wherein: The pixel defining layer comprises: forming a first definition layer on the insulating layer by removing the portion of the first preliminary definition layer; forming a second defining layer on the first defining layer by removing the portion of the second preliminary defining layer; and forming a third defining layer on the second defining layer by removing the portion of the third preliminary defining layer, wherein the first defining layer and the second defining layer are spaced apart from the first groove, and The third defining layer extends into the first trench and covers the inner surface of the first trench.

19. The method according to claim 15, further comprising: forming a common layer disconnected by the first trench on the insulating layer and the pixel defining layer; as well as forming a common electrode on the common layer which is not disconnected by the first trench, Wherein, forming the common layer and forming the common electrode are performed after forming the pixel defining layer.

20. The method according to claim 15, wherein: In forming the insulating layer, a first lower dam located in the peripheral region and surrounding the display region and a second lower dam located in the peripheral region and surrounding the first lower dam are formed, and In forming the first trench, a second trench surrounding the display area is formed in the first lower dam and a third trench surrounding the second trench is formed in the second lower dam.

21. The method according to claim 20, wherein: The second groove and the third groove are formed to have a closed loop shape.

22. The method according to claim 20, wherein: In forming the pixel defining layer, forming a first upper dam spaced apart from the second trench on the first lower dam by removing a portion of the first preliminary defining layer, forming a second upper dam spaced apart from the second trench on the first upper dam by removing a portion of the second preliminary defining layer, and A third upper dam extending into the second trench and covering an inner surface of the second trench is formed on the second upper dam by removing a portion of the third preliminary defining layer.

23. The method according to claim 22, wherein: The first lower dam comprises an organic material, and Each of the first upper dam, the second upper dam, and the third upper dam includes at least one of silicon oxide, silicon nitride, and silicon carbonitride.

24. The method according to claim 20, wherein: In forming the pixel defining layer, forming a fourth upper dam spaced apart from the third trench on the second lower dam by removing a portion of the first preliminary defining layer, forming a fifth upper dam spaced apart from the third trench on the fourth upper dam by removing a portion of the second preliminary defining layer, and A sixth upper dam extending into the third trench and covering an inner surface of the third trench is formed on the fifth upper dam by removing a portion of the third preliminary defining layer.

25. The method according to claim 24, wherein: The second lower dam comprises an organic material, and Each of the fourth upper dam, the fifth upper dam, and the sixth upper dam includes at least one of silicon oxide, silicon nitride, and silicon carbonitride.

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