Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device may include: a substrate including a display area and a non-display area, the display area including a first area and a second area; a plurality of data lines positioned in the first area and the second area; a plurality of readout lines positioned in the first area and the second area, the plurality of readout lines being spaced apart from the plurality of data lines, respectively; a plurality of connection lines extending from the first region to the second region, the plurality of connection lines being electrically connected to corresponding readout lines disposed in the second region among the plurality of readout lines; and a plurality of bridging lines extending from the second area to the first area, the plurality of bridging lines being electrically connected to corresponding data lines disposed in the first area among the plurality of data lines. The plurality of connecting lines and the plurality of bridging lines are not overlapped with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0100691 filed on August 1, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device and an electronic device having the display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0005] The embodiment provides a display device having improved reliability and an electronic device having the display device.

[0006] According to an embodiment of the present disclosure, a display device may include: a substrate including a display area and a non-display area, the display area including a first area and a second area; a plurality of data lines positioned in the first area and the second area; a plurality of readout lines positioned in the first area and the second area, the plurality of readout lines being spaced apart from the plurality of data lines, respectively; a plurality of connection lines extending from the first area to the second area, the plurality of connection lines being electrically connected to corresponding readout lines disposed in the second area among the plurality of readout lines; and a plurality of bridge lines extending from the second area to the first area, the plurality of bridge lines being electrically connected to corresponding data lines disposed in the first area among the plurality of data lines. The plurality of connection lines and the plurality of bridge lines do not overlap each other.

[0007] The display device may further include: a plurality of first lines positioned in a fan-out region disposed in the non-display region, the plurality of first lines being electrically connected to the plurality of connection lines, respectively; a plurality of second lines positioned in the fan-out region, the plurality of second lines being electrically connected to the plurality of bridge lines, respectively; and a pad portion positioned in a pad region disposed in the non-display region. The pad portion may include: a first pad portion including a plurality of first pads electrically connected to the plurality of first lines, respectively; and a second pad portion including a plurality of second pads electrically connected to the plurality of second lines, respectively. The plurality of first lines may be disposed at both sides of the plurality of second lines, and the first pad portion is disposed at both sides of the second pad portion.

[0008] The display device may further include: a plurality of first lines positioned in a fan-out region of the non-display region, the plurality of first lines being electrically connected to the plurality of connection lines, respectively; a plurality of second lines positioned in the fan-out region, the plurality of second lines being electrically connected to the plurality of bridge lines, respectively; and a pad portion positioned in the pad region of the non-display region. The pad portion may include a first pad portion electrically connected to the plurality of first lines and a second pad portion electrically connected to the plurality of second lines. The plurality of second lines may be disposed at both sides of the plurality of first lines, and the second pad portion may be disposed at both sides of the first pad portion.

[0009] The plurality of connection lines may include: a plurality of horizontal connection lines extending from the first region to the second region along a first direction; and a plurality of vertical connection lines positioned in the first region and extending in a second direction intersecting the first direction. The plurality of bridge lines may include: a plurality of horizontal bridge lines extending from the second region to the first region along the first direction; and a plurality of vertical bridge lines positioned in the second region and extending in the second direction.

[0010] The plurality of vertical connection lines, the plurality of vertical bridge lines, the plurality of data lines, and the plurality of readout lines may be disposed in the same layer.

[0011] The plurality of data lines disposed in the first region among the plurality of data lines may be electrically connected to the plurality of vertical bridge lines through the plurality of horizontal bridge lines, respectively. The plurality of readout lines disposed in the second region among the plurality of readout lines may be electrically connected to the plurality of vertical connection lines, respectively, through the plurality of horizontal connection lines.

[0012] The insulating layer may be disposed between one ends of the plurality of horizontal bridge lines and the plurality of vertical bridge lines, and between the other ends of the plurality of horizontal bridge lines and the plurality of data lines disposed in the first region. The insulating layer may be disposed between one ends of the plurality of horizontal connection lines and the plurality of vertical connection lines, and between the other ends of the plurality of horizontal connection lines and the plurality of readout lines disposed in the second region.

[0013] The one ends of the plurality of horizontal bridge lines may be electrically connected to the plurality of vertical bridge lines through a plurality of first contact holes formed through the insulating layer, and the other ends of the plurality of horizontal bridge lines may be electrically connected to the plurality of data lines disposed in the first region among the plurality of data lines through a plurality of second contact holes formed through the insulating layer. The one ends of the plurality of horizontal connection lines may be electrically connected to the plurality of vertical connection lines through a plurality of third contact holes formed through the insulating layer, and the other ends of the plurality of horizontal connection lines may be electrically connected to the plurality of readout lines disposed in the second region among the plurality of readout lines through a plurality of fourth contact holes formed through the insulating layer.

[0014] A plurality of readout lines disposed in the first region among the plurality of readout lines may be directly connected to corresponding first pads among the plurality of first pads. A plurality of data lines disposed in the second region among the plurality of data lines may be directly connected to corresponding second pads among the plurality of second pads.

[0015] In the first region, the plurality of vertical connection lines, the plurality of readout lines, and the plurality of data lines may be arranged to be spaced apart from each other. In the second region, the plurality of vertical bridge lines, the plurality of readout lines, and the plurality of data lines may be arranged to be spaced apart from each other. The plurality of horizontal connection lines and the plurality of horizontal bridge lines may be arranged to be spaced apart from each other.

[0016] The plurality of horizontal connection lines and the plurality of vertical connection lines may be disposed in different layers. The plurality of horizontal bridge lines and the plurality of vertical bridge lines may be disposed in different layers.

[0017] The plurality of horizontal connection lines and the plurality of horizontal bridge lines may be disposed in the same layer. The plurality of vertical connection lines and the plurality of vertical bridge lines may be disposed in the same layer.

[0018] The plurality of horizontal connection lines and the plurality of horizontal bridge lines may be disposed in different layers.

[0019] The display device may further include a plurality of dummy lines respectively disposed between the plurality of connection lines and the plurality of bridge lines in the display region. A DC signal having a constant level is applied to the plurality of dummy lines.

[0020] The plurality of dummy lines may include: a plurality of horizontal dummy lines extending from the first region to the second region along the first direction; a plurality of first vertical dummy lines positioned in the first region, the plurality of first vertical dummy lines extending in the second direction; and a plurality of second vertical dummy lines positioned in the second region, the plurality of second vertical dummy lines extending in the second direction.

[0021] The plurality of horizontal dummy lines may be respectively disposed between the plurality of horizontal bridge lines and the plurality of horizontal connection lines. The plurality of vertical dummy lines may be respectively disposed between the plurality of vertical bridge lines and the plurality of vertical connection lines, and the plurality of vertical dummy lines include the plurality of first vertical dummy lines and the plurality of second vertical dummy lines.

[0022] The plurality of horizontal dummy lines, the plurality of horizontal bridge lines, and the plurality of horizontal connection lines may be disposed in the same layer. The plurality of vertical dummy lines, the plurality of vertical bridge lines, and the plurality of vertical connection lines may be disposed in the same layer.

[0023] The plurality of vertical dummy lines, the plurality of vertical bridge lines, and the plurality of vertical connection lines may be disposed in the same layer. The plurality of horizontal dummy lines may be disposed in a different layer from the plurality of horizontal bridge lines and the plurality of horizontal connection lines.

[0024] The display device may further include a plurality of sub-pixels and a plurality of light-sensing pixels, wherein the plurality of sub-pixels are positioned in the display area and each include a light-emitting element that emits light, and the plurality of light-sensing pixels are positioned in the display area and each include a light-receiving element that outputs a sensing signal corresponding to the light.

[0025] According to an embodiment of the present disclosure, an electronic device may include: a processor configured to provide input image data to a display device; and the display device configured to display an image based on the input image data. The display device includes: a substrate including a display area and a non-display area, the display area including a first area and a second area; a plurality of data lines positioned in the first area and the second area; a plurality of readout lines positioned in the first area and the second area, the plurality of readout lines being spaced apart from the plurality of data lines; a plurality of connection lines extending from the first area to the second area, the plurality of connection lines being electrically connected to corresponding readout lines arranged in the second area among the plurality of readout lines; a plurality of bridge lines extending from the second area to the first area, the plurality of bridge lines being electrically connected to corresponding data lines arranged in the first area among the plurality of data lines; and a plurality of dummy lines, respectively arranged between the plurality of connection lines and the plurality of bridge lines in the display area. A DC signal having a constant level is applied to the plurality of dummy lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that where an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always indicate the same elements.

[0028] Figure 1 and Figure 2 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 3 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0030] Figure 4 It is shown that the Figure 1 A circuit diagram of an example of sub-pixels and light-sensing pixels in a display area shown in FIG.

[0031] Figure 5 is a schematic cross-sectional view illustrating one region of a display device according to an embodiment of the present disclosure.

[0032] Figure 6 It is shown Figure 5 Schematic cross-sectional view of the reflection path of light in the display device shown in .

[0033] Figure 7 It is schematically shown Figure 1 0 is a plan view of a data line, a readout line, a bridge line, a connection line, a first line, and a second line of a display device shown in FIG.

[0034] Figure 8 It is shown Figure 7 Schematic enlargement of the portion EA shown in .

[0035] Fig. 9 , Fig.10 and Fig.11 It is along Figure 8 A schematic cross-sectional view taken along line II' shown in FIG.

[0036] Fig.12 and Fig.13 It is along Figure 8Schematic cross-sectional view taken along line II-II' shown in FIG.

[0037] Fig.14 It is shown Figure 8 A schematic plan view of a modification of .

[0038] Fig.15 It is along Fig.14 Schematic cross-sectional view taken along line III-III' shown in FIG.

[0039] Fig.16 It is along Fig.14 Schematic cross-sectional view taken along line IV-IV' shown in FIG.

[0040] Fig.17 It is shown Fig.14 A schematic plan view of a modification of .

[0041] Fig.18 It is along Fig.17 A schematic cross-sectional view taken along line VV' shown in FIG.

[0042] Fig.19 It is shown Figure 7 A schematic plan view of a modification of .

[0043] Fig. 20 is a schematic block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0044] Fig.21 It shows that Fig. 20 ] is a schematic diagram of an example in which the electronic device shown in FIG. 1 is implemented as a smart phone.

[0045] Fig. 22 It shows that Fig. 20 ] is a schematic diagram of an example in which the electronic device shown in FIG. 1 is implemented as a tablet PC. DETAILED DESCRIPTION

[0046] The present disclosure can apply various changes and different shapes, so only specific examples are shown in detail. However, the examples are not limited to certain shapes, but are applicable to all changes and equivalent materials and replacements. The included drawings are shown in a way that the drawings are enlarged for better understanding.

[0047] The same reference numerals always refer to the same elements. In the accompanying drawings, for clarity, the thickness (thickness) of some lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used in this article, unless the context clearly states otherwise, the singular form is also intended to include the plural form.

[0048] It will also be understood that where the terms "comprises" and / or "includes" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or components is indicated, but the existence and / or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof are not excluded. In addition, the statement that an element such as a layer, region, substrate or plate is placed "on" or "above" another element not only indicates the situation where the element is "directly" placed "on" or "directly above" the other element, but also indicates the situation where another element is between the element and the other element. Conversely, the statement that an element such as a layer, region, substrate or plate is placed "under" or "below" another element not only indicates the situation where the element is "directly" placed "under" or "directly below" the other element, but also indicates the situation where another element is between the element and the other element.

[0049] Hereinafter, various embodiments of the present disclosure and items required for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly states otherwise, the singular form in the present disclosure is also intended to include the plural form.

[0050] Figure 1 and Figure 2 is a schematic plan view showing a display device DD according to an embodiment of the present disclosure.

[0051] exist Figure 1 and Figure 2 , for convenience, the structure of the display device DD (eg, the display panel DP provided in the display device DD) is simply shown based on the display area DA in which an image is displayed.

[0052] refer to Figure 1 and Figure 2 , the display device DD (or display panel DP) may include a substrate SUB, sub-pixels PXL, and light sensing pixels PSR.

[0053] The display device DD may be provided in various shapes. For example, the display device DD may be provided in a rectangular plate shape having two pairs of sides parallel to each other, but the present disclosure is not limited thereto. As long as the display device DD is an electronic device (such as a smart phone, a television, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), a moving picture expert group audio level III (MP3) player, a medical device, a camera, or a wearable device) to which a display surface is applied to at least one surface thereof, this embodiment may be applied.

[0054] The substrate SUB may include a transparent insulating material to allow light to be transmitted therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0055] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0056] The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0057] One region of the substrate SUB may be provided as a display area DA such that the sub-pixels PXL and the light sensing pixels PSR are disposed therein, and another region of the substrate SUB may be provided as a non-display area NDA.

[0058] In an embodiment, the display area DA may include a first area DA1 and a second area DA2. For example, the display area DA may be divided into the first area DA1 and the second area DA2 according to the corresponding relationship between the components of the line portion LP. For example, the first area DA1 may be an area of ​​the display area DA connected to the first line LP1 of the line portion LP, and the second area DA2 may be an area of ​​the display area DA connected to the second line LP2 of the line portion LP.

[0059] The first area DA1 may be disposed adjacent to at least one area of ​​the non-display area NDA in which the first line LP1 is located. For example, the first area DA1 may be disposed on either side of the display panel DP and the second area DA2 to which the second line LP2 is connected is disposed between the first areas DA1.

[0060] The sub-pixel PXL and the light-sensing pixel PSR may be disposed in each of the first area DA1 and the second area DA2 .

[0061] Each of the sub-pixels PXL may include a light-emitting element including a light-emitting layer. In some embodiments, the light-emitting element may include an organic light-emitting diode or an inorganic light-emitting diode having a size ranging from nanometers to micrometers (or nanometers to micrometers), but the present disclosure is not limited thereto. The display device DD may drive the sub-pixels PXL corresponding to the input image data, thereby displaying an image in the first area DA1 and the second area DA2.

[0062] The display area DA may include a sensing area capable of sensing a user's fingerprint, etc. For example, the first area DA1 and the second area DA2 may be sensing areas capable of sensing a user's fingerprint, etc. In the case where the display area DA is completely set as a sensing area, a non-display area NDA surrounding the display area DA may become a non-sensing area.

[0063] The light sensing pixels PSR (or light sensors) may be disposed in the first and second areas DA1 and DA2. Each of the light sensing pixels PSR may include a light receiving element including a light receiving layer. The light receiving layer of the light receiving element may be disposed in the first and second areas DA1 and DA2 to be spaced apart from the light emitting layer of the light emitting element.

[0064] The light sensing pixel PSR can sense light emitted from a light source (e.g., a light emitting element) and reflected by an external object (e.g., a user's finger, etc.). For example, the user's fingerprint can be sensed by the light sensing pixel PSR. Hereinafter, a case where the light sensing pixel PSR is used for fingerprint sensing is described as an example. However, in various embodiments, the light sensing pixel PSR can sense various biometric information such as irises and veins. In addition, the light sensing pixel PSR can sense external light and perform the functions of a gesture sensor, a motion sensor, a proximity sensor, an illumination sensor, or an image sensor, etc.

[0065] A line portion LP, a pad portion PDP, and / or a built-in circuit portion for driving the subpixels PXL and the light sensing pixels PSR may be disposed in the non-display area NDA. The non-display area NDA may include a fan-out area FTA and a pad area PDA.

[0066] The pad area PDA is a region of the non-display area NDA in which the pad part PDP is located, and may be located adjacent to an edge of the non-display area NDA.

[0067] The fan-out area FTA is an area of ​​the non-display area NDA in which the line portion LP is located, and may be adjacent to the display area DA in the non-display area NDA. For example, the fan-out area FTA may be an area of ​​the non-display area NDA located between the pad area PDA and the display area DA. In some embodiments, the non-display area NDA may include an electrostatic discharge protection circuit area in which an electrostatic discharge protection circuit electrically connected to a signal line located in the display area DA to prevent electrostatic discharge from occurring is located.

[0068] The line portion LP may be positioned in the fan-out area FTA, and the pad portion PDP may be positioned in the pad area PDA.

[0069] The line portion LP may be electrically connected to the subpixels PXL and the light sensing pixels PSR to transmit a predetermined signal supplied from the driver DIC to the signal line. The line portion LP may include a fan-out line electrically connecting the driver DIC and the subpixels PXL to each other and electrically connecting the driver DIC and the light sensing pixels PSR to each other.

[0070] In an embodiment, the line portion LP may include a first line LP1 and a second line LP2 .

[0071] The first line LP1 may be provided in an area of ​​the fan-out area FTA positioned between the first area DA1 and the pad portion PDP. The first line LP1 may be provided in plural and include a fan-out line electrically connected to the light sensing pixel PSR positioned in the first area DA1. For example, the first line LP1 may include a fan-out line electrically connected to a readout line connected to the light sensing pixel PSR positioned in the first area DA1 to transmit an electrical signal (e.g., a sensing signal) received from the light sensing pixel PSR to the driver DIC.

[0072] In an embodiment, the first line LP1 may include a fan-out line electrically connected to a readout line connected to the light-sensing pixels PSR positioned in the second area DA2 through a connection line extending from the first area DA1 to the second area DA2 .

[0073] The second line LP2 may be disposed in an area of ​​the fan-out area FTA positioned between the second area DA2 and the pad portion PDP. The second line LP2 may be provided in a plurality and include a fan-out line electrically connected to the sub-pixel PXL positioned in the second area DA2. For example, the second line LP2 may include a fan-out line electrically connected to a data line connected to the sub-pixel PXL positioned in the second area DA2 to transmit a data signal to the sub-pixel PXL.

[0074] In an embodiment, the second line LP2 may include a fan-out line electrically connected to a data line connected to the sub-pixel PXL positioned in the first area DA1 through a bridge line extending from the second area DA2 to the first area DA1 .

[0075] The pad portion PDP may be disposed in the pad area PDA and supply a voltage and a signal of a driving power source to the sub-pixels PXL and the light sensing pixels PSR disposed in the display area DA. The pad portion PDP may be electrically connected to the line portion LP. In an embodiment, the pad portion PDP may include a first pad portion PDP1 and a second pad portion PDP2.

[0076] The first pad portion PDP1 may include first pads P1 electrically connected to the first lines LP1, and the second pad portion PDP2 may include second pads P2 electrically connected to the second lines LP2.

[0077] The first pad P1 may be provided in plural. The first pad P1 may include a first pad P1 electrically connected to a readout line connected to the light sensing pixel PSR positioned in the first area DA1 through a corresponding first line LP1. In addition, the first pad P1 may include a first pad P1 electrically connected to a connection line through a corresponding first line LP1.

[0078] The second pad P2 may be provided in plural. The second pad P2 may include a second pad P2 electrically connected to a data line connected to the sub-pixel PXL positioned in the second area DA2 through a corresponding second line LP2. In addition, the second pad P2 may include a second pad P2 electrically connected to a bridge line through a corresponding second line LP2.

[0079] The display device DD may include a circuit board FPCB connected to the display panel DP through a pad portion PDP. The circuit board FPCB may be a flexible circuit board, but the present disclosure is not limited thereto.

[0080] The circuit board FPCB may process various signals input from the printed circuit board and output the processed signals to the display panel DP. For example, one end of the circuit board FPCB may be attached to the display panel DP, and the other end of the circuit board FPCB facing the one end may be attached to the printed circuit board. The circuit board FPCB may be connected to each of the display panel DP and the printed circuit board by a conductive adhesive member (e.g., an anisotropic conductive film).

[0081] The driver DIC may be mounted on the circuit board FPCB. The driver DIC may be, for example, an integrated circuit (IC). The driver DIC may include a panel driver and a fingerprint detector.

[0082] The panel driver may supply a data signal corresponding to the image data signal to the sub-pixel PXL while sequentially scanning the sub-pixel PXL. The display panel DP may display an image corresponding to the image data signal. The panel driver may supply a drive signal for fingerprint sensing to the sub-pixel PXL. A drive signal may be provided to allow the sub-pixel PXL to emit light, thereby operating as a light source for the light sensing pixel PSR. In an embodiment, the panel driver may supply a drive signal for fingerprint sensing and / or other drive signals to the light sensing pixel PSR. However, the present disclosure is not limited thereto, and the drive signal for fingerprint sensing may be provided by a fingerprint detector.

[0083] The fingerprint detector may detect biometric information such as a user's fingerprint based on a sensing signal received from the light sensing pixel PSR. The fingerprint detector may supply a driving signal to the light sensing pixel PSR and / or the sub-pixel PXL.

[0084] In the display area DA, the first area DA1 may be positioned at both sides of the second area DA2. For example, the second area DA2 may be positioned at the center of the substrate SUB (or the display device DD), and the first area DA1 may be positioned at the edge of the substrate SUB. In other words, the second area DA2 may be positioned at the inner side of the substrate SUB, and the first area DA1 may be positioned at the outer side of the substrate SUB.

[0085] In the fan-out area FTA, the first line LP1 may be positioned at both sides of the second line LP2. For example, the second line LP2 may be positioned at the center of the fan-out area FTA to correspond to the second area DA2, and the first line LP1 may be positioned at the edge of the fan-out area FTA to correspond to the first area DA1. In other words, the second line LP2 may be positioned at the inner side of the fan-out area FTA, and the first line LP1 may be positioned at the outer side of the fan-out area FTA. Therefore, the first line LP1 and the second line LP2 may be separated from each other in the fan-out area FTA.

[0086] In the pad area PDA, the first pad portion PDP1 may be positioned at both sides of the second pad portion PDP2. The second pad portion PDP2 may be positioned at the center of the pad area PDA to correspond to the second line LP2, and the first pad portion PDP1 may be positioned at the edge of the pad area PDA to correspond to the first line LP1. In other words, the second pad portion PDP2 may be positioned at the inner side of the pad area PDA, and the first pad portion PDP1 may be positioned at the outer side of the pad area PDA.

[0087] Figure 3 is a schematic cross-sectional view showing a display device DD according to an embodiment of the present disclosure.

[0088] refer to Figures 1 to 3, the display device DD may include a display module DM and a window WD.

[0089] The display module DM may include a display panel DP and a touch sensor TS.

[0090] The touch sensor TS may be directly disposed on the display panel DP, or disposed on the display panel DP with a single layer such as an adhesive layer or a substrate (or an insulating layer) interposed therebetween.

[0091] The display panel DP may display an image. A self-luminous display panel such as an organic light-emitting display panel (OLED panel) may be used as the display panel DP. A non-self-luminous display panel such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electrowetting display panel (EWD panel) may be used as the display panel DP. In the case where a non-self-luminous display panel is used as the display panel DP, the display device DD may include a backlight unit for supplying light to the display panel DP.

[0092] The touch sensor TS may be disposed on a surface of the display panel DP from which an image is displayed to receive a user's touch input. The touch sensor TS may recognize a touch event of the display device DD by a user's hand or a separate input means. The touch sensor TS may recognize a touch event using a capacitive method.

[0093] The touch sensor TS may sense a touch input using a mutual capacitance method or sense a touch input using a self capacitance method.

[0094] A window WD for protecting an exposed surface of the display module DM may be provided on the display module DM. The window WD may protect the display module DM from external impacts and provide an input surface and / or a display surface to a user. The window WD may be coupled to the display module DM using an optically transparent adhesive member OCA.

[0095] The window WD (or cover glass) may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The multilayer structure may be formed by a continuous process or a bonding process using an adhesive layer. All or a portion of the window WD may have flexibility.

[0096] Figure 4 It is shown that the Figure 1 1 is a circuit diagram of an example of a sub-pixel PXL and a light sensing pixel PSR in a display area DA shown in FIG. Figure 4 , a sub-pixel PXL positioned on an i-th horizontal line (or an i-th pixel row) and connected to a j-th data line Dj is shown in FIG. 5 , where i and j are natural numbers greater than 0.

[0097] refer to Figures 1 to 4, the sub-pixels PXL and the light sensing pixels PSR may be disposed on an i-th horizontal line.

[0098] The subpixel PXL may include a light emitting element LED and a pixel circuit PXC. In an embodiment, the pixel circuit PXC may include first, second, third, fourth, fifth, sixth, and seventh transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a boost capacitor Cbst.

[0099] The first transistor T1 (or driving transistor) may be electrically connected between the first power line PL1 and the first electrode of the light emitting element LED. The first transistor T1 may include a gate electrode electrically connected to the first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power line PL1 to the electrode EP (or power line) via the light emitting element LED based on the voltage of the first node N1. The first power voltage VDD may be provided to the first power line PL1, and the second power voltage VSS may be provided to the electrode EP. The first power voltage VDD may be set to a voltage higher than the second power voltage VSS.

[0100] The second transistor T2 may be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 may be connected to the 1i-th scan line S1i (or the first scan line). The second transistor T2 may be turned on in response to a first scan signal GW[i] (e.g., a first scan signal having a low level) supplied from the 1i-th scan line S1i to electrically connect the j-th data line Dj and the second node N2 to each other. When the second transistor T2 is in the on state, the second transistor T2 may transmit the data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0101] The third transistor T3 may be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be electrically connected to the 4i-th scan line S4i (or the third scan line). When the fourth scan signal GC[i] is supplied to the 4i-th scan line S4i, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the first transistor T1 may have a diode connection form.

[0102] The fourth transistor T4 may be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 may be electrically connected to the 2i-th scan line S2i (or the second scan line). The first initialization power voltage Vint1 may be provided from the second power line PL2. The fourth transistor T4 may be turned on by the second scan signal GI[i] supplied to the 2i-th scan line S2i. When the fourth transistor T4 is turned on, the first initialization power voltage Vint1 may be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0103] The fifth transistor T5 may be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 may be electrically connected to the i-th emission control line Ei. The sixth transistor T6 may be electrically connected between the third node N3 and the light emitting element LED (or the fourth node N4). The fifth transistor T5 and the sixth transistor T6 may be turned off when the emission control signal EM[i] (e.g., the emission control signal EM[i] having a high level) is supplied to the i-th emission control line Ei, and turned on in other cases.

[0104] The seventh transistor T7 may be electrically connected between the first electrode (i.e., the fourth node N4) of the light emitting element LED and the third power line PL3. The gate electrode of the seventh transistor T7 may be electrically connected to the 3i-th scan line S3i. The second initialization power voltage Vint2 may be provided from the third power line PL3. In some embodiments, the second initialization power voltage Vint2 may be different from the first initialization power voltage Vint1. The seventh transistor T7 may be turned on by the third scan signal GB[i] supplied to the 3i-th scan line S3i to supply the second initialization power voltage Vint2 to the first electrode of the light emitting element LED.

[0105] The storage capacitor Cst may be connected or formed between the first power line PL1 and the first node N1.

[0106] The boosting capacitor Cbst (or capacitor) may be connected or formed between the gate electrode of the second transistor T2 and the gate electrode of the first transistor T1 .

[0107] The light sensing pixel PSR may include a sensor circuit SC and a light receiving element LRD. The sensor circuit SC may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0108] The eighth transistor T8 and the tenth transistor T10 may be connected in series between the fifth power line PL5 and a kth readout line RXk (k is a natural number greater than 0).

[0109] The eighth transistor T8 (or the first sensor transistor) may be electrically connected between the fifth power line PL5 and the tenth transistor T10. The gate electrode of the eighth transistor T8 may be electrically connected to the fifth node N5 (or the sensor node). The eighth transistor T8 may control the current flowing from the fifth power line PL5 through the tenth transistor T10 to the kth readout line RXk in response to the voltage of the fifth node N5. The common voltage VCOM may be provided to the fifth power line PL5.

[0110] In some embodiments, the fifth power line PL5 may be electrically connected to the third power line PL3 or integrally formed with the third power line PL3, and the common voltage VCOM applied to the fifth power line PL5 may be equal to the second initialization power voltage Vint2. However, the present disclosure is not limited thereto. In other embodiments, the common voltage VCOM applied to the fifth power line PL5 may be equal to the first initialization power voltage Vint1.

[0111] The tenth transistor T10 ("second sensor transistor" or "switch transistor") may be electrically connected between the eighth transistor T8 and the kth readout line RXk. The gate electrode of the tenth transistor T10 may be electrically connected to the 2ith scan line S2i. The gate electrode of the tenth transistor T10 and the gate electrode of the fourth transistor T4 may share the 2ith scan line S2i.

[0112] The ninth transistor T9 (or the third sensor transistor) may be electrically connected between the fourth power line PL4 (or the reference power line) and the fifth node N5. The gate electrode of the ninth transistor T9 may be electrically connected to the reset control line RSTL. A reset voltage VRST may be provided to the fourth power line PL4. The reset voltage VRST may be a direct current (DC) voltage having a constant level. For example, the reset voltage VRST may be about -7V.

[0113] At least one light receiving element LRD may be electrically connected between the fifth node N5 and the electrode EP to which the second power voltage VSS is supplied.

[0114] The light receiving element LRD may generate charge (or current) based on incident light. The light receiving element LRD may perform a function of photoelectric conversion. For example, the light receiving element LRD may be implemented as a photodiode.

[0115] When the ninth transistor T9 is turned on by the reset signal RST supplied to the reset control line RSTL, the reset voltage VRST can be supplied to the fifth node N5. For example, the voltage of the fifth node N5 can be reset by the reset voltage VRST. The light receiving element LRD can perform a photoelectric conversion function after the reset voltage VRST is applied to the fifth node N5.

[0116] The voltage of the fifth node N5 can be changed by the operation of the light receiving element LRD. The voltage of the fifth node N5 (or the charge or current generated in the light receiving element LRD) can be changed according to the intensity of light incident on the light receiving element LRD and the time of light incidence (or the time the light receiving element LRD is exposed to light).

[0117] When the tenth transistor T10 is turned on when the second scan signal GI[i] is supplied to the 2i-th scan line S2i, a detection value (current and / or voltage) generated based on the voltage of the fifth node N5 may be supplied to the k-th readout line RXk.

[0118] In an embodiment, each of the pixel circuit PXC and the sensor circuit SC may include a P-type transistor and an N-type transistor. Each of the third transistor T3, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 may be formed as an oxide semiconductor transistor including an oxide semiconductor (or a second type semiconductor). For example, each of the third transistor T3, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 may be an N-type oxide semiconductor transistor and include an oxide semiconductor layer as an active layer. However, the present disclosure is not limited thereto.

[0119] Each of the other transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8) may be formed as a polysilicon transistor including a silicon semiconductor (or a first type semiconductor), and include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed by a low temperature polysilicon (LTPS) process.

[0120] In the following, reference will be made to Figure 5 and Figure 6 The stacked structure (or cross-sectional structure) of the sub-pixel PXL including the light emitting element LED and the light sensing pixel PSR including the light receiving element LRD is mainly described.

[0121] Figure 5 is a schematic cross-sectional view showing one region of a display device DD according to an embodiment of the present disclosure. Figure 6 It is shown Figure 5 Schematic cross-sectional view of the reflection path of light in the display device DD shown in FIG.

[0122] exist Figure 5 and Figure 6 In the Figure 4 The sixth transistor T6 and the seventh transistor T7 among the first transistor T1 to the seventh transistor T7 shown in FIG. Figure 4 The ninth transistor T9 among the eighth to tenth transistors T8 to T10 shown in FIG.

[0123] refer to Figures 1 to 6 , the display device DD may include sub-pixels PXL and light sensing pixels PSR disposed on a substrate SUB.

[0124] The pixel circuit layer PCL of the subpixel PXL and the pixel circuit layer PCL of the light sensing pixel PSR may be disposed on the substrate SUB. The pixel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, a sixth insulating layer INS6, and a seventh insulating layer INS7 sequentially stacked on the substrate SUB along the third direction DR3.

[0125] The first insulating layer INS1 (or buffer layer) may be entirely disposed on the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the sixth transistor T6 and the ninth transistor T9. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material (or substance). The first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (Al x O y ). The first insulating layer INS1 may be provided as a single layer, but may be provided as a multilayer including at least two layers. The first insulating layer INS1 may be omitted according to the material and process conditions of the substrate SUB, etc.

[0126] The second insulating layer INS2 (or the first gate insulating layer) may be entirely disposed on the first insulating layer INS1. The second insulating layer INS2 may include the same material as the first insulating layer INS1, or include a suitable material disclosed as a material constituting the first insulating layer INS1 (or a material selected from the materials disclosed as a material constituting the first insulating layer INS1). For example, the second insulating layer INS2 may be an inorganic layer including an inorganic material.

[0127] The third insulating layer INS3 (or the second gate insulating layer) may be entirely disposed on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or include at least one appropriate material disclosed as a material constituting the first insulating layer INS1 (or at least one material selected from the materials disclosed as a material constituting the first insulating layer INS1). For example, the third insulating layer INS3 may be an inorganic layer including an inorganic material.

[0128] The fourth insulating layer INS4 (or interlayer insulating layer) may be entirely disposed on the third insulating layer INS3. The fourth insulating layer INS4 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0129] The fifth insulating layer INS5 (or a passivation layer) may be entirely disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0130] The sixth insulating layer INS6 (or the first via layer) may be entirely disposed on the fifth insulating layer INS5. The sixth insulating layer INS6 may be an inorganic layer including an inorganic material or an organic layer including an organic material. The inorganic layer may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (Al x O y The organic layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0131] The seventh insulating layer INS7 (or the second via layer) may be entirely disposed on the sixth insulating layer INS6. The seventh insulating layer INS7 may include the same material as the sixth insulating layer INS6, or include at least one appropriate material disclosed as a material constituting the sixth insulating layer INS6 (or at least one material selected from the materials disclosed as a material constituting the sixth insulating layer INS6). For example, the seventh insulating layer INS7 may be an organic layer including an organic material.

[0132] At least one conductive layer disposed between the above-mentioned insulating layers may be included in the pixel circuit layer PCL. For example, the conductive layer may include a first conductive layer C1 provided between the substrate SUB and the first insulating layer INS1, a second conductive layer C2 disposed on the second insulating layer INS2, a third conductive layer C3 disposed on the third insulating layer INS3, a fourth conductive layer C4 disposed on the fourth insulating layer INS4, a fifth conductive layer C5 disposed on the fifth insulating layer INS5, and a sixth conductive layer C6 disposed on the sixth insulating layer INS6. The insulating layer and the conductive layer are not limited to the above-mentioned embodiments. In some embodiments, other insulating layers and other conductive layers other than the insulating layers and conductive layers shown above may be disposed in the pixel circuit layer PCL.

[0133] The sixth transistor T6 and the ninth transistor T9 may be disposed in the pixel circuit layer PCL. The sixth transistor T6 may include a first gate electrode GE1, a first semiconductor pattern SCP1, a first terminal TE1, and a second terminal TE2. The ninth transistor T9 may include a second gate electrode GE2, a second semiconductor pattern SCP2, a third terminal TE3, and a fourth terminal TE4.

[0134] The first semiconductor pattern SCP1 and the second semiconductor pattern SCP2 may be disposed on the first insulating layer INS1. The first semiconductor pattern SCP1 may include a polysilicon semiconductor, and the second semiconductor pattern SCP2 may include an oxide semiconductor. Although for convenience, it is shown that the first semiconductor pattern SCP1 including a polysilicon semiconductor and the second semiconductor pattern SCP2 including an oxide semiconductor are formed in the same layer, the first semiconductor pattern SCP1 and the second semiconductor pattern SCP2 may not be formed in the same layer, and may be formed by different processes to be formed in different layers. Each of the first semiconductor pattern SCP1 and the second semiconductor pattern SCP2 may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the other end of the channel region. The first contact region may be a source region, and the second contact region may be a drain region. The second insulating layer INS2 may be disposed on the first semiconductor pattern SCP1 and the second semiconductor pattern SCP2.

[0135] The first gate electrode GE1 and the second gate electrode GE2 may be configured as a second conductive layer C2 disposed on the second insulating layer INS2. Although the first gate electrode GE1 and the second gate electrode GE2 are shown as being formed in the same layer for convenience, the first gate electrode GE1 disposed on the first semiconductor pattern SCP1 and the second gate electrode GE2 disposed on the second semiconductor pattern SCP2 may not be formed in the same layer and may be formed by different processes to be formed in different layers. The second conductive layer C2 may be formed as a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and any oxide or alloy thereof. For example, the second conductive layer C2 may be formed as a multilayer in which titanium (Ti), copper (Cu) and / or indium tin oxide (ITO) are sequentially or repeatedly stacked. The first gate electrode GE1 may overlap with a region of the first semiconductor pattern SCP1. The region of the first semiconductor pattern SCP1 overlapping with the first gate electrode GE1 may be a channel region of the sixth transistor T6. The second gate electrode GE2 may overlap one region of the second semiconductor pattern SCP2. The one region of the second semiconductor pattern SCP2 overlapping the second gate electrode GE2 may be a channel region of the ninth transistor T9.

[0136] A third insulating layer INS3 may be disposed on the first gate electrode GE1 and the second gate electrode GE2 .

[0137] The first terminal TE1, the second terminal TE2, the third terminal TE3 and the fourth terminal TE4 may be configured as a fourth conductive layer C4 disposed on the fourth insulating layer INS4. The fourth conductive layer C4 may be formed as a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and any oxide or alloy thereof.

[0138] The first terminal TE1 may be electrically connected to the second contact region of the first semiconductor pattern SCP1 through a contact hole formed through the second, third, and fourth insulating layers INS2, INS3, and INS4. The first terminal TE1 may be electrically connected to the anode electrode AE ​​of the light emitting element LED.

[0139] The second terminal TE2 may be electrically connected to the first contact region of the first semiconductor pattern SCP1 through another contact hole formed through the second, third, and fourth insulating layers INS2, INS3, and INS4.

[0140] The third terminal TE3 may be electrically connected to the first contact region of the second semiconductor pattern SCP2 through another contact hole formed through the second, third and fourth insulating layers INS2, INS3 and INS4. The third terminal TE3 may be electrically connected to the first electrode EL1 of the light receiving element LRD.

[0141] The fourth terminal TE4 may be electrically connected to the second contact region of the second semiconductor pattern SCP2 through yet another contact hole formed through the second, third, and fourth insulating layers INS2, INS3, and INS4.

[0142] The first terminal TE1, the second terminal TE2, the third terminal TE3 and the fourth terminal TE4 may include the same material as the second conductive layer C2 or the third conductive layer C3, or include a suitable material disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3 (or a material selected from the materials disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3). A fifth insulating layer INS5 may be provided on the first terminal TE1, the second terminal TE2, the third terminal TE3 and the fourth terminal TE4.

[0143] The first bottom metal pattern BML1 and the second bottom metal pattern BML2 may be disposed in the pixel circuit layer PCL. The first bottom metal pattern BML1 may be configured as a first conductive layer C1 disposed on the substrate SUB and overlapped with the sixth transistor T6. The second bottom metal pattern BML2 may be configured as a first conductive layer C1 disposed on the substrate SUB and overlapped with the ninth transistor T9. In some embodiments, the first bottom metal pattern BML1 may be electrically connected to the sixth transistor T6 to stabilize the channel region of the sixth transistor T6. The second bottom metal pattern BML2 may be electrically connected to the ninth transistor T9 to stabilize the channel region of the ninth transistor T9.

[0144] The storage capacitor Cst may be disposed in the pixel circuit layer PCL. The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be configured as a second conductive layer C2. The third insulating layer INS3 may be disposed on the lower electrode LE. The upper electrode UE may be disposed on the third insulating layer INS3. The upper electrode UE may overlap with the lower electrode LE in a plan view with the third insulating layer INS3 interposed therebetween. The upper electrode UE may be configured as a third conductive layer C3, but the present disclosure is not limited thereto. The upper electrode UE may overlap with the lower electrode LE with the third insulating layer INS3 interposed therebetween, thereby forming a capacitor.

[0145] The anode connection portion ACL, the first bridge pattern BRP1, and the second bridge pattern BRP2 may be disposed in the pixel circuit layer PCL.

[0146] The anode connection portion ACL may be configured as a fifth conductive layer C5 disposed on the fifth insulating layer INS5. The anode connection portion ACL may be electrically connected to the first terminal TE1 through a contact hole formed through the fifth insulating layer INS5. The anode connection portion ACL may include the same material as the second conductive layer C2 or the third conductive layer C3, or include an appropriate material disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3 (or a material selected from the materials disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3). A sixth insulating layer INS6 may be disposed on the anode connection portion ACL.

[0147] The first bridge pattern BRP1 and the second bridge pattern BRP2 may be configured as a sixth conductive layer C6. The first bridge pattern BRP1 and the second bridge pattern BRP2 may be disposed on the sixth insulating layer INS6 to be spaced apart from each other. The first bridge pattern BRP1 and the second bridge pattern BRP2 may include the same material as the second conductive layer C2 or the third conductive layer C3, or include an appropriate material disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3 (or a material selected from the materials disclosed as a material constituting the second conductive layer C2 or the third conductive layer C3).

[0148] The first bridge pattern BRP1 may be electrically connected to the anode connection portion ACL through a contact hole formed through the sixth insulating layer INS6. The second bridge pattern BRP2 may be electrically connected to the third terminal TE3 through a contact hole formed through the sixth insulating layer INS6 and the fifth insulating layer INS5. The seventh insulating layer INS7 may be disposed over the first bridge pattern BRP1 and the second bridge pattern BRP2.

[0149] The display element layer DPL may be disposed on the pixel circuit layer PCL of the sub-pixel PXL, and the sensor layer SSL may be disposed on the pixel circuit layer PCL of the light sensing pixel PSR.

[0150] The light emitting element LED and the bank BNK may be disposed in the display element layer DPL. The light emitting element LED may include an anode electrode AE ​​(or a pixel electrode), a light emitting layer EML, and a cathode electrode CE (or a common electrode). The light emitting element LED may be electrically connected to the sixth transistor T6. The light emitting layer EML may include a hole transport layer, an organic material layer (or a light generating layer), and an electron transport layer.

[0151] The light receiving element LRD and the bank BNK may be provided in the sensor layer SSL. The light receiving element LRD may be an optical fingerprint sensor. The light receiving element LRD may sense light reflected by the ridge FR of the user's finger F and the valley FV between the ridge FR, thereby identifying the fingerprint. For example, when the user's finger F is in contact with the window WD on the window WD, the first light L1 output from the light emitting element LED (or the light emitting layer EML) may be reflected by the ridge FR or the valley FV of the finger F, and the reflected second light L2 may reach the light receiving element LRD (or the light receiving layer OPL) of the sensor layer SSL. The light receiving element LRD may distinguish between the second light L2 reflected from the ridge FR of the finger F and the second light L2 reflected from the valley FV of the finger F, thereby identifying the pattern of the user's fingerprint. The light receiving element LRD may be electrically connected to the ninth transistor T9. The light receiving element LRD may include a first electrode EL1 (or a first sensor electrode), a light receiving layer OPL (or a photoelectric conversion layer), and a second electrode EL2 (or a second sensor electrode).

[0152] The anode electrode AE ​​and the first electrode EL1 may be disposed on the seventh insulating layer INS7. The anode electrode AE ​​and the first electrode EL1 may be made of a metal layer (containing, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any alloy thereof) and / or a transparent conductive layer containing, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO). The anode electrode AE ​​may be electrically connected to the first bridge pattern BRP1 through a contact hole formed through the seventh insulating layer INS7. The first electrode EL1 may be electrically connected to the second bridge pattern BRP2 through another contact hole formed through the seventh insulating layer INS7.

[0153] The anode electrode AE ​​and the first electrode EL1 may be simultaneously formed by patterning using a mask.

[0154] A bank BNK may be disposed on the anode electrode AE, the first electrode EL1 , and the seventh insulating layer INS7 .

[0155] The bank BNK may be a pixel defining layer that defines (or divides) the emission area EMA of the sub-pixel PXL and the light receiving area FXA of the light sensing pixel PSR. The bank BNK may be an organic layer including an organic material (or substance). The organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like.

[0156] In some embodiments, the bank BNK may include a light absorbing material or have a light absorber applied thereon to absorb light introduced from the outside. For example, the bank BNK may include a carbon-based black pigment. However, the present disclosure is not limited thereto, and the bank BNK may include an opaque metal material with high light absorptivity, such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0157] The bank BNK may include openings corresponding to the emission area EMA and the light receiving area FXA.

[0158] The light emitting layer EML may be disposed on the anode electrode AE. The light emitting layer EML may include an organic light emitting layer. The light emitting layer EML may emit light such as red light, green light, or blue light according to an organic material, but the present disclosure is not limited thereto.

[0159] A light receiving layer OPL may be disposed on the first electrode EL1. The light receiving layer OPL may emit electrons corresponding to light in a specific wavelength band, thereby sensing the intensity of the light.

[0160] The light receiving layer OPL may include a low molecular organic material (or substance). For example, the light receiving layer OPL may be formed of a phthalocyanine compound, which includes at least one metal selected from the group consisting of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La) and zinc (Zn).

[0161] Optionally, the low molecular organic material included in the light receiving layer OPL can be configured as a double layer, the double layer including a layer containing a phthalocyanine compound and a layer containing carbon 60 (C60), the phthalocyanine compound including at least one metal selected from the group consisting of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La) and zinc (Zn), or configured as a single mixed layer in which the phthalocyanine compound and C60 are mixed with each other.

[0162] However, this is merely exemplary, and the light receiving layer OPL may include a polymer organic layer.

[0163] In an embodiment, according to the selection of the metal component included in the phthalocyanine compound, the light receiving layer OPL can determine the light detection band of the light sensor. For example, the phthalocyanine compound including copper absorbs visible light having a wavelength band of about 600nm to about 800nm. The phthalocyanine compound including tin (Sn) absorbs near-infrared light having a wavelength band of about 800nm ​​to about 1000nm. Therefore, when the selection of the metal included in the phthalocyanine compound is controlled, a light sensor capable of detecting the wavelength band required by the user can be realized. For example, the light receiving element LRD can be formed to selectively absorb light corresponding to a wavelength band of red, light corresponding to a wavelength band of green, or light corresponding to a wavelength band of blue through the light receiving layer OPL.

[0164] The cathode electrode CE may be disposed on the light emitting layer EML, and the second electrode EL2 may be disposed on the light receiving layer OPL. The cathode electrode CE and the second electrode EL2 may correspond to a common electrode integrally formed in the display area DA. The second power voltage VSS may be supplied to the cathode electrode CE and the second electrode EL2.

[0165] The cathode electrode CE and the second electrode EL2 may be formed of a metal layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir or Cr and / or a transparent conductive layer including ITO, IZO, ZnO or ITZO. In an embodiment, the cathode electrode CE and the second electrode EL2 may be formed as a multilayer including at least two layers including a thin metal layer. For example, the cathode electrode CE and the second electrode EL2 may be formed as a triple layer of ITO / Ag / ITO.

[0166] A thin film encapsulation layer TFE may be integrally formed on the cathode electrode CE and the second electrode EL2 .

[0167] The thin film encapsulation layer TFE may be formed as a single layer, and may also be formed as a multilayer. The thin film encapsulation layer TFE may include a plurality of insulating layers covering the light emitting element LED and the light receiving element LRD. The thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked.

[0168] The color filter layer CFL may be disposed on the thin film encapsulation layer TFE. The color filter layer CFL may include a light blocking pattern and a color filter. The light blocking pattern may be disposed in a non-emission area NEA surrounding an emission area EMA of the sub-pixel PXL and a light receiving area FXA of the light sensing pixel PSR, and a color filter may be disposed in the emission area EMA and the light receiving area FXA. The above-mentioned color filter layer CFL may be used as an anti-reflection layer for blocking external light reflection.

[0169] The window WD may be disposed on the color filter layer CFL.

[0170] Figure 7 It is schematically shown Figure 1 0 is a plan view of data lines D1 to Dk+6, readout lines RX1 to RXk+5, bridge lines BRL, connection lines CNL, first lines LP1a to LP1m, and second lines LP2a to LP2m of a display device DD shown in FIG.

[0171] exist Figure 7 In the present invention, parts different from those of the above-described embodiment will be described to avoid redundancy.

[0172] refer to Figures 1 to 7 The display device DD (or display panel DP) may include a substrate SUB, a line portion (see Figure 1 The “line portion LP” shown in FIG. 1 ) and the pad portion PDP.

[0173] The pad portion PDP may be positioned in the pad area PDA and include a first pad portion PDP1 and a second pad portion PDP2 electrically connected to the line portion LP. The first pad portion PDP1 may include a first pad portion PDP2 electrically connected to the first line (see Figure 1 , and the second pad portion PDP2 may include a first pad P1 electrically connected to a second line (see “first line LP1”). Figure 1 The first pad portion PDP1 and the second pad portion PDP2 may be arranged to be spaced apart from each other so as to be physically and electrically separated from each other in the pad area PDA. For example, the first pad portion PDP1 may be positioned adjacent to an edge of the substrate SUB in the pad area PDA, and the second pad portion PDP2 may be positioned in the center of the pad area PDA. The first pad portion PDP1 may be positioned at both sides of the second pad portion PDP2.

[0174] The line portion LP may be positioned in the fan-out area FTA and include a first line LP1 electrically connected to the first pad portion PDP1 and a second line LP2 electrically connected to the second pad portion PDP2. The first line LP1 and the second line LP2 may be arranged to be spaced apart from each other so as to be physically and electrically separated from each other in the fan-out area FTA. For example, the first line LP1 may be positioned adjacent to an edge of the substrate SUB in the fan-out area FTA, and the second line LP2 may be positioned in the center of the fan-out area FTA. The first line LP1 may extend toward the first area DA1 in the fan-out area FTA, and the second line LP2 may extend toward the second area DA2 in the fan-out area FTA. The first line LP1 may be positioned at both sides of the second line LP2.

[0175] The first line LP1 may include a first line electrically connected to the readout lines RX1 to RX4 and RXk+3 to RXk+5 positioned in the first area DA1 through the first contact portion CNT1. The first line may include a 1a line LP1a, a 1c line LP1c, a 1e line LP1e, a 1g line LP1g, a 1h line LP1h, a 1j line LP1j, and a 1l line LP1l, where a, c, e, g, h, j, and l are natural numbers greater than 0.

[0176] In an embodiment, the first line LP1 may include other first lines electrically connected to the connection line CNL extending from the first area DA1 to the second area DA2 through the first contact portion CNT1. The other first lines may include a 1b-th line LP1b, a 1d-th line LP1d, a 1f-th line LP1f, a 1i-th line LP1i, a 1k-th line LP1k, and a 1m-th line LP1m, where b, d, f, i, k, and m are natural numbers greater than 0.

[0177] The second line LP2 may include a second line electrically connected to the data lines D4 to Dk+2 positioned in the second area DA2 through the second contact portion CNT2. The second line may include a 2b line LP2b, a 2d line LP2d, a 2f line LP2f, a 2h line LP2h, a 2j line LP2j, and a 2l line LP2l.

[0178] In an embodiment, the second line LP2 may include other second lines electrically connected to the bridge line BRL extending from the second area DA2 to the first area DA1 through the second contact portion CNT2. The other second lines may include a 2a line LP2a, a 2c line LP2c, a 2e line LP2e, a 2g line LP2g, a 2i line LP2i, a 2k line LP2k, and a 2m line LP2m.

[0179] In the following embodiments, in the case of arbitrarily specifying at least one of the 1a-th line LP1a to the 1m-th line LP1m or in the case of inclusively specifying the 1a-th line LP1a to the 1m-th line LP1m, each of the 1a-th line LP1a to the 1m-th line LP1m or the 1a-th line LP1a to the 1m-th line LP1m will be referred to as “first line LP1” or “plurality of first lines LP1”. In the case of arbitrarily specifying at least one of the 2a-th line LP2a to the 2m-th line LP2m or in the case of inclusively specifying the 2a-th line LP2a to the 2m-th line LP2m, each of the 2a-th line LP2a to the 2m-th line LP2m or the 2a-th line LP2a to the 2m-th line LP2m will be referred to as “second line LP2” or “plurality of second lines LP2”.

[0180] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA may include a first area DA1 and a second area DA2.

[0181] Signal lines to which various signals are applied may be disposed in the first area DA1 and the second area DA2. For example, data lines D1 to Dk+6 to which data signals for adjusting the brightness of each subpixel PXL are applied may be disposed in the first area DA1 and the second area DA2. Readout lines RX1 to RXk+5 that receive sensing signals from the light sensing pixels PSR may be disposed in the first area DA1 and the second area DA2. Various signal lines including power lines and scan lines in addition to the data lines D1 to Dk+6 and the readout lines RX1 to RXk+5 may be disposed in the first area DA1 and the second area DA2.

[0182] In the first area DA1 and the second area DA2, the sub-pixel PXL may be disposed or positioned between the scanning lines (eg, Figure 4 In the first area DA1 and the second area DA2, the light sensing pixels PSR may be disposed or positioned in an area divided by the scan lines (e.g., scan lines S1i to S4i) and the readout lines (e.g., readout lines RX1 to RXk+5).

[0183] The first data line D1, the second data line D2, the third data line D3, the k+3th data line Dk+3, the k+4th data line Dk+4, the k+5th data line Dk+5, and the k+6th data line Dk+6 may be disposed in the first area DA1. For ease of description, it is shown that seven data lines are disposed in the first area DA1. However, the present disclosure is not limited thereto.

[0184] The fourth data line D4, the fifth data line D5, the sixth data line D6, the kth data line Dk, the k+1th data line Dk+1 and the k+2th data line Dk+2 may be disposed in the second area DA2. For ease of description, six data lines are shown disposed in the second area DA2. However, the present disclosure is not limited thereto.

[0185] The first readout line RX1, the second readout line RX2, the third readout line RX3, the fourth readout line RX4, the k+3th readout line RXk+3, the k+4th readout line RXk+4, and the k+5th readout line RXk+5 may be disposed in the first area DA1. For ease of description, it is shown that seven readout lines are disposed in the first area DA1. However, the present disclosure is not limited thereto.

[0186] The fifth readout line RX5, the sixth readout line RX6, the seventh readout line RX7, the kth readout line RXk, the k+1th readout line RXk+1 and the k+2th readout line RXk+2 may be disposed in the second area DA2. For ease of description, six readout lines are shown disposed in the second area DA2. However, the present disclosure is not limited thereto.

[0187] The connection line CNL and the bridge line BRL may be disposed in the display area DA. In an embodiment, the connection line CNL and the bridge line BRL may be disposed in the display area DA without overlapping each other. Coupling capacitance that may occur when the connection line CNL and the bridge line BRL overlap each other may be prevented.

[0188] In an embodiment, the connection line CNL may extend from the first area DA1 to the second area DA2. For example, the connection line CNL may be arranged across the boundary between the first area DA1 and the second area DA2, and extend from the edge of the display area DA to the center (or inner side) of the display area DA. The connection line CNL may be electrically connected to the corresponding first line LP1 through the first contact portion CNT1. The connection line CNL may include: a vertical connection line, which is arranged in the first area DA1 and extends in the second direction DR2; and a horizontal connection line, which is electrically connected to the vertical connection line and extends along the first direction DR1 to pass through the boundary between the first area DA1 and the second area DA2.

[0189] The connection lines CNL may include a first connection line CNL1, a second connection line CNL2, a third connection line CNL3, a fourth connection line CNL4, a fifth connection line CNL5, and a sixth connection line CNL6. Each of the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, the fourth connection line CNL4, the fifth connection line CNL5, and the sixth connection line CNL6 may include a vertical connection line positioned in the first area DA1 and extending in the second direction DR2, and a horizontal connection line extending in the first direction DR1 and crossing a boundary between the first area DA1 and the second area DA2.

[0190] The vertical connection line of the first connection line CNL1 may be electrically connected to the 1b line LP1b through the first contact portion CNT1, and may be electrically connected to the horizontal connection line of the first connection line CNL1 through the third contact hole CH3. The horizontal connection line may be electrically connected to the seventh readout line RX7 disposed in the second area DA2 through the fourth contact hole CH4. The first connection line CNL1 may electrically connect the seventh readout line RX7 and the 1b line LP1b to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the seventh readout line RX7 may be transmitted to the driver DIC via the 1b line LP1b through the first connection line CNL1.

[0191] The vertical connection line of the second connection line CNL2 may be electrically connected to the 1d-line LP1d through the first contact portion CNT1, and may be electrically connected to the horizontal connection line of the second connection line CNL2 through the third contact hole CH3. The horizontal connection line may be electrically connected to the sixth readout line RX6 disposed in the second area DA2 through the fourth contact hole CH4. The second connection line CNL2 may electrically connect the sixth readout line RX6 and the 1d-line LP1d to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the sixth readout line RX6 may be transmitted to the driver DIC via the 1d-line LP1d through the second connection line CNL2.

[0192] The vertical connection line of the third connection line CNL3 may be electrically connected to the 1f line LP1f through the first contact portion CNT1, and electrically connected to the horizontal connection line of the third connection line CNL3 through the third contact hole CH3. The horizontal connection line may be electrically connected to the fifth readout line RX5 disposed in the second area DA2 through the fourth contact hole CH4. The third connection line CNL3 may electrically connect the fifth readout line RX5 and the 1f line LP1f to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the fifth readout line RX5 may be transmitted to the driver DIC via the 1f line LP1f through the third connection line CNL3.

[0193] The vertical connection line of the fourth connection line CNL4 may be electrically connected to the 1m-th line LP1m through the first contact portion CNT1, and electrically connected to the horizontal connection line of the fourth connection line CNL4 through the third contact hole CH3. The horizontal connection line may be electrically connected to the k-th readout line RXk disposed in the second area DA2 through the fourth contact hole CH4. The fourth connection line CNL4 may electrically connect the k-th readout line RXk and the 1m-th line LP1m to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the k-th readout line RXk may be transmitted to the driver DIC via the 1m-th line LP1m through the fourth connection line CNL4.

[0194] The vertical connection line of the fifth connection line CNL5 may be electrically connected to the 1kth line LP1k through the first contact portion CNT1, and electrically connected to the horizontal connection line of the fifth connection line CNL5 through the third contact hole CH3. The horizontal connection line may be electrically connected to the k+1th readout line RXk+1 disposed in the second area DA2 through the fourth contact hole CH4. The fifth connection line CNL5 may electrically connect the k+1th readout line RXk+1 and the 1kth line LP1k to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the k+1th readout line RXk+1 may be transmitted to the driver DIC via the 1kth line LP1k through the fifth connection line CNL5.

[0195] The vertical connection line of the sixth connection line CNL6 may be electrically connected to the 1i-th line LP1i through the first contact portion CNT1, and electrically connected to the horizontal connection line of the sixth connection line CNL6 through the third contact hole CH3. The horizontal connection line may be electrically connected to the k+2-th readout line RXk+2 disposed in the second area DA2 through the fourth contact hole CH4. The sixth connection line CNL6 may electrically connect the k+2-th readout line RXk+2 and the 1i-th line LP1i to each other. Therefore, the sensing signal of the light sensing pixel PSR from the second area DA2 received from the k+2-th readout line RXk+2 may be transmitted to the driver DIC via the 1i-th line LP1i through the sixth connection line CNL6.

[0196] One end of the vertical connection line may be electrically connected to the corresponding first line LP1 through the first contact portion CNT1, and the other end of the vertical connection line may be electrically connected to the corresponding horizontal connection line through the third contact hole CH3. One end of the horizontal connection line may be electrically connected to the vertical connection line through the third contact hole CH3, and the other end of the horizontal connection line may be electrically connected to the corresponding readout line positioned in the second area DA2 through the fourth contact hole CH4.

[0197] In an embodiment, the bridge wire BRL may extend from the second area DA2 to the first area DA1. For example, the bridge wire BRL may be arranged across the boundary between the first area DA1 and the second area DA2, and extend from the center (or inner side) of the display area DA to the edge of the display area DA. The bridge wire BRL may be electrically connected to the corresponding second line LP2 through the second contact portion CNT2. The bridge wire BRL may include: a vertical bridge wire, which is arranged in the second area DA2 and extends in the second direction DR2; and a horizontal bridge wire, which is electrically connected to the vertical bridge wire and extends along the first direction DR1 to pass through the boundary between the first area DA1 and the second area DA2.

[0198] The bridging wires BRL may include a first bridging wire BRL1, a second bridging wire BRL2, a third bridging wire BRL3, a fourth bridging wire BRL4, a fifth bridging wire BRL5, a sixth bridging wire BRL6, and a seventh bridging wire BRL7. Each of the first bridging wire BRL1, the second bridging wire BRL2, the third bridging wire BRL3, the fourth bridging wire BRL4, the fifth bridging wire BRL5, the sixth bridging wire BRL6, and the seventh bridging wire BRL7 may include a vertical bridging wire positioned in the second area DA2 and extending in the second direction DR2, and a horizontal bridging wire extending in the first direction DR1 and crossing a boundary between the first area DA1 and the second area DA2.

[0199] The vertical bridge line of the first bridge line BRL1 may be electrically connected to the 2e-line LP2e through the second contact portion CNT2, and electrically connected to the horizontal bridge line of the first bridge line BRL1 through the first contact hole CH1. The horizontal bridge line may be electrically connected to the first data line D1 disposed in the first area DA1 through the second contact hole CH2. The first bridge line BRL1 may electrically connect the first data line D1 and the 2e-line LP2e to each other. Therefore, the data signal transmitted from the driver DIC to the 2e-line LP2e may be transmitted to the first data line D1 via the first bridge line BRL1.

[0200] The vertical bridge wire of the second bridge wire BRL2 may be electrically connected to the 2c line LP2c through the second contact portion CNT2, and may be electrically connected to the horizontal bridge wire of the second bridge wire BRL2 through the first contact hole CH1. The horizontal bridge wire may be electrically connected to the second data line D2 disposed in the first area DA1 through the second contact hole CH2. The second bridge wire BRL2 may electrically connect the second data line D2 and the 2c line LP2c to each other. Therefore, the data signal transmitted from the driver DIC to the 2c line LP2c may be transmitted to the second data line D2 via the second bridge wire BRL2.

[0201] The vertical bridge line of the third bridge line BRL3 may be electrically connected to the 2a line LP2a through the second contact portion CNT2, and electrically connected to the horizontal bridge line of the third bridge line BRL3 through the first contact hole CH1. The horizontal bridge line may be electrically connected to the third data line D3 disposed in the first area DA1 through the second contact hole CH2. The third bridge line BRL3 may electrically connect the third data line D3 and the 2a line LP2a to each other. Therefore, the data signal transmitted from the driver DIC to the 2a line LP2a may be transmitted to the third data line D3 via the third bridge line BRL3.

[0202] The vertical bridge wire of the fourth bridge wire BRL4 may be electrically connected to the 2g line LP2g through the second contact portion CNT2, and connected to the horizontal bridge wire of the fourth bridge wire BRL4 through the first contact hole CH1. The horizontal bridge wire may be electrically connected to the k+6th data line Dk+6 disposed in the first area DA1 through the second contact hole CH2. The fourth bridge wire BRL4 may electrically connect the k+6th data line Dk+6 and the 2g line LP2g to each other. Therefore, the data signal transmitted from the driver DIC to the 2g line LP2g may be transmitted to the k+6th data line Dk+6 via the fourth bridge wire BRL4.

[0203] The vertical bridge line of the fifth bridge line BRL5 may be electrically connected to the 2i-th line LP2i through the second contact portion CNT2, and electrically connected to the horizontal bridge line of the fifth bridge line BRL5 through the first contact hole CH1. The horizontal bridge line may be electrically connected to the k+5th data line Dk+5 disposed in the first area DA1 through the second contact hole CH2. The fifth bridge line BRL5 may electrically connect the k+5th data line Dk+5 and the 2i-th line LP2i to each other. Therefore, the data signal transmitted from the driver DIC to the 2i-th line LP2i may be transmitted to the k+5th data line Dk+5 via the fifth bridge line BRL5.

[0204] The vertical bridge wire of the sixth bridge wire BRL6 may be electrically connected to the 2kth line LP2k through the second contact portion CNT2, and electrically connected to the horizontal bridge wire of the sixth bridge wire BRL6 through the first contact hole CH1. The horizontal bridge wire may be electrically connected to the k+4th data line Dk+4 disposed in the first area DA1 through the second contact hole CH2. The sixth bridge wire BRL6 may electrically connect the k+4th data line Dk+4 and the 2kth line LP2k to each other. Therefore, the data signal transmitted from the driver DIC to the 2kth line LP2k may be transmitted to the k+4th data line Dk+4 via the sixth bridge wire BRL6.

[0205] The vertical bridge line of the seventh bridge line BRL7 may be electrically connected to the 2mth line LP2m through the second contact portion CNT2, and electrically connected to the horizontal bridge line of the seventh bridge line BRL7 through the first contact hole CH1. The horizontal bridge line may be electrically connected to the k+3th data line Dk+3 disposed in the first area DA1 through the second contact hole CH2. The seventh bridge line BRL7 may electrically connect the k+3th data line Dk+3 and the 2mth line LP2m to each other. Therefore, the data signal transmitted from the driver DIC to the 2mth line LP2m may be transmitted to the k+3th data line Dk+3 via the seventh bridge line BRL7.

[0206] According to the above-described embodiment, the first pads P1 electrically connected to the readout line may be disposed in at least one predetermined area to be disposed adjacent to each other without any intervening second pads, and the second pads P2 electrically connected to the data line may be disposed in at least one predetermined area to be disposed adjacent to each other without any intervening first pads. For example, the second pad portion PDP2 may be positioned at the center of the pad area PDA to correspond to the second area DA2 of the display area DA, and the first pad portion PDP1 may be positioned at both edges of the pad area PDA to correspond to the first area DA1 of the display area DA. The phenomenon that the sensing signal of the light sensing pixel PSR transmitted to the driver DIC through the first pad portion PDP1 is affected by the data signal transmitted to the data line through the second pad portion PDP2 may be reduced or prevented. In addition, the phenomenon that the data signal transmitted to the data line through the second pad portion PDP2 is affected by the sensing signal of the light sensing pixel PSR transmitted to the driver DIC through the first pad portion PDP1 may be reduced or prevented. In the case where the readout pads electrically connected to the readout lines and the data pads electrically connected to the data lines are alternately arranged in the pad area PDA, coupling capacitance (or parasitic capacitance) may occur between the readout pads and the data pads. Therefore, in the above-mentioned embodiment, the first pad portion PDP1 and the second pad portion PDP2 are arranged to be spaced apart from each other and each is positioned in a specific area of ​​the pad area PDA, so that the above-mentioned coupling capacitance can be prevented, thereby improving the reliability of the display device DD.

[0207] According to the above-described embodiment, the first lines LP1 electrically connected to the readout lines may be disposed adjacent to each other in at least one predetermined area without any intervening second lines LP2 in the fan-out area FTA, and the second lines LP2 electrically connected to the data lines may be disposed adjacent to each other in at least one predetermined area without any intervening first lines LP1 in the fan-out area FTA. For example, the second line LP2 may be positioned at the center of the fan-out area FTA to correspond to the second area DA2 of the display area DA, and the first line LP1 may be positioned at both edges of the fan-out area FTA to correspond to the first area DA1 of the display area DA. The phenomenon that the sensing signal of the light sensing pixel PSR transmitted to the first pad portion PDP1 through the first line LP1 is affected by the data signal transmitted to the data line through the second line LP2 may be reduced or prevented. In addition, the phenomenon that the data signal transmitted to the data line through the second line LP2 is affected by the sensing signal of the light sensing pixel PSR transmitted to the first pad portion PDP1 through the first line LP1 may be reduced or prevented. In the case where the readout fan-out lines electrically connected to the readout lines and the data fan-out lines electrically connected to the data lines are alternately arranged in the fan-out area FTA, coupling capacitance (or parasitic capacitance) may occur between the readout fan-out lines and the data fan-out lines. Therefore, in the above-mentioned embodiment, the first line LP1 and the second line LP2 are arranged to be spaced apart from each other or not alternate with each other, and are each positioned in at least one predetermined area of ​​the fan-out area FTA, so that the above-mentioned coupling capacitance can be prevented, thereby improving the reliability of the display device DD.

[0208] In the following, reference will be made to Figures 8 to 13 The connection line CNL electrically connected to the first line LP1 and the bridge line BRL electrically connected to the second line LP2 are described in detail.

[0209] Figure 8 It is shown Figure 7 Schematic enlargement of the portion EA shown in . Figures 9 to 11 It is along Figure 8 A schematic cross-sectional view taken along line II' shown in FIG. Fig.12 and Fig.13 It is along Figure 8 Schematic cross-sectional view taken along line II-II' shown in FIG.

[0210] Fig.10 and Fig.11 Each of the Fig. 9 Modifications related to the positions of the third horizontal connection line CNH3, the third vertical connection line CNV3 and the fifth readout line RX5, etc.

[0211] Fig.13 Shows Fig.12Modifications related to the positions of the first horizontal bridge wire BRH1, the second horizontal bridge wire BRH2, and the third horizontal bridge wire BRH3, etc.

[0212] about Figures 8 to 13 The embodiment shown in , parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0213] refer to Figures 1 to 13 , the first connection line CNL1, the second connection line CNL2 and the third connection line CNL3 may extend from the first area DA1 to the second area DA2. The first bridge line BRL1, the second bridge line BRL2 and the third bridge line BRL3 may extend from the second area DA2 to the first area DA1. Each of the first connection line CNL1, the second connection line CNL2 and the third bridge line CNL3 may have a shape that is bent at least once to be electrically connected to a readout line disposed in the second area DA2. Each of the first bridge line BRL1, the second bridge line BRL2 and the third bridge line BRL3 may have a shape that is bent at least once to be electrically connected to a data line disposed in the first area DA1. In an embodiment, each of the first connection line CNL1, the second connection line CNL2 and the third connection line CNL3 may not overlap with any of the first bridge line BRL1, the second bridge line BRL2 and the third bridge line BRL3.

[0214] The first connection line CNL1 may include a first vertical connection line CNV1 disposed in the first area DA1 and extending in the second direction DR2 and a first horizontal connection line CNH1 positioned to cross the second area DA2 from the first area DA1 and extend in the first direction DR1. One end of the first horizontal connection line CNH1 may be positioned in the first area DA1, and the other end of the first horizontal connection line CNH1 may be positioned in the second area DA2.

[0215] One end of the first vertical connection line CNV1 may be electrically connected to the 1b line LP1b through the first contact portion CNT1. The other end of the first vertical connection line CNV1 may be electrically connected to the first horizontal connection line CNH1 through the third contact hole CH3. The first contact portion CNT1 may be formed by removing a portion of the insulating layer positioned between the first vertical connection line CNV1 and the 1b line LP1b. The third contact hole CH3 may be formed by removing a portion of the insulating layer positioned between the first vertical connection line CNV1 and the first horizontal connection line CNH1.

[0216] One end of the first horizontal connection line CNH1 may be electrically connected to the first vertical connection line CNV1 through the third contact hole CH3. The other end of the first horizontal connection line CNH1 may be electrically connected to the seventh readout line RX7 disposed in the second area DA2 through the fourth contact hole CH4. The fourth contact hole CH4 may be formed by removing a portion of the insulating layer positioned between the first horizontal connection line CNH1 and the seventh readout line RX7.

[0217] The second connection line CNL2 may include a second vertical connection line CNV2 disposed in the first area DA1 and extending in the second direction DR2 and a second horizontal connection line CNH2 positioned to cross the second area DA2 from the first area DA1 and extend in the first direction DR1. One end of the second horizontal connection line CNH2 may be positioned in the first area DA1, and the other end of the second horizontal connection line CNH2 may be positioned in the second area DA2.

[0218] One end of the second vertical connection line CNV2 may be electrically connected to the 1d line LP1d through the first contact CNT1. The other end of the second vertical connection line CNV2 may be electrically connected to the second horizontal connection line CNH2 through the third contact hole CH3. The first contact CNT1 may be formed by removing a portion of the insulating layer positioned between the second vertical connection line CNV2 and the 1d line LP1d. The third contact hole CH3 may be formed by removing a portion of the insulating layer positioned between the second vertical connection line CNV2 and the second horizontal connection line CNH2.

[0219] One end of the second horizontal connection line CNH2 may be electrically connected to the second vertical connection line CNV2 through the third contact hole CH3. The other end of the second horizontal connection line CNH2 may be electrically connected to the sixth readout line RX6 disposed in the second area DA2 through the fourth contact hole CH4. The fourth contact hole CH4 may be formed by removing a portion of the insulating layer positioned between the second horizontal connection line CNH2 and the sixth readout line RX6.

[0220] The third connection line CNL3 may include a third vertical connection line CNV3 disposed in the first area DA1 and extending in the second direction DR2 and a third horizontal connection line CNH3 positioned to cross the second area DA2 from the first area DA1 and extend in the first direction DR1. One end of the third horizontal connection line CNH3 may be positioned in the first area DA1, and the other end of the third horizontal connection line CNH3 may be positioned in the second area DA2.

[0221] One end of the third vertical connection line CNV3 may be electrically connected to the 1f line LP1f through the first contact CNT1. The other end of the third vertical connection line CNV3 may be electrically connected to the third horizontal connection line CNH3 through the third contact hole CH3. The first contact CNT1 may be formed by removing a portion of the insulating layer positioned between the third vertical connection line CNV3 and the 1f line LP1f. The third contact hole CH3 may be formed by removing a portion of the insulating layer positioned between the third vertical connection line CNV3 and the third horizontal connection line CNH3.

[0222] One end of the third horizontal connection line CNH3 may be electrically connected to the third vertical connection line CNV3 through the third contact hole CH3. The other end of the third horizontal connection line CNH3 may be electrically connected to the fifth readout line RX5 disposed in the second area DA2 through the fourth contact hole CH4. The fourth contact hole CH4 may be formed by removing a portion of the insulating layer positioned between the third horizontal connection line CNH3 and the fifth readout line RX5.

[0223] The first bridging line BRL1 may include a first vertical bridging line BRV1 disposed in the second area DA2 and extending in the second direction DR2 and a first horizontal bridging line BRH1 positioned to cross the first area DA1 from the second area DA2 and extend in the first direction DR1. One end of the first horizontal bridging line BRH1 may be positioned in the second area DA2, and the other end of the first horizontal bridging line BRH1 may be positioned in the first area DA1.

[0224] One end of the first vertical bridge wire BRV1 may be electrically connected to the 2e-line LP2e through the second contact portion CNT2. The other end of the first vertical bridge wire BRV1 may be electrically connected to the first horizontal bridge wire BRH1 through the first contact hole CH1. The second contact portion CNT2 may be formed by removing a portion of the insulating layer positioned between the first vertical bridge wire BRV1 and the 2e-line LP2e. The first contact hole CH1 may be formed by removing a portion of the insulating layer positioned between the first vertical bridge wire BRV1 and the first horizontal bridge wire BRH1.

[0225] One end of the first horizontal bridge line BRH1 may be electrically connected to the first vertical bridge line BRV1 through a first contact hole CH1. The other end of the first horizontal bridge line BRH1 may be electrically connected to the first data line D1 positioned in the first area DA1 through a second contact hole CH2. The second contact hole CH2 may be formed by removing a portion of the insulating layer positioned between the first horizontal bridge line BRH1 and the first data line D1.

[0226] The second bridging line BRL2 may include a second vertical bridging line BRV2 disposed in the second area DA2 and extending in the second direction DR2 and a second horizontal bridging line BRH2 positioned to cross the first area DA1 from the second area DA2 and extend in the first direction DR1. One end of the second horizontal bridging line BRH2 may be positioned in the second area DA2, and the other end of the second horizontal bridging line BRH2 may be positioned in the first area DA1.

[0227] One end of the second vertical bridge wire BRV2 may be electrically connected to the 2c-line LP2c through the second contact portion CNT2. The other end of the second vertical bridge wire BRV2 may be electrically connected to the second horizontal bridge wire BRH2 through the first contact hole CH1. The second contact portion CNT2 may be formed by removing a portion of the insulating layer positioned between the second vertical bridge wire BRV2 and the 2c-line LP2c. The first contact hole CH1 may be formed by removing a portion of the insulating layer positioned between the second vertical bridge wire BRV2 and the second horizontal bridge wire BRH2.

[0228] One end of the second horizontal bridge line BRH2 may be electrically connected to the second vertical bridge line BRV2 through the first contact hole CH1. The other end of the second horizontal bridge line BRH2 may be electrically connected to the second data line D2 positioned in the first area DA1 through the second contact hole CH2. The second contact hole CH2 may be formed by removing a portion of the insulating layer positioned between the second horizontal bridge line BRH2 and the second data line D2.

[0229] The third bridging line BRL3 may include a third vertical bridging line BRV3 disposed in the second area DA2 and extending in the second direction DR2 and a third horizontal bridging line BRH3 positioned to cross the first area DA1 from the second area DA2 and extend in the first direction DR1. One end of the third horizontal bridging line BRH3 may be positioned in the second area DA2, and the other end of the third horizontal bridging line BRH3 may be positioned in the first area DA1.

[0230] One end of the third vertical bridge wire BRV3 may be electrically connected to the 2a line LP2a through the second contact portion CNT2. The other end of the third vertical bridge wire BRV3 may be electrically connected to the third horizontal bridge wire BRH3 through the first contact hole CH1. The second contact portion CNT2 may be formed by removing a portion of the insulating layer positioned between the third vertical bridge wire BRV3 and the 2a line LP2a. The first contact hole CH1 may be formed by removing a portion of the insulating layer positioned between the third vertical bridge wire BRV3 and the third horizontal bridge wire BRH3.

[0231] One end of the third horizontal bridge line BRH3 may be electrically connected to the third vertical bridge line BRV3 through the first contact hole CH1. The other end of the third horizontal bridge line BRH3 may be electrically connected to the third data line D3 positioned in the first area DA1 through the second contact hole CH2. The second contact hole CH2 may be formed by removing a portion of the insulating layer positioned between the third horizontal bridge line BRH3 and the third data line D3.

[0232] Each of the readout lines positioned in the first area DA1 may be directly connected to the corresponding first line LP1. For example, the first readout line RX1 positioned in the first area DA1 may be electrically connected to the 1a-th line LP1a through the first contact portion CNT1. The second readout line RX2 positioned in the first area DA1 may be electrically connected to the 1c-th line LP1c through the first contact portion CNT1. The third readout line RX3 positioned in the first area DA1 may be electrically connected to the 1e-th line LP1e through the first contact portion CNT1. The fourth readout line RX4 positioned in the first area DA1 may be electrically connected to the 1g-th line LP1g through the first contact portion CNT1.

[0233] Each of the data lines positioned in the second area DA2 may be directly connected to the corresponding second line LP2. For example, the fourth data line D4 positioned in the second area DA2 may be electrically connected to the 2b line LP2b through the second contact CNT2. The fifth data line D5 positioned in the second area DA2 may be electrically connected to the 2d line LP2d through the second contact CNT2. The sixth data line D6 positioned in the second area DA2 may be electrically connected to the 2f line LP2f through the second contact CNT2.

[0234] In an embodiment, the lines extending in the first direction DR1 and the lines extending in the second direction DR2 may be arranged in different layers. For example, the horizontal connection lines and the horizontal bridge lines extending in the first direction DR1 may be arranged on the fourth insulating layer INS4. The vertical connection lines, the vertical bridge lines, the readout lines and the data lines extending in the second direction DR2 may be arranged on the sixth insulating layer INS6. In other words, the horizontal connection lines and the horizontal bridge lines may be configured as the fourth conductive layer C4, and the vertical connection lines, the vertical bridge lines, the readout lines and the data lines may be configured as the sixth conductive layer C6. However, the present disclosure is not limited thereto. In some embodiments, the horizontal connection lines and the horizontal bridge lines may be configured as the fifth conductive layer C5 or the sixth conductive layer C6, and the vertical connection lines, the vertical bridge lines, the readout lines and the data lines may be configured as the fourth conductive layer C4 or the fifth conductive layer C5.

[0235] In an embodiment, the horizontal connection lines and the horizontal bridge lines extending in the first direction DR1 may be arranged in the same layer. For example, the first horizontal connection line CNH1, the second horizontal connection line CNH2, and the third horizontal connection line CNH3 and the first horizontal bridge line BRH1, the second horizontal bridge line BRH2, and the third horizontal bridge line BRH3 may be configured as a fourth conductive layer C4 and formed by the same process to be arranged on the same layer, for example, on the fourth insulating layer INS4. However, the present disclosure is not limited thereto. In some embodiments, the first horizontal connection line CNH1, the second horizontal connection line CNH2, and the third horizontal connection line CNH3 and the first horizontal bridge line BRH1, the second horizontal bridge line BRH2, and the third horizontal bridge line BRH3 may be arranged in different layers. For example, as Fig.13 As shown in the figure, the first horizontal connection line CNH1, the second horizontal connection line CNH2 and the third horizontal connection line CNH3 can be configured as a fourth conductive layer C4 set on the fourth insulating layer INS4, and the first horizontal bridge line BRH1, the second horizontal bridge line BRH2 and the third horizontal bridge line BRH3 can be configured as a fifth conductive layer C5 set on the fifth insulating layer INS5.

[0236] In an embodiment, the vertical connection lines, vertical bridge lines, readout lines and data lines extending in the second direction DR2 may be arranged in the same layer. For example, the first vertical connection line CNV1, the second vertical connection line CNV2 and the third vertical connection line CNV3, the first vertical bridge line BRV1, the second vertical bridge line BRV2 and the third vertical bridge line BRV3, the first readout line RX1, the second readout line RX2, the third readout line RX3, the fourth readout line RX4, the fifth readout line RX5, the sixth readout line RX6 and the seventh readout line RX7, and the first data line D1, the second data line D2, the third data line D3, the fourth data line D4, the fifth data line D5 and the sixth data line D6 may be configured as the sixth conductive layer C6 and formed by the same process to be arranged on the same layer, for example, on the sixth insulating layer INS6. The first, second, and third horizontal connection lines CNH1, CNH2, and CNH3 and the first, second, and third horizontal bridge lines BRH1, BRH2, and BRH3 may be configured as a fourth conductive layer C4 disposed on the fourth insulating layer INS4. Fig.12 As shown in FIG. 1 , the third data line D3 may be configured as a sixth conductive layer C6 disposed on the sixth insulating layer INS6 and electrically connected to the third horizontal bridge line BRH3 through a second contact hole CH2 formed through the fifth insulating layer INS5 and the sixth insulating layer INS6 .

[0237] More specifically, refer to Fig. 9, one end of the third horizontal connection line CNH3 may be electrically connected to the third vertical connection line CNV3 through a third contact hole CH3 formed through the fifth insulating layer INS5 and the sixth insulating layer INS6. The other end of the third horizontal connection line CNH3 may be electrically connected to the fifth readout line RX5 through a fourth contact hole CH4 formed through the fifth insulating layer INS5 and the sixth insulating layer INS6. The third vertical connection line CNV3 may be electrically connected to the 1f line LP1f through a first contact CNT1 formed through the third insulating layer INS3, the fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6. The 1f line LP1f may be configured as a second conductive layer C2 disposed on the second insulating layer INS2. In an embodiment, the first line LP1 including the 1f line LP1f may be configured as a second conductive layer C2 or a third conductive layer C3. The second line LP2 may also be configured as a second conductive layer C2 or a third conductive layer C3.

[0238] In the above embodiment, it has been described that the third horizontal connection line CNH3 is configured as the fourth conductive layer C4. However, the present disclosure is not limited thereto. In some embodiments, Fig.11 As shown in , the third horizontal connection line CNH3 may be configured as the fifth conductive layer C5 to be disposed on the fifth insulating layer INS5. One end of the third horizontal connection line CNH3 may be electrically connected to the third vertical connection line CNV3 configured as the sixth conductive layer C6 through a third contact hole CH3 formed through the sixth insulating layer INS6, and the other end of the third horizontal connection line CNH3 may be electrically connected to the fifth readout line RX5 configured as the sixth conductive layer C6 through a fourth contact hole CH4 formed through the sixth insulating layer INS6.

[0239] In some embodiments, the first vertical connection line CNV1, the second vertical connection line CNV2, and the third vertical connection line CNV3, the first vertical bridge line BRV1, the second vertical bridge line BRV2, and the third vertical bridge line BRV3, the first readout line RX1, the second readout line RX2, the third readout line RX3, the fourth readout line RX4, the fifth readout line RX5, the sixth readout line RX6, and the seventh readout line RX7, and the first data line D1, the second data line D2, the third data line D3, the fourth data line D4, the fifth data line D5, and the sixth data line D6 may be configured as a fourth conductive layer C4 and formed by the same process to be disposed on the fourth insulating layer INS4. For example, as Fig.10As shown in , the third vertical connection line CNV3 may be configured as a fourth conductive layer C4, and the third horizontal connection line CNH3 may be configured as a sixth conductive layer C6. The third data line D3, the fourth readout line RX4, the third vertical bridge line BRV3, the fourth data line D4, and the fifth readout line RX5 disposed adjacent to the third vertical connection line CNV3 in the first direction DR1 may be configured as a fourth conductive layer C4 disposed on the fourth insulating layer INS4. The third vertical connection line CNV3 may be electrically connected to the 1f line LP1f through a first contact CNT1 formed through the third insulating layer INS3 and the fourth insulating layer INS4.

[0240] According to the above-described embodiment, the connection line CNL and the bridge line BRL are arranged not to overlap each other, so that coupling capacitance that may occur when the connection line CNL and the bridge line BRL overlap each other can be reduced or prevented, thereby improving the reliability of the display device DD.

[0241] Fig.14 It is shown Figure 8 A schematic plan view of a modification of . Fig.15 It is along Fig.14 Schematic cross-sectional view taken along line III-III' shown in FIG. Fig.16 It is along Fig.14 Schematic cross-sectional view taken along line IV-IV' shown in FIG.

[0242] about Figures 14 to 16 The embodiment shown in , parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0243] refer to Figures 1 to 16 , the dummy line DML may be disposed between the connection line CNL and the bridge line BRL. The dummy line DML may be disposed to be spaced apart from each of the connection line CNL and the bridge line BRL. The dummy line DML, the connection line CNL, and the bridge line BRL may not overlap with each other.

[0244] The dummy lines DML may include a first dummy line DML1, a second dummy line DML2, a third dummy line DML3, a fourth dummy line DML4, and a fifth dummy line DML5. In an embodiment, a DC voltage having a constant level may be applied to each of the first dummy line DML1, the second dummy line DML2, the third dummy line DML3, the fourth dummy line DML4, and the fifth dummy line DML5. For example, a reset voltage (see Figure 4 A “reset voltage VRST” shown in FIG. 1 may be applied to each of the first dummy line DML1, the second dummy line DML2, the third dummy line DML3, the fourth dummy line DML4, and the fifth dummy line DML5, but the present disclosure is not limited thereto. In some embodiments, referring to Figure 4The first initialization power voltage described (see Figure 4 ” shown in the “first initialization power voltage Vint1”), the second initialization power voltage (see Figure 4 The second initialization power voltage Vint2 shown in FIG. 1 and the first power voltage Vint2 shown in FIG. 1 are Figure 4 One of the “first power voltage VDD” shown in FIG. 1 may be applied to each of the first dummy line DML1, the second dummy line DML2, the third dummy line DML3, the fourth dummy line DML4, and the fifth dummy line DML5. Although not directly shown in the drawings, the dummy line DML may be electrically connected to a power driver provided in the pad area PDA to be supplied with a reset voltage VRST from the power driver.

[0245] The first dummy lines DML1 may include a first horizontal dummy line DH1 , a 1a-th vertical dummy line DV1 a (or a first vertical dummy line), and a 1b-th vertical dummy line DV1 b (or a second vertical dummy line).

[0246] The first horizontal dummy line DH1 may extend in the first direction DR1 and be disposed to cross the second area DA2 from the first area DA1 or to cross the first area DA1 from the second area DA2. One end of the first horizontal dummy line DH1 may be electrically connected to the 1a-th vertical dummy line DV1a through the fifth contact hole CH5 in the first area DA1. The other end of the first horizontal dummy line DH1 may be electrically connected to the 1b-th vertical dummy line DV1b through the sixth contact hole CH6 in the second area DA2. The one end of the first horizontal dummy line DH1 may be positioned in the first area DA1, and the other end of the first horizontal dummy line DH1 may be positioned in the second area DA2.

[0247] In a plan view, the first horizontal dummy line DH1 may be disposed between the first horizontal connection line CNH1 and the first horizontal bridge line BRH1. The first horizontal dummy line DH1 to which a reset voltage VRST as a DC voltage having a constant level is applied may be positioned between the first horizontal connection line CNH1 and the first horizontal bridge line BRH1 adjacent to each other in the second direction DR2, thereby preventing a crosstalk phenomenon in which a sensing signal applied to the first horizontal connection line CNH1 changes when a data signal applied to the first horizontal bridge line BRH1 changes. In other words, the first horizontal dummy line DH1 may be used as a shielding member for reducing and preventing a coupling capacitance from occurring between the first horizontal connection line CNH1 and the first horizontal bridge line BRH1. The first horizontal dummy line DH1, the first horizontal bridge line BRH1, and the first horizontal connection line CNH1 may be disposed in the same layer. For example, the first horizontal dummy line DH1, the first horizontal bridge line BRH1, and the first horizontal connection line CNH1 may be configured as a fourth conductive layer C4 disposed on the fourth insulating layer INS4, but the present disclosure is not limited thereto.

[0248] The 1a-th vertical dummy line DV1a may extend in the second direction DR2 and be disposed in the first area DA1. The 1a-th vertical dummy line DV1a may be electrically connected to one end of the first horizontal dummy line DH1 through the fifth contact hole CH5. The 1a-th vertical dummy line DV1a may be disposed to be spaced apart from the first vertical connection line CNV1 and the first data line D1 adjacent to each other in the first direction DR1. The 1a-th vertical dummy line DV1a may be positioned between the first vertical connection line CNV1 and the first data line D1 adjacent to each other in the first direction DR1 to prevent or reduce coupling capacitance occurring between the first vertical connection line CNV1 and the first data line D1.

[0249] The 1ath vertical dummy line DV1a, the first data line D1 and the first vertical connection line CNV1 may be disposed in the same layer. For example, the 1ath vertical dummy line DV1a, the first data line D1 and the first vertical connection line CNV1 may be configured as a sixth conductive layer C6 disposed on the sixth insulating layer INS6, but the present disclosure is not limited thereto.

[0250] The 1b-th vertical dummy line DV1b may extend along the second direction DR2 and be disposed in the second area DA2. The 1b-th vertical dummy line DV1b may be electrically connected to the other end of the first horizontal dummy line DH1 through the sixth contact hole CH6. The 1b-th vertical dummy line DV1b may be disposed to be spaced apart from the sixth data line D6 and the seventh readout line RX7 adjacent to each other in the first direction DR1. The 1b-th vertical dummy line DV1b may be positioned between the sixth data line D6 and the seventh readout line RX7 adjacent to each other in the first direction DR1, thereby reducing or preventing coupling capacitance that may occur between the sixth data line D6 and the seventh readout line RX7. The 1b-th vertical dummy line DV1b, the sixth data line D6, and the seventh readout line RX7 may be configured as a sixth conductive layer C6, but the present disclosure is not limited thereto.

[0251] The second dummy lines DML2 may include a second horizontal dummy line DH2 , a 2ath vertical dummy line DV2 a (or a first vertical dummy line), and a 2bth vertical dummy line DV2 b (or a second vertical dummy line).

[0252] The second horizontal dummy line DH2 may extend in the first direction DR1 and be disposed to cross the second area DA2 from the first area DA1 or to cross the first area DA1 from the second area DA2. One end of the second horizontal dummy line DH2 may be electrically connected to the 2a-th vertical dummy line DV2a through the fifth contact hole CH5 in the first area DA1. The other end of the second horizontal dummy line DH2 may be electrically connected to the 2b-th vertical dummy line DV2b through the sixth contact hole CH6 in the second area DA2. The one end of the second horizontal dummy line DH2 may be positioned in the first area DA1, and the other end of the second horizontal dummy line DH2 may be positioned in the second area DA2.

[0253] In a plan view, the second horizontal dummy line DH2 may be disposed between the first horizontal bridge line BRH1 and the second horizontal connection line CNH2. The second horizontal dummy line DH2 may be disposed between the first horizontal bridge line BRH1 and the second horizontal connection line CNH2 that are adjacent to each other in the second direction DR2 to reduce or prevent coupling capacitance that may occur between the first horizontal bridge line BRH1 and the second horizontal connection line CNH2. The second horizontal dummy line DH2, the first horizontal bridge line BRH1 and the second horizontal connection line CNH2 may include the same material and be disposed in the same layer. For example, the second horizontal dummy line DH2, the first horizontal bridge line BRH1 and the second horizontal connection line CNH2 may be configured as a fourth conductive layer C4, but the present disclosure is not limited thereto.

[0254] The 2a-th vertical dummy line DV2a may extend along the second direction DR2 and be disposed in the first area DA1. The 2a-th vertical dummy line DV2a may be electrically connected to one end of the second horizontal dummy line DH2 through the fifth contact hole CH5. The 2a-th vertical dummy line DV2a may be positioned between the first data line D1 and the second readout line RX2 and disposed to be spaced apart from each of the first data line D1 and the second readout line RX2 in the first direction DR1. In an embodiment, the 2a-th vertical dummy line DV2a may be disposed between the first data line D1 and the second readout line RX2 adjacent to each other in the first direction DR1 to reduce or prevent coupling capacitance that may occur between the first data line D1 and the second readout line RX2. The 2a-th vertical dummy line DV2a, the first data line D1 and the second readout line RX2 may include the same material and be disposed in the same layer. For example, the 2a-th vertical dummy line DV2a, the first data line D1 and the second readout line RX2 may be configured as the sixth conductive layer C6, but the present disclosure may not be limited thereto.

[0255] The 2b-th vertical dummy line DV2b may extend along the second direction DR2 and be disposed in the second area DA2. The 2b-th vertical dummy line DV2b may be electrically connected to the other end of the second horizontal dummy line DH2 through the sixth contact hole CH6. The 2b-th vertical dummy line DV2b may be disposed to be spaced apart from the sixth readout line RX6 and the first vertical bridge line BRV1 adjacent to each other in the first direction DR1. In an embodiment, the 2b-th vertical dummy line DV2b may be disposed between the sixth readout line RX6 and the first vertical bridge line BRV1 adjacent to each other in the first direction DR1 to reduce or prevent coupling capacitance that may occur between the sixth readout line RX6 and the first vertical bridge line BRV1. The 2b-th vertical dummy line DV2b, the sixth readout line RX6, and the first vertical bridge line BRV1 may be configured as a sixth conductive layer C6.

[0256] The third dummy lines DML3 may include a third horizontal dummy line DH3 , a 3a th vertical dummy line DV3 a (or a first vertical dummy line), and a 3b th vertical dummy line DV3 b (or a second vertical dummy line).

[0257] The third horizontal dummy line DH3 may extend in the first direction DR1 and be disposed to cross the second area DA2 from the first area DA1 or to cross the first area DA1 from the second area DA2. One end of the third horizontal dummy line DH3 may be electrically connected to the 3a-th vertical dummy line DV3a through the fifth contact hole CH5 in the first area DA1. The other end of the third horizontal dummy line DH3 may be electrically connected to the 3b-th vertical dummy line DV3b through the sixth contact hole CH6 in the second area DA2. The one end of the third horizontal dummy line DH3 may be positioned in the first area DA1, and the other end of the third horizontal dummy line DH3 may be positioned in the second area DA2.

[0258] In a plan view, the third horizontal dummy line DH3 may be disposed between the second horizontal connection line CNH2 and the second horizontal bridge line BRH2. The third horizontal dummy line DH3 may be disposed between the second horizontal connection line CNH2 and the second horizontal bridge line BRH2 that are adjacent to each other in the second direction DR2 to reduce or prevent coupling capacitance that may occur between the second horizontal connection line CNH2 and the second horizontal bridge line BRH2. The third horizontal dummy line DH3, the second horizontal connection line CNH2, and the second horizontal bridge line BRH2 may include the same material and be disposed in the same layer. For example, the third horizontal dummy line DH3, the second horizontal connection line CNH2, and the second horizontal bridge line BRH2 may be configured as a fourth conductive layer C4, but the present disclosure is not limited thereto.

[0259] The 3a vertical dummy line DV3a may extend along the second direction DR2 and be disposed in the first area DA1. The 3a vertical dummy line DV3a may be electrically connected to one end of the third horizontal dummy line DH3 through the fifth contact hole CH5. The 3a vertical dummy line DV3a may be disposed to be spaced apart from the second data line D2 and the second vertical connection line CNV2 in the first direction DR1. The 3a vertical dummy line DV3a may be positioned between the second data line D2 and the second vertical connection line CNV2, thereby reducing or preventing coupling capacitance that may occur between the second data line D2 and the second vertical connection line CNV2. The 3a vertical dummy line DV3a, the second data line D2 and the second vertical connection line CNV2 may include the same material and be disposed in the same layer. For example, the 3a vertical dummy line DV3a, the second data line D2 and the second vertical connection line CNV2 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0260] The 3b-th vertical dummy line DV3b may extend along the second direction DR2 and be disposed in the second area DA2. The 3b-th vertical dummy line DV3b may be electrically connected to the other end of the third horizontal dummy line DH3 through the sixth contact hole CH6. The 3b-th vertical dummy line DV3b may be positioned between the fifth data line D5 and the sixth readout line RX6 and is disposed to be spaced apart from each of the fifth data line D5 and the sixth readout line RX6 in the first direction DR1. The 3b-th vertical dummy line DV3b may be disposed between the fifth data line D5 and the sixth readout line RX6 adjacent to each other in the first direction DR1 to reduce or prevent coupling capacitance that may occur between the fifth data line D5 and the sixth readout line RX6. The 3b-th vertical dummy line DV3b, the fifth data line D5, and the sixth readout line RX6 may include the same material and be disposed in the same layer. For example, the 3b-th vertical dummy line DV3b, the fifth data line D5, and the sixth readout line RX6 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0261] The fourth dummy lines DML4 may include a fourth horizontal dummy line DH4 , a 4a-th vertical dummy line DV4 a (or a first vertical dummy line), and a 4b-th vertical dummy line DV4 b (or a second vertical dummy line).

[0262] The fourth horizontal dummy line DH4 may extend in the first direction DR1 and be disposed to cross the second area DA2 from the first area DA1 or to cross the first area DA1 from the second area DA2. One end of the fourth horizontal dummy line DH4 may be electrically connected to the 4a-th vertical dummy line DV4a through the fifth contact hole CH5 in the first area DA1. The other end of the fourth horizontal dummy line DH4 may be electrically connected to the 4b-th vertical dummy line DV4b through the sixth contact hole CH6 in the second area DA2. The one end of the fourth horizontal dummy line DH4 may be positioned in the first area DA1, and the other end of the fourth horizontal dummy line DH4 may be positioned in the second area DA2.

[0263] In a plan view, the fourth horizontal dummy line DH4 may be disposed between the second horizontal bridge line BRH2 and the third horizontal connection line CNH3. The fourth horizontal dummy line DH4 may be disposed between the second horizontal bridge line BRH2 and the third horizontal connection line CNH3 adjacent to each other in the second direction DR2 to reduce or prevent coupling capacitance that may occur between the second horizontal bridge line BRH2 and the third horizontal connection line CNH3. The fourth horizontal dummy line DH4, the second horizontal bridge line BRH2, and the third horizontal connection line CNH3 may include the same material and be disposed in the same layer. For example, the fourth horizontal dummy line DH4, the second horizontal bridge line BRH2, and the third horizontal connection line CNH3 may be configured as a fourth conductive layer C4, but the present disclosure is not limited thereto.

[0264] The 4a-th vertical dummy line DV4a may extend along the second direction DR2 and be disposed in the first area DA1. The 4a-th vertical dummy line DV4a may be electrically connected to one end of the fourth horizontal dummy line DH4 through the fifth contact hole CH5. The 4a-th vertical dummy line DV4a may be positioned between the second data line D2 and the third readout line RX3 and be disposed to be spaced apart from each of the second data line D2 and the third readout line RX3 in the first direction DR1. The 4a-th vertical dummy line DV4a may be disposed between the second data line D2 and the third readout line RX3 adjacent to each other in the first direction DR1 to reduce or prevent coupling capacitance that may occur between the second data line D2 and the third readout line RX3. The 4a-th vertical dummy line DV4a, the second data line D2, and the third readout line RX3 may include the same material and be disposed in the same layer. For example, the 4a-th vertical dummy line DV4a, the second data line D2, and the third readout line RX3 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0265] The 4b-th vertical dummy line DV4b may extend along the second direction DR2 and be disposed in the second area DA2. The 4b-th vertical dummy line DV4b may be electrically connected to the other end of the fourth horizontal dummy line DH4 through the sixth contact hole CH6. The 4b-th vertical dummy line DV4b may be positioned between the second vertical bridge line BRV2 and the fifth readout line RX5 that are adjacent to each other in the first direction DR1, thereby reducing or preventing the coupling capacitance that occurs between the second vertical bridge line BRV2 and the fifth readout line RX5. The 4b-th vertical dummy line DV4b, the second vertical bridge line BRV2, and the fifth readout line RX5 may include the same material and be disposed in the same layer. For example, the 4b-th vertical dummy line DV4b, the second vertical bridge line BRV2, and the fifth readout line RX5 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0266] The fifth dummy line DML5 may include a fifth horizontal dummy line DH5 , a 5a th vertical dummy line DV5 a (or a first vertical dummy line), and a 5b th vertical dummy line DV5 b (or a second vertical dummy line).

[0267] The fifth horizontal dummy line DH5 may extend in the first direction DR1 and be disposed to cross the second area DA2 from the first area DA1 or to cross the first area DA1 from the second area DA2. One end of the fifth horizontal dummy line DH5 may be electrically connected to the 5a-th vertical dummy line DV5a through the fifth contact hole CH5 in the first area DA1. The other end of the fifth horizontal dummy line DH5 may be electrically connected to the 5b-th vertical dummy line DV5b through the sixth contact hole CH6 in the second area DA2. The one end of the fifth horizontal dummy line DH5 may be positioned in the first area DA1, and the other end of the fifth horizontal dummy line DH5 may be positioned in the second area DA2.

[0268] In a plan view, the fifth horizontal dummy line DH5 may be disposed between the third horizontal connection line CNH3 and the third horizontal bridge line BRH3. The fifth horizontal dummy line DH5 may be disposed between the third horizontal connection line CNH3 and the third horizontal bridge line BRH3 adjacent to each other in the second direction DR2 to reduce or prevent coupling capacitance that may occur between the third horizontal connection line CNH3 and the third horizontal bridge line BRH3. The fifth horizontal dummy line DH5, the third horizontal bridge line BRH3, and the third horizontal connection line CNH3 may include the same material and be disposed in the same layer. For example, the fifth horizontal dummy line DH5, the third horizontal bridge line BRH3, and the third horizontal connection line CNH3 may be configured as a fourth conductive layer C4, but the present disclosure is not limited thereto.

[0269] The 5a-th vertical dummy line DV5a may extend along the second direction DR2 and be disposed in the first area DA1. The 5a-th vertical dummy line DV5a may be electrically connected to one end of the fifth horizontal dummy line DH5 through the fifth contact hole CH5. The 5a-th vertical dummy line DV5a may be positioned between the third data line D3 and the third vertical connection line CNV3 adjacent to each other in the first direction DR1 to reduce or prevent coupling capacitance that may occur between the third data line D3 and the third vertical connection line CNV3. The 5a-th vertical dummy line DV5a, the third data line D3, and the third vertical connection line CNV3 may include the same material and be disposed in the same layer. For example, the 5a-th vertical dummy line DV5a, the third data line D3, and the third vertical connection line CNV3 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0270] The 5b-th vertical dummy line DV5b may extend along the second direction DR2 and be disposed in the second area DA2. The 5b-th vertical dummy line DV5b may be electrically connected to the other end of the fifth horizontal dummy line DH5 through the sixth contact hole CH6. The 5b-th vertical dummy line DV5b may be positioned between the fourth data line D4 and the fifth readout line RX5, which are adjacent to each other in the first direction DR1, to reduce or prevent coupling capacitance that may occur between the fourth data line D4 and the fifth readout line RX5. The 5b-th vertical dummy line DV5b, the fourth data line D4, and the fifth readout line RX5 may include the same material and be disposed in the same layer. For example, the 5b-th vertical dummy line DV5b, the fourth data line D4, and the fifth readout line RX5 may be configured as the sixth conductive layer C6, but the present disclosure is not limited thereto.

[0271] In an embodiment, the horizontal connection line, the horizontal dummy line and the horizontal bridge line may include the same material and be arranged in the same layer. For example, the first horizontal connection line CNH1, the second horizontal connection line CNH2 and the third horizontal connection line CNH3, the first horizontal dummy line DH1, the second horizontal dummy line DH2, the third horizontal dummy line DH3, the fourth horizontal dummy line DH4 and the fifth horizontal dummy line DH5 and the first horizontal bridge line BRH1, the second horizontal bridge line BRH2 and the third horizontal bridge line BRH3 may be configured as a fourth conductive layer C4 arranged on the fourth insulating layer INS4. However, the present disclosure is not limited thereto. In some embodiments, the horizontal connection line and the horizontal bridge line may be arranged in the same layer, and the horizontal dummy line may be arranged in a different layer from the horizontal connection line and the horizontal bridge line.

[0272] In an embodiment, the vertical connection line, the vertical dummy line and the vertical bridge line may include the same material and be arranged in the same layer. For example, the first vertical connection line CNV1, the second vertical connection line CNV2 and the third vertical connection line CNV3, the 1a vertical dummy line DV1a, the 2a vertical dummy line DV2a, the 3a vertical dummy line DV3a, the 4a vertical dummy line DV4a and the 5a vertical dummy line DV5a, the 1b vertical dummy line DV1b, the 2b vertical dummy line DV2b, the 3b vertical dummy line DV3b, the 4b vertical dummy line DV4b and the 5b vertical dummy line DV5b and the first vertical bridge line BRV1, the second vertical bridge line BRV2 and the third vertical bridge line BRV3 may be configured as a sixth conductive layer C6 arranged on the sixth insulating layer INS6.

[0273] According to the above-described embodiment, the dummy line DML to which the reset voltage VRST having a constant level is applied is provided between the connection line CNL electrically connected to the readout line and the bridge line BRL electrically connected to the data line, thereby reducing or preventing coupling capacitance that may occur between the connection line CNL (or the readout line) and the bridge line BRL (or the data line). Therefore, the reliability of the display device DD can be further improved.

[0274] Fig.17 It is shown Fig.14 A schematic plan view of a modification of . Fig.18 It is along Fig.17 A schematic cross-sectional view taken along line VV' shown in FIG.

[0275] about Fig.17 and Fig.18 The embodiment shown in , parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0276] refer to Figures 1 to 7 , Fig.17 and Fig.18 , each of the first horizontal dummy line DH1, the second horizontal dummy line DH2, the third horizontal dummy line DH3, the fourth horizontal dummy line DH4 and the fifth horizontal dummy line DH5 can be set in a different layer from the lines adjacent to each other in the second direction DR2. For example, the first horizontal dummy line DH1 can be set in a different layer from each of the first horizontal connection line CNH1 and the first horizontal bridge line BRH1. The second horizontal dummy line DH2 can be set in a different layer from each of the first horizontal bridge line BRH1 and the second horizontal connection line CNH2. The third horizontal dummy line DH3 can be set in a different layer from each of the second horizontal connection line CNH2 and the second horizontal bridge line BRH2. The fourth horizontal dummy line DH4 can be set in a different layer from each of the second horizontal bridge line BRH2 and the third horizontal connection line CNH3. The fifth horizontal dummy line DH5 can be set in a different layer from each of the third horizontal connection line CNH3 and the third horizontal bridge line BRH3.

[0277] In an embodiment, the first horizontal connection line CNH1, the first horizontal bridge line BRH1, the second horizontal connection line CNH2, the second horizontal bridge line BRH2, the third horizontal connection line CNH3, and the third horizontal bridge line BRH3 may be configured as a fourth conductive layer C4 disposed on the fourth insulating layer INS4. The first horizontal dummy line DH1, the second horizontal dummy line DH2, the third horizontal dummy line DH3, the fourth horizontal dummy line DH4, and the fifth horizontal dummy line DH5 may be configured as a fifth conductive layer C5 disposed on the fifth insulating layer INS5.

[0278] In the above-described embodiment, the first line electrically connected to the readout line (see Figure 1 ” first line LP1 ” shown in FIG. 1 ) and the first pad portion (see Figure 7 Each of the “first pad portions PDP1” shown in FIG. 1 is positioned at an edge (or outside) in the non-display area NDA and is electrically connected to a second line of the data line (see FIG. 1 ). Figure 1 ” second line LP2 ” shown in FIG. 1 ) and the second pad portion (see Figure 7 Each of the “second pad portions PDP2” shown in the figure is positioned at the center (or inside) of the non-display area NDA. However, the present disclosure is not limited thereto. In some embodiments, each of the second line LP2 electrically connected to the data line and the second pad portion PDP2 may be positioned at an edge (or outside) in the non-display area NDA, and each of the first line LP1 electrically connected to the readout line and the first pad portion PDP1 may be positioned at the center (or inside) of the non-display area NDA. Reference will be made to Fig.19 Describe this.

[0279] Fig.19 It is shown Figure 7 A schematic plan view of a modification of .

[0280] about Fig.19 The embodiment shown in , parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0281] refer to Fig.19 , the display device DD (or display panel DP) may include a substrate SUB, a line portion, and a pad portion PDP.

[0282] The pad portion PDP may include a first pad portion PDP1 and a second pad portion PDP2 positioned in the pad area PDA. The first pad portion PDP1 and the second pad portion PDP2 may be arranged to be spaced apart from each other to be physically and electrically separated from each other in the pad area PDA. For example, the second pad portion PDP2 may be positioned adjacent to an edge of the substrate SUB in the pad area PDA, and the first pad portion PDP1 may be positioned in the center of the pad area PDA.

[0283] The substrate SUB may include a display area DA and a non-display area NDA (see Figure 1). The display area DA may include a first area DA1 and a second area DA2. The first area DA1 may be an area of ​​the display area DA corresponding to the first line, and the second area DA2 may be an area of ​​the display area DA corresponding to the second line. The first area DA1 may be positioned at the center of the display area DA, and the second area DA2 may be positioned at an edge of the display area DA disposed adjacent to the non-display area NDA. For example, the second area DA2 may be positioned at both edges of the first area DA1 positioned at the center of the display area DA.

[0284] The line portion may include a first line electrically connected to a readout line disposed in the first area DA1 through a first contact portion CNT1 and a second line electrically connected to a data line disposed in the second area DA2 through a second contact portion CNT2. The first line may include 1a-1m-th lines LP1a to LP1m, and the second line may include 2a-2m-th lines LP2a to LP2m.

[0285] Some of the 1a-1m-th lines LP1a to LP1m may be electrically connected to the readout lines (e.g., the fourth readout line RX4, the fifth readout line RX5, the sixth readout line RX6, the k-th readout line RXk, the k+1-th readout line RXk+1, and the k+2-th readout line RXk+2) positioned in the first area DA1 through the first contact portion CNT1. For example, the 1b-1b, 1d-1d, 1f-1f, 1h-1h, 1j-1j, and 1l-1l of the 1a-1m-th lines LP1a to LP1m may be electrically connected to the readout lines positioned in the first area DA1.

[0286] Other lines among the 1a-th line LP1a to the 1m-th line LP1m may be electrically connected to the connection line CNL through the first contact portion CNT1. For example, the 1a-th line LP1a, the 1c-th line LP1c, the 1e-th line LP1e, the 1g-th line LP1g, the 1i-th line LP1i, the 1k-th line LP1k, and the 1m-th line LP1m among the 1a-th line LP1a to the 1m-th line LP1m may be electrically connected to the connection line CNL through the first contact portion CNT1. For example, the 1g-th line LP1g may be electrically connected to the k+6-th readout line RXk+6 positioned in the second area DA2 through the connection line CNL electrically connected to the first contact portion CNT1.

[0287] The 1a-th to 1m-th lines LP1a to LP1m may be disposed in one area of ​​the fan-out area FTA corresponding to the first area DA1. For example, the 1a-th to 1m-th lines LP1a to LP1m may be positioned at the center of the fan-out area FTA.

[0288] Some of the 2a lines LP2a to 2m lines LP2m may be electrically connected to the data lines (e.g., the first data line D1, the second data line D2, the third data line D3, the fourth data line D4, the k+3th data line Dk+3, the k+4th data line Dk+4, and the k+5th data line Dk+5) positioned in the second area DA2 through the second contact portion CNT2. For example, the 2a line LP2a, the 2c line LP2c, the 2e line LP2e, the 2g line LP2g, the 2h line LP2h, the 2j line LP2j, and the 2l line LP2l among the 2a lines LP2a to 2m lines LP2m may be electrically connected to the data lines positioned in the second area DA2.

[0289] Other lines among the 2a-th line LP2a to the 2m-th line LP2m may be electrically connected to the bridge line BRL through the second contact portion CNT2. For example, the 2b-th line LP2b, the 2d-th line LP2d, the 2f-th line LP2f, the 2i-th line LP2i, the 2k-th line LP2k, and the 2m-th line LP2m among the 2a-th line LP2a to the 2m-th line LP2m may be electrically connected to the bridge line BRL through the second contact portion CNT2.

[0290] The 2a-th to 2m-th lines LP2a to LP2m may be disposed in one area of ​​the fan-out area FTA corresponding to the second area DA2. For example, the 2a-th to 2m-th lines LP2a to LP2m may be positioned at an edge of the fan-out area FTA.

[0291] For example, 2a to 2g lines LP2g may be positioned adjacent to 1a line LP1a, and 2h to 2m lines LP2h to 2m lines LP2m may be positioned adjacent to 1m line LP1m.

[0292] The connection line CNL may extend from the first area DA1 to the second area DA2. For example, the connection line CNL may be arranged across the boundary between the first area DA1 and the second area DA2, and extend from the center (or inner side) of the display area DA to the edge of the display area DA. The connection line CNL may be electrically connected to the corresponding first line through the first contact portion CNT1. The connection line CNL may include: a vertical connection line arranged in the first area DA1 and extending in the second direction DR2; and a horizontal connection line extending along the first direction DR1 and positioned to cross the second area DA2 from the first area DA1.

[0293] The connection lines CNL may include a first connection line CNL1, a second connection line CNL2, a third connection line CNL3, a fourth connection line CNL4, a fifth connection line CNL5, a sixth connection line CNL6, and a seventh connection line CNL7. Each of the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, the fourth connection line CNL4, the fifth connection line CNL5, the sixth connection line CNL6, and the seventh connection line CNL7 may include a vertical connection line positioned in the first area DA1 and extending in the second direction DR2, and a horizontal connection line extending in the first direction DR1 and positioned to cross the second area DA2 from the first area DA1.

[0294] For example, a vertical connection line of the seventh connection line CNL7 among the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, the fourth connection line CNL4, the fifth connection line CNL5, the sixth connection line CNL6 and the seventh connection line CNL7 may be positioned in the first area DA1 and electrically connected to the 1m-th line LP1m through the first contact portion CNT1. The vertical connection line may be electrically connected to the horizontal connection line of the seventh connection line CNL7 through the third contact hole CH3. The horizontal connection line may be electrically connected to the k+3-th readout line RXk+3 disposed in the second area DA2 through the fourth contact hole CH4. Therefore, the light from the light sensing pixel of the second area DA2 (see FIG. 1 ) received by the k+3-th readout line RXk+3 Figure 1 The sensing signal of the “light sensing pixel PSR” shown in FIG. 1 can be transmitted to the driver through the seventh connection line CNL7 via the 1m-th line LP1m (see FIG. 1 ). Figure 2 "Driver DIC" shown in ).

[0295] The bridging line BRL may extend from the second area DA2 to the first area DA1. For example, the bridging line BRL may be disposed across a boundary between the first area DA1 and the second area DA2 and extend from an edge of the display area DA to the center (or inside) of the display area DA. The bridging line BRL may include a vertical bridging line disposed in the second area DA2 and extending in the second direction DR2 and a horizontal bridging line extending along the first direction DR1 and crossing the first area DA1 from the second area DA2.

[0296] The bridging wires BRL may include a first bridging wire BRL1, a second bridging wire BRL2, a third bridging wire BRL3, a fourth bridging wire BRL4, a fifth bridging wire BRL5, and a sixth bridging wire BRL6. Each of the first bridging wire BRL1, the second bridging wire BRL2, the third bridging wire BRL3, the fourth bridging wire BRL4, the fifth bridging wire BRL5, and the sixth bridging wire BRL6 may include a vertical bridging wire positioned in the second area DA2 and extending in the second direction DR2, and a horizontal bridging wire extending in the first direction DR1 and crossing the first area DA1 from the second area DA2.

[0297] For example, a vertical bridge wire of the first bridge wire BRL1 among the first bridge wire BRL1, the second bridge wire BRL2, the third bridge wire BRL3, the fourth bridge wire BRL4, the fifth bridge wire BRL5, and the sixth bridge wire BRL6 may be positioned in the second area DA2 and electrically connected to the 2b-line LP2b through the second contact portion CNT2. The vertical bridge wire may be electrically connected to the horizontal bridge wire of the first bridge wire BRL1 through the first contact hole CH1. The horizontal bridge wire may be electrically connected to the seventh data line D7 disposed in the first area DA1 through the second contact hole CH2. Therefore, the data signal transmitted from the driver DIC to the 2b-line LP2b may be transmitted to the seventh data line D7 via the first bridge wire BRL1.

[0298] In an embodiment, the first to seventh connection lines CNL1 to CNL7 and the first to sixth bridge lines BRL1 to BRL6 may be disposed in the display area DA without overlapping each other.

[0299] According to the above-described embodiment, the first pad portion PDP1 electrically connected to the readout line and the second pad portion PDP2 electrically connected to the data line can be separated from each other in the pad area PDA to be set to be spaced apart from each other. For example, the first pad portion PDP1 can be positioned at the center of the pad area PDA to correspond to the first area DA1 of the display area DA without any intervening second pad, and the second pad portion PDP2 can be positioned at both edges of the pad area PDA to correspond to the second area DA2 of the display area DA without any intervening first pad. The phenomenon that the sensing signal of the light sensing pixel PSR transmitted to the driver DIC through the first pad portion PDP1 is affected by the data signal transmitted to the data line via the second pad portion PDP2 can be reduced or prevented. The phenomenon that the data signal transmitted to the data line via the second pad portion PDP2 is affected by the sensing signal of the light sensing pixel PSR transmitted to the driver DIC through the first pad portion PDP1 can be reduced or prevented.

[0300] According to the above-described embodiment, the 1a lines LP1a to 1m lines LP1m electrically connected to the readout lines and the 2a lines LP2a to 2m lines LP2m electrically connected to the data lines may be separated from each other in the fan-out area FTA to be set to be spaced apart from each other. For example, the 2a lines LP2a to 2m lines LP2m may be positioned at both edges of the fan-out area FTA to correspond to the second area DA2 of the display area DA without any intervening first lines, and the 1a lines LP1a to 1m lines LP1m may be positioned at the center of the fan-out area FTA to correspond to the first area DA1 of the display area DA without any intervening second lines. The phenomenon that the sensing signal of the light sensing pixel PSR transmitted to the first pad portion PDP1 through each of the 1a lines LP1a to 1m lines LP1m is affected by the data signal transmitted to the data line through each of the 2a lines LP2a to 2m lines LP2m may be reduced or prevented. In addition, the phenomenon that the data signal transmitted to the data line through each of the 2a line LP2a to 2m line LP2m is affected by the sensing signal of the light sensing pixel PSR transmitted to the first pad portion PDP1 through each of the 1a line LP1a to 1m line LP1m can be reduced or prevented.

[0301] Fig. 20 is a schematic block diagram showing an electronic device 1000 according to an embodiment of the present disclosure. Fig.21 It shows that Fig. 20 The electronic device 1000 shown in FIG. 1 is a schematic diagram of an example in which the electronic device 1000 is implemented as a smart phone. Fig. 22 It shows that Fig. 20 1 is a schematic diagram of an example in which the electronic device 1000 shown in FIG. 1 is implemented as a tablet PC.

[0302] refer to Figure 20 to Figure 22 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 and Figure 7 In addition, the electronic device 1000 may also include several ports that can communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc. or communicate with other systems. In an embodiment, as shown in FIG. Fig.21 As shown in , the electronic device 1000 may be implemented as a smart phone. In another embodiment, as Fig. 22As shown in , the electronic device 1000 can be implemented as a tablet PC. However, this is merely illustrative, and the electronic device 1000 is not limited to the above example. For example, the electronic device 1000 can be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a notebook computer, or a head-mounted display device, etc.

[0303] The processor 1010 can perform specific calculations or tasks. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, or an application processor. The processor 1010 can be connected to other components through an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0304] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device) and / or a volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device).

[0305] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a compact disk read only memory (CD-ROM), and the like.

[0306] The I / O device 1040 may include an input device such as a keyboard, a keypad, a touch screen, or a mouse, and an output device such as a speaker or a printer. In some embodiments, the display device 1060 may be included in the I / O device 1040 .

[0307] The power supply 1050 may supply power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0308] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. The display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but the present disclosure is not limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0309] According to the present disclosure, a display device can be provided, in which a first line (or a first fan-out line) electrically connected to a read-out line and a second line (or a second fan-out line) electrically connected to a data line are not arranged adjacent to each other in a non-display area but are arranged separately from each other, so that parasitic capacitance that may be generated between the first line and the second line can be reduced, thereby improving the reliability of the display device.

[0310] According to the present disclosure, a display device can be provided, in which a connecting line electrically connected to a readout line and a bridging line electrically connected to a data line are designed not to overlap each other in a display area, so that parasitic capacitance that may be generated between the connecting line and the bridging line can be reduced, thereby improving the reliability of the display device.

[0311] According to the present disclosure, a display device can be provided, in which a dummy line to which a DC voltage having a constant level is applied is arranged between a connecting line and a bridging line in a display area, so that parasitic capacitance that may be generated between the connecting line and the bridging line can be further reduced, thereby improving the reliability of the display device.

[0312] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: A substrate, comprising a display area and a non-display area, wherein the display area comprises a first area and a second area; a plurality of data lines, positioned in the first area and the second area; a plurality of readout lines, positioned in the first region and the second region, the plurality of readout lines being spaced apart from the plurality of data lines, respectively; a plurality of connection lines extending from the first region to the second region, the plurality of connection lines being electrically connected to corresponding readout lines disposed in the second region among the plurality of readout lines; and a plurality of bridge lines extending from the second region to the first region, the plurality of bridge lines being electrically connected to corresponding data lines disposed in the first region among the plurality of data lines, The plurality of connecting lines and the plurality of bridging lines do not overlap with each other.

2. The display device according to claim 1, wherein: The display device further includes: a plurality of first lines positioned in a fan-out area disposed in the non-display area, the plurality of first lines being electrically connected to the plurality of connection lines, respectively; a plurality of second lines located in the fan-out region, the plurality of second lines being electrically connected to the plurality of bridge lines, respectively; and a pad portion positioned in a pad region provided in the non-display region, The pad portion includes: a first pad portion including a plurality of first pads electrically connected to the plurality of first lines respectively; and a second pad portion including a plurality of second pads electrically connected to the plurality of second lines respectively, and The plurality of first lines are disposed at both sides of the plurality of second lines, and the first pad portion is disposed at both sides of the second pad portion.

3. The display device according to claim 2, wherein: A plurality of readout lines disposed in the first region among the plurality of readout lines are directly connected to corresponding first pads among the plurality of first pads, and Among the plurality of data lines, a plurality of data lines disposed in the second region are directly connected to corresponding second pads among the plurality of second pads.

4. The display device according to claim 1, wherein: The display device further includes: a plurality of first lines positioned in a fan-out area disposed in the non-display area, the plurality of first lines being electrically connected to the plurality of connection lines, respectively; a plurality of second lines located in the fan-out region, the plurality of second lines being electrically connected to the plurality of bridge lines, respectively; and a pad portion positioned in a pad region provided in the non-display region, wherein the pad portion includes a first pad portion electrically connected to the plurality of first lines and a second pad portion electrically connected to the plurality of second lines, and The plurality of second lines are disposed at both sides of the plurality of first lines, and the second pad portions are disposed at both sides of the first pad portions.

5. The display device according to claim 1, wherein: The plurality of connection lines include: a plurality of horizontal connection lines extending from the first region to the second region along a first direction; and a plurality of vertical connection lines positioned in the first region and extending in a second direction intersecting the first direction, and The plurality of bridge lines include: a plurality of horizontal bridge lines extending from the second region to the first region along the first direction; and a plurality of vertical bridge lines located in the second region and extending in the second direction.

6. The display device according to claim 5, wherein: The plurality of vertical connection lines, the plurality of vertical bridge lines, the plurality of data lines, and the plurality of readout lines are disposed in a same layer.

7. The display device according to claim 5, wherein: A plurality of data lines disposed in the first region among the plurality of data lines are electrically connected to the plurality of vertical bridge lines through the plurality of horizontal bridge lines, respectively, and Among the plurality of readout lines, the plurality of readout lines disposed in the second region are electrically connected to the plurality of vertical connection lines through the plurality of horizontal connection lines, respectively.

8. The display device according to claim 7, wherein: An insulating layer is disposed between one ends of the plurality of horizontal bridge lines and the plurality of vertical bridge lines and between the other ends of the plurality of horizontal bridge lines and the plurality of data lines disposed in the first region, and The insulating layer is disposed between one ends of the horizontal connection lines and the vertical connection lines and between the other ends of the horizontal connection lines and the readout lines disposed in the second region.

9. The display device according to claim 8, wherein: The plurality of one ends of the plurality of horizontal bridge lines are electrically connected to the plurality of vertical bridge lines through a plurality of first contact holes formed through the insulating layer, and the plurality of other ends of the plurality of horizontal bridge lines are electrically connected to the plurality of data lines disposed in the first region among the plurality of data lines through a plurality of second contact holes formed through the insulating layer, and Among them, the multiple one ends of the multiple horizontal connection lines are electrically connected to the multiple vertical connection lines through a plurality of third contact holes formed through the insulating layer, and the multiple other ends of the multiple horizontal connection lines are electrically connected to the multiple readout lines arranged in the second region among the multiple readout lines through a plurality of fourth contact holes formed through the insulating layer.

10. The display device according to claim 5, wherein: In the first region, the plurality of vertical connection lines, the plurality of readout lines, and the plurality of data lines are arranged to be spaced apart from each other, wherein, in the second region, the plurality of vertical bridge lines, the plurality of readout lines, and the plurality of data lines are arranged to be spaced apart from each other, and Wherein, the plurality of horizontal connection lines and the plurality of horizontal bridge lines are arranged to be spaced apart from each other.

11. The display device according to claim 5, wherein: The plurality of horizontal connection lines and the plurality of vertical connection lines are arranged in different layers, and The plurality of horizontal bridge lines and the plurality of vertical bridge lines are arranged in different layers.

12. The display device according to claim 5, wherein: The plurality of horizontal connection lines and the plurality of horizontal bridge lines are arranged in the same layer, and Wherein, the plurality of vertical connection lines and the plurality of vertical bridge lines are arranged in the same layer.

13. The display device according to claim 5, wherein: The plurality of horizontal connection lines and the plurality of horizontal bridge lines are disposed in different layers.

14. The display device according to claim 5, wherein: The display device further includes a plurality of dummy lines, wherein the plurality of dummy lines are respectively arranged between the plurality of connection lines and the plurality of bridge lines in the display area. Wherein, a DC signal with a constant level is applied to the plurality of dummy lines.

15. The display device according to claim 14, wherein: The plurality of imaginary lines include: a plurality of horizontal imaginary lines extending from the first area to the second area along the first direction; a plurality of first vertical imaginary lines positioned in the first region, the plurality of first vertical imaginary lines extending in the second direction; and A plurality of second vertical dummy lines are positioned in the second region, and the plurality of second vertical dummy lines extend in the second direction.

16. The display device according to claim 15, wherein: The plurality of horizontal dummy lines are respectively arranged between the plurality of horizontal bridge lines and the plurality of horizontal connection lines, and The plurality of vertical dummy lines are respectively arranged between the plurality of vertical bridging lines and the plurality of vertical connecting lines, and the plurality of vertical dummy lines include the plurality of first vertical dummy lines and the plurality of second vertical dummy lines.

17. The display device according to claim 16, wherein: The plurality of horizontal dummy lines, the plurality of horizontal bridge lines and the plurality of horizontal connection lines are arranged in the same layer, and Wherein, the plurality of vertical dummy lines, the plurality of vertical bridge lines and the plurality of vertical connection lines are arranged in the same layer.

18. The display device according to claim 16, wherein: The plurality of vertical dummy lines, the plurality of vertical bridge lines, and the plurality of vertical connection lines are arranged in the same layer, and The plurality of horizontal dummy lines, the plurality of horizontal bridge lines, and the plurality of horizontal connection lines are arranged in different layers.

19. The display device according to claim 1, wherein: The display device also includes a plurality of sub-pixels and a plurality of light-sensing pixels, wherein the plurality of sub-pixels are positioned in the display area and each include a light-emitting element that emits light, and the plurality of light-sensing pixels are positioned in the display area and each include a light-receiving element that outputs a sensing signal corresponding to the light.

20. An electronic device, wherein: The electronic device comprises: a processor configured to provide input image data to a display device; and The display device is configured to display an image based on the input image data, Wherein, the display device comprises: A substrate, comprising a display area and a non-display area, wherein the display area comprises a first area and a second area; a plurality of data lines, positioned in the first area and the second area; a plurality of readout lines positioned in the first region and the second region, the plurality of readout lines being spaced apart from the plurality of data lines; a plurality of connection lines extending from the first region to the second region, the plurality of connection lines being electrically connected to corresponding readout lines disposed in the second region among the plurality of readout lines; a plurality of bridge lines extending from the second region to the first region, the plurality of bridge lines being electrically connected to corresponding data lines disposed in the first region among the plurality of data lines; and a plurality of dummy lines, respectively arranged between the plurality of connection lines and the plurality of bridge lines in the display area, Wherein, a DC signal with a constant level is applied to the plurality of dummy lines.

Images