Display device and electronic device including the same

Abstract

A display device and an electronic device are provided. The display device includes a substrate, a circuit layer, and an element layer. The sub-region of the substrate includes a bending region. The display area of the substrate includes emission areas, a non-emission area between the emission areas, and a light sensing area in a portion of the non-emission area. The element layer includes a light emitting element in the emission region and a light sensing element in the light sensing region. The circuit layer includes a data bending line disposed in the bending area and electrically connected to the data line, and a readout bending line disposed in the bending area and electrically connected to the readout line. The bending region includes a first wiring group region in which two or more of the data bending lines are disposed, and a second wiring group region in which two or more of the readout bending lines are disposed.

Description

Technical Field

[0001] The present disclosure relates to a display device and an electronic device including the display device. Background Art

[0002] As an information-oriented society develops, there are increasing demands for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] In order to be applied to various electronic devices, the display device additionally incorporates various input functions in addition to the function of displaying an image.

[0004] For example, the display device may incorporate a touch sensing function that senses the location of a touch on the screen based on changes in capacitance. Alternatively, the display device may incorporate a scanning function that is used to detect the curvature of an object in contact with the screen based on differences in the amount of light reflected from the object. Summary of the invention

[0005] The display device may include light emitting elements respectively arranged in areas corresponding to emission areas arranged in a display area for realizing an image display function, light emitting pixel drivers respectively electrically connected to the light emitting elements, and a display driving circuit for transmitting data signals of the light emitting pixel drivers through data lines.

[0006] When the display device incorporates a scanning function, the display device may further include a scanning driving circuit that receives a light sensing signal of a light sensing element that senses the amount of light through a readout line.

[0007] The substrate of the display device may include a main region having a display region, and a sub-region protruding from one side of the main region. The sub-region may include a curved region configured to be curved, a first sub-region between the main region and the curved region, and a second sub-region overlapping the main region through the curved region having a curved shape.

[0008] A display driving circuit and a scan driving circuit may be disposed in the second sub-region.

[0009] The second sub-area may have a limited width, so the pad line connected to the scan drive circuit may overlap the pad line connected to the display drive circuit. Therefore, there is a problem that unnecessary parasitic capacitance and signal coupling defects may occur, resulting in signal distortion in the pad line connected to the scan drive circuit. Therefore, it is difficult to improve the accuracy of the scanning function.

[0010] In view of the above, aspects of the present disclosure provide a display device which can improve the accuracy of a scanning function by reducing signal distortion in a pad line while incorporating the scanning function.

[0011] According to aspects of the present disclosure, a display device is provided, comprising: a substrate including a main area and a sub-area protruding from one side of the main area, the main area including a display area in which a light-emitting element and a light-sensing element are arranged and a non-display area arranged around the display area, a curved area configured to be curved is arranged in the sub-area; and a circuit layer arranged on the substrate. The circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements, respectively; light-sensing pixel drivers electrically connected to the light-sensing elements, respectively; data lines electrically connected to the light-emitting pixel drivers, the data lines including data line groups, each data line group including at least two data lines; and readout lines electrically connected to the light-sensing pixel drivers, the readout lines including readout line groups, each readout line group including at least two readout lines. The readout lines in one readout line group arranged in the curved area can be arranged adjacent to each other without data lines being interposed between adjacent readout lines.

[0012] The readout line group and the data line group may be arranged side by side in a first direction intersecting a direction in which the sub-region extends from the main region. The data line and the readout line may extend in a second direction in the bending region. The readout line group may be spaced apart from the data line group in the first direction.

[0013] The circuit layer further includes a DC power bending line disposed in the bending region. In a plan view, each of the readout lines overlaps at least a portion of the DC power bending line in the bending region.

[0014] The data line, the readout line and the DC power bending line are included in the same conductive layer. In a plan view, each of the readout lines is disposed between the DC power bending lines in the bending region.

[0015] The readout line is disposed on an insulating layer covering the data line and the DC power flex line.

[0016] In a plan view, each of the sense lines is disposed between the DC power bending lines in the bending region.

[0017] At least one of the DC power bending lines is disposed between the sense lines in the bending region in a plan view.

[0018] In a plan view, a separation region provided between the sense lines overlaps with the DC power bending line in the bending region.

[0019] In a plan view, one of the sense lines overlaps with a separation region between two of the DC power bending lines in the bending region, and overlaps with a portion of each of the two DC power bending lines.

[0020] Each of the sense lines also overlaps with at least one DC power bending line disposed between the two DC power bending lines.

[0021] The circuit layer further includes touch sensor lines arranged in the bending area, extending in the second direction and electrically connected to the touch sensor layer, respectively, the touch sensor lines including touch sensor line groups, each touch sensor line group including at least two touch sensor lines. The touch sensor line groups are arranged side by side with the data line group and the readout line group in the first direction.

[0022] The circuit layer includes a first semiconductor layer disposed on a substrate, a first inorganic insulating layer covering the first semiconductor layer, a first conductive layer disposed on the first inorganic insulating layer, a second inorganic insulating layer covering the first conductive layer, a second conductive layer disposed on the second inorganic insulating layer, a third inorganic insulating layer covering the second conductive layer, a second semiconductor layer disposed on the third inorganic insulating layer, a fourth inorganic insulating layer covering the second semiconductor layer, a third conductive layer disposed on the fourth inorganic insulating layer, a fifth inorganic insulating layer covering the third conductive layer, a fourth conductive layer disposed on the fifth inorganic insulating layer, a first planarization layer covering the fourth conductive layer, a fifth conductive layer disposed on the first planarization layer, a second planarization layer covering the fifth conductive layer, a sixth conductive layer disposed on the second planarization layer, and a third planarization layer covering the sixth conductive layer. The fifth conductive layer includes a data bending line and a DC power bending line. The readout bending line is disposed in the fifth conductive layer or the sixth conductive layer.

[0023] The display device further includes a bending hole and a bank covering the bending hole, the bending hole being provided in an area corresponding to the bending area and being formed through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer. The bank includes a first bank layer which is the same layer as the first planarizing layer and covers the bending hole, a second bank layer which is the same layer as the second planarizing layer and covers the first bank layer, and a third bank layer which is the same layer as the third planarizing layer and is provided on the second bank layer. The data line and the DC power bending line are provided on the first bank layer and covered by the second bank layer.

[0024] According to aspects of the present disclosure, an electronic device is provided, comprising: a display device configured to emit light for displaying an image; and a cover window and a bracket, the cover window and the bracket facing each other and configured to accommodate the display device. The display device comprises: a substrate, comprising a main area and a sub-area protruding from one side of the main area, the main area comprising a display area in which an emission area is arranged and a non-display area arranged around the display area; a circuit layer, arranged on the substrate; an element layer, arranged on the circuit layer; an encapsulation layer, arranged on the element layer; and a touch sensor layer, arranged on the encapsulation layer. The sub-area comprises a curved area configured to be curved, a first sub-area arranged between one side of the curved area and the main area, and a second sub-area connected to the other side of the curved area. The display area also comprises a light sensing area arranged in a portion of the non-emitting area, the non-emitting area being a separation area between the emitting areas. The element layer comprises light emitting elements respectively arranged in the emitting area, and light sensing elements respectively arranged in the light sensing area. The circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements, respectively; light-sensing pixel drivers electrically connected to the light-sensing elements, respectively; data lines arranged in the display area and electrically connected to the light-emitting pixel drivers, readout lines arranged in the display area and electrically connected to the light-sensing pixel drivers, data bending lines arranged in the bending area and electrically connected to the data lines, respectively; readout bending lines arranged in the bending area and electrically connected to the readout lines, respectively; and touch sensor bending lines arranged in the bending area, extending in the second direction, and electrically connected to the touch sensor lines of the touch sensor layer, respectively. The bending area includes a first wiring group area in which at least two data bending lines are arranged, a second wiring group area in which at least two readout bending lines are arranged, and a third wiring group area in which at least two touch sensor bending lines are arranged.

[0025] The circuit layer also includes a DC power line that is arranged in the non-display area and transmits DC power of different voltage levels, and a DC power bending line that is arranged in the bending area and electrically connected to the DC power line. In the second wiring group area, two or more of the DC power bending lines are arranged. The first wiring group area, the second wiring group area, and the third wiring group area are arranged side by side in a first direction that intersects with the direction in which the sub-area protrudes from the main area. The data bending line, the readout bending line, and the DC power bending line extend in a second direction that intersects with the first direction and are arranged between the first sub-area and the second sub-area. The readout bending line is spaced apart from the data bending line in the first direction. Each of the readout bending lines overlaps at least a portion of the separation area between the DC power bending lines.

[0026] The data bending line, the readout bending line and the DC power bending line are included in the same conductive layer. In a plan view, each of the readout bending lines is disposed between the DC power bending lines.

[0027] In a plan view, the sense bending line is disposed on an insulating layer covering the data bending line and the DC power bending line.

[0028] Each of the sense bending lines is disposed between the DC power bending lines.

[0029] The separation area between the sense bending lines overlaps with the DC power bending line. One of the sense bending lines overlaps with the separation area between two of the DC power bending lines and overlaps with a portion of each of the two DC power bending lines.

[0030] In a plan view, each of the sense bending lines also overlaps with at least one DC power bending line disposed between the two DC power bending lines.

[0031] The display device according to the embodiment includes a substrate, a circuit layer, an element layer, an encapsulation layer and a touch sensor layer. The substrate includes a main area and a sub-area protruding from one side of the main area, and the sub-area includes a curved area configured to be curved. The element layer includes light-emitting elements respectively arranged in the emission area of ​​the display area and light-sensing elements respectively arranged in the light-sensing area of ​​the display area. The circuit layer includes light-emitting pixel drivers respectively electrically connected to the light-emitting elements, light-sensing pixel drivers respectively electrically connected to the light-sensing elements, data lines electrically connected to the light-emitting pixel drivers, readout lines electrically connected to the light-sensing pixel drivers, data curved lines arranged in the curved area and respectively electrically connected to the data lines, and readout curved lines arranged in the curved area and respectively electrically connected to the readout lines. The curved area includes a first wiring group area in which at least two data curved lines are arranged and a second wiring group area in which at least two readout curved lines are arranged.

[0032] Thus, according to an embodiment, the data bending line is arranged in a first wiring group area of ​​the bending region, and the readout bending line is arranged in a second wiring group area different from the first wiring group area of ​​the bending region. Therefore, since the readout bending line can be spaced apart from the data bending line, it is possible to alleviate a defect in which a light sensing signal of the readout bending line is distorted by a data signal of the data bending line.

[0033] In addition, according to an embodiment, the circuit layer may further include a direct current (DC) power bending line that is disposed in the bending region and transmits DC power, such as the first power and the second power. The DC power bending line may be disposed in the second wiring group region together with the readout bending line.

[0034] In this manner, a light sensing signal for reading out the bending line can be stably maintained by the DC power, thereby reducing distortion in the light sensing signal for reading out the bending line.

[0035] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0037] Figure 1 is a perspective view showing an electronic device according to one embodiment;

[0038] Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in ;

[0039] Figure 3 It is shown Figure 2 A plan view of a display device;

[0040] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA';

[0041] Figure 5 It is shown Figure 2 A plan view of a main area and sub-areas of a display device shown in ;

[0042] Figure 6 It is shown Figure 5 a layout diagram of part B;

[0043] Figure 7 It is shown Figure 6 A diagram of the scanning function of the light sensing area shown in FIG.

[0044] Figure 8 It is shown Figure 4 The block diagram of the circuit layer;

[0045] Fig. 9 yes Figure 8 The equivalent circuit diagram of the light-emitting pixel driver shown in;

[0046] Fig.10 yes Figure 8 An equivalent circuit diagram of a light sensing pixel driver shown in ;

[0047] Fig.11 It is shown Figure 4 A plan view of a touch sensor layer;

[0048] Fig.12 It is shown Fig.11 an enlarged view of a portion D of;

[0049] Fig.13 It is along Fig.12A cross-sectional view taken along line EE';

[0050] Fig.14 The first embodiment shows Figure 5 a plan view of section C;

[0051] Fig.15 It is along Fig.14 A cross-sectional view taken along line F-F';

[0052] Fig.16 According to the first embodiment, Fig.14 A cross-sectional view taken along line G-G';

[0053] Fig.17 According to the second embodiment, Fig.14 A cross-sectional view taken along line G-G';

[0054] Fig.18 The third embodiment shows Figure 5 a plan view of section C;

[0055] Fig.19 It is along Fig.18 A cross-sectional view taken along line G-G';

[0056] Fig. 20 The fourth embodiment shows Figure 5 a plan view of section C;

[0057] Fig.21 It is along Fig. 20 A cross-sectional view taken along line G-G';

[0058] Fig. 22 The fifth embodiment shows Figure 5 a plan view of section C;

[0059] Fig.23 It is along Fig. 22 A cross-sectional view taken along line G-G';

[0060] Fig.24 The sixth embodiment is shown in FIG. Figure 5 a plan view of section C;

[0061] Fig.25 According to the sixth embodiment, Fig.24 A cross-sectional view taken along line G-G'; and

[0062] Fig.26 According to the seventh embodiment, Fig.24 A cross-sectional view taken along line G-G'. DETAILED DESCRIPTION

[0063] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0064] In order to describe the embodiments of the present disclosure, some of parts that are not related to the description may not be provided.

[0065] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0066] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and / or vice versa. In addition, the term "overlap" may include layers, stacks, facing or facing, extending across, covering or partially covering, or any other suitable terms as will be understood and appreciated by those of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from" or "set side by side with" or "offset from" and any other suitable equivalents as will be understood and appreciated by those of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0067] For ease of description, the spatially relative terms "below", "below", "lower", "above", "upper" may be used herein to describe the relationship between one element or assembly and another element or assembly as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to also include different orientations of the device in use or operation. For example, in the case where the device shown in the figure is flipped, a device located "below" or "below" another device can be placed "above" the other device. Therefore, the illustrative term "below" can include both the lower position and the upper position. The device may also be oriented in other directions, and therefore the spatially relative terms may be interpreted differently depending on the orientation.

[0068] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "including," "has," "have," "having," "includes," and / or "comprising" are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0069] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate description and illustration thereof. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be named in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0070] As used herein, the term "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of a particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0071] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a combined or separate sense and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0072] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an ideal or overly formal meaning unless explicitly defined in the specification.

[0073] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0074] Figure 1 is a perspective view showing an electronic device according to one embodiment. Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in FIG.

[0075] refer to Figure 1 The electronic device 10 according to one embodiment is a device having a function of displaying an image in a display area. The electronic device 10 can provide portability. For example, the electronic device 10 may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0076] However, the electronic device 10 according to one embodiment is not limited to a portable electronic device, and may be a large device such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device.

[0077] The electronic device 10 according to one embodiment may include a cover window 11 and a lower cover 12, which are provided as a housing to protect the display device 100 (see Figure 2 ).

[0078] refer to Figure 2 The electronic device 10 may further include a display device 100 , a bracket 13 , and a main circuit board 14 accommodated between the cover window 11 and the lower cover 12 .

[0079] The display device 100 may include a main area MA including a display area DA displaying an image and a non-display area NDA around the display area DA, and a sub area SBA protruding from one side of the main area MA.

[0080] The display device 100 may also include a display driving circuit 200 arranged in the sub-area SBA, a display circuit board 300 attached to one side of the sub-area SBA, a touch driving circuit 400 and a scan driving circuit 500 mounted on the display circuit board 300, and a cable 600 extending from one side of the display circuit board 300.

[0081] In the present specification, the first direction DR1 may be a direction parallel to the short side of the electronic device 10 in a plan view, that is, a horizontal direction of the electronic device 10. The second direction DR2 may be a direction parallel to the long side of the electronic device 10 in a plan view, that is, a vertical direction of the electronic device 10. The third direction DR3 may be a thickness direction of the electronic device 10.

[0082] The electronic device 10 may have a rectangular shape in a plan view. For example, in a plan view, the electronic device 10 may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the electronic device 10 is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0083] The cover window 11 may be disposed on the display device 100 to cover the top surface of the display device 100. The cover window 11 may serve to protect the top surface of the display device 100.

[0084] The cover window 11 may include a transparent light-transmitting portion and an opaque light-blocking portion.

[0085] The light transmitting portion may overlap the display area DA of the display device 100 in the third direction DR3 , and the light blocking portion may overlap the non-display area NDA of the display device 100 in the third direction DR3 .

[0086] The cover window 11 may include a top surface portion forming a top surface of the electronic device 10, a left surface portion forming a left side surface of the electronic device 10, and a right surface portion forming a right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and the right surface portion thereof may extend from the right side of the top surface portion.

[0087] Each of the top, left, and right surface portions of the cover window 11 may include a light-transmitting portion and a light-blocking portion.

[0088] The light-transmitting portion of the cover window 11 may be disposed on most of each of the top, left, and right surface portions of the cover window 11 .

[0089] The light blocking portion of the cover window 11 can be set at the upper edge and lower edges of the top surface portion of the cover window 11, the upper edge, left edge and lower edge of the left surface portion of the cover window 11, and the upper edge, right edge and lower edge of the right surface portion of the cover window 11.

[0090] The display device 100 may be disposed under the cover window 11 .

[0091] That is, the cover window 11 may be provided on the display device 100 .

[0092] The display device 100 may include a main area MA and a sub area SBA protruding from one side of the main area MA.

[0093] The main area MA may include a display area DA displaying an image and a non-display area NDA which is a peripheral area of ​​the display area DA.

[0094] The display area DA may be disposed in most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0095] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be an edge area of ​​the main area MA.

[0096] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2.

[0097] The length of the sub-region SBA in the first direction DR1 may be less than or equal to the length of the main region MA in the first direction DR1. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2, but is not limited thereto.

[0098] Since a portion of the sub-area SBA is bendable, a portion of the sub-area SBA may overlap with the main area MA in the third direction DR3 .

[0099] The display driving circuit 200 may be disposed in the sub-area SBA.

[0100] The display device 100 may include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from the left side of the top surface portion, and the right surface portion of the display device 100 may extend from the right side of the top surface portion.

[0101] Each of the top, left, and right surface portions of the display device 100 may include a display area DA and a non-display area NDA.

[0102] The display area DA may be disposed on most of each of the top surface portion, the left surface portion, and the right surface portion of the display device 100 .

[0103] The non-display area NDA may be disposed at upper and lower edges of a top surface portion of the display device 100 , upper, left and lower edges of a left surface portion of the display device 100 , and upper, right and lower edges of a right surface portion of the display device 100 .

[0104] The display driving circuit 200 may be mounted in the sub-area SBA of the display device 100 , and the display circuit board 300 may be attached thereto.

[0105] One end of the display circuit board 300 may be attached to a pad disposed on a lower edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0106] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0107] Based on the control signal and the power voltage provided from the display circuit board 300, the display driving circuit 200 can respectively Figure 8 ) the data signal Vdata (see Fig. 9 ) is output to the light emitting pixel driver EPD of the display area DA (see Figure 8 ).

[0108] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted in the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, this is only an example, and one embodiment is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0109] According to one embodiment, the touch driving circuit 400 and the scan driving circuit 500 may also be installed in the sub-area SBA of the display device 100 .

[0110] Alternatively, if Figure 2 As shown in , the touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0111] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 (see FIG. Figure 4 ).

[0112] The touch driving circuit 400 may apply a touch driving signal to the first driving line TL1 (see FIG. Fig.11 ) and the second driving line TL2 (see Fig.11), and based on the sensing line RL (see Fig.11 ) to detect the change of the charge of the capacitor to determine whether there is a user's touch or proximity. The user's touch means that an object such as a user's finger or a pen is in direct contact with the top surface of the cover window 11 disposed on the touch sensor layer 150. The user's proximity means that an object such as a pen or a user's finger hovers above the top surface of the cover window 11. The touch drive circuit 400 can output touch data including the user's touch coordinates to the main processor 15.

[0113] The scan driving circuit 500 may be electrically connected to a light sensing pixel driver DPD (see FIG. Figure 8 ).

[0114] The scanning driving circuit 500 can periodically collect the light sensing area ODA (see FIG. Figure 6 ) in the light sensing element PD (see Fig.10 In addition, based on the collected light sensing signals, the scan drive circuit 500 can output scan data including the shape of the object in contact with the screen to the main processor 15 by detecting the difference in the amount of light reflected by the object in contact with the screen.

[0115] The bracket 13 may be disposed under the display device 100 .

[0116] The bracket 13 may include plastic, metal, or both. The bracket 13 may include a first camera hole CMH1 into which the camera 16 is inserted, a battery hole BH into which the battery 18 is disposed, and a cable hole CAH through which a cable 600 connected to the display circuit board 300 passes.

[0117] The main circuit board 14 and the battery 18 may be disposed under the bracket 13. The main circuit board 14 may be a printed circuit board or a flexible printed circuit board.

[0118] The main circuit board 14 may include a main processor 15, a camera 16, and a main connector 17. The main processor 15 may be formed as an integrated circuit.

[0119] The camera 16 may be disposed on both the top and bottom surfaces of the main circuit board 14 , the main processor 15 may be disposed on the top surface of the main circuit board 14 , and the main connector 17 may be disposed on the bottom surface of the main circuit board 14 .

[0120] The main processor 15 may control all functions of the electronic device 10 .

[0121] For example, the main processor 15 may output digital video data to the display driving circuit 200 through the display circuit board 300 so that the display device 100 displays an image. In addition, the main processor 15 may receive touch data including the touch coordinates of the user from the touch driving circuit 400, determine whether the user has touched or approached, and then perform an operation corresponding to the user's touch input or approach input. For example, the main processor 15 may perform an operation indicated by an icon touched by the user or run an application.

[0122] In addition, the main processor 15 may receive scan data from the scan driving circuit 500 and perform an operation or execute an application program based on whether the scan data is valid.

[0123] The main processor 15 may be an application processor formed of an integrated circuit, a central processing unit, or a system on chip.

[0124] The camera 16 may process image frames of still images or videos obtained by an image sensor in a camera mode and output them to the main processor 15 .

[0125] The cable 600 passing through the cable hole CAH of the bracket 13 may be connected to the main connector 17. Thus, the main circuit board 14 may be electrically connected to the display circuit board 300.

[0126] The battery 18 may be disposed so as not to overlap with the main circuit board 14 in the third direction DR3. The battery 18 may overlap with the battery hole BH of the bracket 13 in the third direction DR3.

[0127] In addition, the main circuit board 14 may also be equipped with a mobile communication module capable of transmitting and receiving radio signals with at least one of a base station, an external terminal, and a server in a mobile communication network. The radio signal may include various types of data according to the transmission and reception of a voice signal, a video call signal, or a text / multimedia message.

[0128] The lower cover 12 may be disposed below the main circuit board 14 and the battery 18. The lower cover 12 may be fastened to the bracket 13. The lower cover 12 may cover the upper side surface, the lower side surface, and the bottom surface of the electronic device 10. The lower cover 12 may include plastic, metal, or both plastic and metal.

[0129] The lower cover 12 may include a second camera hole CMH2 through which the bottom surface of the camera 16 is exposed. The position of the camera 16 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera 16 are not limited to Figure 2 The embodiment shown in .

[0130] Next, a display device 100 according to one embodiment will be described.

[0131] Figure 3 It is shown Figure 2 A plan view of a display device. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'. Figure 5 It is shown Figure 2 A plan view of the main area and sub-areas of the display device shown in FIG. Figure 6 It is shown Figure 5 Layout diagram of part B.

[0132] Figure 3 and Figure 4 The display device 100 is shown when the display device 100 is bent in the sub-area SBA.

[0133] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micron or nanometer light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0134] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be flexibly formed so that it can be curved, bent, folded, or rolled.

[0135] refer to Figure 3 , at least one surface of the display device 100 includes a main area MA, and light for displaying an image is emitted from the main area MA.

[0136] The main area MA includes an emission area EA (see Figure 6 ) and a non-display area NDA arranged around the display area DA.

[0137] In a plan view, the display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined curvature or may be right angles. The planar shape of the display area DA is not limited to a rectangular shape and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0138] The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0139] refer to Figure 4 , the display device 100 further includes a sub-area SBA protruding from one side of the main area MA.

[0140] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA to one side in the second direction DR2 .

[0141] Since a portion of the sub-area SBA is bent, a portion of the sub-area SBA may be disposed on the rear surface of the display device 100 .

[0142] According to one embodiment, a display device 100 includes a substrate 110 having a main area MA and a sub-area SBA, a circuit layer 120 disposed on the substrate 110 , an element layer 130 disposed on the circuit layer 120 , an encapsulation layer 140 disposed on the element layer 130 , and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0143] The display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150 in order to reduce reflection of external light.

[0144] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that may be bent, folded, or rolled.

[0145] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0146] refer to Figure 5 , the substrate 110 includes a main area MA and a sub-area SBA.

[0147] The main area MA includes a display area DA located at the center and a non-display area NDA provided at the periphery of the display area DA.

[0148] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2.

[0149] The sub-region SBA includes a curved bending area BA, a first sub-region SB1 disposed between one side of the bending area BA and the main area MA, and a second sub-region SB2 connected to the other side of the bending area BA.

[0150] The display driving circuit 200 , the touch driving circuit 400 , and the scan driving circuit 500 may be disposed in the second sub-region SB2 .

[0151] In the second direction DR2, one side of the second sub-region SB2 may be connected to the bending area BA, and on the other side of the second sub-region SB2, a signal pad SPD connected to the display circuit board 300 may be arranged.

[0152] refer to Figure 6 , the display area DA includes the emission areas EA, the non-emission areas NEA as separation areas between the emission areas EA, and the light sensing areas ODA disposed in portions of the non-emission areas NEA.

[0153] Each of the emission areas EA may be an area that emits light in a wavelength band corresponding to one of two or more different colors having brightness corresponding to an image signal.

[0154] Each of the emission areas EA may have a rhombus planar shape or a rectangular planar shape. However, this is merely an example, and the planar shapes of the plurality of emission areas EA according to one embodiment are not limited to Figure 6 That is, in a plan view, the plurality of emission areas EA may have a polygonal shape such as a diamond shape or a hexagonal shape in addition to a rectangular shape, a circular shape, or an elliptical shape.

[0155] The emission area EA may include a first emission area EA1 that emits light of a first color having a predetermined wavelength band, a second emission area EA2 that emits light of a second color having a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color having a wavelength band lower than the wavelength band of the second color.

[0156] For example, the first color may be red having a wavelength band of about 600 nm to about 750 nm, the second color may be green having a wavelength band of about 480 nm to about 560 nm, and the third color may be blue having a wavelength band of about 370 nm to about 460 nm. However, this is only an example, and the wavelength bands of the first color, the second color, and the third color according to one embodiment of the present specification are not limited thereto.

[0157] Since the emission area EA includes a first emission area EA1, a second emission area EA2 and a third emission area EA3, each of the unit pixels UPX can be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2 and one or more third emission areas EA3 adjacent to each other in the emission area EA.

[0158] Each of the unit pixels UPX may be a unit for displaying various colors of light including white. That is, various colors of light displayed by the unit pixel UPX may be implemented as a mixture of light emitted from two or more emission areas EA included in each unit pixel UPX.

[0159] In the case where the first color of the first emission area EA1, the second color of the second emission area EA2, and the third color of the third emission area EA3 are red, green, and blue, respectively, the third emission area EA3 may have a greater width than the first emission area EA1, and the second emission area EA2 may have a smaller width than the first emission area EA1. However, this is only an example, and the width of each of the emission areas EA is not limited to Figure 6 Width shown in .

[0160] In addition, the first emission area EA1 and the third emission area EA3 may be alternately arranged in the first direction DR1 or the second direction DR2. In addition, the second emission area EA2 may be arranged side by side in the first direction DR1 or the second direction DR2. The second emission area EA2 may be disposed between the first emission area EA1 and the third emission area EA3 in the first direction DR1.

[0161] In this case, each of the unit pixels UPX may include one first emission area EA1, one third emission area EA3, and two second emission areas EA2 disposed adjacent to each other. However, this is only an example, and the arrangement pattern of the components of the unit pixel UPX and the emission areas EA according to one embodiment is not limited to Figure 6 The content shown in .

[0162] According to one embodiment, the display area DA includes a light sensing area ODA disposed in a portion of the non-emission area NEA.

[0163] For example, the light sensing area ODA may be disposed between the second emission areas EA2 having a relatively small width in the second direction DR2. In each of the first direction DR1 and the second direction DR2, one or more emission areas EA may be disposed between the light sensing areas ODA.

[0164] Reference again Figure 8 The circuit layer 120 on the substrate 110 includes circuit layers corresponding to the emission areas EA (see Figure 6 ) of the light-emitting pixel driver EPD (see Figure 8 ), respectively corresponding to the light sensing area ODA (see Figure 6 ) of the light sensing pixel driver DPD (see Figure 8 ), the data line DL electrically connected to the light-emitting pixel driver EPD (see Figure 8), and a readout line ROL electrically connected to the light sensing pixel driver DPD (see Figure 8 ).

[0165] The element layer 130 includes light emitting elements LE corresponding to the emission areas EA (see Fig. 9 ) and the light sensing elements PD corresponding to the light sensing areas ODA (see Fig.10 ).

[0166] The encapsulation layer 140 may cover the element layer 130, and may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0167] The touch sensor layer 150 may be disposed on the encapsulation layer 140, and may be disposed in a region corresponding to the main area MA. The touch sensor layer 150 may include a touch electrode for sensing a touch of a person or an object.

[0168] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 , and interfaces thereof, and this is to prevent degradation of visibility of an image due to external light reflection.

[0169] The cover window 11 of the electronic device 10 may be disposed on the polarizing layer 160. The cover window 11 may be attached to the polarizing layer 160 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

[0170] The cover window 11 may be made of an inorganic material such as glass or an organic material such as plastic or polymer material.

[0171] Due to the cover window 11 , the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 may be protected from electrical and physical impacts on the display surface.

[0172] The display device 100 according to one embodiment may include a light sensing element PD disposed in the light sensing area ODA, and thus may provide a scanning function to detect a shape of an object in contact with a screen.

[0173] Figure 7 It is shown Figure 6 The scanning function of the light sensing area is shown in the diagram.

[0174] refer to Figure 7, the fingerprint of the user's finger FG in contact with the cover window 11 includes ridges RID and valleys VAL disposed between the ridges RID. The ridges RID in the fingerprint are in contact with the cover window 11. However, the valleys VAL in the fingerprint are spaced apart from the cover window 11. That is, the top surface of the cover window 11 facing the valleys VAL is in contact with the air.

[0175] The light emitted from the emission area EA may be reflected by the user's finger FG in contact with the cover window 11 and detected by the light sensing element PD of the light sensing area ODA. However, since the refractive index of the finger FG is different from that of air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0176] Therefore, based on the difference in the amount of light incident on the light sensing element PD in the light sensing area ODA, the ridges RID and valleys VAL of the fingerprint can be derived, so that the fingerprint pattern of the finger FG can be detected.

[0177] Figure 8 It is shown Figure 4 Block diagram of the circuit layer.

[0178] refer to Figure 8 The circuit layer 120 includes light-emitting pixel drivers EPD respectively arranged in areas corresponding to the emission areas EA of the display area DA, light-sensing pixel drivers DPD respectively arranged in areas corresponding to the light-sensing areas ODA of the display area DA, data lines DL arranged in the display area DA and electrically connected to the light-emitting pixel drivers EPD, and readout lines ROL arranged in the display area DA and electrically connected to the light-sensing pixel drivers DPD.

[0179] The display device 100 according to one embodiment may include a method for outputting a data signal Vdata (see FIG. 1 ) to each of the light emitting pixel drivers EPD. Fig. 9 ), a display driving circuit 200 for collecting light sensing signals from a light sensing pixel driver DPD, a gate driving circuit 101 for providing one or more gate signals to a light emitting pixel driver EPD and a light sensing pixel driver DPD, and an emission control signal EC (see Fig. 9 )'s emission control circuit 102, a power supply unit 700 that provides various DC power voltages to the light emitting pixel driver EPD and the light sensing pixel driver DPD, and a timing controller 800 that controls the driving timing.

[0180] The timing controller 800 receives an image signal provided from the outside of the display device 100. The timing controller 800 may output the image data DATA and the data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101, and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate the scan control signal SCS and the emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through the scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through the emission control driving line.

[0181] The display driving circuit 200 may convert the image data DATA into analog data voltages and output them to the data lines DL.

[0182] The gate driving circuit 101 may generate a gate signal in response to a scan control signal SCS and sequentially output the gate signal to the gate lines GL1 to GLn (n is a natural number greater than 1).

[0183] The power supply unit 700 may provide various types of DC power required to drive the light emitting pixel driver EPD and the light sensing pixel driver DPD.

[0184] For example, the DC power provided by the power supply unit 700 may include a first power ELVDD (see Fig. 9 ) and the second power ELVSS (see Fig. 9 ), and a first initialization voltage VINT (see Fig. 9 ).

[0185] In addition, the DC power provided by the power supply unit 700 may also include a reset voltage Vrst for resetting (see Fig.10 ), and a second initialization voltage VAINT (see Fig.10 ).

[0186] The emission control circuit 102 may respond to the emission control drive signal ECS by converting the emission control signal EC (see Fig. 9 ) are sequentially output to the emission control line ECL. The emission control signal EC of the emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. On the other hand, the emission control circuit 102 may not be provided separately from the gate driving circuit 101, and may be incorporated into the gate driving circuit 101.

[0187] The scan driving circuit 500 may be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD.

[0188] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD, and the scan driving circuit 500 may detect the shape of the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0189] The scan driving circuit 500 can generate scan data according to the size of the photocurrent detected by the light sensing element PD and transmit it to the main processor 15, and the main processor 15 can compare the scan data with the reference data and run the application based on whether the scan data matches the user's fingerprint.

[0190] Fig. 9 yes Figure 8 The equivalent circuit diagram of the light-emitting pixel driver is shown in FIG.

[0191] refer to Fig. 9 The circuit layer 120 includes light emitting pixel drivers EPD corresponding to the emission areas EA, and data lines DL configured to transmit data signals Vdata to the light emitting pixel drivers EPD. The light emitting pixel drivers EPD of the circuit layer 120 are electrically connected to the light emitting elements LE of the element layer 130, respectively.

[0192] The circuit layer 120 may further include a first power line VDL transmitting the first power ELVDD to the light emitting pixel driver EPD, and an initialization voltage line VIL transmitting the first initialization voltage VINT to the light emitting pixel driver EPD.

[0193] In addition, the circuit layer 120 may also include a scan write line GWL that transmits a scan write signal GW to the light-emitting pixel driver EPD, a scan initialization line GIL that transmits a scan initialization signal GI to the light-emitting pixel driver EPD, an emission control line ECL that transmits an emission control signal EC to the light-emitting pixel driver EPD, and a gate control line GCL that transmits a gate control signal GC to the light-emitting pixel driver EPD.

[0194] refer to Fig. 9 One of the light-emitting pixel drivers EPD of the circuit layer 120 may include a driving transistor DT that generates a driving current to drive a light-emitting element LE electrically connected to the one light-emitting pixel driver EPD. In addition, the one light-emitting pixel driver EPD may also include two or more transistors ST1 to ST6 electrically connected to the driving transistor DT and at least one capacitor (first capacitor) PC1.

[0195] The anode electrode 131 of the light emitting element LE (see Fig.13 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (see Fig.13 ) may be electrically connected to a second power line VSL that transmits a second power ELVSS having a voltage level lower than that of the first power ELVDD.

[0196] The light emitting element LE may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. Alternatively, the light emitting element LE may be an inorganic light emitting element including a light emitting layer made of an inorganic semiconductor. Alternatively, the light emitting element LE may be a quantum dot light emitting element having a quantum dot light emitting layer. Alternatively, the light emitting element LE may be a micro light emitting diode.

[0197] The parasitic capacitor Cel is connected in parallel with the light emitting element LE between the anode electrode 131 and the cathode electrode 134 .

[0198] The driving transistor DT is connected in series to the light emitting element LE between the first power line VDL and the second power line VSL. That is, the first electrode (e.g., source electrode) of the driving transistor DT can be electrically connected to the first power line VDL through the fifth transistor ST5. In addition, the second electrode (e.g., drain electrode) of the driving transistor DT can be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor ST6.

[0199] The first electrode of the driving transistor DT may be electrically connected to the data line DL through the second transistor ST2 .

[0200] The gate electrode of the driving transistor DT may be electrically connected to the first power line VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the driving transistor DT and the first power line VDL.

[0201] Therefore, the potential of the gate electrode of the driving transistor DT can be maintained by the first capacitor PC1.

[0202] Therefore, when the data signal Vdata of the data line DL is transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2 , a voltage difference corresponding to the data signal Vdata and the first power ELVDD may be generated between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT.

[0203] In this case, when a voltage difference between a gate electrode of the driving transistor DT and a first electrode of the driving transistor DT (ie, a gate-source voltage difference) is greater than or equal to a threshold voltage, the driving transistor DT may be turned on.

[0204] Subsequently, when the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving transistor DT can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Therefore, a drain-source current corresponding to the data signal Vdata can be generated by the turned-on driving transistor DT, and the drain-source current can be provided as a driving current of the light emitting element LE.

[0205] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0206] The second transistor ST2 may be connected between the first electrode of the driving transistor DT and the data line DL.

[0207] The first transistor ST1 may be connected between a gate electrode of the driving transistor DT and a second electrode of the driving transistor DT.

[0208] The first transistor ST1 may include a plurality of sub-transistors connected in series. For example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

[0209] A first electrode of the first sub-transistor ST11 may be connected to the gate electrode of the driving transistor DT, a second electrode of the first sub-transistor ST11 may be connected to a first electrode of the second sub-transistor ST12, and a second electrode of the second sub-transistor ST12 may be connected to a second electrode of the driving transistor DT.

[0210] In this way, it is possible to prevent the potential of the gate electrode of the driving transistor DT from changing due to the leakage current caused by the non-conducting first transistor ST1 .

[0211] A gate electrode of each of the second transistor ST2 , the first sub-transistor ST11 , and the second sub-transistor ST12 may be connected to the scan write line GWL.

[0212] Therefore, when the scan write signal GW is transmitted through the scan write line GWL, the second transistor ST2 , the first sub-transistor ST11 , and the second sub-transistor ST12 may be turned on.

[0213] In this case, the data signal Vdata may be transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2 .

[0214] In addition, the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT may have the same potential through the turned-on first sub-transistor ST11 and the turned-on second sub-transistor ST12 .

[0215] Therefore, the driving transistor DT may be turned on.

[0216] The third transistor ST3 may be connected between the gate electrode of the driving transistor DT and the initialization voltage line VIL.

[0217] The third transistor ST3 may include a plurality of sub-transistors connected in series. For example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

[0218] A first electrode of the third sub-transistor ST31 may be connected to the gate electrode of the driving transistor DT, a second electrode of the third sub-transistor ST31 may be connected to a first electrode of the fourth sub-transistor ST32, and a second electrode of the fourth sub-transistor ST32 may be connected to the initialization voltage line VIL.

[0219] In this way, it is possible to prevent the potential of the gate electrode of the driving transistor DT from changing due to the leakage current caused by the non-conducting third transistor ST3.

[0220] A gate electrode of each of the third and fourth sub-transistors ST31 and ST32 may be connected to the scan initialization line GIL.

[0221] Therefore, when the scan initialization signal GI is transmitted through the scan initialization line GIL, the third and fourth sub-transistors ST31 and ST32 are turned on, and thus, the potential of the gate electrode of the driving transistor DT may be initialized to the first initialization voltage VINT of the initialization voltage line VIL.

[0222] The fourth transistor ST4 may be connected between the anode electrode of the light emitting element LE and the initialization voltage line VIL.

[0223] A gate electrode of the fourth transistor ST4 may be connected to the gate control line GCL.

[0224] Therefore, when the gate control signal GC is transmitted through the gate control line GCL, the fourth transistor ST4 may be turned on.

[0225] In this case, the potential of the anode electrode of the light emitting element LE may be initialized to the first initialization voltage VINT of the initialization voltage line VIL through the turned-on fourth transistor ST4 .

[0226] Therefore, it is possible to prevent the light emitting element LE from being driven by the current remaining in the anode electrode.

[0227] The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL.

[0228] The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LE.

[0229] A gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line ECL.

[0230] Therefore, when the emission control signal EC is transmitted through the emission control line ECL, the fifth transistor ST5 and the sixth transistor ST6 are turned on, and thus, the drain-source current of the driving transistor DT may be provided as a driving current of the light emitting element LE.

[0231] although Fig. 9 The driving transistor DT and the first transistor ST1 to the sixth transistor ST6 included in the light-emitting pixel driver EPD are shown as P-type metal oxide semiconductor field effect transistors (MOSFET), but it should be noted that the light-emitting pixel driver EPD of one embodiment is not limited to Fig. 9 That is, at least one of the driving transistor DT and the first to sixth transistors ST1 to ST6 included in the light emitting pixel driver EPD according to one embodiment may be an N-type MOSFET.

[0232] Fig.10 yes Figure 8 The equivalent circuit diagram of the light sensing pixel driver is shown in FIG.

[0233] refer to Fig.10 The circuit layer 120 may further include a reset control line RSTL electrically connected to the light sensing pixel driver DPD.

[0234] Each of the light-sensing pixel drivers DPD may include two or more sensing transistors LT1 , LT2 , and LT3 , and may be electrically connected between each light-sensing element PD and the scan driving circuit 500 .

[0235] Each of the light-sensing pixel drivers DPD may include a first sensing transistor LT1 , a second sensing transistor LT2 , and a third sensing transistor LT3 .

[0236] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a light sensing signal.

[0237] The light sensing element PD may be a photodiode including a sensing anode electrode, a sensing cathode electrode, and a photoelectric conversion layer disposed between the sensing anode electrode and the sensing cathode electrode.

[0238] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a PN type or PIN type inorganic material. Alternatively, the light sensing element PD may also be an organic photodiode including an electron donor material that generates donor ions and an electron acceptor material that generates acceptor ions.

[0239] When photocharges generated in the photoelectric conversion layer move in response to incident light, a photocurrent may be generated between the sensing anode electrode and the sensing cathode electrode.

[0240] As an example, photocharges generated in the photoelectric conversion layer by light incident on the light sensing element PD may accumulate in the first node N1. In this case, the voltage of the first node N1 electrically connected to the sensing cathode electrode may decrease. When the voltage of the first node N1 decreases below the threshold voltage of the first sensing transistor LT1, the first sensing transistor LT1 may be turned on. When the light sensing element PD and the readout line ROL are connected to the first node N1 by turning on the first sensing transistor LT1 and the third sensing transistor LT3, the sensing voltage may be detected by the readout line ROL.

[0241] The first sensing transistor LT1 may be turned on by the voltage of the first node N1 to connect the second initialization voltage line VIL2 to the second electrode of the third sensing transistor LT3 .

[0242] The first sensing transistor LT1 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the first node N1 input to a gate electrode thereof.

[0243] On the other hand, the first electrode of the first sensing transistor LT1 is shown to be connected to the second initialization voltage line VIL2 , but is not limited thereto, and may be connected to the first power line VDL or the initialization voltage line VIL.

[0244] The second sensing transistor LT2 may be turned on by the reset control signal RST of the reset control line RSTL to connect the first node N1 to the reset voltage line VRL. Therefore, the potential of the first node N1 may be reset.

[0245] The third sensing transistor LT3 may be turned on by the scanning write signal GW of the scanning write line GWL to connect the second electrode of the first sensing transistor LT1 and the readout line ROL.

[0246] An active layer of each of the first, second, and third sensing transistors LT1, LT2, and LT3 may include any one of polysilicon, amorphous silicon, and an oxide semiconductor.

[0247] For example, the active layer of each of the first sensing transistor LT1 and the third sensing transistor LT3 may be made of polysilicon, and the active layer of the second sensing transistor LT2 may be made of an oxide semiconductor. In this case, the first sensing transistor LT1 and the third sensing transistor LT3 may be formed of a P-type MOSFET, and the second sensing transistor LT2 may be formed of an N-type MOSFET.

[0248] Fig.11 It is shown Figure 4 A plan view of the touch sensor layers. Fig.12 It is shown Fig.11 An enlarged view of portion D of FIG. Fig.13 It is along Fig.12 A cross-sectional view taken along line EE'.

[0249] Fig.11 A capacitive touch sensor layer 150 is shown. In this case, the touch drive circuit 400 can sense touch based on changes in capacitance. However, Fig.11 This is just an example for simple description, and the touch sensor layer 150 according to one embodiment is not limited to Fig.11 The example shown in .

[0250] To simplify the description, Fig.11 Only some of the components of touch sensor layer 150 are shown.

[0251] refer to Fig.11 , the touch sensor layer 150 may be disposed in the main area MA. The touch sensor layer 150 may include a touch sensing area TSA for sensing a user's touch and a touch peripheral area TPA around the touch sensing area TSA.

[0252] The touch sensing area TSA has a width wider than the display area DA and may be similar to the display area DA. Therefore, the touch peripheral area TPA which is the periphery of the touch sensing area TSA may be similar to the non-display area NDA which is the periphery of the display area DA.

[0253] For example, the touch sensing area TSA may overlap the display area DA and an edge of the non-display area NDA that contacts the display area DA. In this case, the touch peripheral area TPA may overlap the rest of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0254] The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE, which are arranged in a matrix configuration in the touch sensing area TSA and generate mutual capacitance, and touch sensor lines TSL, which are arranged in the touch peripheral area TPA.

[0255] The sensor electrodes SE may include driving electrodes TE (touch driving electrodes) to which a driving signal is applied and sensing electrodes RE (receiving electrodes) through which a voltage charged in a mutual capacitance is detected.

[0256] The touch sensor line TSL may include a first driving line TL1 , a second driving line TL2 , and a sensing line RL.

[0257] Each of the first and second driving lines TL1 and TL2 may be electrically connected to two or more driving electrodes TE extending in the second direction DR2 among the driving electrodes TE.

[0258] The first driving line TL1 may extend from one side (eg, a lower side) of the touch sensing area TSA to the sub-area SBA in the second direction DR2 .

[0259] The second driving line TL2 can extend from the other side (e.g., the upper side) of the touch sensing area TSA opposite to the one side to the sub-area SBA in the second direction DR2 through a portion of the touch peripheral area TPA, and the portion of the touch peripheral area TPA contacts the other side (e.g., the left side) of the touch sensing area TSA in the first direction DR1.

[0260] The sensing line RL may be electrically connected to two or more sensing electrodes RE extending in the first direction DR1 among the sensing electrodes RE.

[0261] The sensing electrodes RE may extend in parallel in the first direction DR1. The sensing electrodes RE adjacently disposed in the first direction DR1 may be electrically connected to each other through protrusions in the first direction DR1.

[0262] The driving electrodes TE may extend in parallel in the second direction DR2. Adjacent driving electrodes TE in the second direction DR2 may be connected to each other via bridge electrodes BE in the second direction DR2 (see FIG. Fig.12 ) are electrically connected to each other.

[0263] Each of the driving electrode TE and the sensing electrode RE may have a shape surrounding the dummy electrode DE disposed at the center thereof.

[0264] Each of the dummy electrodes DE may be spaced apart from the driving electrode TE and / or the sensing electrode RE surrounding it. The dummy electrode DE may be maintained in a floating state.

[0265] although Fig.11 It is shown that each of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE has a rhombus planar shape, but one embodiment is not limited to Fig.11For example, the planar shape of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE may be a quadrilateral shape other than a rhombus shape, a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0266] The display device 100 according to one embodiment may include a signal pad SPD disposed in the second sub-region SB2 and connected to the display circuit board 300 .

[0267] refer to Fig.12 The driving electrode TE and the sensing electrode RE may be formed of the same conductive layer and may be spaced apart from each other. The bridging electrode BE may be provided as a conductive layer different from that of the driving electrode TE and the sensing electrode RE.

[0268] although Fig.12 The bridging electrode BE having a shape including at least one bent portion is shown, but the shape of the bridging electrode BE according to one embodiment is not limited to Fig.12 The shapes shown in .

[0269] The driving electrodes TE adjacent in the second direction DR2 may be electrically connected to each other through two or more bridge electrodes BE In this way, the reliability of the electrical connection between the driving electrodes TE may be improved.

[0270] although Fig.12 It is shown that two bridging electrodes BE parallel to each other are disposed between the driving electrodes TE adjacent to each other in the second direction DR2, but one embodiment is not limited to Fig.12 The example shown in .

[0271] The bridge electrode BE may be electrically connected to the driving electrode TE through the touch contact hole TCNT1 .

[0272] The driving electrode TE, the sensing electrode RE, and the bridging electrode BE may have a grid or mesh structure in a plan view. The dummy electrode DE may also have a grid or mesh structure in a plan view. In this way, since the overlapping width of the driving electrode TE, the sensing electrode RE, the dummy electrode DE, and the bridging electrode BE in the emission area EA can be reduced, the reduction in light emission efficiency caused by the driving electrode TE, the sensing electrode RE, the dummy electrode DE, and the bridging electrode BE can be reduced.

[0273] although Fig.12 It is shown that each of the emission areas EA has a rhombus or rectangular planar shape, but the planar shape of the emission area EA according to one embodiment is not limited to Fig.12 That is, each of the emission areas EA may have a planar shape such as a polygonal shape other than a quadrangular shape, a circular shape, or an elliptical shape.

[0274] refer to Fig.13 According to one embodiment, a display device 100 may include a substrate 110, a circuit layer 120 disposed on the substrate 110, an element layer 130 disposed on the circuit layer 120, an encapsulation layer 140 disposed on the element layer 130, and a touch sensor layer 150 disposed on the encapsulation layer 140.

[0275] The circuit layer 120 may include light emitting pixel drivers EPD respectively disposed in regions corresponding to the emission areas EA, and light sensing pixel drivers DPD respectively disposed in regions corresponding to the light sensing areas ODA.

[0276] Each of the light emitting pixel drivers EPD may include a driving transistor DT and two or more transistors ST1 to ST6 electrically connected to the driving transistor DT.

[0277] Each of the light-sensing pixel drivers DPD may include two or more sensing transistors LT1 , LT2 , and LT3 .

[0278] According to one embodiment, the driving transistor DT, the two or more transistors ST1 to ST6 , and the two or more sensing transistors LT1 , LT2 , and LT3 may each include a semiconductor layer having a channel region, a source region, and a drain region, and a gate electrode overlapping the channel region of the semiconductor layer.

[0279] The circuit layer 120 may include a buffer layer 121 disposed on the substrate 110, a first semiconductor layer disposed on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer, a second semiconductor layer disposed on the first interlayer insulating layer 124, and a third gate insulating layer 124 covering the second semiconductor layer. 5. A third gate conductive layer arranged on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer, a first source / drain conductive layer arranged on the second interlayer insulating layer 126, a first planarizing layer 127 covering the first source / drain conductive layer, a second source / drain conductive layer arranged on the first planarizing layer 127, a second planarizing layer 128 covering the second source / drain conductive layer, a third source / drain conductive layer arranged on the second planarizing layer 128, and a third planarizing layer 129 covering the third source / drain conductive layer.

[0280] In one example, the driving transistor DT, two or more transistors ST1 to ST6, and some of the two or more sensing transistors LT1, LT2 and LT3 (e.g., the driving transistor DT) may each include a channel region CADT formed by a first semiconductor layer on a buffer layer 121, a source region SADT and a drain region DADT, and a gate electrode GEDT disposed on a first gate insulating layer 122.

[0281] In addition, the driving transistor DT, two or more transistors ST1 to ST6, and some other transistors among the two or more sensing transistors LT1, LT2 and LT3 (for example, the third transistor ST3) can each be provided as an N-type MOSFET, which includes a channel region CA3 formed by the second semiconductor layer on the first interlayer insulating layer 124, a source region SA3 and a drain region DA3, and a gate electrode GE3 on the third gate insulating layer 125.

[0282] For example, among the driving transistor DT, two or more transistors ST1 to ST6 and two or more sensing transistors LT1, LT2 and LT3, the first transistor ST1 and the third transistor ST3 of the light-emitting pixel driver EPD and the second sensing transistor LT2 of the light-sensing pixel driver DPD can each be provided as an N-type MOSFET including a second semiconductor layer.

[0283] The buffer layer 121 serves to block oxygen or moisture having passed through the substrate 110 , and may include an inorganic insulating material.

[0284] In addition, the buffer layer 121 may cover a light blocking layer (not shown) disposed on the substrate 110 to reduce leakage current of the first semiconductor layer caused by light.

[0285] The buffer layer 121 may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0286] Each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the first interlayer insulating layer 124 may be formed of at least one inorganic layer (i.e., an inorganic insulating layer). For example, each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the first interlayer insulating layer 124 may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0287] Each of the first planarization layer 127 and the second planarization layer 128 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0288] Each of the first semiconductor layer and the second semiconductor layer may include one of semiconductor materials of polycrystalline silicon, amorphous silicon, and an oxide semiconductor.

[0289] For example, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0290] In each of the driving transistor DT, the two or more transistors ST1 to ST6, and the two or more sensing transistors LT1, LT2, and LT3, source and drain regions may be connected to both sides of the channel region, respectively. The source and drain regions may have higher conductivity than the channel region.

[0291] In each of the driving transistor DT, the two or more transistors ST1 to ST6 , and the two or more sensing transistors LT1 , LT2 , and LT3 , a gate electrode overlaps a channel region.

[0292] The first capacitor PC1 of the light emitting pixel driver EPD may be disposed as an overlap region between the gate electrode GEDT of the driving transistor DT and the capacitor electrode CAE. The capacitor electrode CAE may be formed of a second gate conductive layer on the second gate insulating layer 123 covering the first gate conductive layer.

[0293] The anode electrode 131 of the element layer 130 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through the first anode connection electrode ANDE1 , the second anode connection electrode ANDE2 , and the third anode connection electrode ANDE3 .

[0294] The first anode connection electrode ANDE1 may be formed of a first source / drain conductive layer on the second interlayer insulating layer 126 .

[0295] The first anode connection electrode ANDE1 may be electrically connected to the drain area DA6 of the sixth transistor ST6 through a first anode contact hole ANCT1 formed through the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0296] The second anode connection electrode ANDE2 may be formed of a second source / drain conductive layer disposed on the first planarization layer 127 .

[0297] The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 formed through the first planarization layer 127 .

[0298] The third anode connection electrode ANDE3 may be formed of a third source / drain conductive layer disposed on the second planarization layer 128 .

[0299] The third anode connection electrode ANDE3 may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 formed through the second planarization layer 128 .

[0300] The anode electrode 131 of the light emitting element LE may be disposed on the third planarization layer 129 covering the third anode connection electrode ANDE3 .

[0301] The anode electrode 131 may be electrically connected to the third anode connection electrode ANDE3 through a fourth anode contact hole ANCT4 formed through the third planarization layer 129 .

[0302] The second source / drain conductive layer on the first planarization layer 127 may further include a data line DL (see FIG. 1 ) for transmitting a data signal Vdata to the light emitting pixel driver EPD. Figure 8 ).

[0303] The third source / drain conductive layer on the second planarization layer 128 may include a readout line ROL (see FIG. 1 ) that outputs a light sensing signal of the light sensing pixel driver DPD. Figure 8 ).

[0304] Each of the first gate conductive layer, the second gate conductive layer, the third gate conductive layer, the first source / drain conductive layer, the second source / drain conductive layer and the third source / drain conductive layer can be formed as a single layer containing molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu), or a multilayer containing at least two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0305] For example, each of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer may be formed as a single layer including molybdenum (Mo), aluminum (Al), copper (Cu), etc. In addition, each of the first source / drain conductive layer, the second source / drain conductive layer, and the third source / drain conductive layer may be formed as a triple layer of Ti / Al / Ti.

[0306] The element layer 130 may include light emitting elements LE respectively disposed in regions corresponding to the emission areas EA, and light sensing elements PD respectively disposed in regions corresponding to the light sensing areas ODA.

[0307] The light emitting element LE may have a structure in which a light emitting layer is interposed between an anode electrode and a cathode electrode facing each other. The light sensing element PD may have a structure in which a photoelectric conversion layer is interposed between a sensing anode electrode and a sensing cathode electrode facing each other.

[0308] For example, each of the light emitting elements LE may include an anode electrode 131 and a cathode electrode 134 facing each other, and a light emitting layer 133 disposed therebetween.

[0309] Alternatively, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134 .

[0310] That is, the element layer 130 may include anode electrodes 131 respectively arranged in areas corresponding to the emission area EA, pixel defining layers 132 arranged in areas corresponding to the non-emission area NEA and covering edges of the anode electrodes 131, first common layers 135 respectively arranged on the anode electrodes 131, light-emitting layers 133 respectively arranged on the first common layers 135, second common layers 136 arranged in areas corresponding to the emission area EA and on the light-emitting layers 133, and cathode electrodes 134 arranged on the second common layer 136.

[0311] The anode electrode 131 may be disposed in each of the emission areas EA, and may be electrically connected to one light emitting pixel driver EPD of the circuit layer 120. The anode electrode 131 may be referred to as a pixel electrode.

[0312] The anode electrode 131 may be formed of a metal material having high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of Al and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, a stacked structure of an APC alloy and ITO (ITO / APC / ITO), etc. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0313] The first common layer 135 on the anode electrode 131 may be disposed in each of the emission areas EA. The first common layer 135 may include a hole transport layer. Alternatively, the first common layer 135 may further include a hole injection layer between the anode electrode 131 and the hole transport layer.

[0314] The light emitting layer 133 on the first common layer 135 may be disposed in each of the emission areas EA. The light emitting layer 133 of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may include organic light emitting materials having different materials or contents.

[0315] For example, the light emitting layer 133 may be formed of an organic light emitting material that converts electron-hole pairs into light.

[0316] The organic light emitting material may include a host material and a dopant, and the dopant may include a phosphorescent material or a fluorescent material.

[0317] The light emitting layer 133 of the first emission area EA1 emitting light of the first color may include a host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP).

[0318] In addition, the dopant of the light-emitting layer 133 of the first emission region EA1 can be selected as any one or more phosphorescent materials selected from bis(1-phenylisoquinoline)iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinoline)iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinoline)iridium (PQIr) and platinum octaethylporphyrin (PtOEP), or a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene.

[0319] The light emitting layer 133 of the second emission region EA2 emitting light of a second color having a wavelength band lower than that of the first color may include a host material including CBP or mCP.

[0320] In addition, a phosphorescent material including tris(2-phenylpyridine)iridium (Ir(ppy)3) or a phosphorescent material including tris(8-hydroxyquinoline)aluminum (Alq 3 )'s fluorescent material is used as a dopant for the light emitting layer 133 of the second emission area EA2.

[0321] The light emitting layer 133 of the third emission region EA3 emitting light of a third color having a wavelength band lower than that of the second color may include a host material including CBP or mCP.

[0322] A phosphorescent material including (4,6-F2ppy)2Irpic or L2BD111 may be selected as a dopant of the light emitting layer 133 of the third emission area EA3.

[0323] The description of the organic light emitting material of the light emitting layer 133 is only an example, and the material of the light emitting layer 133 according to one embodiment is not limited to the above description.

[0324] The second common layer 136 under the cathode electrode 134 may be completely disposed in the display area DA including the emission area EA. The second common layer 136 may include an electron transport layer. Alternatively, the second common layer 136 may further include an electron injection layer between the cathode electrode 134 and the electron transport layer.

[0325] The cathode electrode 134 may be entirely disposed in the display area DA including the emission area EA, and may be electrically connected to the second power line VSL (see FIG. 1 ). Fig. 9 ). The cathode electrode 134 may be referred to as a common electrode.

[0326] The cathode electrode 134 may include a transparent conductive material (TCO) such as ITO or IZO that can transmit light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the cathode electrode 134 is made of a semi-transmissive conductive material, it can be expected that the light output efficiency can be improved due to the microcavity effect.

[0327] On the other hand, although not shown separately, the light sensing elements PD of the element layer 130 have a substantially similar structure to the light emitting elements LE except that they include a photoelectric conversion layer instead of the light emitting layer 133 , and thus a redundant description will be omitted below.

[0328] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0329] The encapsulation layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142 and a third encapsulation layer 143, the first encapsulation layer 141 being disposed on the component layer 130 and being made of an inorganic insulating material, the second encapsulation layer 142 being disposed on the first encapsulation layer 141, overlapping the component layer 130 and being made of an organic insulating material, and the third encapsulation layer 143 being disposed on the first encapsulation layer 141, covering the second encapsulation layer 142 and being made of an inorganic insulating material.

[0330] The second encapsulation layer 142 may be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0331] The second encapsulation layer 142 may be prepared by dropping an organic material in a liquid state onto the first encapsulation layer 141 , widely spreading the dropped organic material to cover the display area DA, and then, curing the spread organic material.

[0332] Therefore, the display device 100 according to one embodiment may further include a dam (not shown) to limit the spread of the organic material of the second encapsulation layer 142 .

[0333] One or more dams may be provided in the non-display area NDA in the form of surrounding the periphery of the display area DA.

[0334] Since the second encapsulation layer 142 spreads to the dam, the third encapsulation layer 143 may directly contact the first encapsulation layer 141 between the dam and the edge of the substrate 110 in the non-display area NDA. Therefore, an encapsulation structure formed by adhesion of an inorganic material may be provided.

[0335] Each of the first encapsulation layer 141 and the third encapsulation layer 143 may have a structure in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked.

[0336] The touch sensor layer 150 may include a third buffer layer 151 disposed on the encapsulation layer 140, a bridging electrode BE disposed on the third buffer layer 151, a sensor insulating layer 152 covering the bridging electrode BE, a driving electrode TE and a sensing electrode RE disposed on the sensor insulating layer 152, and an outer coating layer 153 covering the driving electrode TE and the sensing electrode RE.

[0337] Each of the third buffer layer 151 and the sensor insulating layer 152 may have a structure in which one or more inorganic layers of a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked.

[0338] The overcoat layer 153 may be made of an organic material that can be formed by a low temperature process. For example, the overcoat layer 153 may be made of a negative photoresist material.

[0339] Each of the bridge electrode BE, the driving electrode TE, and the sensing electrode RE may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0340] Each of the dummy electrode DE disposed in each of the driving electrode TE and the sensing electrode RE, the first and second driving lines TL1 and TL2 connected to the driving electrode TE, and the sensing line RL connected to the sensing electrode RE may be disposed on the same layer as the driving electrode TE and the sensing electrode RE.

[0341] The driving electrode TE may be electrically connected to the bridge electrode BE through the touch contact hole TCNT1 formed through the sensor insulating layer 152 .

[0342] The driving electrode TE, the sensing electrode RE, the dummy electrode DE, the first and second driving lines TL1 and TL2, and the sensing line RL may have a structure including a low-reflection layer. In this way, the amount of light incident from the outside, reflected within the display device 100 and emitted (i.e., reflection of external light) may be reduced.

[0343] Next, the bending area BA of the sub-area SBA according to each of the embodiments will be described.

[0344] Fig.14 The first embodiment shows Figure 5 Floor plan of Section C. Fig.15 It is along Fig.14 A cross-sectional view taken along line F-F'. Fig.16 According to the first embodiment, Fig.14 A cross-sectional view taken along line G-G'. Fig.17 According to the second embodiment, Fig.14 A cross-sectional view taken along line G-G'.

[0345] As described above, the display device 100 according to one embodiment includes the substrate 110 , the circuit layer 120 , the element layer 130 , the encapsulation layer 140 , and the touch sensor layer 150 .

[0346] The substrate 110 includes a main area MA and a sub-area SBA protruding from one side thereof. The main area MA includes a display area DA disposed in most of the main area MA, and a non-display area NDA disposed around the display area DA. The display area DA includes an emission area EA, a non-emission area NEA as a partition area between the emission areas EA, and a light sensing area ODA disposed in a portion of the non-emission area NEA.

[0347] The element layer 130 includes light emitting elements LE respectively disposed in the emission areas EA, and light sensing elements PD respectively disposed in the light sensing areas ODA.

[0348] refer to Fig.14According to the first embodiment, the circuit layer 120 of the display device 100 includes light emitting pixel drivers EPD respectively electrically connected to the light emitting elements LE of the element layer 130, light sensing pixel drivers DPD respectively electrically connected to the light sensing elements PD of the element layer 130, data lines DL arranged in the display area DA and electrically connected to the light emitting pixel drivers EPD, readout lines ROL arranged in the display area DA and electrically connected to the light sensing pixel drivers DPD, data bending lines (i.e., data line groups) DBDL arranged in the bending area BA of the sub-area SBA and electrically connected to the data lines DL, and readout bending lines (i.e., readout line groups) ROBDL arranged in the bending area BA and electrically connected to the readout lines ROL, respectively.

[0349] The bending area BA includes a first wiring group area LG1 in which two or more of the data bending lines DBDL are densely located and a second wiring group area LG2 in which two or more of the readout bending lines ROBDL are densely located.

[0350] In the bending area BA, the first wiring group area LG1 and the second wiring group area LG2 may be arranged side by side in a first direction DR1 intersecting a second direction DR2 in which the sub-area SBA protrudes from the main area MA.

[0351] The data bending line DBDL disposed in the first wiring group region LG1 and the readout bending line ROBDL disposed in the second wiring group region LG2 may extend in a second direction DR2 intersecting the first direction DR1 between the first subregion SB1 and the second subregion SB2 .

[0352] Therefore, in the first direction DR1, the readout bending line ROBDL can be spaced apart from the data bending line DBDL. Therefore, the parasitic capacitance between the readout bending line ROBDL and the data bending line DBDL can be reduced. In addition, the defect in which the signal of the readout bending line ROBDL is coupled with the signal of the data bending line DBDL can be reduced. Therefore, the signal distortion in the readout bending line ROBDL can be reduced, and thus the accuracy of the scanning function can be improved.

[0353] According to the first embodiment, the circuit layer 120 may further include data link lines DCNL which are disposed in the non-display area NDA and electrically connect the data lines DL to the data bending lines DBDL, respectively.

[0354] In addition, the circuit layer 120 may further include data pad lines DPDL disposed in the second sub-region SB2 and electrically connecting the data bending lines DBDL to the display driving circuit 200. The circuit layer 120 may further include readout connection lines ROCNL disposed in the non-display area NDA and electrically connecting the readout lines ROL to the readout bending lines ROBDL. The circuit layer 120 may further include readout pad lines ROPDL disposed in the second sub-region SB2 and electrically connecting the readout bending lines ROBDL.

[0355] refer to Fig.15 According to the first embodiment, the display device 100 may further include a bending hole BDH and a dam BNK covering the bending hole BDH, wherein the bending hole BDH is arranged in an area corresponding to the bending area BA and is formed through an inorganic layer including a buffer layer 121 of a circuit layer 120, a first gate insulating layer 122, a second gate insulating layer 123, a first interlayer insulating layer 124, a third gate insulating layer 125 and a second interlayer insulating layer 126.

[0356] The bank BNK may extend from the first sub-region SB1 to the second sub-region SB2 .

[0357] The bank BNK may include a bank layer formed of an organic layer.

[0358] In one example, the bank BNK may include a first bank layer BNL1 formed of the same layer as the first planarization layer 127 , and a second bank layer BNL2 covering the first bank layer BNL1 and formed of the same layer as the second planarization layer 128 .

[0359] The bank BNK may further include a third bank layer BNL3 disposed on the second bank layer BNL2 and formed of the same layer as the pixel defining layer 132 .

[0360] Alternatively, the bank BNK may further include a fourth bank layer (not shown) disposed on the third bank layer BNL3 and formed of the same layer as the spacer (not shown) disposed on a portion of the pixel defining layer 132 .

[0361] The data bending line DBDL may be disposed on the first bank layer BNL1 which is the same layer as the first planarization layer 127. That is, the second source / drain conductive layer may include the data bending line DBDL.

[0362] The data link line DCNL may be included in the first gate conductive layer on the first gate insulating layer 122 or the second gate conductive layer on the second gate insulating layer 123 .

[0363] The data pad line DPDL may be included in the first gate conductive layer on the first gate insulating layer 122 or the second gate conductive layer on the second gate insulating layer 123 .

[0364] The data bending line DBDL may be electrically connected to the data link line DCNL through the first data connection hole DTCH1 , and may be electrically connected to the data pad line DPDL through the second data connection hole DTCH2 .

[0365] Each of the first data connection hole DTCH1 and the second data connection hole DTCH2 may be formed through the first bank layer BNL1, the second interlayer insulating layer 126, the third gate insulating layer 125, and the first interlayer insulating layer 124. Alternatively, when the data connection line DCNL and the data pad line DPDL are included in the first gate conductive layer, each of the first data connection hole DTCH1 and the second data connection hole DTCH2 may also be formed through the second gate insulating layer 123.

[0366] like Fig.14 As shown in, according to the first embodiment, the circuit layer 120 may further include a DC power line DCSPL and a DC power bending line DCBDL, the DC power line DCSPL is arranged in the non-display area NDA and transmits DC power of different voltage levels, and the DC power bending line DCBDL is arranged in the bending area BA, extends in the second direction DR2 and is electrically connected to the DC power lines DCSPL, respectively.

[0367] In the second wiring group area LG2, two or more of the DC power bending lines DCBDL may be more densely positioned.

[0368] That is, each of the readout bending lines ROBDL may overlap at least a portion of a separation region between the DC power bending lines DCBDL.

[0369] In this way, the signal of the readout bending line ROBDL can be more stably maintained by the DC power of the DC power bending line DCBDL, thereby further reducing signal distortion in the readout bending line ROBDL.

[0370] According to the first embodiment, the DC power may include a first power ELVDD and a second power ELVSS for driving the light emitting element LE.

[0371] In this case, the DC power line DCSPL may include a first power line VDSPL transmitting the first power ELVDD and a second power line VSSPL transmitting the second power ELVSS.

[0372] Furthermore, the DC power bending line DCBDL may include a first power bending line VDBDL connected to the first power line VDSPL, and a second power bending line VSBDL connected to the second power line VSSPL.

[0373] The first power bending line VDBDL may be connected to the first power pad line VDPDL in the second sub-region SB2 .

[0374] The second power bending line VSBDL may be connected to the second power pad line VSPDL in the second sub-region SB2 .

[0375] However, this is only an example, and the DC power according to the first embodiment may also include a first initialization voltage VINT for initializing the light emitting pixel driver EPD and a second initialization voltage VAINT for initializing the light sensing pixel driver DPD. In this case, the DC power supply line DCSPL may also include a first initialization voltage supply line (not shown) and a second initialization voltage supply line (not shown). In addition, the DC power bending line DCBDL may also include a first initialization voltage bending line (not shown) and a second initialization voltage bending line (not shown).

[0376] refer to Fig.16 The second power bending line VSBDL as one of the DC power bending lines DCBDL may be included in the same conductive layer as the data bending line DBDL. That is, similar to the data bending line DBDL, the second power bending line VSBDL may be included in the second source / drain conductive layer on the first bank layer BNL1.

[0377] According to the first embodiment, the readout bending line ROBDL may be disposed on the insulating layer covering the data bending line DBDL and the DC power bending line DCBDL (eg, the second power bending line VSBDL), that is, on the second bank layer BNL2.

[0378] When the data bending line DBDL is set in the first wiring group area LG1, the readout bending line ROBDL and the DC power bending line DCBDL (e.g., the second power bending line VSBDL) can be set together in the second wiring group area LG2, and the second wiring group area LG2 is set side by side with the first wiring group area LG1 in the first direction DR1.

[0379] In this manner, the readout bending line ROBDL may be spaced apart from the data bending line DBDL, which may reduce a defect in which a light sensing signal of the readout bending line ROBDL is distorted by a data signal of the data bending line DBDL.

[0380] According to the first embodiment, each of the readout bending lines ROBDL may be disposed between the DC power bending lines DCBDL (eg, the second power bending line VSBDL). In addition, at least one of the DC power bending lines DCBDL (eg, the second power bending line VSBDL) may be disposed between the readout bending lines ROBDL.

[0381] According to the first embodiment, each of the readout bending lines ROBDL may be spaced apart from the DC power bending line DCBDL (eg, the second power bending line VSBDL) in the first direction DR1.

[0382] In this manner, due to the DC power of the DC power bending line DCBDL (eg, the second power bending line VSBDL), a defect in which a signal of the readout bending line ROBDL interferes with the readout bending line ROBDL can be reduced. Therefore, the accuracy of the scanning function can be improved.

[0383] Alternatively, if Fig.17 As shown in , according to the second embodiment, each of the readout bending lines ROBDL may completely overlap with the separation area between the DC power bending lines DCBDL (e.g., the second power bending lines VSBDL). That is, the width of each of the readout bending lines ROBDL in the first direction DR1 may be equal to the width of the separation area between the DC power bending lines DCBDL (e.g., the second power bending lines VSBDL).

[0384] In this way, the light sensing signal for reading out the bending line ROBDL can be more stably maintained by the DC power, so that the accuracy of the scanning function can be further improved.

[0385] On the other hand, Fig.14 As shown in, according to the first embodiment, the circuit layer 120 may also include a touch sensor bending line (i.e., a touch sensor line group) TSBDL, which is arranged in the bending area BA, extends in the second direction DR2 and is electrically connected to the touch sensor lines TSL of the touch sensor layer 150, respectively.

[0386] The touch sensor bending lines TSBDL may be electrically connected to the touch sensor pad lines TSPDL in the second sub-region SB2 , respectively.

[0387] The bending area BA may further include a third wiring group area LG3 in which two or more of the touch sensor bending lines TSBDL are densely located.

[0388] The third wiring group region LG3 may be arranged side by side with the first wiring group region LG1 and the second wiring group region LG2 in the first direction DR1.

[0389] Fig.18 The third embodiment shows Figure 5 Floor plan of Section C. Fig.19 It is along Fig.18 A cross-sectional view taken along line G-G'.

[0390] refer to Fig.18 and Fig.19 According to the third embodiment, the display device 100 and Fig.14 , Fig.15 and Fig.16 The display device 100 of the first embodiment shown in FIG. 1 is substantially the same except that the readout bending line ROBDL is included in the same layer as the DC power bending line DCBDL (eg, the second power bending line VSBDL), and thus a redundant description will be omitted below.

[0391] According to the third embodiment, similar to the data bending line DBDL and the DC power bending line DCBDL (eg, the second power bending line VSBDL), the readout bending line ROBDL may be included in the second source / drain conductive layer on the first bank layer BNL1 .

[0392] The third embodiment can be easily applied to the circuit layer 120 having a structure that does not include the third source / drain conductive layer and the third planarization layer 129 .

[0393] Fig. 20 The fourth embodiment shows Figure 5 Floor plan of Section C. Fig.21 It is along Fig. 20 A cross-sectional view taken along line G-G'.

[0394] refer to Fig. 20 and Fig.21 The display device 100 according to the fourth embodiment is basically the same as Fig.14 , Fig.15 and Fig.16 The display device 100 of the first embodiment shown in FIG. 1 is the same except that the separation area between the readout bending lines ROBDL overlaps with the DC power bending line DCBDL (eg, the second power bending line VSBDL), and thus a redundant description will be omitted below.

[0395] According to the fourth embodiment, one of the readout bending lines ROBDL may overlap with a separation area between two DC power bending lines DCBDL (e.g., second power bending line VSBDL) and also overlap with a portion of each of the two DC power bending lines DCBDL (e.g., second power bending line VSBDL).

[0396] In this way, due to the capacitance generated in the overlapping area between the readout bending line ROBDL and the DC power bending line DCBDL (e.g., the second power bending line VSBDL), the period during which the signal of the readout bending line ROBDL is maintained can be increased. Therefore, signal distortion in the readout line ROL can be reduced.

[0397] Fig. 22 The fifth embodiment shows Figure 5 Floor plan of Section C. Fig.23 It is along Fig. 22 A cross-sectional view taken along line G-G'.

[0398] refer to Fig. 22 and Fig.23 The display device 100 according to the fifth embodiment is basically the same as Fig.14 , Fig.15 and Fig.16 The display device 100 of the first embodiment shown in FIG. 1 is the same except that two or more of the DC power bending lines DCBDL (eg, the second power bending lines VSBDL) are disposed between the readout bending lines ROBDL, and thus redundant description will be omitted below.

[0399] According to the fifth embodiment, when the number of separation areas between the DC power bending lines DCBDL (eg, the second power bending lines VSBDL) is an integral multiple of the number of the readout bending lines ROBDL, this can be easily applied to the circuit layer 120 .

[0400] Fig.24 The sixth embodiment is shown in FIG. Figure 5 Floor plan of Section C. Fig.25 According to the sixth embodiment, Fig.24 A cross-sectional view taken along line G-G'. Fig.26 According to the seventh embodiment, Fig.24 A cross-sectional view taken along line G-G'.

[0401] refer to Fig.24 and Fig.25 The display device 100 according to the sixth embodiment is basically the same as Fig. 20 and Fig.21 The display device 100 of the fourth embodiment shown in FIG. 1 is the same as that of the fourth embodiment, except that one of the readout bending lines ROBDL overlaps with at least one DC power bending line DCBDL (e.g., the second power bending line VSBDL) provided between two of the DC power bending lines DCBDL (e.g., the second power bending line VSBDL), and therefore redundant description will be omitted below.

[0402] refer to Fig.26The display device 100 according to the seventh embodiment is basically the same as Fig.24 and Fig.25 The display device 100 of the sixth embodiment shown in FIG. 1 is the same as that of the display device 100 of the sixth embodiment shown in FIG. 1 , except that one of the readout bending lines ROBDL overlaps not only with at least one DC power bending line DCBDL (e.g., the second power bending line VSBDL) disposed between two of the DC power bending lines DCBDL (e.g., the second power bending line VSBDL), but also overlaps with a portion of each of the two DC power bending lines DCBDL (e.g., the second power bending line VSBDL), and therefore redundant description will be omitted below.

[0403] According to the sixth and seventh embodiments, as the overlapping area between the readout bending line ROBDL and the DC power bending line DCBDL (eg, the second power bending line VSBDL) increases, signal distortion in the readout bending line ROBDL can be reduced.

[0404] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A display device, comprising: Substrate, comprising: a main area including a display area in which a light emitting element and a light sensing element are disposed and a non-display area disposed around the display area, and a sub-region protruding from one side of the main region, wherein a curved region configured to be curved is provided in the sub-region; and A circuit layer is disposed on the substrate, Wherein, the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements, respectively, light sensing pixel drivers, electrically connected to the light sensing elements respectively, a data line electrically connected to the light emitting pixel driver, the data line comprising a data line group, each of the data line groups comprising at least two data lines, and a readout line electrically connected to the light sensing pixel driver, the readout line comprising a readout line group, each of the readout line groups comprising at least two readout lines, The readout lines in one readout line group arranged in the bending region are arranged adjacent to each other, and no data line is interposed between adjacent readout lines.

2. The display device according to claim 1, wherein: The readout line group and the data line group are arranged side by side in a first direction, the first direction intersecting with a direction in which the sub-region extends from the main region, wherein the data line and the readout line extend in the second direction in the bending region, and The readout line group is spaced apart from the data line group in the first direction.

3. The display device according to claim 2, wherein: The circuit layer also includes: a DC power bending line disposed in the bending region, and wherein, in a plan view, each of the sense lines overlaps with at least a portion of the DC power bending line in the bending region.

4. The display device according to claim 3, wherein: The data line, the readout line and the DC power bending line are included in the same conductive layer, and Wherein, in a plan view, each of the sense lines is disposed between the DC power bending lines in the bending region.

5. The display device according to claim 3, wherein: The readout line is disposed on an insulating layer covering the data line and the DC power bending line.

6. The display device according to claim 5, wherein: In a plan view, each of the sense lines is disposed between the DC power bending lines in the bending region.

7. The display device according to claim 5, wherein: At least one of the DC power bending lines is disposed between the sense lines in the bending region in a plan view.

8. The display device according to claim 5, wherein: In a plan view, a separation region provided between the sense lines overlaps with the DC power bending line in the bending region.

9. The display device according to claim 8, wherein: In a plan view, one of the sense lines overlaps with a separation area between two of the DC power bending lines and a portion of each of the two DC power bending lines in the bending area.

10. The display device according to claim 9, wherein: Each of the sense lines also overlaps with at least one DC power bending line disposed between the two DC power bending lines.

11. The display device according to claim 3, wherein: The circuit layer further includes touch sensor lines arranged in the bending region, the touch sensor lines extending in the second direction and electrically connected to the touch sensor layer, respectively, the touch sensor lines including touch sensor line groups, each of the touch sensor line groups including at least two touch sensor lines, and The touch sensor line group is arranged side by side with the data line group and the readout line group.

12. The display device according to claim 3, wherein: The circuit layer comprises: A first semiconductor layer is disposed on the substrate; a first inorganic insulating layer, covering the first semiconductor layer; a first conductive layer, disposed on the first inorganic insulating layer; a second inorganic insulating layer, covering the first conductive layer; a second conductive layer, disposed on the second inorganic insulating layer; a third inorganic insulating layer, covering the second conductive layer; A second semiconductor layer is disposed on the third inorganic insulating layer; a fourth inorganic insulating layer, covering the second semiconductor layer; a third conductive layer, disposed on the fourth inorganic insulating layer; a fifth inorganic insulating layer, covering the third conductive layer; a fourth conductive layer, disposed on the fifth inorganic insulating layer; a first planarization layer, covering the fourth conductive layer; a fifth conductive layer, disposed on the first planarization layer; a second planarization layer, covering the fifth conductive layer; a sixth conductive layer, disposed on the second planarization layer; and a third planarization layer, covering the sixth conductive layer, wherein the fifth conductive layer includes the data line and the DC power bending line, and Wherein, the readout line is arranged in the fifth conductive layer or the sixth conductive layer.

13. The display device according to claim 12, further comprising: a bending hole, which is disposed in a region corresponding to the bending region and is formed through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer; as well as a bank covering the curved hole, Wherein, the embankment comprises: a first bank layer, the first bank layer being the same layer as the first planarization layer and covering the bent hole; a second bank layer which is the same layer as the second planarization layer and covers the first bank layer; and a third bank layer which is the same layer as the third planarization layer and is disposed on the second bank layer, and The data line and the DC power bending line are disposed on the first bank layer and covered by the second bank layer.

14. An electronic device comprising: A display device configured to emit light for displaying an image; as well as a cover window and a bracket, the cover window and the bracket facing each other and configured to accommodate the display device, Wherein, the display device comprises: a substrate including a main region and a sub-region protruding from one side of the main region, the main region including a display region in which an emission region is arranged and a non-display region disposed around the display region; A circuit layer is disposed on the substrate; A component layer, disposed on the circuit layer; a packaging layer, disposed on the component layer; and A touch sensor layer is disposed on the packaging layer, wherein the sub-region includes a curved region configured to be curved, a first sub-region disposed between one side of the curved region and the main region, and a second sub-region connected to the other side of the curved region, wherein the display area further includes a light sensing area disposed in a portion of a non-emitting area, the non-emitting area being a separation area between the emitting areas, The element layer includes light emitting elements respectively arranged in the emission area and light sensing elements respectively arranged in the light sensing area. Wherein, the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements, respectively, light sensing pixel drivers, electrically connected to the light sensing elements respectively, a data line disposed in the display area and electrically connected to the light-emitting pixel driver, a readout line disposed in the display area and electrically connected to the light sensing pixel driver, data bending lines, disposed in the bending region and electrically connected to the data lines, respectively, readout bending lines disposed in the bending region and electrically connected to the readout lines, respectively, and touch sensor bending lines disposed in the bending region, extending in the second direction, and electrically connected to the touch sensor lines of the touch sensor layer, respectively; and Wherein, the bending area includes: A first wiring group region is provided with at least two data bending lines, a second wiring group region in which at least two readout bending lines are arranged, and A third wiring group area is provided with at least two touch sensor bending wires.

15. The electronic device according to claim 14, wherein: The circuit layer also includes: A DC power supply line disposed in the non-display area and transmitting DC power of different voltage levels; and DC power bending lines, which are disposed in the bending region and are electrically connected to the DC power supply lines, respectively, wherein, in the second wiring group area, two or more of the DC power bending lines are arranged, wherein the first wiring group region, the second wiring group region and the third wiring group region are arranged side by side in a first direction, and the first direction intersects with a direction in which the sub-region protrudes from the main region, wherein the data bending line, the readout bending line, and the DC power bending line extend in the second direction intersecting the first direction and are arranged between the first sub-region and the second sub-region, wherein the readout bending line is spaced apart from the data bending line in the first direction, and wherein each of the readout bending lines overlaps at least a portion of a separation region between the DC power bending lines.

16. The electronic device according to claim 15, wherein: The data bending line, the readout bending line, and the DC power bending line are included in the same conductive layer, and Wherein, in a plan view, each of the readout bending lines is arranged between the DC power bending lines.

17. The electronic device according to claim 15, wherein: The readout bending line is disposed on an insulating layer covering the data bending line and the DC power bending line.

18. The electronic device according to claim 17, wherein: In a plan view, each of the sense bending lines is disposed between the DC power bending lines.

19. The electronic device according to claim 17, wherein: A separation region between the readout bending lines overlaps the DC power bending line, and One of the readout bending lines overlaps with a separation region between two of the DC power bending lines and overlaps with a portion of each of the two DC power bending lines.

20. The electronic device according to claim 19, wherein: In a plan view, each of the sense bending lines also overlaps with at least one DC power bending line disposed between the two DC power bending lines.

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