Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a base layer, a circuit layer over the base layer, and an element layer over the circuit layer, and the element layer includes a light emitting element and a light receiving element adjacent to the light emitting element, the light emitting element includes a first pixel electrode electrically connected to the circuit layer, a light emitting layer over the first pixel electrode, and a second pixel electrode over the light emitting layer, and the light receiving element includes a first sensing electrode electrically connected to the circuit layer, a photoelectric conversion layer over the first sensing electrode, and a second sensing electrode over the photoelectric conversion layer, and the second sensing electrode has a thickness different from a thickness of the second pixel electrode.

Description

Technical Field

[0001] Herein, the present disclosure relates to a reliable display device and a method of manufacturing the display device. Background Art

[0002] Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles are being developed, and the fields of use of the display devices are diverse. Therefore, the types of display panels used to display images on the display devices are also diverse. The display panel includes a light-emitting display panel, and the light-emitting display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, a quantum dot light-emitting display panel, and the like.

[0003] The display device provides various functions to enable organic communication with a user, such as providing information to the user by displaying an image or sensing the user's input. Recent display devices include a function for sensing biometric information of the user. Summary of the invention

[0004] The present disclosure provides a display device and a method for manufacturing the display device, which can not only improve the sensing accuracy of biometric information but also improve the display quality.

[0005] A display device according to one or more embodiments of the present disclosure may include a base layer, a circuit layer above the base layer, and an element layer above the circuit layer, and the element layer may include a light-emitting element and a light-receiving element adjacent to the light-emitting element, the light-emitting element includes a first pixel electrode electrically connected to the circuit layer, a light-emitting layer above the first pixel electrode, and a second pixel electrode above the light-emitting layer, and the light-receiving element may include a first sensing electrode electrically connected to the circuit layer, a photoelectric conversion layer above the first sensing electrode, and a second sensing electrode above the photoelectric conversion layer, and the second sensing electrode has a thickness different from that of the second pixel electrode.

[0006] A thickness of the second sensing electrode may be greater than a thickness of the second pixel electrode.

[0007] The second pixel electrode may include a pixel electrode layer, and the second sensing electrode may include a first sensing electrode layer extending from the pixel electrode layer, and a second sensing electrode layer over the first sensing electrode layer.

[0008] The second pixel electrode may include a pixel electrode layer, and the second sensing electrode may include a first sensing electrode layer, and a second sensing electrode layer over the first sensing electrode layer and extending from the pixel electrode layer.

[0009] The element layer may define a light emitting region overlapping the light emitting layer in a plan view and a non-light emitting region surrounding the light emitting region.

[0010] The second pixel electrode may include a first pixel electrode portion corresponding to the light emitting area and a second pixel electrode portion corresponding to the non-light emitting area.

[0011] A thickness of the first pixel electrode portion may be different from a thickness of the second pixel electrode portion.

[0012] A thickness of the second pixel electrode portion may be greater than a thickness of the first pixel electrode portion.

[0013] A thickness of the second pixel electrode portion may be substantially equal to a thickness of the second sensing electrode.

[0014] The element layer may define a sensing region overlapping the photoelectric conversion layer and a non-sensing region surrounding the sensing region.

[0015] The second sensing electrode may include a first sensing electrode portion corresponding to the sensing area and a second sensing electrode portion corresponding to the non-sensing area.

[0016] A thickness of the first sensing electrode portion may be different from a thickness of the second sensing electrode portion.

[0017] A thickness of the first sensing electrode portion may be greater than a thickness of the second sensing electrode portion.

[0018] A thickness of the second sensing electrode portion may be substantially equal to a thickness of the second pixel electrode.

[0019] The second pixel electrode and the second sensing electrode may be electrically connected to each other.

[0020] The circuit layer may include a pixel driving circuit electrically connected to the light emitting element to control the operation of the light emitting element, and a sensing driving circuit electrically connected to the light receiving element to control the operation of the light receiving element.

[0021] The display device may further include a black matrix over the element layer and including an opening, and a color filter over the element layer and overlapping the opening.

[0022] According to one or more embodiments, a method for manufacturing a display device may include: forming a circuit layer above a base layer; and forming an element layer including a light emitting element and a light receiving element above the circuit layer, the forming of the element layer including: forming a first pixel electrode of the light emitting element and a first sensing electrode of the light receiving element above the circuit layer; forming a light emitting layer above the first pixel electrode, and forming a photoelectric conversion layer above the first sensing electrode; and forming a second pixel electrode above the light emitting layer, and forming a second sensing electrode above the photoelectric conversion layer, the thickness of the second sensing electrode being greater than the thickness of the second pixel electrode.

[0023] Forming the second pixel electrode and the second sensing electrode may include: forming a first pixel electrode layer over the light emitting layer, and forming a first sensing electrode layer over the photoelectric conversion layer; and forming a second sensing electrode layer over the first sensing electrode layer.

[0024] The first pixel electrode layer and the first sensing electrode layer may be formed integrally with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the drawings:

[0026] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0027] Figure 2 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0028] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure;

[0029] Figure 4A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure;

[0030] Figure 4B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure;

[0031] Figure 5 is a circuit diagram showing pixels and sensors of a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 6 is a cross-sectional view showing a pixel and a sensor of a display device according to one or more embodiments of the present disclosure;

[0033] Fig. 7A is an enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 7B is an enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 7C is an enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure; and

[0036] FIG. 8A to FIG. 8Gis a cross-sectional view for describing a step of forming a portion of a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects and features of some embodiments of the present disclosure and the methods for realizing them. The embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0038] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0039] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity / descriptive purposes. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise indicated.

[0040] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but rather include deviations in shapes due to, for example, manufacturing.

[0041] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0042] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper", "upper side" etc. may be used herein to describe the relationship between an element or feature and another (multiple) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "below" may include both the orientations of above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0043] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending throughout, covering or partially covering, or any other suitable term as will be understood and appreciated by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from" or "set side by side with" or "offset with" and any other suitable equivalents as will be understood and appreciated by a person of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0044] It will be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may refer collectively to direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or on another component without intermediate components.

[0045] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly" "below" another part, but also includes the situation that there is another other part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." that describe the relationship between components can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0046] For the purposes of this disclosure, expressions such as "at least one of ...," "any of ...," or "one or more of ...," when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of ...," "a plurality of," "one of ...," and other prepositional phrases, when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list.

[0047] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different categories or different groups in this article. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0048] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and / or the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0049] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprise", "including", "have", "having", "including" and "including" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0050] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in a reverse order to the described order.

[0051] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. For example, "substantially" may include a range of ±5% of the corresponding value. In view of the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable deviation range for a particular value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0052] In addition, any numerical range disclosed and / or listed herein is intended to include all sub-ranges of the same numerical precision contained in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including 1.0 and 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any sub-ranges contained in the range explicitly described herein.

[0053] In some embodiments, known structures and devices may be described in the accompanying drawings for one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. It will be understood by those skilled in the art that these functional blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. These can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Functional blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each functional block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from those of hardware. In addition, in some embodiments, functional blocks, units and / or modules can be physically divided into two or more interactive separate functional blocks, units and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, the functional blocks, units and / or modules may be physically combined into more complex functional blocks, units and / or modules without departing from the scope of the present disclosure.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0055] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0056] refer to Figure 1 and Figure 2 The display device DD according to one or more embodiments of the present disclosure may have a rectangular shape having long sides parallel to the first direction DR1 and short sides parallel to the second direction DR2 crossing the first direction DR1. However, not limited thereto, the display device DD may have various shapes such as a circle and a polygon.

[0057] The display device DD may be activated according to the electrical signal. The display device DD may include various embodiments. For example, the display device DD may be applied to electronic devices such as smart watches, tablet computers, laptop computers, desktop computers, and smart TVs.

[0058] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the expression "when viewed on a plane" may mean a state viewed from the third direction DR3.

[0059] An upper surface of the display device DD may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated in the display device DD may be provided to a user through the display surface IS.

[0060] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which the image IM is displayed. The user views the image IM through the transmission area TA. In one or more embodiments, the transmission area TA is shown as a quadrilateral shape with rounded vertices. However, this is shown as an example, and the transmission area TA may have various shapes, and the present disclosure is not limited to any one embodiment.

[0061] The border area BZA may be adjacent to the transmission area TA. The border area BZA may have a color (e.g., a preset color). The border area BZA may surround the transmission area TA. Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is shown as an example, and the border area BZA may be positioned adjacent to only one side of the transmission area TA, or may be omitted.

[0062] The display device DD can sense external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, the external input may include contact through a part of the user's body (such as the user's hand US_F), or contact through a separate device (e.g., an active pen or digitizer, etc.), and may also include an external input (e.g., hovering) applied near the display device DD or adjacent to the display device DD at a certain distance (e.g., a preset distance). In addition, the external input may have various forms, such as force, pressure, temperature, and light.

[0063] The display device DD may sense biometric information of a user that may be applied from the outside. A biometric information sensing area capable of sensing the biometric information of the user may be provided to the display surface IS of the display device DD. The biometric information sensing area may be provided to the entire area of ​​the transmissive area TA or to a partial area thereof. Figure 1 It is shown that the entire transmission area TA according to one or more embodiments of the present disclosure may be used as a biometric information sensing area.

[0064] The display device DD may include a window WM, a display module DM, and a case EDC. In one or more embodiments, the window WM and the case EDC are coupled to each other to form an appearance of the display device DD.

[0065] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other with an adhesive, or may include a glass substrate and a plastic film bonded to each other with an adhesive.

[0066] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0067] The display panel DP according to one or more embodiments of the present disclosure may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0068] refer to Figure 2 , the display panel DP may include a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to one or more embodiments of the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a rigid display panel or a foldable display panel that can be folded around a folding axis.

[0069] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a polyimide-based resin, but its material is not limited thereto. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0070] The circuit layer DP_CL may be located on the base layer BL. The circuit layer DP_CL may be located between the base layer BL and the element layer DP_ED. The circuit layer DP_CL may include at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer may include at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit and a sensor driving circuit, the pixel driving circuit being included in each of a plurality of pixels for displaying an image, and the sensor driving circuit being included in each of a plurality of sensors for identifying external information. The external information may be biometric information. According to one or more embodiments of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, an illuminance sensor, and the like. In addition, the sensor may be an optical sensor for optically identifying biometric information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0071] The element layer DP_ED may include a light emitting element included in each pixel and a light receiving element included in each sensor. According to one or more embodiments of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that senses light reflected from a user's fingerprint or reacts to light reflected from a user's fingerprint. Figure 6 The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0072] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film contains an inorganic material and can protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic film contains an organic material and can protect the element layer DP_ED from foreign matter such as dust particles.

[0073] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly located on the encapsulation layer TFE. According to one or more embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a continuous process. For example, when the input sensing layer ISL is directly located on the display panel DP, the adhesive film may not be located between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be located between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL is not manufactured by a continuous process with the display panel DP, but the input sensing layer ISL may be manufactured by a process separate from the process of the display panel DP, and then bonded to the upper surface of the display panel DP with an adhesive film.

[0074] The input sensing layer ISL may sense an external input (e.g., a user's touch), change the external input into a preset input signal, and provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input in a capacitive manner. The display panel DP may receive an input signal from the input sensing layer ISL and generate an image corresponding to the input signal.

[0075] The display module DM may further include a color filter layer CFL. According to one or more embodiments of the present disclosure, the color filter layer CFL may be located on the input sensing layer ISL. However, the present disclosure is not limited thereto. The color filter layer CFL may be located between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0076] Details of the structures of the input sensing layer ISL and the color filter layer CFL will be described later.

[0077] The display device DD according to one or more embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the color filter layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0078] The housing EDC may be connected to the window WM. The housing EDC may be connected to the window WM to provide a preset internal space. The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. In one or more embodiments, a battery module may be located between the display module DM and the housing EDC, which provides the power required for the overall operation of the display device DD.

[0079] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0080] refer to Figure 3 The display device DD may include a display panel DP, a panel driver, and a driving controller 100. According to one or more embodiments of the present disclosure, the panel driver may include a data driver 200, a scan driver 300, a light emitting driver 350, a voltage generator 400, and a readout circuit 500.

[0081] The driving controller 100 may receive the image signal RGB and the control signal CTRL. The driving controller 100 may generate the image data signal DATA obtained by converting the data format of the image signal RGB so as to meet the interface specification with the data driver 200. The driving controller 100 may output the first control signal SCS, the second control signal ECS, the third control signal DCS, and the fourth control signal RCS.

[0082] The data driver 200 may receive the third control signal DCS and the image data signal DATA from the driving controller 100. The data driver 200 may convert the image data signal DATA into a data signal, and may output the data signal to a plurality of data lines DL1 to DLm (wherein m is a natural number greater than 1) to be described later. The data signal may be an analog voltage corresponding to a grayscale value of the image data signal DATA.

[0083] The scan driver 300 may receive a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal through the scan line in response to the first control signal SCS.

[0084] The voltage generator 400 may generate voltages suitable for operation of the display panel DP In one or more embodiments, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0085] The display panel DP may include a transmissive area TA ( Figure 1 The display area DA and the frame area BZA ( Figure 1 The non-display area NDA shown in FIG.

[0086] The display panel DP may include a plurality of pixels PX located in the display area DA and a plurality of sensors FX located in the display area DA. According to one or more embodiments of the present disclosure, each of the plurality of sensors FX may be located between two adjacent pixels PX. The plurality of pixels PX and the plurality of sensors FX may be alternately arranged in the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. For example, two or more pixels PX may be located between two adjacent sensors FX in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be located between two adjacent sensors FX in the second direction DR2 among the plurality of sensors FX.

[0087] The display panel DP may include initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh (where n and h are natural numbers greater than 1). The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the light emission control lines EML1 to EMLn extend in the second direction DR2. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the light emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the first direction DR1. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the first direction DR1 and are arranged to be spaced apart from each other in the second direction DR2.

[0088] The plurality of pixels PX may be electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto and may be changed.

[0089] The plurality of sensors FX may be electrically connected to the write scan lines SWL1 to SWLn and the readout lines RL1 to RLh, respectively. Each of the plurality of sensors FX may be electrically connected to one scan line. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may be variable. According to one or more embodiments of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 4, or 1 / 8 of the number of data lines DL1 to DLm.

[0090] The scan driver 300 may be located in the non-display area NDA of the display panel DP. The scan driver 300 may receive a first control signal SCS from the drive controller 100. The scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn in response to the first control signal SCS, and output a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn in response to the first control signal SCS, and output a black scan signal to the black scan lines SBL1 to SBLn. Alternatively, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0091] The light emitting driver 350 may be located in the non-display area NDA of the display panel DP. The light emitting driver 350 may receive a second control signal ECS from the driving controller 100. The light emitting driver 350 may output a light emitting control signal to the light emitting control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 300 may be connected to the light emitting control lines EML1 to EMLn. In this case, the light emitting driver 350 may be omitted, and the scan driver 300 may output a light emitting control signal to the light emitting control lines EML1 to EMLn.

[0092] The readout circuit 500 may receive a fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive a readout signal from the readout lines RL1 to RLh in response to the fourth control signal RCS. The readout circuit 500 may process the readout signal received from the readout lines RL1 to RLh, generate a sensing signal S_FS, and may provide the generated sensing signal S_FS to the driving controller 100. Based on the sensing signal S_FS, the driving controller 100 may recognize biometric information.

[0093] Figure 4A and Figure 4B is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0094] refer to Figure 4A , the display panel DP may include a plurality of pixels PXR, PXG1, PXG2, and PXB and a plurality of sensors FX.

[0095] A plurality of pixels PXR, PXG1, PXG2, and PXB may be grouped into a plurality of reference pixel units RPU. According to one or more embodiments of the present disclosure, each reference pixel unit RPU may include four pixels, such as two first pixels PXG1 and PXG2 (hereinafter referred to as the first green pixel and the second green pixel), a third pixel PXR (hereinafter referred to as the red pixel), and a fourth pixel PXB (hereinafter referred to as the blue pixel). However, the number of pixels included in each reference pixel unit RPU is not limited thereto. Alternatively, each reference pixel unit RPU may include three pixels, such as the first green pixel PXG1 (or the second green pixel PXG2), the red pixel PXR, and the blue pixel PXB.

[0096] The first green pixel PXG1 and the second green pixel PXG2 include a first light-emitting element ED_G1 and a second light-emitting element ED_G2 (hereinafter referred to as the first green light-emitting element and the second green light-emitting element), respectively, the red pixel PXR may include a third light-emitting element ED_R (hereinafter referred to as the red light-emitting element), and the blue pixel PXB may include a fourth light-emitting element ED_B (hereinafter referred to as the blue light-emitting element). According to one or more embodiments of the present disclosure, each of the first green light-emitting element ED_G1 and the second green light-emitting element ED_G2 may output a first color light (e.g., green light), the red light-emitting element ED_R may output a second color light (e.g., red light) different from the first color light, and the blue light-emitting element ED_B may output a third color light (e.g., blue light) different from the first color light and the second color light. The green light output from the first green light-emitting element ED_G1 may have substantially the same wavelength as the green light output from the second green light-emitting element ED_G2.

[0097] In the first direction DR1 and the second direction DR2, the red light emitting elements ED_R and the blue light emitting elements ED_B may be arranged alternately and repeatedly with each other. The first green light emitting elements ED_G1 and the second green light emitting elements ED_G2 may be arranged alternately and repeatedly in the first direction DR1, and alternately and repeatedly in the second direction DR2. In the first direction DR1 and the second direction DR2, the first green light emitting elements ED_G1 and the second green light emitting elements ED_G2 may be arranged in rows and columns different from those of the red light emitting elements ED_R and the blue light emitting elements ED_B.

[0098] According to one or more embodiments of the present disclosure, the red light emitting element ED_R may have a size larger than the first green light emitting element ED_G1 and the second green light emitting element ED_G2. In addition, the size of the blue light emitting element ED_B may be greater than or equal to the size of the red light emitting element ED_R. The size of each of the light emitting elements ED_R, ED_G1, ED_G2, and ED_B is not limited thereto, and various modifications and applications may be made. For example, in one or more embodiments of the present disclosure, the light emitting elements ED_R, ED_G1, ED_G2, and ED_B may have substantially the same size as each other.

[0099] The first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have a shape different from that of the red light emitting element ED_R and the blue light emitting element ED_B. According to one or more embodiments of the present disclosure, each of the red light emitting element ED_R and the blue light emitting element ED_B may have an octagonal shape that is longer in the first direction DR1 than in the second direction DR2. The red light emitting element ED_R and the blue light emitting element ED_B may have substantially the same size, or may have different corresponding sizes. The red light emitting element ED_R and the blue light emitting element ED_B may have substantially the same shape as each other, or may have different corresponding shapes. The shape of each of the red light emitting element ED_R and the blue light emitting element ED_B is not limited thereto. For example, each of the red light emitting element ED_R and the blue light emitting element ED_B may have an octagonal shape having substantially the same length in the first direction DR1 and the second direction DR2, or may have one of a square shape and a rectangular shape.

[0100] Each of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have an octagonal shape that is longer in the second direction DR2 than in the first direction DR1. According to one or more embodiments of the present disclosure, the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have substantially the same size and shape as each other. However, the shapes of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 are not limited thereto. Each of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have an octagonal shape having substantially the same length in the first direction DR1 and the second direction DR2, or may have one of a square shape and a rectangular shape.

[0101] The first green light emitting element ED_G1 may be electrically connected to the first green pixel driving circuit G1_PD. For example, the first green light emitting element ED_G1 may include a first green anode electrode G1_AE and a first green light emitting layer G1_EL, and the first green anode electrode G1_AE may be connected to the first green pixel driving circuit G1_PD through a contact hole.

[0102] The second green light emitting element ED_G2 may be electrically connected to the second green pixel driving circuit G2_PD. For example, the second green light emitting element ED_G2 may include a second green anode electrode G2_AE and a second green light emitting layer G2_EL, and the second green anode electrode G2_AE may be connected to the second green pixel driving circuit G2_PD through a contact hole.

[0103] The first green light emitting layer G1_EL and the second green light emitting layer G2_EL may have substantially the same size as each other. The first green light emitting layer G1_EL and the second green light emitting layer G2_EL may have substantially the same or different shapes. According to one or more embodiments of the present disclosure, the first green light emitting layer G1_EL and the second green light emitting layer G2_EL may have different shapes on substantially the same plane. The first green anode electrode G1_AE and the second green anode electrode G2_AE may have different sizes and shapes.

[0104] The red light emitting element ED_R may be electrically connected to the red pixel driving circuit R_PD. For example, the red light emitting element ED_R may include a red anode electrode R_AE and a red light emitting layer R_EL, and the red anode electrode R_AE may be connected to the red pixel driving circuit R_PD through a contact hole. The blue light emitting element ED_B may be electrically connected to the blue pixel driving circuit B_PD. For example, the blue light emitting element ED_B may include a blue anode electrode B_AE and a blue light emitting layer B_EL, and the blue anode electrode B_AE may be connected to the blue pixel driving circuit B_PD through a contact hole.

[0105] Each of the sensors FX may include a light sensing unit LSU and a sensor driving circuit O_SD. The light sensing unit LSU may include at least one light receiving element. According to one or more embodiments of the present disclosure, the light sensing unit LSU may include k light receiving elements, and one of the k light receiving elements may be connected to the sensor driving circuit O_SD. Here, k may be a natural number greater than or equal to 1. Figure 4AA case where k is 2 is shown. When k is 2, the light sensing unit LSU may include two light receiving elements (hereinafter referred to as the first light receiving element OPD1 and the second light receiving element OPD2). According to one or more embodiments of the present disclosure, two light receiving elements (for example, the first light receiving element OPD1 and the second light receiving element OPD2) may be positioned to correspond to one reference pixel unit RPU. However, the number of light receiving elements positioned corresponding to each reference pixel unit RPU is not limited thereto. For example, one light receiving element may be positioned to correspond to each reference pixel unit RPU.

[0106] Each of the first light receiving element OPD1 and the second light receiving element OPD2 may be located between the red light emitting element ED_R and the blue light emitting element ED_B in the second direction DR2. Each of the first light receiving element OPD1 and the second light receiving element OPD2 may be adjacent to the first green light emitting element ED_G1 or the second green light emitting element ED_G2 in the first direction DR1. In the first reference pixel unit row, the first light receiving element OPD1 and the first green light emitting element ED_G1 may be adjacent to each other in the first direction DR1, and the second light receiving element OPD2 and the second green light emitting element ED_G2 may be adjacent to each other in the first direction DR1. In the second reference pixel unit row, the first light receiving element OPD1 and the second green light emitting element ED_G2 may be adjacent to each other in the first direction DR1, and the second light receiving element OPD2 and the first green light emitting element ED_G1 may be adjacent to each other in the first direction DR1. According to one or more embodiments of the present disclosure, each of the first light receiving element OPD1 and the second light receiving element OPD2 may be located between the first green light emitting element ED_G1 and the second green light emitting element ED_G2 , and may be adjacent to each other in the first direction DR1 .

[0107] The first light receiving element OPD1 and the second light receiving element OPD2 may have substantially the same size and shape as each other. Each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a size smaller than the red light emitting element ED_R and the blue light emitting element ED_B. According to one or more embodiments of the present disclosure, the size of each of the first light receiving element OPD1 and the second light receiving element OPD2 may be less than or equal to the size of the first green light emitting element ED_G1 and the second green light emitting element ED_G2. However, the size of each of the first light receiving element OPD1 and the second light receiving element OPD2 is not limited, and various modifications and applications may be made. Each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a shape different from that of the red light emitting element ED_R and the blue light emitting element ED_B. According to one or more other embodiments of the present disclosure, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a square shape. The shape of each of the first light receiving element OPD1 and the second light receiving element OPD2 is not limited thereto. Alternatively, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a rectangular shape that is longer in the first direction DR1 than in the second direction DR2 .

[0108] The sensor driving circuit O_SD may be connected to one of the first light receiving element OPD1 and the second light receiving element OPD2 (e.g., the first light receiving element OPD1). The sensor driving circuit O_SD may have substantially the same length as the red pixel driving circuit R_PD and the blue pixel driving circuit B_PD in the first direction DR1. The sensor driving circuit O_SD may overlap one of the first light receiving element OPD1 and the second light receiving element OPD2 (e.g., the first light receiving element OPD1) on a plane. The sensor driving circuit O_SD may overlap one of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 (e.g., the first green light emitting element ED_G1) on a plane.

[0109] The first light receiving element OPD1 may include a first sensing anode electrode O_AE1 and a first photoelectric conversion layer O_RL1, and the second light receiving element OPD2 may include a second sensing anode electrode O_AE2 and a second photoelectric conversion layer O_RL2. The first sensing anode electrode O_AE1 may be directly connected to the sensor driving circuit O_SD through a contact hole.

[0110] Each of the sensors FX may further include a routing line RW electrically connecting the first light receiving element OPD1 and the second light receiving element OPD2 to each other. The routing line RW may be electrically connected to the first sensing anode electrode O_AE1 and the second sensing anode electrode O_AE2. According to one or more embodiments of the present disclosure, the routing line RW may be integrally formed with the first sensing anode electrode O_AE1 and the second sensing anode electrode O_AE2.

[0111] The routing line RW, the first sensing anode electrode O_AE1, and the second sensing anode electrode O_AE2 may be located on the same layer as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE. In this case, the routing line RW, the first sensing anode electrode O_AE1, and the second sensing anode electrode O_AE2 may include substantially the same material as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE, and may be provided by substantially the same process as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE.

[0112] The first light receiving element OPD1 and the second light receiving element OPD2 can be connected in parallel with the sensor driving circuit O_SD through the routing line RW. Therefore, the first light receiving element OPD1 and the second light receiving element OPD2 can be turned on or off synchronously or substantially simultaneously by the sensor driving circuit O_SD. The first light receiving element OPD1 connected to the sensor driving circuit O_SD can be referred to as a main light receiving element. The second light receiving element OPD2 electrically connected to the first light receiving element OPD1 through the routing line RW can be referred to as a dummy light receiving element.

[0113] like Figure 4B As shown in , when k is 4, the light sensing unit LSUa may include four light receiving elements (hereinafter referred to as the first light receiving element OPD1, the second light receiving element OPD2, the third light receiving element OPD3, and the fourth light receiving element OPD4). One of the first light receiving element OPD1, the second light receiving element OPD2, the third light receiving element OPD3, and the fourth light receiving element OPD4 (for example, the third light receiving element OPD3) may be connected to the sensor driving circuit O_SDa.

[0114] Each of the sensors FX may also include three routing lines (hereinafter referred to as the first routing line RW1, the second routing line RW2, and the third routing line RW3) that electrically connect the first light receiving element OPD1, the second light receiving element OPD2, the third light receiving element OPD3, and the fourth light receiving element OPD4 to each other. The first routing line RW1 may electrically connect two light receiving elements (e.g., the first light receiving element OPD1 and the third light receiving element OPD3) that are adjacent to each other in the first direction DR1 among the four light receiving elements OPD1, OPD2, OPD3, and OPD4. The second routing line RW2 may electrically connect two light receiving elements (e.g., the first light receiving element OPD1 and the second light receiving element OPD2) that are adjacent to each other in the second direction DR2 among the four light receiving elements OPD1, OPD2, OPD3, and OPD4. The third routing line RW3 can electrically connect two light receiving elements (e.g., the third light receiving element OPD3 and the fourth light receiving element OPD4) adjacent to each other in the second direction DR2 among the four light receiving elements OPD1, OPD2, OPD3, and OPD4. The third light receiving element OPD3 directly connected to the sensor driving circuit O_SDa can be referred to as a main light receiving element. The remaining first light receiving element OPD1, second light receiving element OPD2, and fourth light receiving element OPD4 can be referred to as dummy light receiving elements.

[0115] The first light receiving element OPD1 may include a first sensing anode electrode O_AE1 and a first photoelectric conversion layer O_RL1. The second light receiving element OPD2 may include a second sensing anode electrode O_AE2 and a second photoelectric conversion layer O_RL2. The third light receiving element OPD3 may include a third sensing anode electrode O_AE3 and a third photoelectric conversion layer O_RL3. The fourth light receiving element OPD4 may include a fourth sensing anode electrode O_AE4 and a fourth photoelectric conversion layer O_RL4. The third sensing anode electrode O_AE3 may be directly connected to the sensor driving circuit O_SDa through a contact hole. The sensor driving circuit O_SDa may have a length greater than that of the red pixel driving circuit R_PD and the blue pixel driving circuit B_PD in the first direction DR1. Therefore, the sensor driving circuit O_SDa may be positioned to overlap with two of the first light receiving element OPD1 to the fourth light receiving element OPD4 (e.g., the first light receiving element OPD1 and the third light receiving element OPD3) on a plane. The sensor driving circuit O_SDa may overlap two green light emitting elements (eg, the first green light emitting element ED_G1 and the second green light emitting element ED_G2 ) on a plane.

[0116] The first routing line RW1 may be electrically connected to the first sensing anode electrode O_AE1 and the third sensing anode electrode O_AE3. The second routing line RW2 may be electrically connected to the first sensing anode electrode O_AE1 and the second sensing anode electrode O_AE2. The third routing line RW3 may be electrically connected to the third sensing anode electrode O_AE3 and the fourth sensing anode electrode O_AE4. According to one or more embodiments of the present disclosure, the first to third routing lines RW1 to RW3 may be integrally formed with the first to fourth sensing anode electrodes O_AE1 to O_AE4.

[0117] The first routing line RW1, the second routing line RW2, and the third routing line RW3, and the first to fourth sensing anode electrodes O_AE1 to O_AE4 may be located on the same layer as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE. In this case, the first routing line RW1, the second routing line RW2, and the third routing line RW3, and the first to fourth sensing anode electrodes O_AE1 to O_AE4 may include substantially the same material as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE, and may be provided by substantially the same process as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE.

[0118] The first light receiving element OPD1, the second light receiving element OPD2, the third light receiving element OPD3 and the fourth light receiving element OPD4 can be connected in parallel with the sensor driving circuit O_SDa through the first routing line RW1, the second routing line RW2 and the third routing line RW3. Therefore, the first light receiving element OPD1, the second light receiving element OPD2, the third light receiving element OPD3 and the fourth light receiving element OPD4 can be turned on or off synchronously or substantially simultaneously by the sensor driving circuit O_SDa.

[0119] The sensor driving circuits O_SD and O_SDa may include a plurality of transistors. According to one or more embodiments of the present disclosure, the sensor driving circuits O_SD and O_SDa and the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD may be formed synchronously or substantially simultaneously through substantially the same process as each other. In addition, the scan driver 300 (see Figure 3 ) may include transistors formed by substantially the same process as the sensor driving circuits O_SD and O_SDa and the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD.

[0120] Figure 5 is a circuit diagram showing pixels and sensors of a display panel according to one or more embodiments of the present disclosure.

[0121] Figure 5 Shows Figure 3 An equivalent circuit diagram of one pixel PX among the plurality of pixels PX is shown in . Because the plurality of pixels PX have substantially the same circuit structure as each other, and the circuit structure of the pixel PX is described below, a detailed description of the remaining pixels PX will be omitted.

[0122] also, Figure 5 Shows Figure 3 An equivalent circuit diagram of one sensor FX among the plurality of sensors FX is shown in . Since the plurality of sensors FX have substantially the same circuit structure as each other, and the circuit structure of the sensor FX is described below, a detailed description of the remaining sensors FX will be omitted.

[0123] refer to Figure 5 , the pixels PX can be connected to the data lines DL1 to DLm (see Figure 3 ) in the i-th data line DLi, the initialization scan lines SIL1 to SILn (see Figure 3 ) in the j-th initialization scan line SILj, the compensation scan lines SCL1 to SCLn (see Figure 3 ) in the j-th compensation scanning line SCLj, the writing scanning lines SWL1 to SWLn (see Figure 3 ) in the j-th write scan line SWLj, the black scan lines SBL1 to SBLn (see Figure 3 ) and the j-th black scan line SBLj, and the light emission control lines EML1 to EMLn (see Figure 3 ) in the j-th light emitting control line EMLj (wherein 1≤i≤m, and 1≤j≤n).

[0124] The pixel PX may include a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may be a light emitting diode. According to one or more embodiments of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer. The pixel driving circuit PDC may be electrically connected to the light emitting element ED to control the operation of the light emitting element ED.

[0125] The pixel driving circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may have a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may have an oxide semiconductor layer. One or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor, and one or more of the other transistors thereof may be an N-type transistor. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS transistor, and the third transistor T3 and the fourth transistor T4 may be an NMOS transistor. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be low temperature polysilicon semiconductor transistors.

[0126] The configuration of the pixel driving circuit PDC according to one or more embodiments of the present disclosure is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel driving circuit PDC shown in is only an example, and the configuration of the pixel driving circuit PDC may be modified. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors or N-type transistors.

[0127] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal BSj, and the jth emission control signal EMj to the pixel PX, respectively. The i-th data line DLi can transmit the i-th data signal DSi to the pixel PX. The i-th data signal DSi can have the same value as that input to the display device DD (see Figure 3 ) of the image signal RGB (see Figure 3 ) corresponds to the voltage level.

[0128] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS, respectively, to the pixels PX. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT1 and VINT2, respectively, to the pixels PX.

[0129] The first transistor T1 may be connected between the light emitting element ED and a first driving voltage line VL1 receiving a first driving voltage ELVDD. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a sixth transistor T6, a second electrode connected to a pixel anode electrode P_AN of the light emitting element ED via a seventh transistor T7, and a third electrode connected to one end of the capacitor Cst (e.g., one end connected to the first node ND1). According to a switching operation of the second transistor T2, the first transistor T1 may receive an i-th data signal DSi transmitted by an i-th data line DLi, and may provide a driving current Id to the light emitting element ED.

[0130] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode connected to the j-th write scan line SWLj. The second transistor T2 may be turned on according to the j-th write scan signal SWj received through the j-th write scan line SWLj, and may then transmit the i-th data signal DSi that may be transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0131] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node ND1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode (or the second node ND2) of the first transistor T1, and a third electrode connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal SCj received through the j-th compensation scan line SCLj, and may connect the third electrode and the second electrode of the first transistor T1 to each other, thereby enabling diode-connection of the first transistor T1.

[0132] The fourth transistor T4 may be connected between the first node ND1 and the first initialization voltage line VL3 to which the first initialization voltage VINT1 may be applied. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3, a second electrode connected to the first node ND1, and a third electrode connected to the jth initialization scan line SILj. The fourth transistor T4 may be turned on according to the jth initialization scan signal SIj received through the jth initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT1 to the first node ND1 to initialize the potential of the third electrode of the first transistor T1 (e.g., the potential of the first node ND1).

[0133] The sixth transistor T6 may include a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a third electrode connected to the j-th light emitting control line EMLj.

[0134] The seventh transistor T7 may include a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the pixel anode electrode P_AN of the light emitting element ED, and a third electrode connected to the j-th light emitting control line EMLj.

[0135] The sixth transistor T6 and the seventh transistor T7 are synchronously or substantially simultaneously turned on according to the jth emission control signal EMj received through the jth emission control line EMLj. The first driving voltage ELVDD applied by the turned-on sixth transistor T6 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED.

[0136] The fifth transistor T5 may include a first electrode connected to a second initialization voltage line VL4, a second electrode connected to a second electrode of the seventh transistor T7, and a third electrode connected to a black scan line SBLj, wherein the second initialization voltage VINT2 may be transmitted to the second initialization voltage line VL4. The voltage level of the second initialization voltage VINT2 may be lower than or equal to the voltage level of the first initialization voltage VINT1.

[0137] As described above, one end of the capacitor Cst may be connected to the third electrode of the first transistor T1 , and the other end thereof may be connected to the first driving voltage line VL1 .

[0138] The pixel cathode electrode P_CA of the light emitting element ED may be connected to a second driving voltage line VL2 that transmits a second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD. According to one or more embodiments of the present disclosure, the second driving voltage ELVSS may have a voltage level lower than the first initialization voltage VINT1 and the second initialization voltage VINT2.

[0139] According to one or more embodiments of the present disclosure, in the display panel DP (see Figure 3 ), the jth light emitting control signal EMj may include a light emitting period and a non-light emitting period. During the non-light emitting period, the jth light emitting control signal EMj may have a high level. During the non-light emitting period, the jth initialization scan signal SIj may be activated. During the activation period (hereinafter referred to as the first activation period) of the jth initialization scan signal SIj, when the jth initialization scan signal SIj having a high level is provided through the jth initialization scan line SILj, the fourth transistor T4 may be turned on in response to the jth initialization scan signal SIj having a high level. The first initialization voltage VINT1 may be transmitted to the third electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first node ND1 may be initialized by the first initialization voltage VINT1. Therefore, the first activation period may be defined as the initialization period of the pixel PX.

[0140] Next, when the jth compensation scan signal SCj is activated during an activation period (hereinafter referred to as a second activation period) of the jth compensation scan signal SCj and the jth compensation scan signal SCj having a high level is provided through the jth compensation scan line SCLj, the third transistor T3 may be turned on. The first transistor T1 may be diode-connected by the turned-on third transistor T3 and biased in a forward direction. The first activation period may not overlap with the second activation period.

[0141] The j-th write scan signal SWj may be activated in the second activation period. The j-th write scan signal SWj has a low level during the activation period (hereinafter referred to as the fourth activation period). During the fourth activation period, the second transistor T2 may be turned on by the j-th write scan signal SWj having a low level. Then, in the i-th data signal DSi provided from the i-th data line DLi, a compensation voltage may be applied to the third electrode of the first transistor T1, and the compensation voltage may be reduced by about the threshold voltage of the first transistor T1. For example, the potential of the third electrode of the first transistor T1 may be the compensation voltage. The fourth activation period may overlap with the second activation period. The duration of the second activation period may be greater than the duration of the fourth activation period.

[0142] The first driving voltage ELVDD and the compensation voltage may be applied to both ends of the capacitor Cst. Charge corresponding to the voltage difference between both ends of the capacitor Cst may be stored in the capacitor Cst. Here, the high level period of the j-th compensation scan signal SCj may be referred to as a compensation period of the pixel PX.

[0143] The jth black scan signal BSj may be activated in the second activation period of the jth compensation scan signal SCj. The jth black scan signal BSj may have a low level during the activation period (hereinafter referred to as the third activation period). During the third activation period, the fifth transistor T5 may be turned on by receiving the jth black scan signal BSj having a low level via the jth black scan line SBLj. A portion of the drive current Id may escape through the fifth transistor T5 as a bypass current Ibp. The third activation period may overlap with the second activation period. The duration of the second activation period may be greater than the duration of the third activation period. The third activation period may be before the fourth activation period and may not overlap with the fourth activation period.

[0144] In the case where the pixel PX displays a black image, when the light emitting element ED emits light, although the minimum driving current of the first transistor T1 flows as the driving current Id, the pixel PX may not display the black image normally. Therefore, the fifth transistor T5 according to one or more embodiments of the present disclosure can disperse a part of the minimum driving current of the first transistor T1 as a bypass current Ibp to another current path other than the current path toward the light emitting element ED. When the minimum driving current is applied to the first transistor T1, if the gate-source voltage of the first transistor T1 is lower than the threshold voltage, the leakage current may flow to the first transistor T1, so that the first transistor T1 is turned off. If the first transistor T1 is turned off, the minimum driving current (for example, a current of about 10pA or less) flowing to the first transistor T1 can be transmitted to the light emitting element ED, and a black grayscale image can be displayed. When the pixel PX displays a black image, the influence of the bypass current Ibp on the minimum driving current is relatively large. When the pixel PX displays an image such as a general image or a white image, the bypass current Ibp has almost no effect on the driving current Id. Therefore, when a black image is displayed, a current (e.g., a light emitting current Ied) reduced by the amount of the bypass current Ibp (removed from the driving current Id and passing through the fifth transistor T5) can be transmitted to the light emitting element ED, so that a black image can be properly displayed. Therefore, the pixel PX can realize an accurate black grayscale image by using the fifth transistor T5, and thus, the contrast can be improved.

[0145] Next, the j-th light emitting control signal EMj provided from the j-th light emitting control line EMLj may be changed from a high level to a low level. Each of the sixth transistor T6 and the seventh transistor T7 may be turned on by the j-th light emitting control signal EMj having a low level. Then, a driving current Id may be generated according to a voltage difference between a voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD. The driving current Id may be provided to the light emitting element ED through the seventh transistor T7, so that the light emitting current Ied flows through the light emitting element ED.

[0146] refer to Figure 5 , the sensor FX can be connected to the readout lines RL1 to RLh (see Figure 3 ) in the d-th readout line RLd (where 1≤d≤h), the j-th write scan line SWLj and the sensing control line CL.

[0147] The sensor FX may include a light receiving element OPD and a sensing drive circuit SDC. The light receiving element OPD may be a photodiode. According to one or more embodiments of the present disclosure, the light receiving element OPD may be an organic photodiode, which may include an organic material as a photoelectric conversion layer. The anode electrode O_AN (hereinafter referred to as the sensing anode electrode) of the light receiving element OPD may be connected to the first sensing node SN1. The cathode electrode O_CA (hereinafter referred to as the sensing cathode electrode) of the light receiving element OPD may be connected to a second drive voltage line VL2, which transmits a second drive voltage ELVSS. The sensing drive circuit SDC may be electrically connected to the light receiving element OPD to control the operation of the light receiving element OPD.

[0148] The sensing drive circuit SDC may include three transistors ST1 to ST3. The three transistors ST1 to ST3 may be a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. According to one or more embodiments of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, it is not limited thereto, and for example, at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0149] In addition, one or more of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be a P-type transistor, and the other transistors among them may be an N-type transistor. According to one or more embodiments of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, it is not limited thereto, and in one or more other embodiments, for example, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be N-type transistors, or all of them may be P-type transistors.

[0150] One or more of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (e.g., the reset transistor ST1) may be transistors of substantially the same type as the third transistor T3 and the fourth transistor T4 of the pixel PX. The amplifying transistor ST2 and the output transistor ST3 may be transistors of substantially the same type as the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 of the pixel PX.

[0151] The circuit configuration of the sensing drive circuit SDC according to one or more embodiments of the present disclosure is not limited to Figure 5 Circuit configuration. Figure 5 The sensing drive circuit SDC shown in FIG. 1 is only one example, and the configuration of the sensing drive circuit SDC may be modified and implemented.

[0152] The reset transistor ST1 may include a first electrode connected to a reset receiving line VL5 receiving a reset voltage RST, a second electrode connected to a first sensing node SN1, and a third electrode connected to a sensing control line CL receiving a sensing control signal CS. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage RST in response to the sensing control signal CS. According to one or more embodiments of the present disclosure, the sensing control signal CS may be a jth compensation scan signal SCj provided from the jth compensation scan line SCLj. In this case, the sensing control line CL may be electrically connected to the jth compensation scan line SCLj. For example, the reset transistor ST1 may receive the jth compensation scan signal SCj provided from the jth compensation scan line SCLj as the sensing control signal CS. However, the present disclosure is not limited thereto. The sensing control line CL may be electrically insulated from the scan lines SWLj, SCLj, SILj, and SBLj. Alternatively, the sensing control signal CS may be a signal separated from the jth compensation scan signal SCj. The timing at which the sensing control signal CS is activated and the timing at which the jth compensation scan signal SCj is activated may be different from each other.

[0153] According to one or more embodiments of the present disclosure, the reset voltage RST may be a DC voltage maintained at a voltage level lower than the second driving voltage ELVSS. However, the present disclosure is not limited thereto. The reset voltage RST may have a voltage level lower than the second driving voltage ELVSS at least during the activation period of the sensing control signal CS. According to one or more other embodiments of the present disclosure, the reset voltage RST may be generated as the same voltage as any one of the first initialization voltage VINT1 and the second initialization voltage VINT2.

[0154] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series with each other. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter referred to as a first sub-reset transistor and a second sub-reset transistor). In this case, the third electrode of the first sub-reset transistor and the third electrode of the second sub-reset transistor may be connected to the sensing control line CL. In addition, the second electrode of the first sub-reset transistor may be electrically connected to the first electrode of the second sub-reset transistor. In addition, the reset voltage RST may be applied to the first electrode of the first sub-reset transistor, and the second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto, and various modifications may be made.

[0155] The amplifying transistor ST2 may include a first electrode connected to a sensing drive line SVL receiving a sensing drive voltage SVD, a second electrode connected to a second sensing node SN2, and a third electrode connected to a first sensing node SN1. The amplifying transistor ST2 may be turned on according to the potential of the first sensing node SN1 so that the sensing drive voltage SVD may be applied to the second sensing node SN2. According to one or more embodiments of the present disclosure, the sensing drive voltage SVD may be one of a first driving voltage ELVDD and a first initialization voltage VINT1 and a second initialization voltage VINT2. When the sensing drive voltage SVD is the first driving voltage ELVDD, the sensing drive line SVL may be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SVD is the first initialization voltage VINT1, the sensing drive line SVL may be electrically connected to the first initialization voltage line VL3. When the sensing drive voltage SVD is the second initialization voltage VINT2, the sensing drive line SVL may be electrically connected to the second initialization voltage line VL4.

[0156] The output transistor ST3 may include a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode connected to the output control line receiving the output control signal. The output transistor ST3 may transmit the dth sensing signal FSd to the dth readout line RLd in response to the output control signal. The output control signal may be a jth write scan signal SWj provided through the jth write scan line SWLj. For example, the output transistor ST3 may receive the jth write scan signal SWj provided from the jth write scan line SWLj as the output control signal.

[0157] The light receiving element OPD of the sensor FX may be exposed to the light emitted from the light emitting element ED. According to one or more embodiments of the present disclosure, the light receiving element OPD may generate photocharges corresponding to the received light, and the generated photocharges may be accumulated in the first sensing node SN1. For example, when the user's hand US_F (see Figure 1 ) Touch display device DD (see Figure 1 ) of the display surface IS (see Figure 1 ) and the light emitting element ED emits light, the light receiving element OPD receives the light emitted from the light emitting element ED by the user's hand US_F (see Figure 1 ) reflected light, and can generate photocharges corresponding to the received reflected light.

[0158] When the output transistor ST3 is turned on, the dth sensing signal FSd flowing from the sensing drive line SVL through the amplifying transistor ST2 and the output transistor ST3 to the dth readout line RLd is determined by the amount of charge of the first sensing node SN1. According to one or more embodiments of the present disclosure, when the output transistor ST3 is a P-type transistor, the larger the amount of photocharge generated by the light receiving element OPD and stored in the first sensing node SN1, the smaller the size of the dth sensing signal FSd may be.

[0159] Figure 6 is a cross-sectional view illustrating a pixel and a sensor of a display device according to one or more embodiments of the present disclosure.

[0160] refer to Figure 6 , the display panel DP may include a base layer BL, a circuit layer DP_CL located on the base layer BL, a device layer DP_ED, and an encapsulation layer TFE.

[0161] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may be a polyimide-based resin layer, but its material is not limited thereto. The synthetic resin layer may include at least any one of an acrylic-based resin, a methacrylic-based resin, polyisoprene, an ethylene-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In addition, the base layer may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0162] The circuit layer DP_CL may be located on the base layer BL. According to one or more embodiments of the present disclosure, the circuit layer DP_CL may include Figure 5 According to one or more other embodiments of the present disclosure, Figure 6 The pixel driving circuit PDC (see FIG. Figure 5 ), such as a pixel transistor P_TR. According to one or more other embodiments of the present disclosure, the pixel transistor P_TR may be electrically connected to a light emitting element ED included in the element layer DP_ED. According to one or more other embodiments of the present disclosure, the pixel transistor P_TR may be connected to a pixel driving circuit PDC (see Figure 5 ) of the seventh transistor T7 (see Figure 5 However, the present disclosure is not limited thereto, and the transistor corresponding to the pixel transistor P_TR in the pixel driving circuit PDC may vary according to the circuit configuration of the pixel.

[0163] In addition, according to one or more embodiments of the present disclosure, Figure 6 The sensing driving circuit SDC included in the circuit layer DP_CL is shown (see Figure 5 ) part of the configuration, for example, the sensor transistor O_TR. According to one or more other embodiments of the present disclosure, the sensor transistor O_TR may be connected to the sensing drive circuit SDC (see Figure 5 ) of the reset transistor ST1 (see Figure 5 ) corresponding transistor. However, the present disclosure is not limited thereto, and corresponds to the sensing drive circuit SDC (see Figure 5 ) in the sensor transistor O_TR can vary depending on the circuit configuration of the sensor.

[0164] The element layer DP_ED may be located on the circuit layer DP_CL. According to one or more embodiments of the present disclosure, the element layer DP_ED may include a light emitting element ED, a light receiving element OPD, and an element defining film PDL. According to one or more other embodiments of the present disclosure, the light emitting element ED may include a first green light emitting element ED_G1 and a second green light emitting element ED_G2 (see Figure 4A )、Red light emitting element ED_R (see Figure 4A ) and blue light emitting element ED_B (see Figure 4A ). Although the light emitting element ED Figure 6 , are illustrated as light emitting elements ED, but the description applied to the light emitting elements ED may be equally applied to the first and second green light emitting elements ED_G1 and ED_G2, the red light emitting element ED_R, and the blue light emitting element ED_B.

[0165] According to one or more embodiments of the present disclosure, the light emitting element ED may include a pixel anode electrode P_AN (or a first pixel electrode), a pixel hole auxiliary layer P_HCL, a light emitting layer P_EL, a pixel electron auxiliary layer P_ECL and a pixel cathode electrode P_CA (or a second pixel electrode).

[0166] According to one or more embodiments of the present disclosure, the light receiving element OPD may include a sensing anode electrode O_AN (or a first sensing electrode), a sensing hole auxiliary layer O_HCL, a photoelectric conversion layer PCL, a sensing electron auxiliary layer O_ECL and a sensing cathode electrode O_CA (or a second sensing electrode).

[0167] The pixel anode electrode P_AN and the sensing anode electrode O_AN are located on the circuit layer DP_CL. The pixel anode electrode P_AN may be connected to the pixel transistor P_TR by passing through a contact hole of an insulating layer included in the circuit layer DP_CL. However, the present disclosure is not limited thereto, and the pixel anode electrode P_AN may be connected to a connection electrode electrically connected to the pixel transistor P_TR by passing through a contact hole of an insulating layer included in the circuit layer DP_CL. The sensing anode electrode O_AN may be connected to the sensor transistor O_TR by passing through a contact hole of an insulating layer included in the circuit layer DP_CL. However, the present disclosure is not limited thereto, and the sensing anode electrode O_AN may be connected to a connection electrode electrically connected to the sensor transistor O_TR by passing through a contact hole of an insulating layer included in the circuit layer DP_CL.

[0168] The element defining film PDL is located on the circuit layer DP_CL, the pixel anode electrode P_AN and the sensing anode electrode O_AN. The first opening OP1 of the element defining film PDL exposes at least a portion of the pixel anode electrode P_AN. The second opening OP2 of the element defining film PDL exposes at least a portion of the sensing anode electrode O_AN.

[0169] According to one or more embodiments of the present disclosure, a plurality of pixels PX (see Figure 3 ) may be arranged in a regular pattern on the display panel DP (see Figure 3 ) plane. A plurality of pixels PX are arranged therein (see Figure 3 ) may be defined as a pixel region, and one pixel region may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA.

[0170] According to one or more embodiments of the present disclosure, the light emitting region PXA may include a green light emitting region in which a green pixel is positioned, a red light emitting region in which a red pixel is positioned, and a blue light emitting region in which a blue pixel is positioned. Figure 6 Only the light emitting region PXA is shown in FIG. 1 , but the light emitting region PXA may correspond to at least one of a green light emitting region, a red light emitting region, and a blue light emitting region. The first opening OP1 of the element defining film PDL may define the light emitting region PXA.

[0171] According to one or more embodiments of the present disclosure, the non-luminescent region NPXA may include a green non-luminescent region adjacent to the green luminescent region, a red non-luminescent region adjacent to the red luminescent region, and a blue non-luminescent region adjacent to the blue luminescent region. Figure 6 Only the non-luminescent region NPXA is shown in FIG. 1 , but the non-luminescent region NPXA may correspond to at least one of a green non-luminescent region, a red non-luminescent region, and a blue non-luminescent region.

[0172] According to one or more embodiments of the present disclosure, a plurality of sensors FX (see Figure 3 ) may be arranged in a regular pattern on the display panel DP (see Figure 3 ) plane. There are multiple sensors FX (see Figure 3 ) may be defined as a light receiving sensing area, and one light receiving sensing area may include a sensing area SA and a non-sensing area NSA adjacent to the sensing area SA. According to one or more embodiments of the present disclosure, the second opening OP2 of the element defining film PDL may define the sensing area SA. The non-sensing area NSA may surround the sensing area SA (e.g., in a plan view).

[0173] In one or more embodiments of the present disclosure, the element-defining film PDL may further include a black material. The element-defining film PDL may further include a black organic dye / pigment such as carbon black or aniline black. The element-defining film PDL may be formed by mixing a blue organic material and a black organic material. The element-defining film PDL may further include a liquid-repelling organic material.

[0174] The pixel hole auxiliary layer P_HCL may be located on the pixel anode electrode P_AN. The sensing hole auxiliary layer O_HCL may be located on the sensing anode electrode O_AN. The pixel hole auxiliary layer P_HCL may be located in a region corresponding to the first opening OP1. The pixel hole auxiliary layer P_HCL may not overlap with the non-light emitting area NPXA on a plane.

[0175] The sensing hole auxiliary layer O_HCL may be located on the sensing anode electrode O_AN. The sensing hole auxiliary layer O_HCL may be located in a region corresponding to the second opening OP2. The sensing hole auxiliary layer O_HCL may not overlap with the non-sensing area NSA on a plane.

[0176] According to one or more embodiments of the present disclosure, the pixel hole auxiliary layer P_HCL and the sensing hole auxiliary layer O_HCL may be electrically insulated from each other.

[0177] The light emitting layer P_EL may be located on the pixel hole auxiliary layer P_HCL. A plurality of light emitting layers P_EL may be located in a plurality of pixels PX. The light emitting layer P_EL may include a first green light emitting layer G1_EL and a second green light emitting layer G2_EL (see Figure 4A ), red light emitting layer R_EL (see Figure 4A ) and the blue light-emitting layer B_EL (see Figure 4A ). Figure 6 The light emitting layer P_EL is shown. The light emitting layer P_EL may correspond to the first green light emitting layer G1_EL and the second green light emitting layer G2_EL (see Figure 4A ), red light emitting layer R_EL (see Figure 4A ) and the blue light-emitting layer B_EL (see Figure 4A The light emitting layer P_EL may be located in a region corresponding to the first opening OP1.

[0178] The pixel electronic auxiliary layer P_ECL may be located on the light emitting layer P_EL. The pixel electronic auxiliary layer P_ECL may be commonly located on a plurality of pixels PX (see Figure 3). According to one or more embodiments of the present disclosure, the pixel electronic auxiliary layer P_ECL may be located in the light emitting area PXA and the non-light emitting area NPXA. The pixel electronic auxiliary layer P_ECL may include a green electronic auxiliary layer, a red electronic auxiliary layer, and a blue electronic auxiliary layer corresponding to the first green light emitting layer G1_EL and the second green light emitting layer G2_EL, the red light emitting layer R_EL, and the blue light emitting layer B_EL. In one or more other embodiments, the green electronic auxiliary layer, the red electronic auxiliary layer, and the blue electronic auxiliary layer may be electrically connected to each other.

[0179] The sensing electron auxiliary layer O_ECL may be located on the photoelectric conversion layer PCL. The sensing electron auxiliary layer O_ECL may be commonly located on a plurality of sensors FX (see Figure 3 ). According to one or more embodiments of the present disclosure, the sensing electronic auxiliary layer O_ECL may be located in the sensing area SA and the non-sensing area NSA. According to one or more other embodiments of the present disclosure, the pixel electronic auxiliary layer P_ECL and the sensing electronic auxiliary layer O_ECL may be electrically connected to each other. The pixel electronic auxiliary layer P_ECL and the sensing electronic auxiliary layer O_ECL may be commonly formed by processes substantially the same as each other.

[0180] Pixel cathode electrode P_CA (see Figure 5 ) may be located on the pixel electronic auxiliary layer P_ECL. The pixel cathode electrode P_CA (see Figure 5 ) may be commonly located in a plurality of pixels PX. According to one or more embodiments of the present disclosure, the pixel cathode electrode P_CA (see Figure 5 ) may be located in the light emitting region PXA and the non-light emitting region NPXA. The pixel cathode electrode P_CA (see Figure 5 ) may include a green cathode electrode, a red cathode electrode, and a blue cathode electrode corresponding to the first green light emitting layer G1_EL and the second green light emitting layer G2_EL, the red light emitting layer R_EL, and the blue light emitting layer B_EL. In one or more other embodiments, the green cathode electrode, the red cathode electrode, and the blue cathode electrode may be electrically connected to each other.

[0181] The sensing cathode electrode O_CA may be located on the sensing electron auxiliary layer O_ECL. The sensing cathode electrode O_CA may be commonly located in a plurality of sensors FX. According to one or more embodiments of the present disclosure, the sensing cathode electrode O_CA may be located in the sensing area SA and the non-sensing area NSA. According to one or more other embodiments of the present disclosure, the pixel cathode electrode P_CA and the sensing cathode electrode O_CA may be electrically connected to each other.

[0182] The sensing cathode electrode O_CA may include a first sensing electrode layer O_CAL1 and a second sensing electrode layer O_CAL2. The first sensing electrode layer O_CAL1 may be positioned to overlap with the sensing area SA and the non-sensing area NSA. The second sensing electrode layer O_CAL2 may be located on the first sensing electrode layer O_CAL1. The second sensing electrode layer O_CAL2 may overlap with the sensing area SA and may not overlap with the non-sensing area NSA. The first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 may be electrically connected to each other. The thickness of the sensing cathode electrode O_CA in the sensing area SA in which the second sensing electrode layer O_CAL2 is formed may be greater than the thickness of the sensing cathode electrode O_CA in the non-sensing area NSA in which the second sensing electrode layer O_CAL2 is not formed. Details on this point will be described later.

[0183] The capping layer CPL may be located on the pixel cathode electrode P_CA (see Figure 5 ) and the sensing cathode electrode O_CA. The capping layer CPL may include a multilayer or a single layer. In one or more embodiments of the present disclosure, the capping layer CPL may be an organic layer or an inorganic layer. For example, when the capping layer CPL includes an inorganic material, the capping layer CPL may include an alkali metal compound such as MgF2, etc. For example, when the capping layer CPL includes an organic material, the organic material may include α-NPD (N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine), NPB (N,N'-di(1-naphthyl)-N,N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenylbenzidine), m-MTDAT A ((4,4',4"-tri[phenyl(m-tolyl)amino]triphenylamine)), Alq3 (tris(8-hydroxyquinoline)aluminum(III)), CuPc (copper(II)phthalocyanine), TPD15 (N4,N4,N4',N4'-tetra(biphenyl-4-yl)biphenyl-4,4'-diamine), TCTA (4,4',4"-tri(carbazole-9-yl)triphenylamine), epoxy resin or acrylate (such as methacrylate). However, the present disclosure is not limited thereto.

[0184] The encapsulation layer TFE may be located on the capping layer CPL. The encapsulation layer TFE may cover a plurality of pixels PX (see Figure 3 ) and multiple sensor FX (see Figure 3). In one or more embodiments, the encapsulation layer TFE may directly cover the capping layer CPL. The encapsulation layer TFE may include at least one inorganic layer or one organic layer. In one or more other embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer located between the two inorganic layers. In one or more other embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers (hereinafter referred to as inorganic encapsulation layers) and a plurality of organic layers (hereinafter referred to as organic encapsulation layers) alternately stacked on top of each other. The inorganic encapsulation layer protects the light emitting element ED and the light receiving element OPD from moisture / oxygen. The organic encapsulation layer protects the light emitting element ED and the light receiving element OPD from foreign matter such as dust particles. The inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but the present disclosure is not limited thereto. The organic encapsulation layer may include an acrylic-based organic layer, but the present disclosure is not limited thereto.

[0185] The input sensing layer ISL may be directly located on the encapsulation layer TFE. The input sensing layer ISL may include a first conductive layer ICL1, a first insulating layer IIL1, a second conductive layer ICL2, and a second insulating layer IIL2. The first conductive layer ICL1 may be located on the encapsulation layer TFE. Figure 6 A structure in which the first conductive layer ICL1 is directly located on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto. The input sensing layer ISL may further include a basic insulating layer located between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the basic insulating layer, and the first conductive layer ICL1 may be located on the basic insulating layer. According to one or more embodiments of the present disclosure, the basic insulating layer may include an inorganic insulating material.

[0186] The first insulating layer IIL1 may cover the first conductive layer ICL1. The second conductive layer ICL2 may be located on the first insulating layer IIL1. Although a structure in which the input sensing layer ISL may include the first conductive layer ICL1 and the second conductive layer ICL2 is shown, the present disclosure is not limited thereto. For example, the input sensing layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0187] The second insulating layer IIL2 may be located on the second conductive layer ICL2. The second insulating layer IIL2 may include an organic insulating material. The second insulating layer IIL2 may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from not only moisture / oxygen but also foreign matter.

[0188] The color filter layer CFL may be located on the input sensing layer ISL. The color filter layer CFL may be located directly on the second insulating layer IIL2. The color filter layer CFL may include a color filter CF, a dummy color filter DCF, a black matrix BM, and an overcoat layer OCL.

[0189] The color filter CF may include a first color filter, a second color filter, and a third color filter. The first color filter may have a first color, the second color filter may have a second color, and the third color filter may have a third color. According to one or more embodiments of the present disclosure, the first color may be red, the second color may be green, and the third color may be blue. Figure 6 The color filter CF shown in FIG. 4 may correspond to one of the first color filter, the second color filter, and the third color filter.

[0190] According to one or more embodiments of the present disclosure, the dummy color filter DCF may be positioned to correspond to the sensing area SA. The dummy color filter DCF may overlap the sensing area SA and the non-sensing area NSA. According to one or more other embodiments of the present disclosure, the dummy color filter DCF may have a color substantially the same as one of the first color filter, the second color filter, and the third color filter. According to one or more other embodiments of the present disclosure, the dummy color filter DCF may have a green color substantially the same as the second color filter. However, the present disclosure is not limited thereto. The color filter layer CFL may not include the dummy color filter DCF.

[0191] The black matrix BM may be positioned to overlap the first conductive layer ICL1 and the second conductive layer ICL2. According to one or more embodiments of the present disclosure, the black matrix BM may overlap the non-luminous area NPXA and the non-sensing area NSA. In one or more other embodiments, the black matrix BM may overlap the first non-luminous area and the third non-luminous area. The black matrix BM may not overlap the luminous area PXA and the sensing area SA. According to one or more other embodiments of the present disclosure, a portion of the color filter CF may overlap the black matrix BM. In addition, a portion of the dummy color filter DCF may overlap the black matrix BM.

[0192] The outer coating OCL may include an organic insulating material. The outer coating OCL may be provided with a thickness sufficient to remove the step difference between the color filter CF and the dummy color filter DCF. The material of the outer coating OCL may have a predetermined thickness and may flatten the upper surface of the color filter layer CFL. For example, the outer coating OCL may include an acrylate-based organic material.

[0193] The window WM may be located on the color filter layer CFL.

[0194] 7A to 7C is an enlarged cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Fig. 7A A circuit layer DP_CL, a light emitting element ED, a light receiving element OPD, an element defining film PDL, a capping layer CPL, and an encapsulation layer TFE included in the display panel DP are illustrated. Hereinafter, descriptions of components substantially the same as those described above will be omitted.

[0195] refer to Fig. 7A , the element layer DP_ED may include a light emitting element ED, a light receiving element OPD, and an element defining film PDL. The light emitting element ED may include a pixel anode electrode P_AN, a pixel hole auxiliary layer P_HCL, a light emitting layer P_EL, a pixel electron auxiliary layer P_ECL, and a pixel cathode electrode P_CA. Hereinafter, for ease of explanation, the pixel anode electrode P_AN will be referred to as a first pixel electrode, and the pixel cathode electrode P_CA will be referred to as a second pixel electrode. The light emitting element ED may be electrically connected to a pixel transistor P_TR included in the circuit layer DP_CL.

[0196] A light-emitting region PXA overlapping the light-emitting layer P_EL and a non-light-emitting region NPXA surrounding the light-emitting region PXA may be defined in the element layer DP_ED. The light-emitting region PXA may be one of the green light-emitting region, the red light-emitting region, and the blue light-emitting region described above. In addition, the non-light-emitting region NPXA may be one of the green non-light-emitting region surrounding the green light-emitting region, the red non-light-emitting region surrounding the red light-emitting region, and the blue non-light-emitting region surrounding the blue light-emitting region described above.

[0197] The second pixel electrode P_CA may include a pixel electrode layer P_CAL. The pixel electrode layer P_CAL may be commonly located at a plurality of pixels PX (see Figure 3 ). According to one or more embodiments of the present disclosure, the pixel electrode layer P_CAL may be located in the light emitting area PXA and the non-light emitting area NPXA. The pixel electrode layer P_CAL may have a configuration substantially the same as the second pixel electrode P_CA. The pixel electrode layer P_CAL may include a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When the pixel electrode layer P_CAL is a transmissive electrode, the pixel electrode layer P_CAL may include a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). When the pixel electrode layer P_CAL is a semi-transmissive electrode or a reflective electrode, the pixel electrode layer P_CAL may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Yb, W, or a compound thereof (e.g., LiF) or a mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al.

[0198] The second pixel electrode P_CA may include a first pixel electrode portion P_CAP1 corresponding to the light emitting area PXA, and a second pixel electrode portion P_CAP2 corresponding to the non-light emitting area NPXA. The first pixel electrode portion P_CAP1 may overlap the light emitting area PXA in a plane, and thus may overlap the light emitting layer P_EL in a plane. The second pixel electrode portion P_CAP2 may overlap the non-light emitting area NPXA.

[0199] According to one or more embodiments of the present disclosure, the light receiving element OPD may include a sensing anode electrode O_AN, a sensing hole auxiliary layer O_HCL, a photoelectric conversion layer PCL, a sensing electron auxiliary layer O_ECL, and a sensing cathode electrode O_CA. Hereinafter, for ease of explanation, the sensing anode electrode O_AN will be referred to as a first sensing electrode, and the sensing cathode electrode O_CA will be referred to as a second sensing electrode.

[0200] A sensing area SA overlapping the photoelectric conversion layer PCL and a non-sensing area NSA surrounding the sensing area SA may be defined in the element layer DP_ED For example, the sensing area SA may be defined by the second opening OP2 of the element defining film PDL.

[0201] According to one or more embodiments of the present disclosure, the second sensing electrode O_CA may include a first sensing electrode layer O_CAL1 extending from the pixel electrode layer P_CAL, and a second sensing electrode layer O_CAL2 located on the first sensing electrode layer O_CAL1. The second sensing electrode layer O_CAL2 may be located on the first sensing electrode layer O_CAL1 in a portion overlapping with the photoelectric conversion layer PCL so as to correspond to the sensing area SA. The second sensing electrode layer O_CAL2 may be formed in a process separate from that of the first sensing electrode layer O_CAL1. The second sensing electrode layer O_CAL2 may be formed by using a separate mask after forming the first sensing electrode layer O_CAL1. Details on this point will be described later.

[0202] According to one or more embodiments of the present disclosure, the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 may include substantially the same material as each other. For example, each of the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 may include a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When each of the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 is a transmissive electrode, each of them may include a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). When each of the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 is a semi-transmissive electrode or a reflective electrode, each of them may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or a compound thereof (e.g., LiF) or a mixture thereof (e.g., a mixture of Ag and Mg), or include a material having a multilayer structure such as LiF / Ca or LiF / Al. However, not limited thereto, the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 may include different materials. The first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 directly contacting the first sensing electrode layer O_CAL1 may be electrically connected to each other.

[0203] The second sensing electrode O_CA may include a first sensing electrode portion O_CAP1 corresponding to the sensing area SA, and a second sensing electrode portion O_CAP2 corresponding to the non-sensing area NSA. The first sensing electrode portion O_CAP1 may overlap the photoelectric conversion layer PCL on a plane.

[0204] According to one or more embodiments of the present disclosure, the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the second sensing electrode O_CA may be different from each other. For example, the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the first sensing electrode portion O_CAP1 may be different from each other. The thickness Th2 of the first sensing electrode portion O_CAP1 may be greater than the thickness Th1 of the second pixel electrode P_CA. The first sensing electrode portion O_CAP1 may include a second sensing electrode layer O_CAL2 and a portion of the first sensing electrode layer O_CAL1. The first sensing electrode layer O_CAL1 may have a structure extending from the pixel electrode layer P_CAL. The thickness of the first sensing electrode layer O_CAL1 and the thickness Th1 of the second pixel electrode P_CA may be substantially the same as each other. The difference between the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the first sensing electrode portion O_CAP1 may be substantially the same as the thickness of the second sensing electrode layer O_CAL2.

[0205] According to one or more embodiments of the present disclosure, the thickness Th2 of the first sensing electrode portion O_CAP1 may be greater than the thickness Th3 of the second sensing electrode portion O_CAP2. Because the first sensing electrode portion O_CAP1 may include the second sensing electrode layer O_CAL2 and a portion of the first sensing electrode layer O_CAL1, and because the second sensing electrode portion O_CAP2 may include a portion of the first sensing electrode layer O_CAL1, the thickness Th2 of the first sensing electrode portion O_CAP1 may be greater than the thickness Th3 of the second sensing electrode portion O_CAP2 by the thickness of the second sensing electrode layer O_CAL2. The thickness Th3 of the second sensing electrode portion O_CAP2 may be substantially equal to the thickness Th1 of the second pixel electrode P_CA. The first sensing electrode layer O_CAL1 may be formed by substantially the same process as the second pixel electrode P_CA, and may have a structure extending from the pixel electrode layer P_CAL. Because the second sensing electrode portion O_CAP2 is composed of a portion of the first sensing electrode layer O_CAL1, the thickness Th3 of the second sensing electrode portion O_CAP2 and the thickness Th1 of the second pixel electrode P_CA may be substantially the same as each other. In addition, since the first sensing electrode layer O_CAL1 may be formed by substantially the same process as the pixel electrode layer P_CAL, the pixel electrode layer P_CAL and the first sensing electrode layer O_CAL1 may have an integral shape. The second sensing electrode O_CA may be electrically connected to the second pixel electrode P_CA through the first sensing electrode layer O_CAL1.

[0206] According to one or more embodiments of the present disclosure, a difference between a thickness Th1 of the second pixel electrode P_CA and a thickness Th2 of the second sensing electrode O_CA may be approximately to about For example, the thickness of the second sensing electrode layer O_CAL2 may be about to about Due to the thickness Th1 of the second pixel electrode P_CA, the light emitted from the light emitting layer P_EL can form a secondary resonance according to the wavelength of the light, thereby improving the light emission efficiency. In addition, due to the thickness Th2 of the second sensing electrode O_CA overlapping with the sensing area SA on the plane, the light reflected by the user's fingerprint can form a secondary resonance according to the wavelength of the reflected light, thereby improving the light receiving efficiency. Because the second pixel electrode P_CA and the second sensing electrode O_CA are electrically connected to each other, the greater the thickness of the second sensing electrode O_CA, the lower the total resistance of the second pixel electrode P_CA and the second sensing electrode O_CA. When the total resistance of the second pixel electrode P_CA and the second sensing electrode O_CA is reduced, the heating phenomenon of the display panel DP can be improved, and the heat generated by the pixel PX (see Figure 3) display quality. Since the display panel DP according to one or more embodiments of the present disclosure may include the second sensing electrode layer O_CAL2, the thickness Th2 of the second sensing electrode O_CA may be formed to be greater than the thickness Th1 of the second pixel electrode P_CA. Therefore, a reliable display panel DP may be provided.

[0207] refer to Figure 7B , the second pixel electrode P_CAa included in the light-emitting element EDa of the display panel DPa may include a first pixel electrode layer P_CAL1 located on the pixel electronic auxiliary layer P_ECL, and a second pixel electrode layer P_CAL2 located on the first pixel electrode layer P_CAL1. The second pixel electrode layer P_CAL2 may be located on the first pixel electrode layer P_CAL1 so as to correspond to the non-light-emitting area NPXA. The second pixel electrode layer P_CAL2 may not overlap with the light-emitting area PXA in a plane, and may overlap with the non-light-emitting area NPXA in a plane. The second pixel electrode layer P_CAL2 may be formed in a process separated from the process of the first pixel electrode layer P_CAL1. The second pixel electrode layer P_CAL2 may be formed by using a separate mask after forming the first pixel electrode layer P_CAL1. According to one or more embodiments of the present disclosure, the first pixel electrode layer P_CAL1 and the second pixel electrode layer P_CAL2 may contain substantially the same material as each other.

[0208] The second pixel electrode P_CAa included in the light emitting element EDa may include a first pixel electrode portion P_CAP1 corresponding to the light emitting area PXA and a second pixel electrode portion P_CAP2a corresponding to the non-light emitting area NPXA. The first pixel electrode portion P_CAP1 may overlap the light emitting area PXA on a plane, and the second pixel electrode portion P_CAP2a may overlap the non-light emitting area NPXA.

[0209] According to one or more embodiments of the present disclosure, the thickness Th1 of the first pixel electrode portion P_CAP1 and the thickness Th4 of the second pixel electrode portion P_CAP2a may be different from each other. For example, the thickness Th4 of the second pixel electrode portion P_CAP2a may be greater than the thickness Th1 of the first pixel electrode portion P_CAP1. The first pixel electrode portion P_CAP1 may include a portion of the first pixel electrode layer P_CAL1. The second pixel electrode portion P_CAP2a may include a second pixel electrode layer P_CAL2 and a portion of the first pixel electrode layer P_CAL1. Therefore, the difference between the thickness Th4 of the second pixel electrode portion P_CAP2a and the thickness Th1 of the first pixel electrode portion P_CAP1 may be substantially equal to the thickness of the second pixel electrode layer P_CAL2.

[0210] According to one or more embodiments of the present disclosure, the second sensing electrode O_CAa included in the light receiving element OPDa may include a first sensing electrode layer O_CAL1 extending from the first pixel electrode layer P_CAL1 and a second sensing electrode layer O_CAL2a located on the first sensing electrode layer O_CAL1. For example, the second sensing electrode layer O_CAL2a may be located on the first sensing electrode layer O_CAL1 so as to correspond to the sensing area SA and the non-sensing area NSA. The second sensing electrode layer O_CAL2a may be formed in a process separate from the process of the first sensing electrode layer O_CAL1. The second sensing electrode layer O_CAL2a may be formed by using a separate mask after forming the first sensing electrode layer O_CAL1. According to one or more other embodiments of the present disclosure, the first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2a may contain substantially the same material as each other.

[0211] The second sensing electrode O_CAa may include a first sensing electrode portion O_CAP1a corresponding to the sensing area SA and a second sensing electrode portion O_CAP2a corresponding to the non-sensing area NSA. The first sensing electrode portion O_CAP1a and the second sensing electrode portion O_CAP2a may overlap the sensing area SA and the non-sensing area NSA on a plane, respectively.

[0212] According to one or more embodiments of the present disclosure, thickness Th2 of first sensing electrode portion O_CAP1a and thickness Th3a of second sensing electrode portion O_CAP2a may be substantially the same as each other. Each of first sensing electrode portion O_CAP1a and second sensing electrode portion O_CAP2a may include first sensing electrode layer O_CAL1 and second sensing electrode layer O_CAL2a.

[0213] The thickness Th4 of the second pixel electrode portion P_CAP2a may be substantially equal to the thickness Th3a of the second sensing electrode portion O_CAP2a. The second pixel electrode layer P_CAL2 included in the second pixel electrode portion P_CAP2a may extend from the second sensing electrode layer O_CAL2a included in the second sensing electrode portion O_CAP2a. For example, the thickness Th4 of the second pixel electrode portion P_CAP2a, the thickness Th2 of the first sensing electrode portion O_CAP1a, and the thickness Th3a of the second sensing electrode portion O_CAP2a may be substantially the same as each other. The thickness Th1 of the first pixel electrode portion P_CAP1 including only the first pixel electrode layer P_CAL1 may be smaller than the thickness Th4 of the second pixel electrode portion P_CAP2a, smaller than the thickness Th2 of the first sensing electrode portion O_CAP1a, and smaller than the thickness Th3a of the second sensing electrode portion O_CAP2a. The difference between each of the thickness Th1 of the first pixel electrode portion P_CAP1 and the thickness Th4 of the second pixel electrode portion P_CAP2a, the thickness Th2 of the first sensing electrode portion O_CAP1a, and the thickness Th3a of the second sensing electrode portion O_CAP2a may be approximately to about

[0214] refer to Figure 7C , the second sensing electrode O_CAb included in the light receiving element OPDb may include a first sensing electrode layer O_CAL1a located on the sensing electron auxiliary layer O_ECL, and a second sensing electrode layer O_CAL2b located on the first sensing electrode layer O_CAL1a and extending from the pixel electrode layer P_CAL. For example, the first sensing electrode layer O_CAL1a may be located on the sensing electron auxiliary layer O_ECL so as to correspond to the sensing area SA and overlap the photoelectric conversion layer PCL in a plane. The second sensing electrode layer O_CAL2b may be located on the first sensing electrode layer O_CAL1a and the sensing electron auxiliary layer O_ECL so as to correspond to the sensing area SA and the non-sensing area NSA. The second sensing electrode layer O_CAL2b may be formed in a process separate from the process of the first sensing electrode layer O_CAL1a.

[0215] The second sensing electrode O_CAb may include a first sensing electrode portion O_CAP1b corresponding to the sensing area SA and a second sensing electrode portion O_CAP2 corresponding to the non-sensing area NSA. The first sensing electrode portion O_CAP1b may overlap the photoelectric conversion layer PCL on a plane.

[0216] When the general Figure 7C The display panel DPb shown in FIG. Fig. 7AWhen compared with the display panel DP shown in , the difference between them is that the positions of the first sensing electrode layer O_CAL1a and the second sensing electrode layer O_CAL2b are changed relative to each other. For example, the first sensing electrode layer O_CAL1a can be formed to overlap with the photoelectric conversion layer PCL on a plane by using a separate mask, and then the second sensing electrode layer O_CAL2b can be formed as a common layer together with the pixel electrode layer P_CAL.

[0217] According to one or more embodiments of the present disclosure, the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the second sensing electrode O_CAb may be different from each other. For example, the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the second sensing electrode O_CAb overlapping with the sensing area SA on a plane may be different from each other. The thickness Th2 of the second sensing electrode O_CAb overlapping with the sensing area SA on a plane may be greater than the thickness Th1 of the second pixel electrode P_CA. The difference between the thickness Th1 of the second pixel electrode P_CA and the thickness Th2 of the second sensing electrode O_CAb may be substantially the same as the thickness of the first sensing electrode layer O_CAL1a. The thickness of the first sensing electrode layer O_CAL1a may be about to about

[0218] FIG. 8A to FIG. 8G is a cross-sectional view for describing a step of forming a portion of a display device according to one or more embodiments of the present disclosure.

[0219] refer to Fig. 8A , a circuit layer DP_CL located on the base layer BL may be formed. The circuit layer DP_CL may include a pixel driving circuit PDC (see Figure 5 ) and the sensing drive circuit SDC (see Figure 5 ). Fig. 8A The pixel driving circuit PDC (see Figure 5 ) and a pixel transistor P_TR as part of a sensing drive circuit SDC (see Figure 5 ) is a part of the sensor transistor O_TR.

[0220] refer to Figure 8B , a first pixel electrode P_AN, a first sensing electrode O_AN, and an element defining film PDL may be formed. The first pixel electrode P_AN may be electrically connected to the pixel transistor P_TR through a contact hole passing through an insulating layer included in the circuit layer DP_CL. The first sensing electrode O_AN may be electrically connected to the sensor transistor O_TR through a contact hole passing through an insulating layer included in the circuit layer DP_CL.

[0221] The element defining film PDL may form an opening by patterning the preliminary insulating layer. For example, a first opening OP1 exposing a portion of the first pixel electrode P_AN and a second opening OP2 exposing a portion of the first sensing electrode O_AN may be formed. The element defining film PDL may include an organic insulating material. The element defining film PDL may also include a black material. In addition, the element defining film PDL may also include a black organic dye / pigment such as carbon black or aniline black.

[0222] refer to Figure 8C A pixel hole auxiliary layer P_HCL may be formed on the first pixel electrode P_AN, and a light emitting layer P_EL may be formed on the pixel hole auxiliary layer P_HCL. In addition, a sensing hole auxiliary layer O_HCL may be formed on the first sensing electrode O_AN, and a photoelectric conversion layer PCL may be formed on the sensing hole auxiliary layer O_HCL.

[0223] The pixel hole auxiliary layer P_HCL and the sensing hole auxiliary layer O_HCL may be formed in common. For example, the pixel hole auxiliary layer P_HCL and the sensing hole auxiliary layer O_HCL may be located as a common layer on the first pixel electrode P_AN, the first sensing electrode O_AN, and the element defining film PDL by using a physical vapor deposition method in common. Hereinafter, the pixel hole auxiliary layer P_HCL and the sensing hole auxiliary layer O_HCL may be formed to correspond to the openings OP1 and OP2 by patterning using a fine metal mask in an area overlapping the first opening OP1 and the second opening OP2.

[0224] Hereinafter, by using substantially the same fine metal mask, the light emitting layer P_EL may be formed to correspond to the first opening OP1 (see Figure 8B ), and the photoelectric conversion layer PCL may be formed to correspond to the second opening OP2 (see Figure 8B In one or more embodiments, a patterned light emitting layer P_EL is shown as an example, but the present disclosure is not limited thereto. A common light emitting layer may be commonly located in a plurality of pixels PX (see Figure 3 ). In this case, the common light-emitting layer can generate white light or blue light.

[0225] refer to Fig.8D , a common layer may be formed on the light emitting layer P_EL, the photoelectric conversion layer PCL, and the element definition film PDL. The common layer may be commonly located in a plurality of pixels PX (see Figure 3 ) and multiple sensor FX (see Figure 3 For example, the common layer may include the first opening OP1 (see Figure 8B ) corresponding to the pixel electronic auxiliary layer P_ECL, the second pixel electrode P_CA, and the second opening OP2 (see Figure 8B) corresponding to the sensing electron auxiliary layer O_ECL, and included in the second sensing electrode O_CA (see Figure 6 ) in the first sensing electrode layer O_CAL1. The sensing electron auxiliary layer O_ECL may extend from the pixel electron auxiliary layer P_ECL, and the first sensing electrode layer O_CAL1 may extend from the second pixel electrode P_CA. For example, the sensing electron auxiliary layer O_ECL and the pixel electron auxiliary layer P_ECL may be commonly formed in substantially the same process as each other, and the first sensing electrode layer O_CAL1 and the second pixel electrode P_CA may be commonly formed in substantially the same process as each other. In one or more embodiments, the second pixel electrode P_CAa (see Figure 7B ) may include a first pixel electrode layer P_CAL1 (see Figure 7B ) and a second pixel electrode layer P_CAL2 (see Figure 7B In this case, the first pixel electrode layer P_CAL1 (see Figure 7B ) and the first sensing electrode layer O_CAL1 may be integrally formed in substantially the same process as each other.

[0226] refer to Fig. 8E and Figure 8F , a second sensing electrode layer O_CAL2 may be formed on the first sensing electrode layer O_CAL1 to provide a second sensing electrode O_CA.

[0227] After forming the first sensing electrode layer O_CAL1 and the second pixel electrode P_CA, the second sensing electrode layer O_CAL2 may be formed on the first sensing electrode layer O_CAL1. For example, the second sensing electrode layer O_CAL2 may be formed on the first sensing electrode layer O_CAL1 in a region overlapping the photoelectric conversion layer PCL.

[0228] The second sensing electrode layer O_CAL2 may be formed by using a mask MSK located on the first sensing electrode layer O_CAL1. According to one or more embodiments of the present disclosure, the second sensing electrode layer O_CAL2 may be formed by deposition so as to correspond to the opening M_OP of the mask MSK. However, not limited thereto, a preliminary second sensing electrode layer may be formed on the second pixel electrode P_CA and the first sensing electrode layer O_CAL1, and by arranging a mask in an area overlapping with the photoelectric conversion layer PCL, the second sensing electrode layer O_CAL2 may be formed by a process of patterning the entire area except for the area overlapping with the photoelectric conversion layer PCL. The mask MSK may include a fine metal mask.

[0229] According to one or more embodiments of the present disclosure, the thickness of the second pixel electrode P_CA and the thickness of the second sensing electrode O_CA may be different from each other. For example, the thickness of the second pixel electrode P_CA and the thickness of the second sensing electrode O_CA overlapping with the photoelectric conversion layer PCL on a plane may be different from each other. The thickness of the second sensing electrode O_CA overlapping with the photoelectric conversion layer PCL on a plane may be greater than the thickness of the second pixel electrode P_CA. The thickness of the first sensing electrode layer O_CAL1 and the thickness of the second pixel electrode P_CA may be substantially the same as each other. Therefore, the difference between the thickness of the second sensing electrode O_CA overlapping with the photoelectric conversion layer PCL on a plane and the thickness of the second pixel electrode P_CA may be substantially equal to the thickness of the second sensing electrode layer O_CAL2.

[0230] The thickness of the second sensing electrode layer O_CAL2 may be about to about The first sensing electrode layer O_CAL1 and the second sensing electrode layer O_CAL2 may be electrically connected to each other. The second pixel electrode P_CA and the first sensing electrode layer O_CAL1 may be electrically connected to each other. Therefore, the second pixel electrode P_CA and the second sensing electrode O_CA may be electrically connected to each other. The greater the thickness of the second sensing electrode O_CA, the lower the total resistance of the second pixel electrode P_CA and the second sensing electrode O_CA. When the total resistance of the second pixel electrode P_CA and the second sensing electrode O_CA is reduced, the display panel DP (see Fig. 7A ) and can improve the heating phenomenon caused by the pixel PX (see Figure 3 ) display quality. Since the display panel DP according to one or more embodiments of the present disclosure may include the second sensing electrode layer O_CAL2, a reliable display panel DP (see Fig. 7A ).

[0231] In one or more embodiments, in the first sensing electrode layer O_CAL1a (see Figure 7C ) is formed to overlap with the photoelectric conversion layer PCL on a plane, the second sensing electrode layer O_CAL2b (see Figure 7C ) is formed as a common layer together with the pixel electrode layer P_CAL.

[0232] refer to Figure 8G , the capping layer CPL may be located on the second pixel electrode P_CA and the second sensing electrode O_CA. The capping layer CPL may include multiple layers or a single layer. In one or more embodiments of the present disclosure, the capping layer CPL may be an organic layer or an inorganic layer.

[0233] Since the display panel according to one or more embodiments of the present disclosure may include a second sensing electrode layer located on the first sensing electrode layer, the thickness of the second sensing electrode may be formed to be greater than the thickness of the second pixel electrode. Therefore, the resistance of the second sensing electrode and the second pixel electrode may be reduced, thereby providing a reliable display panel.

[0234] Although the above has been described with reference to one or more embodiments of the present disclosure, those skilled in the art or those of ordinary skill in the art will understand that various modifications and changes may be made to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the claims (functional equivalents of which shall be included therein).

[0235] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the specification but should be determined by the described claims (functional equivalents thereof will be included therein).

Claims

1. A display device, comprising: Base layer; a circuit layer, above the base layer; as well as A component layer, above the circuit layer, and comprising: a light emitting element, comprising a first pixel electrode electrically connected to the circuit layer, a light emitting layer above the first pixel electrode, and a second pixel electrode above the light emitting layer; as well as A light receiving element is adjacent to the light emitting element and includes a first sensing electrode electrically connected to the circuit layer, a photoelectric conversion layer above the first sensing electrode, and a second sensing electrode above the photoelectric conversion layer, and the second sensing electrode has a thickness different from that of the second pixel electrode.

2. The display device according to claim 1, wherein: The thickness of the second sensing electrode is greater than the thickness of the second pixel electrode.

3. The display device according to claim 2, wherein: The second pixel electrode includes a pixel electrode layer, and The second sensing electrode includes a first sensing electrode layer extending from the pixel electrode layer and a second sensing electrode layer above the first sensing electrode layer.

4. The display device according to claim 2, wherein: The second pixel electrode includes a pixel electrode layer, and The second sensing electrode includes a first sensing electrode layer and a second sensing electrode layer above the first sensing electrode layer and extending from the pixel electrode layer.

5. The display device according to claim 1, wherein: The element layer defines a light emitting region overlapping the light emitting layer in a plan view and a non-light emitting region surrounding the light emitting region.

6. The display device according to claim 5, wherein: The second pixel electrode includes a first pixel electrode portion corresponding to the light emitting area and a second pixel electrode portion corresponding to the non-light emitting area.

7. The display device according to claim 6, wherein: A thickness of the first pixel electrode portion is different from a thickness of the second pixel electrode portion.

8. The display device according to claim 7, wherein: The thickness of the second pixel electrode portion is greater than the thickness of the first pixel electrode portion.

9. The display device according to claim 7, wherein: The thickness of the second pixel electrode portion is equal to the thickness of the second sensing electrode.

10. The display device according to claim 1, wherein: The element layer defines a sensing region overlapping the photoelectric conversion layer and a non-sensing region surrounding the sensing region.

11. The display device according to claim 10, wherein: The second sensing electrode includes a first sensing electrode portion corresponding to the sensing area and a second sensing electrode portion corresponding to the non-sensing area.

12. The display device according to claim 11, wherein: A thickness of the first sensing electrode portion is different from a thickness of the second sensing electrode portion.

13. The display device according to claim 12, wherein: The thickness of the first sensing electrode portion is greater than the thickness of the second sensing electrode portion.

14. The display device according to claim 12, wherein: The thickness of the second sensing electrode portion is equal to the thickness of the second pixel electrode.

15. The display device according to claim 1, wherein: The second pixel electrode and the second sensing electrode are electrically connected to each other.

16. The display device according to claim 1, wherein: The circuit layer comprises: a pixel driving circuit electrically connected to the light emitting element to control the operation of the light emitting element; and A sensing drive circuit is electrically connected to the light receiving element to control the operation of the light receiving element.

17. The display device according to claim 16, comprising: a black matrix, over the element layer and including an opening; as well as A color filter is above the element layer and overlaps the opening.

18. A method for manufacturing a display device, the method comprising: forming a circuit layer over the base layer; as well as An element layer including a light emitting element and a light receiving element is formed above the circuit layer, and forming the element layer includes: forming a first pixel electrode of the light emitting element and a first sensing electrode of the light receiving element above the circuit layer; forming a light emitting layer above the first pixel electrode, and forming a photoelectric conversion layer above the first sensing electrode; and A second pixel electrode is formed on the light emitting layer, and a second sensing electrode is formed on the photoelectric conversion layer, wherein a thickness of the second sensing electrode is greater than a thickness of the second pixel electrode.

19. The method according to claim 18, wherein: Forming the second pixel electrode and the second sensing electrode includes: forming a first pixel electrode layer above the light emitting layer, and forming a first sensing electrode layer above the photoelectric conversion layer; and A second sensing electrode layer is formed above the first sensing electrode layer.

20. The method according to claim 19, wherein: The first pixel electrode layer and the first sensing electrode layer are formed integrally with each other.

Images