Display device, pixel circuit and driving method thereof

Abstract

The invention discloses a display device, a pixel circuit and a driving method thereof. The pixel circuit includes: a first storage sub-circuit (7) connected between a first node (N1) and a second node (N2); the driving sub-circuit (6) is used for controlling the connection or disconnection of the third node (N3) and the fourth node (N4) under the control of the first node (N1); the third node (N3) is connected with the first power supply end (VDD); the light-emitting control sub-circuit (5) is used for controlling the fourth node (N4) to be connected or disconnected with the first pole of the sub-pixel (L0); a second storage sub-circuit (10) for storing the potential of the first node (N1); the data writing sub-circuit (1) is used for inputting voltage to the second node (N2); the compensation sub-circuit (2) is used for controlling the connection or disconnection of the first node (N1) and the third node (N3) under the control of a first scanning signal end (Gate1 (n)); or is used for controlling the connection or disconnection of the first node (N1) and the fourth node (N4) under the control of the first scanning signal end (Gate1 (n)). The pixel circuit and the driving method thereof can improve the display effect of the display device.

Description

Display device, pixel circuit and driving method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device, a pixel circuit and a driving method thereof. Background Art

[0002] Organic electroluminescent displays (OLEDs) are a new generation of display products, following liquid crystal displays (LCDs). Due to their superior color saturation, fast response time, foldability, and thinness, they are gradually becoming the mainstream and leading display technology. However, OLEDs still require further improvement.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display device, a pixel circuit and a driving method thereof, which can improve the display effect.

[0005] According to one aspect of the present disclosure, there is provided a pixel circuit for a display device, the pixel circuit comprising:

[0006] A first storage sub-circuit connected between the first node and the second node;

[0007] a driving subcircuit connected to the first node, the third node, and the fourth node, and configured to control the third node to be connected to or disconnected from the fourth node under the control of the first node; the third node being connected to the first power supply terminal;

[0008] a light emitting control subcircuit connected to the fourth node and the first electrode of the sub-pixel, and configured to control the fourth node to be connected to or disconnected from the first electrode of the sub-pixel;

[0009] a second storage sub-circuit, connected to the first node, and configured to store the potential of the first node;

[0010] a data writing sub-circuit, connected to the second node, and configured to input a voltage to the second node;

[0011] a compensation sub-circuit connected to the first scan signal terminal and the first node;

[0012] The compensation sub-circuit is further connected to the third node, and is used to control the connection or disconnection between the first node and the third node under the control of the first scan signal terminal; or

[0013] The compensation sub-circuit is further connected to the fourth node, and is configured to control the connection or disconnection between the first node and the fourth node under the control of the first scan signal terminal.

[0014] Furthermore, in a display frame of the display device, the driving process of the pixel circuit includes a compensation phase and a data writing phase, and the compensation phase is before the data writing phase;

[0015] During the compensation phase, the compensation subcircuit controls the first node to be connected to the third node or the fourth node, the third node is connected to the first power supply terminal, and the data writing subcircuit inputs a first voltage to the second node;

[0016] During the data writing phase, the data writing sub-circuit inputs a second voltage to the second node.

[0017] Furthermore, the data writing phase includes a first phase and a second phase;

[0018] In the first stage, the compensation subcircuit controls the first node to be connected to the third node or the fourth node, the third node is connected to the first power supply terminal, and the data writing subcircuit inputs a second voltage to the second node;

[0019] In the second stage, the compensation sub-circuit controls the first node to be disconnected from the third node or the fourth node, and the data writing sub-circuit inputs a second voltage to the second node.

[0020] Furthermore, the pixel circuit further includes:

[0021] The first reset sub-circuit is connected to the reset signal terminal, the first initialization signal terminal and the first node, and is used to control the first initialization signal terminal to be connected or disconnected from the first node under the control of the first reset signal terminal.

[0022] Furthermore, the first reset sub-circuit includes:

[0023] A first reset transistor, wherein a control electrode of the first reset transistor is connected to the reset signal terminal, a first electrode of the first reset transistor is connected to the first initialization signal terminal, and a second electrode of the first reset transistor is connected to the first node.

[0024] Furthermore, the pixel circuit further includes:

[0025] a second reset sub-circuit, connected to the first scanning signal terminal, the second initialization signal terminal, and the first electrode of the sub-pixel, for controlling the connection or disconnection between the second initialization signal terminal and the first electrode of the sub-pixel under the control of the first scanning signal terminal;

[0026] The second reset sub-circuit includes:

[0027] A second reset transistor, wherein the control electrode of the second reset transistor is connected to the first scanning signal terminal, the first electrode of the second reset transistor is connected to the second initialization signal terminal, and the second electrode of the second reset transistor is connected to the first electrode of the sub-pixel.

[0028] Furthermore, the data writing sub-circuit includes:

[0029] A data writing transistor, wherein a control electrode of the data writing transistor is connected to the second scanning signal terminal, a first electrode of the data writing transistor is connected to the data signal terminal, and a second electrode of the data writing transistor is connected to the second node.

[0030] Furthermore, the driving sub-circuit includes:

[0031] A driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the fourth node.

[0032] Furthermore, the compensation sub-circuit includes:

[0033] A compensation transistor, wherein a control electrode of the compensation transistor is connected to the first scanning signal terminal, a first electrode of the compensation transistor is connected to the third node or the fourth node, and a second electrode of the compensation transistor is connected to the first node.

[0034] Furthermore, the light emitting control subcircuit is also connected to the first power supply terminal and the third node, and is used to control the connection or disconnection between the first power supply terminal and the third node.

[0035] Furthermore, the light emitting control subcircuit includes a first light emitting control transistor connected in series between the first power supply terminal and the third node.

[0036] Furthermore, the light emitting control subcircuit further includes a second light emitting control transistor connected in series between the fourth node and the first electrode of the sub-pixel.

[0037] Furthermore, the first storage sub-circuit includes a first capacitor, and the second storage sub-circuit includes a second capacitor.

[0038] According to one aspect of the present disclosure, a driving method for a pixel circuit is provided. The driving method is used for the pixel circuit, and the driving method includes:

[0039] enabling the driving sub-circuit to control the third node and the fourth node to be connected or disconnected under the control of the first node;

[0040] The light emitting control subcircuit controls the fourth node to be connected to or disconnected from the first electrode of the sub-pixel;

[0041] enabling the second storage sub-circuit to store the potential of the first node;

[0042] enabling the data writing sub-circuit to input a voltage to the second node;

[0043] The compensation subcircuit controls the first node and the third node to be connected or disconnected under the control of the first scan signal terminal; or, the compensation subcircuit controls the first node and the fourth node to be connected or disconnected under the control of the first scan signal terminal.

[0044] According to one aspect of the present disclosure, a display device is provided, comprising the pixel circuit and a sub-pixel connected to the pixel circuit.

[0045] The display device, pixel circuit, and driving method thereof disclosed herein, during a driving process, cause a driving subcircuit to control the third node to be connected to a fourth node, and cause a compensation subcircuit to control the first node to be connected to the third node or the fourth node. Since the third node is connected to a first power supply terminal, the first node can be charged via the first power supply terminal to compensate for the threshold voltage of the driving subcircuit, thereby solving the problem of poor display effect caused by different threshold voltages, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure.

[0047] FIG. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0048] FIG3( a ), FIG3 ( b ), and FIG3 ( c ) are operation timing diagrams of the pixel circuit shown in FIG2 .

[0049] FIG. 4 is another circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0050] FIG5 is an operation timing diagram of the pixel circuit shown in FIG4 .

[0051] FIG. 6 is another circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0052] FIG7 is an operation timing diagram of the pixel circuit shown in FIG6 .

[0053] FIG. 8 is another circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0054] FIG9 is an operation timing diagram of the pixel circuit shown in FIG8 .

[0055] FIG. 10 is a schematic diagram showing the arrangement of sub-pixels of a display device according to an embodiment of the present disclosure.

[0056] Explanation of the accompanying symbols: 1. data writing subcircuit; 2. compensation subcircuit; 3. first reset subcircuit; 4. second reset subcircuit; 5. light-emitting control subcircuit; 6. driving subcircuit; 7. first storage subcircuit; 8. sub-pixel row; 9. sub-pixel column; 10. second storage subcircuit; EM1(n), first light-emitting control signal terminal; EM2(n), second light-emitting control signal terminal; Gate1(n-1), reset signal terminal; Gate1(n), first scan signal terminal; Gate2(n), second scan signal terminal; Init1, first initialization signal terminal; Init2 , second initialization signal terminal; VDD, first power supply terminal; VSS, second power supply terminal; C1, first capacitor; C2, second capacitor; Data, data signal terminal; L0, sub-pixel; EM(n), light-emitting control signal terminal; EM(n-1), auxiliary control signal terminal; T1, first reset transistor; T2, compensation transistor; T3, driving transistor; T4, data writing transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, second reset transistor; N1, first node; N2, second node; N3, third node; N4, fourth node. DETAILED DESCRIPTION

[0057] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0058] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar words used in this disclosure and the claims do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are for ease of description only and are not limited to a single position or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. When describing some embodiments, the terms "connected" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "connected" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0059] The transistors used in the present disclosure can be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0060] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0061] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. When the transistor is a thin film transistor, the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0062] An embodiment of the present disclosure provides a pixel circuit. The pixel circuit is used for a display device. As shown in Figure 10, the display device may include multiple sub-pixels L0 and multiple pixel circuits, and the multiple pixel circuits are connected to the multiple sub-pixels L0 in a one-to-one correspondence. The multiple sub-pixels L0 include multiple first sub-pixels, multiple second sub-pixels and multiple third sub-pixels. The first sub-pixels, the second sub-pixels and the third sub-pixels have different luminous colors. For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light. The above-mentioned multiple sub-pixels L0 can be distributed in an array and constitute multiple sub-pixel rows 8 and multiple sub-pixel columns 9. A sub-pixel row 8 includes multiple sub-pixels L0 distributed along the row direction, and a sub-pixel column 9 includes multiple sub-pixels L0 distributed along the column direction. Among them, a first sub-pixel, a second sub-pixel and a third sub-pixel can constitute a pixel. The above-mentioned multiple sub-pixels L0 can form multiple pixels.

[0063] As shown in FIG1 , the pixel circuit may include a first storage subcircuit 7, a driving subcircuit 6, a light emitting control subcircuit 5, a second storage subcircuit 10, a data writing subcircuit 1, and a compensation subcircuit 2, wherein:

[0064] The first storage sub-circuit 7 is connected between the first node N1 and the second node N2. The driving sub-circuit 6 is connected to the first node N1, the third node N3, and the fourth node N4, and is configured to control the connection or disconnection between the third node N3 and the fourth node N4 under the control of the first node N1. The third node N3 is connected to the first power supply terminal VDD. The light-emitting control sub-circuit 5 is connected to the fourth node N4 and the first electrode of the sub-pixel L0, and is configured to control the connection or disconnection between the fourth node N4 and the first electrode of the sub-pixel L0. The second storage sub-circuit 10 is connected to the first node N1 and is configured to store the potential of the first node N1. The data writing sub-circuit 1 is connected to the second node N2 and is configured to input a voltage to the second node N2. The compensation sub-circuit 2 is connected to the first scan signal terminal Gate1(n) and the first node N1. In which, the compensation sub-circuit 2 is also connected to the third node N3, and is used to control the connection or disconnection of the first node N1 and the third node N3 under the control of the first scanning signal terminal Gate1(n); or, the compensation sub-circuit 2 is also connected to the fourth node N4, and is used to control the connection or disconnection of the first node N1 and the fourth node N4 under the control of the first scanning signal terminal Gate1(n).

[0065] In the pixel circuit of the embodiment of the present disclosure, during the driving process, the driving sub-circuit 6 controls the third node N3 to be connected to the fourth node N4, and the compensation sub-circuit 2 controls the first node N1 to be connected to the third node N3 or the fourth node N4. Since the third node N3 is connected to the first power supply terminal VDD, the first node N1 can be charged by the first power supply terminal VDD to compensate for the threshold voltage of the driving sub-circuit 6, thereby solving the problem of poor display effect caused by different threshold voltages, thereby improving the display effect.

[0066] The following describes in detail the various components of the pixel circuit according to the embodiment of the present disclosure:

[0067] As shown in Figures 1 and 2, the first storage sub-circuit 7 is connected between a first node N1 and a second node N2. For example, the first storage sub-circuit 7 may include a first capacitor C1. A first electrode of the first capacitor C1 is connected to the first node N1, and a second electrode of the first capacitor C1 is connected to the second node N2.

[0068] As shown in Figures 1 and 2, the driver sub-circuit 6 is connected to a first node N1, a third node N3, and a fourth node N4, and is configured to control the connection or disconnection between the third node N3 and the fourth node N4 under the control of the first node N1. For example, the driver sub-circuit 6 may include a driver transistor T3, wherein a control electrode of the driver transistor T3 is connected to the first node N1, a first electrode of the driver transistor T3 is connected to the third node N3, and a second electrode of the driver transistor T3 is connected to the fourth node N4. The third node N3 may be connected to a first power supply terminal VDD.

[0069] As shown in Figures 1 and 2, the data writing sub-circuit 1 is connected to the second node N2 and is used to input a voltage to the second node N2. For example, the data writing sub-circuit 1 may include a data writing transistor T4. The control electrode of the data writing transistor T4 is connected to the second scanning signal terminal Gate2(n), the first electrode of the data writing transistor T4 is connected to the data signal terminal Data, and the second electrode of the data writing transistor T4 is connected to the second node N2. For a plurality of pixel circuits connected one-to-one with a plurality of sub-pixels L0 located in a sub-pixel row 8, the second scanning signal terminal Gate2(n) connected to the data writing sub-circuit 1 of each pixel circuit can be connected to the same signal line. For two pixel circuits connected one-to-one with two sub-pixels L0 located in different sub-pixel rows 8, the second scanning signal terminal Gate2(n) connected to the data writing sub-circuit 1 of the two pixel circuits are connected to different signal lines.

[0070] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a first reset subcircuit 3. The first reset subcircuit 3 is connected to the reset signal terminal Gate1(n-1), the first initialization signal terminal Init1, and the first node N1, and is configured to control the connection or disconnection of the first initialization signal terminal Init1 with the first node N1 under the control of the first reset signal terminal Gate1(n-1). For example, the first reset subcircuit 3 may include a first reset transistor T1. The control electrode of the first reset transistor T1 is connected to the reset signal terminal Gate1(n-1), the first electrode of the first reset transistor T1 is connected to the first initialization signal terminal Init1, and the second electrode of the first reset transistor T1 is connected to the first node N1.

[0071] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a second reset subcircuit 4. The second reset subcircuit 4 is connected to the first scan signal terminal Gate1(n), the second initialization signal terminal Init2, and the first electrode of the subpixel L0, and is used to control the second initialization signal terminal Init2 to connect or disconnect with the first electrode of the subpixel L0 under the control of the first scan signal terminal Gate1(n). For example, the second reset subcircuit 4 may include a second reset transistor T7. The control electrode of the second reset transistor T7 is connected to the first scan signal terminal Gate1(n), the first electrode of the second reset transistor T7 is connected to the second initialization signal terminal Init2, and the second electrode of the second reset transistor T7 is connected to the first electrode of the subpixel L0. The plurality of subpixel rows 8 include adjacent (n-1)th subpixel rows and nth subpixel rows, where n is greater than or equal to 2. The pixel circuit connected to the subpixel L0 in the (n-1)th subpixel row is referred to as the (n-1)th level pixel circuit, and the pixel circuit connected to the subpixel L0 in the nth subpixel row is referred to as the nth level pixel circuit. The reset signal terminal connected to the first reset sub-circuit 3 in the n-th pixel circuit and the first scanning signal terminal connected to the second reset sub-circuit 4 in the (n-1)-th pixel circuit are connected to the same signal line.

[0072] As shown in Figures 1 and 2, the second storage sub-circuit 10 is connected to the first node N1 and is configured to store the potential of the first node N1. For example, the second storage sub-circuit 10 may include a second capacitor C2. A first electrode of the second capacitor C2 is connected to the first node N1, and a second electrode of the first capacitor C1 is connected to the second power supply terminal VSS.

[0073] As shown in Figure 8 , the compensation sub-circuit 2 is connected to the first scan signal terminal Gate1(n) and the first node N1. The compensation sub-circuit 2 is also connected to the third node N3 and is configured to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scan signal terminal Gate1(n). For example, the compensation sub-circuit 2 includes a compensation transistor T2. The control electrode of the compensation transistor T2 is connected to the first scan signal terminal Gate1(n), the first electrode of the compensation transistor T2 is connected to the third node N3, and the second electrode of the compensation transistor T2 is connected to the first node N1.

[0074] In another embodiment, as shown in Figures 1 and 2, the compensation sub-circuit 2 is connected to the first scan signal terminal Gate1(n), the first node N1, and the fourth node N4, and is configured to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the first scan signal terminal Gate1(n). For example, the compensation sub-circuit 2 includes a compensation transistor T2. The control electrode of the compensation transistor T2 is connected to the first scan signal terminal Gate1(n), the first electrode of the compensation transistor T2 is connected to the fourth node N4, and the second electrode of the compensation transistor T2 is connected to the first node N1.

[0075] As shown in Figures 1 and 6, the light-emission control subcircuit 5 is connected to the fourth node N4 and the first electrode of the sub-pixel L0, and is used to control whether the fourth node N4 is connected to the first electrode of the sub-pixel L0. For example, the light-emission control subcircuit 5 may include a second light-emission control transistor T6. The control electrode of the second light-emission control transistor T6 is connected to the light-emission control signal terminal EM(n), the first electrode of the second light-emission control transistor T6 is connected to the fourth node N4, and the second electrode of the second light-emission control transistor T6 is connected to the first electrode of the sub-pixel L0. The second electrode of the sub-pixel L0 may be connected to the second power supply terminal VSS.

[0076] In another embodiment, as shown in FIG2 , the light control subcircuit 5 is connected to a first power supply terminal VDD, a first light control signal terminal EM1(n), a third node N3, a fourth node N4, a second light control signal terminal EM2(n), and a first electrode of a sub-pixel L0. The subcircuit 5 is configured to control the connection or disconnection between the first power supply terminal VDD and the third node N3 under the control of the first light control signal terminal EM1(n), and to control the connection or disconnection between the fourth node N4 and the first electrode of the sub-pixel L0 under the control of the second light control signal terminal EM2(n). For example, the light control subcircuit 5 may include a first light control transistor T5 and a second light control transistor T6. The control electrode of the first light control transistor T5 is connected to the first light control signal terminal EM1(n), and the first light control transistor T5 is connected in series between the first power supply terminal VDD and the third node N3. That is, the first electrode of the first light control transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the first light control transistor T5 is connected to the third node N3. The control electrode of the second light-emitting control transistor T6 is connected to the second light-emitting control signal terminal EM2(n), and the second light-emitting control transistor T6 is connected in series between the fourth node N4 and the first electrode of the sub-pixel L0. That is, the first electrode of the second light-emitting control transistor T6 is connected to the fourth node N4, and the second electrode of the second light-emitting control transistor T6 is connected to the first electrode of the sub-pixel L0.

[0077] In another embodiment, as shown in FIG4 , the light control subcircuit 5 is connected to a first power supply terminal VDD, an auxiliary control signal terminal EM(n-1), a third node N3, a fourth node N4, the light control signal terminal EM(n), and a first electrode of the subpixel L0. The subcircuit 5 is configured to control the connection or disconnection between the first power supply terminal VDD and the third node N3 under the control of the auxiliary control signal terminal EM(n-1), and to control the connection or disconnection between the fourth node N4 and the first electrode of the subpixel L0 under the control of the light control signal terminal EM(n). For example, the light control subcircuit 5 may include a first light control transistor T5 and a second light control transistor T6. The control electrode of the first light control transistor T5 is connected to the auxiliary control signal terminal EM(n-1), the first electrode of the first light control transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the first light control transistor T5 is connected to the third node N3. The control electrode of the second light control transistor T6 is connected to the light control signal terminal EM(n), the first electrode of the second light control transistor T6 is connected to the fourth node N4, and the second electrode of the second light control transistor T6 is connected to the first electrode of the subpixel L0. The auxiliary control signal terminal connected to the light emitting control subcircuit 5 in the n-th pixel circuit and the light emitting control signal terminal connected to the light emitting control subcircuit 5 in the (n-1)-th pixel circuit are connected to the same signal line.

[0078] As shown in Figures 2 and 3(a), in a display frame of the display device, the driving process of the pixel circuit includes an initialization phase S1, a compensation phase S2, a data writing phase S3, and a light-emitting phase S4. The initialization phase S1 precedes the compensation phase S2, which precedes the data writing phase S3, and the light-emitting phase S4 follows the data writing phase S3. During the compensation phase S2, the compensation sub-circuit 2 controls the first node N1 to connect to the third node N3 or the fourth node N4. The third node N3 is connected to the first power supply terminal VDD, which charges the first node N1. The data writing sub-circuit 1 inputs a first voltage to the second node N2. During the data writing phase S3, the data writing sub-circuit 1 inputs a second voltage to the second node N2. Furthermore, as shown in Figure 3(b), the data writing phase S3 can include a first phase and a second phase. During the first phase (from time t0 to time (t0+T)), the compensation sub-circuit 2 connects the first node N1 to the third node N3 or the fourth node N4, connects the third node N3 to the first power supply terminal VDD, and the data writing sub-circuit 1 inputs the second voltage to the second node N2. During the second phase (from time (t0+T) to time t1), the compensation sub-circuit 2 disconnects the first node N1 from the third node N3 or the fourth node N4, and the data writing sub-circuit 1 inputs the second voltage to the second node N2.

[0079] The operation process of the pixel circuit in FIG2 will be described in detail below in conjunction with the operation timing diagram of the pixel circuit shown in FIG3(a), wherein, taking the above-mentioned transistor as a P-type transistor as an example, the conduction level is a low level.

[0080] As shown in Figures 2 and 3(a), in the initialization stage S1, the first scanning signal terminal Gate1(n), the first light-emitting control signal terminal EM1(n) and the second light-emitting control signal terminal EM2(n) are high, the reset signal terminal Gate1(n-1) and the second scanning signal terminal Gate2(n) are low, the first reset transistor T1 is turned on, the potential VN1 of the first node N1 is written as Vinit1 by the first initialization signal terminal Init1, the data write transistor T4 is turned on, and the data signal terminal Data inputs the first voltage (VH) to the second node N2, that is, the potential VN2 of the second node N2 is written as VH by the data signal terminal Data; the voltage across the first capacitor C1 is reset.

[0081] As shown in Figures 2 and 3(a), in the compensation stage S2, the reset signal terminal Gate1(n-1) and the second light-emitting control signal terminal EM2(n) are high, the first scanning signal terminal Gate1(n), the first light-emitting control signal terminal EM1(n) and the second scanning signal terminal Gate2(n) are low, the second reset transistor T7 is turned on, the first electrode of the sub-pixel L0 is reset, the first light-emitting control transistor T5, the driving transistor T3 and the compensation transistor T2 are turned on, the first power supply terminal VDD is connected to the first node N1, and when the potential VN1 of the first node N1 is written as [Vdd+Vth(T3)], the driving transistor T3 is turned off, and Vdd is the potential of the first power supply terminal VDD; the data writing transistor T4 remains on, and the potential VN2 of the second node N2 remains at VH.

[0082] As shown in FIG2 and FIG3(a), in the data writing phase S3, the potential of the data signal terminal Data changes from the first voltage (VH) to the second voltage (VL), the reset signal terminal Gate1(n-1), the first scan signal terminal Gate1(n), the first light-emitting control signal terminal EM1(n), and the second light-emitting control signal terminal EM2(n) are high, the second scan signal terminal Gate2(n) is low, the data writing transistor T4 is turned on, and the data signal terminal Data inputs the second voltage (VL) to the second node N2, that is, the potential VN2 of the second node N2 changes from VH to VL. Under the coupling effect of the first capacitor C1, the potential VN1 of the first node N1 also changes, specifically as follows: VN1=Vdd+Vth+△V*C1 / (C1+C2);

[0083] Wherein, Vth is the threshold voltage of the driving transistor, ΔV is the change in potential of the data signal terminal Data from VH to VL, that is, ΔV=VL-VH.

[0084] As shown in Figures 2 and 3(a), in the light-emitting stage S4, the reset signal terminal Gate1(n-1), the first scan signal terminal Gate1(n) and the second scan signal terminal Gate2(n) are high, the first light-emitting control signal terminal EM1(n) and the second light-emitting control signal terminal EM2(n) are low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the sub-pixel L0 emits light.

[0085] In the light-emitting stage S4, the gate-source voltage of the driving transistor T3 is Vgs=VN1-Vdd=Vth+ΔV*C1 / (C1+C2); the driving transistor T3 operates in the saturation region, and the calculation formula of its light-emitting current Ioled is:

[0086] Here, k = μ*Cox*(W / L), where μ is the mobility of the driver transistor T3, Cox is the gate oxide capacitance, and W / L is the width-to-length ratio of the driver transistor T3's channel. The calculation formula for Ioled shows that Ioled is independent of the potential of the first power supply terminal VDD (Vdd) and the threshold voltage (Vth) of the driver transistor T3. This compensates for these factors, resulting in improved display uniformity.

[0087] The operation process of the pixel circuit in FIG2 will be described in detail below in conjunction with the operation timing diagram of the pixel circuit shown in FIG3(b), wherein, taking the above-mentioned transistor as a P-type transistor as an example, the conduction level is a low level.

[0088] As shown in Figures 2 and 3(b), in the initialization stage S1, the first scanning signal terminal Gate1(n), the first light-emitting control signal terminal EM1(n) and the second light-emitting control signal terminal EM2(n) are high, the reset signal terminal Gate1(n-1) and the second scanning signal terminal Gate2(n) are low, the first reset transistor T1 is turned on, the potential VN1 of the first node N1 is written as Vinit1 by the first initialization signal terminal Init1, the data write transistor T4 is turned on, and the data signal terminal Data inputs the first voltage (VH) to the second node N2, that is, the potential VN2 of the second node N2 is written as VH by the data signal terminal Data; the voltage across the first capacitor C1 is reset.

[0089] As shown in Figures 2 and 3(b), during the compensation phase S2, the reset signal terminal Gate1(n-1) and the second light-emitting control signal terminal EM2(n) are high, the first scan signal terminal Gate1(n), the first light-emitting control signal terminal EM1(n), and the second scan signal terminal Gate2(n) are low, the second reset transistor T7 is turned on, the first electrode of the sub-pixel L0 is reset, the first light-emitting control transistor T5, the driving transistor T3, and the compensation transistor T2 are turned on, the first power supply terminal VDD is connected to the first node N1, and when the potential VN1 of the first node N1 is written to [VDD+Vth(T3)], the driving transistor T3 is turned off; the data writing transistor T4 remains on, and the potential VN2 of the second node N2 remains at VH. It can be seen that compared with the timing diagram shown in Figure 3(a), the operation process of the pixel circuit in the initialization phase S1 and the compensation phase S2 in the timing diagram shown in Figure 3(b) is consistent with that in Figure 3(a).

[0090] As shown in FIG2 and FIG3(b), in the data writing phase S3, when t0 < time t < (t0 + T), the potential of the data signal terminal Data changes from the first voltage (VH) to the second voltage (VL), the second scanning signal terminal Gate2(n) is low, and the data writing transistor T4 is turned on; at time t0, the data signal terminal Data inputs the second voltage (VL) to the second node N2, that is, the potential VN2 of the second node N2 changes from VH to VL. Under the coupling effect of the first capacitor C1, the potential VN1(t0) of the first node N1 at time t0 also changes, specifically as follows: VN1(t0) = Vdd + Vth + ΔV*C1 / (C1 + C2);

[0091] At time t0, the gate-source voltage Vgs of the driving transistor T3 is: Vgs(t0)=VN1(t0)-Vdd=Vth+ΔV*C1 / (C1+C2) Formula 1;

[0092] Here, ΔV is the change in potential at the data signal terminal Data from VH to VL, that is, ΔV=VL-VH.

[0093] When t0 < time t < (t0 + T), the first scanning signal terminal Gate1(n) and the first light-emitting control signal terminal EM1(n) remain low, and the first power supply terminal VDD continues to charge the first node N1. The first stage is the stage between time t0 and time (t0 + T).

[0094] At time (t0+T), since the first power supply terminal VDD continues to charge the first node N1 during the time interval T, the potential VN1(t0+T) of the first node N1 at time (t0+T) increases by ΔW compared to VN1(t0), as shown in the following example:

[0095] At the moment (t0+T), the gate-source voltage Vgs of the driving transistor T3 is:

[0096] From formula 1 and formula 2, we can get:

[0097] According to the law of charge conservation, the following formula can be obtained:

[0098] In Formula 4, k=μ*Cox*(W / L), μ is the mobility of the driving transistor T3, Cox is the gate oxide layer capacitance, and W / L is the width-to-length ratio of the channel of the driving transistor T3.

[0099] Integrating formula 4, we can get the following formula:

[0100] From formula 5, we can get:

[0101] From Formula 1, Formula 3, and Formula 6, we can get:

[0102] In the data writing phase S3, when time t>(t0+T), the gate-source voltage of the driving transistor T3 remains unchanged. The second phase is the phase from (t0+T) to the cut-off time (t1) in the data writing phase S3.

[0103] As shown in Figures 2 and 3(b), in the light-emitting stage S4, the reset signal terminal Gate1(n-1), the first scan signal terminal Gate1(n) and the second scan signal terminal Gate2(n) are high, the first light-emitting control signal terminal EM1(n) and the second light-emitting control signal terminal EM2(n) are low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the sub-pixel L0 emits light.

[0104] In the light emitting stage S4, the gate-source voltage of the driving transistor T3 is:

[0105] The driving transistor T3 operates in the saturation region, and the calculation formula of its light-emitting current Ioled is:

[0106] In the related art, when mobility drifts, the value of the light-emitting current will change. For example, when the mobility increases, the light-emitting current will increase. In the present disclosure, it can be seen from Formula 7 and the calculation formula of the light-emitting current Ioled that when the mobility increases, the gate-source voltage Vgs of the driving transistor T3 will decrease, thereby suppressing the increase of Ioled and achieving compensation for the mobility drift. By adjusting the length of the time T, the compensation effect can be adjusted. At the same time, the size of Ioled is independent of the potential (Vdd) of the first power supply terminal VDD and the threshold voltage (Vth) of the driving transistor T3, thereby achieving compensation for the potential (Vdd) of the first power supply terminal VDD and the threshold voltage (Vth) of the driving transistor T3, which can bring better display uniformity.

[0107] The operation of the pixel circuit in FIG2 is described in detail with reference to the operating timing diagram of the pixel circuit shown in FIG3(c). For example, the transistor described above is a P-type transistor, and the conduction level is low. Compared to the timing diagram shown in FIG3(b), in the timing diagram shown in FIG3(c), the operation of the pixel circuit in the initialization phase S1 is consistent with that in FIG3(b), the operation of the pixel circuit in the compensation phase S2 is consistent with that in FIG3(b), and the operation of the pixel circuit in the first phase of the data writing phase S3 (from time t0 to time (t0+T)) is consistent with that in FIG3(b). In the second phase of the data writing phase S3 (from time (t0+T) to time t1), the first light-emitting control signal terminal EM1(n) is low, the first power supply terminal VDD is connected to the first electrode of the driving transistor T3, and the gate-source voltage of the driving transistor T3 is as shown in the above formula 6. In addition, in the timing diagram shown in FIG3( c ), the working process of the pixel circuit in the light emitting stage S4 is consistent with that in FIG3( b ), and the calculation formula of the light emitting current is as shown in the above formula 8.

[0108] The operation of the pixel circuit in FIG4 is described in detail with reference to the operation timing diagram shown in FIG5 . For example, the aforementioned transistor is a P-type transistor, and the conduction level is low. Compared to the pixel circuit shown in FIG2 , in the pixel circuit shown in FIG4 , the control electrode of the first emission control transistor T5 is connected to the auxiliary control signal terminal EM(n-1), and the control electrode of the second emission control transistor T6 is connected to the emission control signal terminal EM(n). The operation process of the pixel circuit shown in FIG4 is substantially the same as the operation process of the pixel circuit shown in FIG2 [operating according to the operation timing diagram shown in FIG3(b)], with the only difference being that: in the initialization stage S1, the auxiliary control signal terminal EM(n-1) is high, the light-emitting control signal terminal EM(n) is low, and the second light-emitting control transistor T6 is turned on; in the compensation stage S2, the auxiliary control signal terminal EM(n-1) is low, the light-emitting control signal terminal EM(n) is high, and the first light-emitting control transistor T5 is turned on; in the data writing stage S3, the auxiliary control signal terminal EM(n-1) is low, the light-emitting control signal terminal EM(n) is high, and the first light-emitting control transistor T5 remains turned on; in the light-emitting stage S4, the auxiliary control signal terminal EM(n-1) and the light-emitting control signal terminal EM(n) are both low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on, and the light-emitting current is calculated as shown in the above-mentioned formula 8.

[0109] The operation process of the pixel circuit in FIG6 is described in detail in conjunction with the operation timing diagram shown in FIG7 . For example, the aforementioned transistor is a P-type transistor, and the conduction level is low. Compared to the pixel circuit shown in FIG4 , the pixel circuit shown in FIG6 does not include the first light-emitting control transistor T5. The operation process of the pixel circuit shown in FIG6 is substantially the same as that of the pixel circuit shown in FIG4 (operating according to the operation timing diagram shown in FIG5 ), with the only difference being that, during the initialization phase S1 , the light-emitting control signal terminal EM(n) is high, and the second light-emitting control transistor T6 is turned off. The calculation formula for the light-emitting current of sub-pixel L0 in the pixel circuit shown in FIG6 is as shown in Formula 8 above.

[0110] The operation process of the pixel circuit in FIG8 is described in detail in conjunction with the operation timing diagram shown in FIG9 . For example, the above-mentioned transistor is an N-type transistor, and the conduction level is a high level. The operation process of the pixel circuit shown in FIG8 is substantially the same as the operation process of the pixel circuit shown in FIG2 (operating according to the operation timing diagram shown in FIG3(b)), with the only difference being that when the compensation transistor T2 is turned on, the first node N1 is connected to the third node N3. The calculation formula for the light-emitting current Ioled of the sub-pixel L0 in the pixel circuit shown in FIG8 is as shown in the above-mentioned formula 8. In addition, in FIG9 , the above-mentioned first voltage is VL and the second voltage is VH.

[0111] The present disclosure also provides a method for driving a pixel circuit, for driving the pixel circuit of the above embodiment. The method for driving the pixel circuit may include: causing the driving subcircuit 6 to control the third node N3 to connect or disconnect with the fourth node N4 under the control of the first node N1; causing the light-emitting control subcircuit 5 to control the fourth node N4 to connect or disconnect with the first electrode of the subpixel L0; causing the second storage subcircuit 10 to store the potential of the first node N1; causing the data writing subcircuit 1 to input a voltage to the second node N2; causing the compensation subcircuit 2 to control the first node N1 to connect or disconnect with the third node N3 under the control of the first scanning signal terminal Gate1(n); or causing the compensation subcircuit 2 to control the first node N1 to connect or disconnect with the fourth node N4 under the control of the first scanning signal terminal Gate1(n). Since the pixel circuit driven by the driving method of the present disclosure is the same as the pixel circuit in the above embodiment, it has the same beneficial effects and will not be described in detail here.

[0112] The present disclosure also provides a display device. The display device may include any of the aforementioned pixel circuits and a sub-pixel L0 connected to the pixel circuit. The display device may be any product or component with a display function, such as a portable phone, a smartphone, a video phone, a smart tablet, a smartwatch, a tablet personal computer, a vehicle navigation system, a television, a computer monitor, a notebook computer, a head-mounted display, or the like. Since the pixel circuit in the display device of the present disclosure is the same as the pixel circuit in the aforementioned embodiment, it has the same beneficial effects and will not be further described here.

[0113] The above is merely a preferred embodiment of the present disclosure and does not constitute any form of limitation to the present disclosure. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not intended to limit the present disclosure. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A pixel circuit for a display device, characterized in that: The pixel circuit comprises: A first storage subcircuit connected between the first node and the second node; a driving subcircuit connected to the first node, the third node and the fourth node, and configured to control the third node to be connected or disconnected with the fourth node under the control of the first node; the third node is connected to the first power supply terminal; a light emitting control subcircuit connected to the fourth node and the first electrode of the sub-pixel, and used for controlling the fourth node to be connected or disconnected from the first electrode of the sub-pixel; A second storage subcircuit, connected to the first node, and used to store the potential of the first node; a data writing subcircuit, connected to the second node, and used for inputting a voltage to the second node; a compensation sub-circuit connected to the first scanning signal terminal and the first node; The compensation subcircuit is further connected to the third node, and is used to control the first node to be connected or disconnected with the third node under the control of the first scanning signal terminal; or The compensation sub-circuit is also connected to the fourth node, and is used to control the first node to be connected or disconnected with the fourth node under the control of the first scanning signal terminal.

2. The pixel circuit according to claim 1, characterized in that: In a display frame of the display device, the driving process of the pixel circuit includes a compensation phase and a data writing phase; In the compensation stage, the compensation subcircuit controls the first node to be connected to the third node or the fourth node, the third node is connected to the first power supply terminal, and the data writing subcircuit inputs a first voltage to the second node; In the data writing phase, the data writing sub-circuit inputs a second voltage to the second node.

3. The pixel circuit according to claim 2, characterized in that: The data writing phase includes a first phase and a second phase; In the first stage, the compensation sub-circuit controls the first node and the third node or The fourth node is connected, the third node is connected to the first power supply terminal, and the data writing subcircuit inputs a second voltage to the second node; In the second stage, the compensation sub-circuit controls the first node to be disconnected from the third node or the fourth node, and the data writing sub-circuit inputs a second voltage to the second node.

4. The pixel circuit according to claim 1, characterized in that: The pixel circuit further comprises: The first reset subcircuit is connected to the reset signal terminal, the first initialization signal terminal and the first node, and is used for controlling the first initialization signal terminal to be connected or disconnected with the first node under the control of the first reset signal terminal.

5. The pixel circuit according to claim 4, characterized in that: The first reset subcircuit comprises: A first reset transistor, wherein a control electrode of the first reset transistor is connected to the reset signal terminal, a first electrode of the first reset transistor is connected to the first initialization signal terminal, and a second electrode of the first reset transistor is connected to the first node.

6. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: A second reset subcircuit is connected to the first scanning signal terminal, the second initialization signal terminal and the first electrode of the subpixel, and is used to control the second initialization signal terminal to be connected or disconnected with the first electrode of the subpixel under the control of the first scanning signal terminal; The second reset sub-circuit comprises: A second reset transistor, wherein a control electrode of the second reset transistor is connected to the first scanning signal terminal, a first electrode of the second reset transistor is connected to the second initialization signal terminal, and a second electrode of the second reset transistor is connected to the first electrode of the sub-pixel.

7. The pixel circuit according to claim 1, characterized in that: The data writing sub-circuit comprises: A data writing transistor, wherein a control electrode of the data writing transistor is connected to the second scanning signal terminal, a first electrode of the data writing transistor is connected to the data signal terminal, and a second electrode of the data writing transistor is connected to the second node.

8. The pixel circuit according to claim 1, characterized in that: The driving subcircuit comprises: A driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the fourth node.

9. The pixel circuit according to claim 1, characterized in that: The compensation subcircuit comprises: A compensation transistor, wherein a control electrode of the compensation transistor is connected to the first scanning signal terminal, a first electrode of the compensation transistor is connected to the third node or the fourth node, and a second electrode of the compensation transistor is connected to the first node.

10. The pixel circuit according to claim 1, characterized in that: The light emitting control subcircuit is also connected to the first power supply terminal and the third node, and is used to control the first power supply terminal to be connected or disconnected from the third node.

11. The pixel circuit according to claim 10, characterized in that: The light emission control subcircuit includes a first light emission control transistor connected in series between the first power supply terminal and the third node.

12. The pixel circuit according to claim 1 or 10, characterized in that: The light emission control subcircuit further includes a second light emission control transistor connected in series between the fourth node and the first electrode of the subpixel.

13. The pixel circuit according to claim 1, characterized in that: The first storage sub-circuit includes a first capacitor, and the second storage sub-circuit includes a second capacitor.

14. A method for driving a pixel circuit, characterized in that: The driving method is used to drive the pixel circuit according to any one of claims 1 to 13, and the driving method comprises: The driving subcircuit controls the third node to be connected to or disconnected from the fourth node under the control of the first node; The light emitting control subcircuit controls the fourth node to be connected to or disconnected from the first electrode of the sub-pixel; enabling the second storage sub-circuit to store the potential of the first node; enabling the data writing sub-circuit to input a voltage to the second node; The compensation sub-circuit controls the first node to be connected or disconnected with the third node under the control of the first scanning signal terminal; or the compensation sub-circuit controls the first node to be connected or disconnected with the third node under the control of the first scanning signal terminal. The first node is controlled to be connected or disconnected with the fourth node.

15. A display device, characterized in that: The invention comprises the pixel circuit according to any one of claims 1 to 13 and a sub-pixel connected to the pixel circuit.

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