Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises: a substrate; a signal line; a buffer layer; an active layer; a second signal line; a first passivation layer; a planarization layer; a pixel electrode; a first via extending through the buffer layer and exposing at least a portion of the signal line; and a second via extending through the first passivation layer and exposing at least a portion of the signal line. And relative to the same second signal line, a first minimum distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the second signal line on the substrate is greater than a second minimum distance between the orthographic projection of the second via hole on the substrate and the orthographic projection of the second signal line on the substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal display panels have been widely used. Generally, a liquid crystal display panel includes an opposing substrate and an array substrate facing each other. Thin film transistors, gate lines, data lines, pixel electrodes, common electrodes and common electrode signal lines are arranged on the array substrate and the opposing substrate. Between the two substrates, a liquid crystal material is injected to form a liquid crystal layer. A common problem associated with liquid crystal display panels is light leakage. In order to prevent light leakage, a black matrix is ​​arranged on the opposing substrate. A liquid crystal display panel with a larger black matrix can better prevent light leakage. However, the use of a black matrix with a larger area reduces the aperture ratio of the liquid crystal display device.

[0003] Organic light emitting diode (OLED) display is driven by a driving current that needs to be kept constant to control the illumination. The OLED display panel includes a plurality of pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate signal line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0004] On the one hand, the present disclosure provides an array substrate, comprising a plurality of signal lines and a plurality of second signal lines, wherein the signal lines and the second signal lines cross each other to define a plurality of sub-pixels; the array substrate comprises: a substrate; a signal line located on the substrate substrate; a buffer layer located on a side of the signal line away from the substrate substrate; an active layer located on a side of the buffer layer away from the substrate substrate; a second signal line located on a side of the active layer away from the signal line; a first passivation layer located on a side of the second signal line away from the substrate substrate; a planarization layer located on a side of the second signal line away from the active layer; a pixel electrode located on a side of the planarization layer away from the substrate substrate; a first via hole extending at least through the buffer layer and exposing at least a portion of the signal line; and a second via hole extending at least through the first passivation layer and exposing at least a portion of the pixel electrode; wherein, relative to the same second signal line, a first minimum distance between an orthographic projection of the first via hole on the substrate substrate and an orthographic projection of the second signal line on the substrate substrate is greater than a second minimum distance between an orthographic projection of the second via hole on the substrate substrate and an orthographic projection of the second signal line on the substrate substrate.

[0005] Optionally, the signal line includes a first part and a second part; the first part is the part of the signal line located in the first via; the second part is electrically connected to the first part; along the extension direction of the second signal line, the first part has a first line width, the second part has a second line width, and the first line width is greater than the second line width.

[0006] Optionally, the second signal line includes a main body and a protruding portion protruding away from the main body; the main body extends along an extension direction of the second signal line; the protruding portion protrudes away from the main body along a direction different from the extension direction of the second signal line; the orthographic projection of the main body on the substrate separates the orthographic projection of the protruding portion on the substrate from the orthographic projection of the first via on the substrate; and the orthographic projection of the protruding portion on the substrate separates the orthographic projection of the signal line on the substrate from the orthographic projection of the second via on the substrate.

[0007] Optionally, an orthographic projection of the active layer on the base substrate at least partially overlaps with the orthographic projection of the protrusion on the base substrate.

[0008] Optionally, the active layer includes a first electrode region, a second electrode region, and a channel region located between the first electrode region and the second electrode region; the first electrode region includes a first electrode, and the second electrode region includes a second electrode; wherein the channel region, at least a portion of the first electrode, and at least a portion of the second electrode are an integral structure; and the material of at least a portion of the first electrode and at least a portion of the second electrode is the same as that of the channel region and is subjected to a conductorization process; the first electrode extends to the first via to be connected to the signal line; and the pixel electrode extends to the second via to be connected to the second electrode.

[0009] Optionally, the array substrate further includes a shading member; wherein the shading member and the signal line are located in the same layer; and an orthographic projection of the shading member on the base substrate at least partially overlaps with the orthographic projection of the second signal line on the base substrate.

[0010] Optionally, the array substrate further includes a shading member; wherein an orthographic projection of the shading member on the base substrate at least partially overlaps with an orthographic projection of a portion of the second signal line on the base substrate; and along an extension direction of the signal line, at least one of two boundaries of the orthographic projection of the portion of the second signal line on the base substrate is completely located between the two boundaries of the orthographic projection of the shading member on the base substrate.

[0011] Optionally, the array substrate further includes a light shielding member; wherein a minimum distance between the light shielding member and the signal line is in a range of 1.0 μm to 5.0 μm.

[0012] Optionally, the array substrate further comprises a third via hole extending at least through the planarization layer; wherein an orthographic projection of the third via hole on the base substrate partially overlaps with an orthographic projection of the light shielding member on the base substrate.

[0013] Optionally, the buffer layer includes a first part and a second part; the first part is the side wall of the first via; the first part separates the second part from the first via; the orthographic projection of the first part on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the signal line on the substrate; and a first height of the first part relative to the surface of the substrate is greater than a second height of the second part relative to the surface of the substrate.

[0014] Optionally, an average line width of the signal line is in a range of 0.7 μm to 3.5 μm.

[0015] Optionally, the material of the channel region, at least a portion of the first electrode, and at least a portion of the second electrode comprises M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0; and at least a portion of the first electrode and at least a portion of the second electrode are subjected to a lightly doped drain process.

[0016] Optionally, the first electrode includes a first electrode portion and a second electrode portion electrically connected to each other; and the first electrode portion and the second electrode portion are made of different materials.

[0017] Optionally, the material of the first electrode portion includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0; the second electrode portion includes a metal material; and the first electrode portion, at least a portion of the second electrode and the channel region are an integrated structure.

[0018] Optionally, at least part of the first electrode portion extends into the second electrode portion.

[0019] Optionally, the array substrate further includes: an insulating layer located on a side of the active layer away from the base substrate; a gate located on a side of the insulating layer away from the active layer; and a via extending through the insulating layer and the buffer layer to expose a surface of a portion of the signal line; wherein the first electrode portion is located on the same layer as the gate; and the first electrode portion extends to the via to be connected to the signal line.

[0020] Optionally, the array substrate further includes: an insulating layer located on a side of the active layer away from the base substrate; a gate located on a side of the insulating layer away from the active layer; an interlayer dielectric layer located on a side of the gate away from the insulating layer; and a via extending through the interlayer dielectric layer, the insulating layer and the buffer layer to expose a surface of a portion of the signal line; wherein the first electrode portion is in a layer located on a side of the interlayer dielectric layer away from the insulating layer; and the first electrode portion extends to the via to be connected to the signal line.

[0021] Optionally, the second electrode includes a third electrode portion and a fourth electrode portion which are electrically connected to each other; and the third electrode portion and the fourth electrode portion are made of different materials.

[0022] Optionally, the material of the third electrode portion includes M1O a N b, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0; the fourth electrode portion includes a metal material; and at least a portion of the first electrode, the channel region and the third electrode portion are an integrated structure.

[0023] Optionally, the array substrate further includes: an insulating layer located on a side of the active layer away from the base substrate; a gate located on a side of the insulating layer away from the active layer; an interlayer dielectric layer located on a side of the gate away from the insulating layer; and a via extending through the interlayer dielectric layer and the insulating layer to expose a portion of the surface of the third electrode portion; wherein the fourth electrode portion is in a layer located on a side of the interlayer dielectric layer away from the insulating layer; and the fourth electrode portion extends to the via to be connected to the third electrode portion.

[0024] Optionally, the channel region, the entire first electrode and the entire second electrode are an integrated structure.

[0025] Optionally, the array substrate further includes a via hole extending through the buffer layer to expose a surface of a portion of the signal line; wherein the first electrode portion extends to the via hole to be connected to the signal line.

[0026] Optionally, the array substrate also includes: an insulating layer located on the base substrate, and a gate located on a side of the insulating layer away from the base substrate; wherein the signal line, the channel region, the first electrode and the second electrode are located as a whole between the insulating layer and the base substrate; the signal line, the channel region, the first electrode and the second electrode are all directly in contact with the surface of the base substrate; and the signal line, the channel region, the first electrode and the second electrode are all in direct contact with the surface of the insulating layer.

[0027] Optionally, in a cross section along a plane perpendicular to the substrate and perpendicular to the length direction and intersecting the signal line, the first electrode covers an upper surface of at least a portion of the signal line, wherein the signal line extends along the length direction; and an orthographic projection of the first electrode on the substrate at least partially overlaps with an orthographic projection of the signal line on the substrate.

[0028] Optionally, in a cross section along a plane perpendicular to the substrate and perpendicular to the length direction and intersecting the signal line, the signal line covers at least a portion of the upper surface of the first electrode, wherein the signal line extends along the length direction; and an orthographic projection of the signal line on the substrate at least partially overlaps with an orthographic projection of the first electrode on the substrate.

[0029] Optionally, the array substrate further comprises a pixel electrode electrically connected to the second electrode; wherein the pixel electrode, the channel region, at least a portion of the first electrode and at least a portion of the second electrode are located in the same layer and are an integrated structure.

[0030] Optionally, the array substrate further includes: a gate electrode located on a side of the active layer away from the base substrate; a passivation layer located on a side of the gate electrode away from the base substrate; and a common electrode located on a side of the passivation layer away from the base substrate; wherein the common electrode and the pixel electrode are configured to form an electric field in response to a voltage at the second electrode, thereby driving an image display in a sub-pixel.

[0031] Optionally, the array substrate further includes a common electrode configured to be provided with a low voltage signal; wherein the common electrode, the channel region, at least a portion of the first electrode and at least a portion of the second electrode are located in the same layer and made of the same material.

[0032] Optionally, the array substrate further includes: a gate electrode located on a side of the active layer away from the base substrate; a passivation layer located on a side of the gate electrode away from the base substrate; a pixel electrode located on a side of the passivation layer away from the base substrate; and a via hole extending at least through the passivation layer to expose a portion of the surface of the second electrode; wherein the pixel electrode extends to the via hole to be connected to the second electrode; and the common electrode and the pixel electrode are configured to form an electric field in response to a voltage at the second electrode, thereby driving an image display in a sub-pixel.

[0033] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0035] Figure 1A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0036] Figure 1B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 1C is a plan view of an array substrate according to some embodiments of the present disclosure.

[0038] Figure 1Dis a plan view of an array substrate according to some embodiments of the present disclosure.

[0039] Figure 1E is a plan view of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 1F is a plan view of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 2 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0042] Figure 3 It is shown Figure 2 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0043] Figure 4 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0044] Figure 5 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0045] Figure 6 It is shown Figure 5 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0046] Figure 7 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0047] Figure 8 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0048] Fig. 9 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0049] Fig.10 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0050] Fig.11 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0051] Fig.12 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0052] Fig.13 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0053] Fig.14Ais a plan view of an array substrate according to some embodiments of the present disclosure.

[0054] Fig. 14B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0055] Fig. 14C is a plan view of an array substrate according to some embodiments of the present disclosure.

[0056] Fig.14D is a plan view of an array substrate according to some embodiments of the present disclosure.

[0057] Fig.14E is a plan view of an array substrate according to some embodiments of the present disclosure.

[0058] Fig.14F is a plan view of an array substrate according to some embodiments of the present disclosure.

[0059] Fig.15 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0060] Fig.16 It is shown Fig.15 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0061] Fig.17 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0062] Fig.18 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0063] Fig.19 It is shown Fig.18 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0064] Fig. 20 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0065] Fig.21 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0066] Fig. 22 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0067] Fig.23 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0068] Fig.24is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0069] Fig.25 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0070] Fig.26 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0071] Fig.27A is a plan view of an array substrate according to some embodiments of the present disclosure.

[0072] Fig.27B is a plan view of an array substrate according to some embodiments of the present disclosure.

[0073] Fig.27C is a plan view of an array substrate according to some embodiments of the present disclosure.

[0074] Fig.27D is a plan view of an array substrate according to some embodiments of the present disclosure.

[0075] Fig.27E is a plan view of an array substrate according to some embodiments of the present disclosure.

[0076] Fig.27F is a plan view of an array substrate according to some embodiments of the present disclosure.

[0077] Fig.28 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0078] Fig.29 It is shown Fig.28 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0079] Fig.30 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0080] Fig.31 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0081] Fig.32 It is shown Fig.31 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG.

[0082] Fig.33 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0083] Fig.34is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0084] Fig.35 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0085] Fig.36 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0086] Fig.37 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0087] Fig.38 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0088] Fig.39 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0089] FIG. 40A to FIG. 40H The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0090] FIG. 41A to FIG. 41H The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0091] FIG. 42A to FIG. 42G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0092] FIG. 43A to FIG. 43G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0093] FIG. 44A to FIG. 44G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0094] Figures 45A to 45G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0095] FIG. 46A to FIG. 46F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0096] FIG. 47A to FIG. 47F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0097] FIG. 48A to FIG. 48G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0098] FIG. 49A to FIG. 49G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0099] FIG. 50A to FIG. 50F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0100] Figures 51A to 51F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0101] FIG. 52A to FIG. 52F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0102] Figures 53A to 53F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0103] FIG. 54A to FIG. 54E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0104] FIG. 55A to FIG. 55E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0105] FIG. 56A to FIG. 56G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0106] FIG. 57A to FIG. 57G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0107] Figures 58A to 58F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0108] Figures 59A to 59F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0109] Figures 60A to 60F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0110] Figures 61A to 61F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0111] Figures 62A to 62E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0112] Figures 63A to 63E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure.

[0113] Fig.64 The layout of signal lines in an array substrate according to some embodiments of the present disclosure is shown.

[0114] Fig.65The relative positions of via holes in an array substrate according to some embodiments of the present disclosure are shown.

[0115] Fig.66 The structure of the second signal line in the array substrate according to some embodiments of the present disclosure is shown.

[0116] Fig.67 is a scanning electron microscopy image of a portion of an array substrate in some embodiments according to the present disclosure.

[0117] Fig.68 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0118] Fig.69 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

[0119] Fig.70 The relative positions of via holes in an array substrate according to some embodiments of the present disclosure are shown.

[0120] Fig.71 is a scanning electron microscopy image of a portion of an array substrate in some embodiments according to the present disclosure.

[0121] Fig.72 is a scanning electron microscopy image of a portion of an array substrate in some embodiments according to the present disclosure. DETAILED DESCRIPTION

[0122] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0123] The present disclosure provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and disadvantages of the prior art. On the one hand, the array substrate includes: a base substrate; a signal line and an active layer located on the base substrate; and an organic planarization layer located on a side of the first electrode, the active layer and the second electrode away from the signal line.

[0124] Figure 1A is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 2 Can be along Figure 1A A cross-sectional view of the line A-A' in FIG. Figure 1A and Figure 2In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) located on the base substrate BS; a buffer layer BUF located on a side of the signal line SL away from the base substrate BS; and an active layer ACT located on a side of the buffer layer BUF away from the base substrate BS. The active layer ACT includes a first electrode region, a second electrode region, and a channel region CR located between the first electrode region and the second electrode region. The first electrode region includes a first electrode E1, and the second electrode region includes a second electrode E2. In some embodiments, the array substrate further includes an insulating layer IN (for example, a gate insulating layer) located on a side of the active layer ACT (for example, located on the first electrode E1, the channel region CR, and the second electrode E2) away from the buffer layer BUF.

[0125] In some embodiments, the array substrate further includes a gate G located on a side of the insulating layer IN away from the channel region CR. The gate G defines an area of ​​the channel region CR. For example, an orthographic projection of the gate G on the base substrate substantially overlaps an orthographic projection of the channel region CR on the base substrate BS.

[0126] In some embodiments, the array substrate further includes a shading member LS located on the base substrate BS. Optionally, the shading member LS is located on the same layer as the signal line SL, for example, formed using the same mask and / or the same material in the same patterning process. The shading member LS is configured to prevent light from being irradiated on the channel region CR. Optionally, the orthographic projection of the shading member LS on the base substrate BS overlaps at least partially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99% or 100%) with the orthographic projection of the channel region CR on the base substrate BS.

[0127] In some embodiments, the array substrate further includes: an interlayer dielectric layer ILD, which is located on the side of the gate G away from the base substrate BS; a first passivation layer PVX1, which is located on the side of the interlayer dielectric layer ILD away from the base substrate BS; a planarization layer PLN, which is located on the side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; a second passivation layer PVX2, which is located on the side of the planarization layer PLN away from the first passivation layer PVX1; and a pixel electrode PE, which is located on the side of the second passivation layer PVX2 away from the planarization layer PLN. The pixel electrode PE optionally extends at least through the second passivation layer PVX2, the planarization layer PLN and the first passivation layer PVX1 to be connected to the second electrode E2.

[0128] In some embodiments, the array substrate further comprises a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1. Optionally, the common electrode CE is located on a side of the second passivation layer PVX2 close to the planarization layer PLN.

[0129] In some embodiments, the array substrate further includes a second signal line SL2. In some embodiments, the second signal line SL2 is a gate line that provides a gate drive signal for the transistor. In some embodiments, the gate is a part of the gate line GL. The orthographic projection of the channel region CR on the substrate overlaps the orthographic projection of the gate on the substrate.

[0130] The array substrate can be implemented in various suitable display panels. Suitable array substrates include liquid crystal display array substrates, organic light emitting diode array substrates, micro light emitting diode array substrates and mini light emitting diode array substrates.

[0131] In some embodiments, the array substrate is a liquid crystal display array substrate. The pixel electrode PE is a pixel electrode in each of the multiple sub-pixels in the liquid crystal display array substrate. The common electrode CE is a common electrode in the liquid crystal display array substrate. In one example, the common electrode CE is an electrode extending in the multiple sub-pixels in the liquid crystal display array substrate.

[0132] In some embodiments, the array substrate is a light emitting diode display array substrate. The pixel electrode PE is the anode of each light emitting diode of the plurality of light emitting diodes in the light emitting diode display array substrate. The common electrode CE is the cathode in the light emitting diode display array substrate. In one example, the common electrode is the cathode extending in the plurality of sub-pixels in the light emitting diode display array substrate. In another example, the common electrode CE is located on a side of the light emitting layer and the pixel electrode PE away from the base substrate BS.

[0133] Various suitable semiconductor materials and various suitable manufacturing methods can be used to manufacture the channel region CR. In some embodiments, the semiconductor material includes M1O a N b, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element. For example, the semiconductor material is a metal oxide material or a metal oxynitride material. Examples of suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide, HfInZnO (HIZO), amorphous InZnO (amorphous IGZO), InZnO, amorphous InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Examples of suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the channel region CR includes indium gallium zinc oxide.

[0134] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first electrode E1 or the second electrode E2. Examples of suitable conductive materials include metals, alloys, metal oxides and any combination thereof. Examples of suitable conductive materials for manufacturing the first electrode E1 or the second electrode E2 include, but are not limited to, molybdenum, aluminum, titanium, gold, copper, hafnium, tantalum, alloys such as aluminum neodymium (AlNd), molybdenum niobium (MoNb), and stacks such as molybdenum-neodymium-copper stacked structures, MTD (molybdenum-titanium-niobium) stacked structures, MTD molybdenum-nickel-titanium-copper stacked structures, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium stacked structures, molybdenum-neodymium-copper-MTD stacked structures, molybdenum-aluminum-aluminum stacked structures, molybdenum-aluminum-molybdenum stacked structures, MoNb-copper-MoNb stacked structures, and AlNd-molybdenum-AlNd stacked structures.

[0135] In some embodiments, the conductive material used to manufacture the first electrode E1 or the second electrode E2 includes M1O a N b, wherein M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents an oxygen element, and N represents a nitrogen element. For example, the conductive material is a metal oxide material or a metal oxynitride material. Examples of suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide, HfInZnO (HIZO), InGaZnO (IGZO), crystalline InZnO, amorphous InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, InGaO (IGO), InGaZnSnO (IGZTO), and lanthanide-doped oxide semiconductors (Ln-OS). The crystallinity may be amorphous, partially crystalline, or crystalline. Examples of suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof. In one example, the first electrode E1 or the second electrode E2 includes indium gallium zinc oxide.

[0136] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O, the first electrode E1 or the second electrode E2 is different from the channel region CR in that the first electrode E1 or the second electrode E2 is subjected to a conductorization process. The channel region CR has a conductivity different from that of the first electrode E1 and different from that of the second electrode E2. a N b When M1O in the first electrode E1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When M1O in the first electrode E1 or the second electrode E2 a N b In another example, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When M1O in the first electrode E1 or the second electrode E2 a N b Alternatively, use about 1×10 15 Atom / cm 3 to about 1×1020 atoms / cm 3The doping concentration is within the range of about 1×10 15 Atom / cm 3 About 1×10 16 Atom / cm 3 , about 1×10 16 Atom / cm 3 About 1×10 17 Atom / cm 3 , about 1×10 17 Atom / cm 3 About 1×10 18 Atom / cm 3 , about 1×10 18 Atom / cm 3 About 1×10 20 Atom / cm 3 , and about 1×10 19 Atom / cm 3 About 1×10 20 Atom / cm 3 , to perform a lightly doped drain process. Optionally, the lightly doped drain process is performed using an n-type dopant to enhance conductivity. Examples of n-type dopants include Group VA elements of the periodic table, including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0137] Figure 3 It is shown Figure 2 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Figure 1A , Figure 2 and Figure 3 The first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least part of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0138] In some embodiments, reference Figure 1A , Figure 2 and Figure 3 The second electrode E2 includes a third electrode portion E2-1 and a fourth electrode portion E2-2 which are electrically connected to each other. The third electrode portion E2-1 and the fourth electrode portion E2-2 are made of different materials. Optionally, the fourth electrode portion E2-2 is in direct contact with the third electrode portion E2-1 and is located on a side of the third electrode portion E2-1 away from the substrate BS.

[0139] The first electrode portion E1-1 or the third electrode portion E2-1 may be manufactured using various suitable conductive materials and various suitable manufacturing methods. In some embodiments, the conductive material used to manufacture the first electrode portion E1-1 or the third electrode portion E2-1 includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0 and b≥0, for example, the conductive material is a metal oxide material or a metal oxynitride material. In some embodiments, when the material of the channel region CR, the first electrode portion E1-1 and the third electrode portion E2-1 includes M1O a N b When the material of the channel region CR, the first electrode portion E1-1 or the third electrode portion E2-1 includes M1O a N b When M1O in the first electrode portion E1-1 or the third electrode portion E2-1 a N b The substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0140] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second electrode portion E1-2 or the fourth electrode portion E2-2. Examples of suitable conductive materials include metals, alloys, metal oxides, and any combination thereof. In one example, the second electrode portion E1-2 or the fourth electrode portion E2-2 includes a molybdenum-neodymium-copper laminate structure, an MTD-copper laminate structure, or a molybdenum-neodymium-copper-MTD laminate structure.

[0141] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the buffer layer BUF. For example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of materials suitable for manufacturing the buffer layer BUF include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. Optionally, the buffer layer BUF may have a single-layer structure or a stacked structure including two or more sublayers (for example, a stacked structure including a silicon oxide sublayer and a silicon nitride sublayer). Optionally, the thickness of the buffer layer BUF is in the range of about 300nm to about 600nm. For example, the buffer layer BUF may include a silicon oxide sublayer having a thickness of 1% to 90% of the total thickness of the buffer layer BUF. In one example, the buffer layer BUF has a stacked structure including a silicon oxide sublayer and a silicon nitride sublayer. In another example, the buffer layer BUF has a stacked structure including a first silicon oxide sublayer and a second silicon oxide sublayer. The inventors of the present disclosure have found that the buffer layer BUF having a stacked structure including two or more sublayers can prevent the signal line from being oxidized by the surface of the silicon oxide material.

[0142] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the planarization layer PLN, for example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition process. Examples of suitable insulating materials include organic insulating materials such as resin materials.

[0143] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the second electrode portion E1-2 is located in the via hole v. Optionally, the second electrode portion E1-2 extends to the via hole v to be connected to the signal line SL. Figure 2 In one example depicted in FIG, the via v extends through the interlayer dielectric layer ILD, the insulating layer IN, and the buffer layer BUF. In another example, the second electrode portion E1-2 is formed after forming the gate G. For example, the second electrode portion E1-2 is in a layer located on a side of the gate G away from the substrate BS.

[0144] In some embodiments, the array substrate includes a via hole v' extending at least through the insulating layer IN. At least a portion of the fourth electrode portion E2-2 is located in the via hole v'. Optionally, the fourth electrode portion E2-2 extends to the via hole v' to be connected to the third electrode portion E2-1. Figure 2 In one example depicted in FIG. 8 , the via v′ extends through the interlayer dielectric layer ILD and the insulating layer IN.

[0145] Figure 1B is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1B The structure of the array substrate depicted in Figure 1A The structure of the array substrate depicted in is similar, except that Figure 1B The array substrate depicted in FIG. 1 does not have a light shielding member.

[0146] Figure 1C is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1C The structure of the array substrate depicted in Figure 1A The structure of the array substrate depicted in is similar, except that Figure 1C The array substrate depicted in FIG. has a dual-gate thin film transistor. Figure 1C As shown, the two parts of the gate are parts of the second signal line SL2. The second signal line SL2 includes a protrusion that protrudes from the body of the second signal line in a direction substantially parallel to the length direction LD. The orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of one of the two parts of the active layer ACT on the substrate.

[0147] Figure 1D is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1D The structure of the array substrate depicted in Figure 1C The structure of the array substrate depicted in is similar, except that Figure 1D The array substrate depicted in FIG. 1 does not have a light shielding member.

[0148] Figure 1E is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1E The structure of the array substrate depicted in Figure 1C The structure of the array substrate is similar to that described in FIG. Figure 1C and Figure 1E In the array substrate depicted in FIG, the second signal line SL2 includes a protrusion GP that protrudes away from the body MB of the second signal line SL2. The body MB extends in a direction substantially perpendicular to the length direction LD, for example, and the protrusion GP extends in a direction substantially parallel to the length direction LD, for example. The protrusion GP includes a portion that serves as, for example, a gate of a transistor. Figure 1C In the array substrate depicted in FIG, the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on both sides of the body MB. Figure 1E In the array substrate depicted in FIG. 1 , the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on the same side of the body MB.

[0149] Figure 1F is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1F The structure of the array substrate depicted in Figure 1E The structure of the array substrate depicted in is similar, except that Figure 1F The array substrate depicted in FIG. 1 does not have a light shielding member.

[0150] In some embodiments, the insulating layer IN is formed to extend substantially throughout the array substrate, such as Figure 2 shown.

[0151] In some embodiments, the insulating layer does not extend substantially throughout the array substrate. For example, the orthographic projection of the insulating layer on the base substrate does not overlap at least partially with the orthographic projection of the signal line on the base substrate, and does not overlap at least partially with the orthographic projection of the first electrode or the second electrode on the base substrate.

[0152] Figure 4 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 4 The structure shown is Figure 2 The structure shown is similar, but with Figure 2 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Figure 4 The array substrate depicted in FIG.

[0153] Figure 5 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 5 Can be along Figure 1A Cross-sectional view along line A-A'. Figure 6 It is shown Figure 5 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Figure 5 and Figure 6 In some embodiments, the first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least a portion of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0154] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first electrode portion E1-1 or the second electrode E2. In some embodiments, the conductive material used to manufacture the first electrode portion E1-1 or the second electrode E2 includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0 and b≥0, for example, the conductive material is a metal oxide material or a metal oxynitride material. In some embodiments, when the material of the channel region CR, the first electrode portion E1-1 and the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode portion E1-1 or the second electrode E2 includes M1O aN b When M1O in the first electrode portion E1-1 or the second electrode E2 a N b The substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0155] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second electrode portion E1-2. Examples of suitable conductive materials include metals, alloys, metal oxides, and any combination thereof. In one example, the second electrode portion E1-2 includes a molybdenum-neodymium-copper laminate structure, an MTD-copper laminate structure, or a molybdenum-neodymium-copper-MTD laminate structure.

[0156] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the second electrode portion E1-2 is located in the via hole v. Optionally, the second electrode portion E1-2 extends to the via hole v to be connected to the signal line SL. Figure 5 In one example depicted in FIG, the via v extends through the insulating layer IN and the buffer layer BUF. In another example, the second electrode portion E1-2 and the gate G are located in the same layer and include the same electrode material. In another example, the second electrode portion E1-2 and the gate G are formed in the same patterning process using the same mask.

[0157] Reference Figure 5 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a light shielding member LS located on the base substrate BS; a buffer layer BUF located on a side of the signal line SL and the light shielding member LS away from the base substrate BS; a first electrode E1 (for example, a source of the transistor), a channel region CR, and a second electrode E2 (for example, a drain of the transistor), which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which are located at least on the channel region CR (for example, located on the first electrode E1, the channel region CR, and the drain of the transistor); CR and the second electrode E2) are located on the side away from the buffer layer BUF; the gate G, which is located on the side of the insulating layer IN away from the buffer layer BUF; the first passivation layer PVX1, which is located on the side of the gate G away from the insulating layer IN; the planarization layer PLN, which is located on the side of the first passivation layer PVX1 away from the insulating layer IN; the common electrode CE, which is located on the side of the planarization layer PLN away from the first passivation layer PVX1; the second passivation layer PVX2, which is located on the side of the common electrode CE away from the planarization layer PLN; and the pixel electrode PE, which is located on the side of the second passivation layer PVX2 away from the common electrode CE.

[0158] Figure 7 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 7The structure shown is Figure 5 The structure shown is similar, but with Figure 5 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Figure 7 The array substrate depicted in FIG.

[0159] Figure 8 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Figure 8 In some embodiments, the material of the channel region CR, the first electrode E1 and the second electrode E2 includes M1O a N b The channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Optionally, the first electrode E1 or the second electrode E2 is different from the channel region CR in that the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0160] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the first electrode E1 is located in the via hole v. Optionally, the first electrode E1 extends to the via hole v to be connected to the signal line SL.

[0161] Reference Figure 8 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a light shielding member LS located on the base substrate BS; a buffer layer BUF located on a side of the signal line SL and the light shielding member LS away from the base substrate BS; a first electrode E1 (for example, a source of the transistor), a channel region CR, and a second electrode E2 (for example, a drain of the transistor), which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located at least on the channel region CR (for example, on the first electrode E1, the channel region CR, and the drain of the transistor); R, and the second electrode E2) are located on the side away from the buffer layer BUF; the gate G, which is located on the side of the insulating layer IN away from the buffer layer BUF; the first passivation layer PVX1, which is located on the side of the gate G away from the insulating layer IN; the planarization layer PLN, which is located on the side of the first passivation layer PVX1 away from the insulating layer IN; the common electrode CE, which is located on the side of the planarization layer PLN away from the first passivation layer PVX1; the second passivation layer PVX2, which is located on the side of the common electrode CE away from the planarization layer PLN; and the pixel electrode PE, which is located on the side of the second passivation layer PVX2 away from the planarization layer PLN.

[0162] Fig. 9 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig. 9 The structure shown is Figure 8 The structure shown is similar, but with Figure 8The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig. 9 The array substrate depicted in FIG.

[0163] Fig.10 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.11 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.11 is along Fig.10 Cross-sectional view of line BB' in FIG. Fig.10 and Fig.11 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (e.g., a data line providing a data signal to a transistor) located on the base substrate BS; a first electrode E1 (e.g., a source of the transistor), a channel region CR, and a second electrode E2 (e.g., a drain of the transistor), which are located on a side of the signal line SL away from the base substrate BS; an insulating layer IN (e.g., a gate insulating layer), which is located on a side of at least the channel region CR (e.g., located on the first electrode E1, the channel region CR, and the second electrode E2) away from the base substrate BS; A gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2, which is located on a side of the common electrode CE away from the planarization layer PLN; and a pixel electrode PE, which is located on a side of the second passivation layer PVX2 away from the planarization layer PLN.

[0164] Fig.12 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.13 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.13 is along Fig.12 Cross-sectional view of line C-C' in FIG. Fig.12 and Fig.13In some embodiments, the array substrate includes: a base substrate BS; a first electrode E1 (e.g., a source of a transistor), a channel region CR, and a second electrode E2 (e.g., a drain of a transistor) located on the base substrate BS; a signal line SL (e.g., a data line providing a data signal to the transistor), which is located on a side of at least the first electrode E1 away from the base substrate BS; an insulating layer IN (e.g., a gate insulating layer), which is located on a side of the signal line SL, the first electrode E1, the channel region CR, and the second electrode E2 away from the base substrate BS; a gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2, which is located on a side of the common electrode CE away from the planarization layer PLN; and a pixel electrode PE, which is located on a side of the second passivation layer PVX2 away from the planarization layer PLN.

[0165] Reference Fig.10 , Fig.11 , Fig.12 and Fig.13 In some embodiments, the material of the channel region CR, the first electrode E1 and the second electrode E2 includes M1O a N b The channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Optionally, the first electrode E1 or the second electrode E2 is different from the channel region CR in that the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0166] Reference Fig.10 , Fig.11 , Fig.12 and Fig.13 In some embodiments, the signal line SL is in direct contact with the first electrode E1. Fig.12 and Fig.13 In the example depicted in FIG, the entirety of the combination of the signal line SL, the channel region CR, the first electrode E1, and the second electrode E2 is located between the insulating layer IN and the base substrate BS. The signal line SL, the channel region CR, the first electrode E1, and the second electrode E2 all directly contact the surface (e.g., the upper surface) of the base substrate BS. Alternatively, the signal line SL, the channel region CR, the first electrode E1, and the second electrode E2 all directly contact the surface (e.g., the lower surface) of the insulating layer IN.

[0167] Reference Fig.10 and Fig.11 , in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (eg Fig.11), the first electrode E1 covers at least a portion of the upper surface of the signal line SL, and optionally also covers at least one of the two side surfaces of the signal line SL, wherein the signal line SL extends along the length direction LD. The orthographic projection of the first electrode E1 on the substrate substrate BS at least partially overlaps with the orthographic projection of the signal line SL on the substrate substrate BS.

[0168] Reference Fig.12 and Fig.13 , in a cross section along a plane perpendicular to the base substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (eg, Fig.13 In the cross section shown in FIG. 1 , the signal line SL covers at least a portion of the upper surface of the first electrode E1, and optionally also covers at least a side surface of the first electrode E1, wherein the signal line SL extends along the length direction LD. The orthographic projection of the signal line SL on the substrate BS at least partially overlaps with the orthographic projection of the first electrode E1 on the substrate BS.

[0169] exist Figures 1A to 1D , Figures 2 to 13 In the array substrate described in FIG. 1 , various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the common electrode CE or the pixel electrode PE. In some embodiments, the conductive material used to manufacture the first electrode E1 or the second electrode E2 includes M1O a N b , wherein M1 is a single metal or a combination of multiple metals, a>0 and b≥0, for example, the conductive material is a metal oxide material or a metal oxynitride material. Examples of suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide, HfInZnO (HIZO), amorphous InZnO (amorphous IGZO), InZnO, amorphous InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb and Cd-Sn-O. Examples of suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride or a combination thereof. In one example, the common electrode CE includes indium gallium zinc oxide or indium zinc oxide. In another example, the pixel electrode PE includes indium tin oxide or indium zinc oxide.

[0170] Fig.14A is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.15 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.15 Can be along Fig.14A The cross-sectional view of the line D-D' in FIG. Fig.14A and Fig.15In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a light shielding member LS located on the base substrate BS; a buffer layer BUF located on a side of the signal line SL and the light shielding member LS away from the base substrate BS; a first electrode E1 (for example, a source of a transistor), a channel region CR, a second electrode E2 (for example, a drain of a transistor) and a pixel electrode PE located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), It is located on at least the side of the channel region CR and the pixel electrode PE away from the buffer layer BUF; the gate G is located on the side of the insulating layer IN away from the channel region CR; the interlayer dielectric layer ILD is located on the side of the gate G away from the insulating layer IN; the first passivation layer PVX1 is located on the side of the interlayer dielectric layer ILD away from the insulating layer IN; the planarization layer PLN is located on the side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; and the common electrode CE is located on the side of the planarization layer PLN away from the first passivation layer PVX1.

[0171] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the first electrode E1 or a portion of the second electrode E2 is subjected to a process to make it more conductive. a N b When M1O in the first electrode E1 or the second electrode E2 a N b At least a portion of the substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0172] Fig.16 It is shown Fig.15 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Fig.14A , Fig.15 and Fig.16 The first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least part of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0173] In some embodiments, reference Fig.14A , Fig.15 and Fig.16The second electrode E2 includes a third electrode portion E2-1 and a fourth electrode portion E2-2 which are electrically connected to each other. The third electrode portion E2-1 and the fourth electrode portion E2-2 are made of different materials. Optionally, the fourth electrode portion E2-2 is in direct contact with the third electrode portion E2-1 and is located on a side of the third electrode portion E2-1 away from the substrate BS.

[0174] Fig.14A and Fig.15 The structure of the array substrate depicted in Figure 1A and Figure 2 The structure of the array substrate depicted in is similar, but Figure 1A and Figure 2 The difference between the structure of the array substrate described in at least one embodiment is that: Fig.14A and Fig.15 In the array substrate depicted in , the pixel electrode PE and the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2 are located in the same layer.

[0175] In some embodiments, the pixel electrode PE, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 are an integrated structure. In some embodiments, the material of the pixel electrode PE, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 includes M1O a N b Optionally, the pixel electrode PE, at least a portion of the first electrode E1, or at least a portion of the second electrode E2 is different from the channel region CR in that the pixel electrode PE, at least a portion of the first electrode E1, or at least a portion of the second electrode E2 undergoes a conductorization process. In one example, the pixel electrode PE, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 include indium gallium tin oxide.

[0176] In some embodiments, the second electrode portion E1-2 and the fourth electrode portion E2-2 are formed after forming the gate G. For example, the second electrode portion E1-2 and the fourth electrode portion E2-2 are in a layer located at a side of the gate G away from the substrate BS.

[0177] Fig. 14B is a plan view of an array substrate according to some embodiments of the present disclosure. Fig. 14B The structure of the array substrate depicted in Fig.14A The structure of the array substrate depicted in is similar, except that Fig. 14B The array substrate depicted in FIG. 1 does not have a light shielding member.

[0178] Fig. 14C is a plan view of an array substrate according to some embodiments of the present disclosure. Fig. 14CThe structure of the array substrate depicted in Fig.14A The structure of the array substrate depicted in is similar, except that Fig. 14C The array substrate depicted in FIG. has a dual-gate thin film transistor. Fig. 14C As shown, the two parts of the gate are parts of the second signal line SL2. The second signal line SL2 includes a protrusion that protrudes from the body of the second signal line in a direction substantially parallel to the length direction LD. The orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of one of the two parts of the active layer ACT on the substrate.

[0179] Fig.14D is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.14D The structure of the array substrate depicted in Fig. 14C The structure of the array substrate depicted in is similar, except that Fig.14D The array substrate depicted in FIG. 1 does not have a light shielding member.

[0180] Fig.14E is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.14E The structure of the array substrate depicted in Fig. 14C The structure of the array substrate is similar to that described in FIG. Fig. 14C and Fig.14E In the array substrate depicted in FIG, the second signal line SL2 includes a protrusion GP protruding away from the main body MB of the second signal line SL2. The main body MB extends in a direction substantially perpendicular to the length direction LD, for example, and the protrusion GP extends in a direction substantially parallel to the length direction LD, for example. The protrusion GP includes a portion used as, for example, a gate of a transistor. Fig. 14C In the array substrate depicted in FIG, the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on both sides of the body MB. Fig.14E In the array substrate depicted in FIG. 1 , the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on the same side of the body MB.

[0181] Fig.14F is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.14F The structure of the array substrate depicted in Fig.14E The structure of the array substrate depicted in is similar, except that Fig.14F The array substrate depicted in FIG. 1 does not have a light shielding member.

[0182] In some embodiments, the insulating layer IN is formed to extend substantially throughout the array substrate, such as Fig.15 shown.

[0183] In some embodiments, the insulating layer does not extend substantially throughout the array substrate. For example, the orthographic projection of the insulating layer on the base substrate does not overlap at least partially with the orthographic projection of the signal line on the base substrate, and does not overlap at least partially with the orthographic projection of the first electrode or the second electrode on the base substrate.

[0184] Fig.17 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.17 The structure shown is Fig.15 The structure shown is similar, but with Fig.15 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig.17 The array substrate depicted in FIG.

[0185] Fig.18 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.18 Can be along Fig.14A Cross-sectional view along line D-D'. Fig.19 It is shown Fig.18 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Fig.18 and Fig.19 In some embodiments, the first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least a portion of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0186] Reference Fig.18 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a shading member LS located on the base substrate BS; a buffer layer BUF, which is located on a side of the signal line SL and the shading member LS away from the base substrate BS; a first electrode E1 (for example, a source of a transistor), a channel region CR, a second electrode E2 (for example, a drain of a transistor) and a pixel electrode PE, which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the pixel electrode PE away from the buffer layer BUF; a gate G, which is located on a side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1, which is located on a side of the gate G away from the insulating layer IN; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0187] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the first electrode E1 or a portion of the second electrode E2 is subjected to a process to make it more conductive. a N b When M1O in the first electrode E1 or the second electrode E2 a N b At least a portion of the substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0188] Fig.18 and Fig.19 The structure of the array substrate depicted in Figure 5 and Figure 6 The structure of the array substrate depicted in is similar, but Figure 5 and Figure 6 The difference between the structure of the array substrate described in at least one embodiment is that: Fig.18 and Fig.19 In the array substrate depicted in , the pixel electrode PE and the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2 are located in the same layer.

[0189] In some embodiments, the second electrode portion E1-2 and the gate G are located in the same layer and include the same electrode material. In another example, the second electrode portion E1-2 and the gate G are formed in the same patterning process using the same mask.

[0190] Fig. 20 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig. 20 The structure shown is Fig.18 The structure shown is similar, but with Fig.18 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig. 20 The array substrate depicted in FIG.

[0191] Fig.21 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.21 In some embodiments, the material of the pixel electrode PE, the channel region CR, the first electrode E1 and the second electrode E2 includes M1O a N bThe pixel electrode PE, the channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Optionally, the pixel electrode PE, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the pixel electrode PE, the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0192] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the first electrode E1 is located in the via hole v. Optionally, the first electrode E1 extends to the via hole v to be connected to the signal line SL.

[0193] Reference Fig.21 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a shading member LS located on the base substrate BS; a buffer layer BUF, which is located on a side of the signal line SL and the shading member LS away from the base substrate BS; a pixel electrode PE, a first electrode E1 (for example, a source of a transistor), a channel region CR, and a second electrode E2 (for example, a drain of a transistor), which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the pixel electrode PE away from the buffer layer BUF; a gate G, which is located on a side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1, which is located on a side of the gate G away from the insulating layer IN; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0194] Fig. 22 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig. 22 The structure shown is Fig.21 The structure shown is similar, but with Fig.21 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig. 22 The array substrate depicted in FIG.

[0195] Fig.23 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.24 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.24 is along Fig.23 The cross-sectional view of the line E-E' in FIG. Fig.23 and Fig.24In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) located on the base substrate BS; a pixel electrode PE, a first electrode E1 (for example, a source of a transistor), a channel region CR, and a second electrode E2 (for example, a drain of a transistor), which are located on a side of the signal line SL away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the pixel electrode PE away from the base substrate BS; a gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0196] Fig.25 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.26 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.26 is along Fig.25 Cross-sectional view of line F-F' in FIG. Fig.25 and Fig.26 In some embodiments, the array substrate includes: a base substrate BS; a pixel electrode PE, a first electrode E1 (e.g., a source of a transistor), a channel region CR, and a second electrode E2 (e.g., a drain of a transistor) located on the base substrate BS; a signal line SL (e.g., a data line providing a data signal to the transistor), which is located on a side of at least the first electrode E1 away from the base substrate BS; an insulating layer IN (e.g., a gate insulating layer), which is located on a side of the signal line SL, the pixel electrode PE, the first electrode E1, the channel region CR, and the second electrode E2 away from the base substrate BS; a gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a common electrode CE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0197] Reference Fig.23 , Fig.24 , Fig.25 and Fig.26 In some embodiments, the material of the pixel electrode PE, the channel region CR, the first electrode E1 and the second electrode E2 includes M1O a N bThe pixel electrode PE, the channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Optionally, the pixel electrode PE, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the pixel electrode, the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0198] Reference Fig.23 , Fig.24 , Fig.25 and Fig.26 In some embodiments, the signal line SL is in direct contact with the first electrode E1. Fig.25 and Fig.26 In the embodiment depicted in FIG, the entirety of the combination of the signal line SL, the pixel electrode PE, the channel region CR, the first electrode E1, and the second electrode E2 is located between the insulating layer IN and the base substrate BS. The signal line SL, the pixel electrode PE, the channel region CR, the first electrode E1, and the second electrode E2 all directly contact the surface (e.g., the upper surface) of the base substrate BS. Optionally, the signal line SL, the pixel electrode PE, the channel region CR, the first electrode E1, and the second electrode E2 all directly contact the surface (e.g., the lower surface) of the insulating layer IN.

[0199] Reference Fig.23 and Fig.24 , in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (eg Fig.24 ), the first electrode E1 covers at least a portion of the upper surface of the signal line SL, and optionally also covers at least one of the two side surfaces of the signal line SL, wherein the signal line SL extends along the length direction LD. The orthographic projection of the first electrode E1 on the substrate substrate BS at least partially overlaps with the orthographic projection of the signal line SL on the substrate substrate BS.

[0200] Reference Fig.25 and Fig.26 , in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (for example, Fig.26 In the cross section shown in FIG. 1 , the signal line SL covers at least a portion of the upper surface of the first electrode E1, and optionally also covers at least a side surface of the first electrode E1, wherein the signal line SL extends along the length direction LD. The orthographic projection of the signal line SL on the substrate BS at least partially overlaps with the orthographic projection of the first electrode E1 on the substrate BS.

[0201] Fig.27A is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.28 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.28 is along Fig.27A Cross-sectional view of line G-G' in Fig. Fig.27A and Fig.28 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a light shielding member LS located on the base substrate BS; a buffer layer BUF located on a side of the signal line SL and the light shielding member LS away from the base substrate BS; a first electrode E1 (for example, a source of a transistor), a channel region CR, a second electrode E2 (for example, a drain of a transistor) and a common electrode CE located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), It is located on the side of at least the channel region CR and the common electrode CE away from the buffer layer BUF; the gate G is located on the side of the insulating layer IN away from the channel region CR; the interlayer dielectric layer ILD is located on the side of the gate G away from the insulating layer IN; the first passivation layer PVX1 is located on the side of the interlayer dielectric layer ILD away from the insulating layer IN; the planarization layer PLN is located on the side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; and the pixel electrode PE is located on the side of the planarization layer PLN away from the first passivation layer PVX1.

[0202] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the first electrode E1 or a portion of the second electrode E2 is subjected to a process to make it more conductive. a N b When M1O in the first electrode E1 or the second electrode E2 a N b At least a portion of the substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0203] Fig.29 It is shown Fig.28 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Fig.27A , Fig.28 and Fig.29 The first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least part of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0204] In some embodiments, reference Fig.27A, Fig.28 and Fig.29 The second electrode E2 includes a third electrode portion E2-1 and a fourth electrode portion E2-2 which are electrically connected to each other. The third electrode portion E2-1 and the fourth electrode portion E2-2 are made of different materials. Optionally, the fourth electrode portion E2-2 is in direct contact with the third electrode portion E2-1 and is located on a side of the third electrode portion E2-1 away from the substrate BS.

[0205] exist Fig.27A and Fig.28 In the array substrate depicted in , the common electrode CE is located in the same layer as the channel region CR, at least a portion of the first electrode E1, or at least a portion of the second electrode E2, and the pixel electrode PE is located on a side of the first passivation layer PVX1 away from the channel region CR, at least a portion of the first electrode E1, or at least a portion of the second electrode E2. Fig.14A and Fig.15 In the array substrate depicted in the figure, the pixel electrode PE is located on the same layer as the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2, and the common electrode CE is located on a side of the first passivation layer PVX1 away from the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2.

[0206] In some embodiments, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 are an integrated structure. In some embodiments, the material of the common electrode CE, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 includes M1O a N b Optionally, the common electrode CE, at least a portion of the first electrode E1, or at least a portion of the second electrode E2 is different from the channel region CR in that the common electrode CE, at least a portion of the first electrode E1, or at least a portion of the second electrode E2 undergoes a conductorization process. In an example, the common electrode CE, the channel region CR, at least a portion of the first electrode E1, and at least a portion of the second electrode E2 include indium gallium tin oxide.

[0207] In some embodiments, the second electrode portion E1-2 and the fourth electrode portion E2-2 are formed after forming the gate G. For example, the second electrode portion E1-2 and the fourth electrode portion E2-2 are in a layer located at a side of the gate G away from the substrate BS.

[0208] Fig.27B is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.27B The structure of the array substrate depicted in Fig.27A The structure of the array substrate depicted in is similar, except that Fig.27BThe array substrate depicted in FIG. 1 does not have a light shielding member.

[0209] Fig.27C is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.27C The structure of the array substrate depicted in Fig.27A The structure of the array substrate depicted in is similar, except that Fig.27C The array substrate depicted in FIG. has a dual-gate thin film transistor. Fig.27C As shown, the two parts of the gate are parts of the second signal line SL2. The second signal line SL2 includes a protrusion that protrudes from the body of the second signal line in a direction substantially parallel to the length direction LD. The orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of one of the two parts of the active layer ACT on the substrate.

[0210] Fig.27D is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.27D The structure of the array substrate depicted in Fig.27C The structure of the array substrate depicted in is similar, except that Fig.27D The array substrate depicted in FIG. 1 does not have a light shielding member.

[0211] Fig.27E is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.27E The structure of the array substrate depicted in Fig.27C The structure of the array substrate is similar to that described in FIG. Fig.27C and Fig.27E In the array substrate depicted in FIG, the second signal line SL2 includes a protrusion GP protruding away from the main body MB of the second signal line SL2. The main body MB extends in a direction substantially perpendicular to the length direction LD, for example, and the protrusion GP extends in a direction substantially parallel to the length direction LD, for example. The protrusion GP includes a portion used as, for example, a gate of a transistor. Fig.27C In the array substrate depicted in FIG. 1 , the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on both sides of the body MB. Fig.27E In the array substrate depicted in FIG. 1 , the protrusion GP and the pixel electrode PE electrically connected to the same transistor are located on the same side of the body MB.

[0212] Fig.27F is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.27F The structure of the array substrate depicted in Fig.27E The structure of the array substrate depicted in is similar, except that Fig.27F The array substrate depicted in FIG. 1 does not have a light shielding member.

[0213] In some embodiments, the insulating layer IN is formed to extend substantially throughout the array substrate, such as Fig.28 shown.

[0214] In some embodiments, the insulating layer does not extend substantially throughout the array substrate. For example, the orthographic projection of the insulating layer on the base substrate does not overlap at least partially with the orthographic projection of the signal line on the base substrate, and does not overlap at least partially with the orthographic projection of the first electrode or the second electrode on the base substrate.

[0215] Fig.30 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.30 The structure shown is Fig.28 The structure shown is similar, but with Fig.28 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig.30 The array substrate depicted in FIG.

[0216] Fig.31 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.31 Can be along Fig.27A Cross-sectional view along line G-G'. Fig.32 It is shown Fig.31 Schematic diagram of the structure of the first electrode, the channel region and the second electrode in the array substrate depicted in FIG. Fig.31 and Fig.32 In some embodiments, the first electrode E1 includes a first electrode portion E1-1 and a second electrode portion E1-2 that are electrically connected to each other. The first electrode portion E1-1 and the second electrode portion E1-2 are made of different materials. Optionally, at least a portion of the first electrode portion E1-1 extends into the second electrode portion E1-2.

[0217] Reference Fig.31 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a shading member LS located on the base substrate BS; a buffer layer BUF, which is located on a side of the signal line SL and the shading member LS away from the base substrate BS; a first electrode E1 (for example, a source of a transistor), a channel region CR, a second electrode E2 (for example, a drain of a transistor) and a common electrode CE, which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the common electrode CE away from the buffer layer BUF; a gate G, which is located on a side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1, which is located on a side of the gate G away from the insulating layer IN; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a pixel electrode PE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0218] In some embodiments, when the material of the channel region CR, the first electrode E1 or the second electrode E2 includes M1O a N b When the material of the channel region CR, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the first electrode E1 or a portion of the second electrode E2 is subjected to a process to make it more conductive. a N b When M1O in the first electrode E1 or the second electrode E2 a N b At least a portion of the substrate is subjected to a lightly doped drain process (eg, a lightly doped ion implantation process).

[0219] exist Fig.31 and Fig.32 In the array substrate depicted in , the common electrode CE is located in the same layer as the channel region CR, at least a portion of the first electrode E1, or at least a portion of the second electrode E2, and the pixel electrode PE is located on a side of the first passivation layer PVX1 away from the channel region CR, at least a portion of the first electrode E1, or at least a portion of the second electrode E2. Fig.18 and Fig.19 In the array substrate depicted in the figure, the pixel electrode PE is located on the same layer as the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2, and the common electrode CE is located on a side of the first passivation layer PVX1 away from the channel region CR, at least a portion of the first electrode E1 or at least a portion of the second electrode E2.

[0220] In some embodiments, the second electrode portion E1-2 and the gate G are located in the same layer and include the same electrode material. In another example, the second electrode portion E1-2 and the gate G are formed in the same patterning process using the same mask.

[0221] Fig.33 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.33 The structure shown is Fig.31 The structure shown is similar, but with Fig.31 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig.33 The array substrate depicted in FIG.

[0222] Fig.34 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.34In some embodiments, the materials of the common electrode CE, the channel region CR, the first electrode E1 and the second electrode E2 include M1OaNb. The channel region CR, the first electrode E1 and the second electrode E2 are an integral structure. Optionally, the common electrode CE, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the common electrode CE, the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0223] In some embodiments, the array substrate includes a via hole v extending at least through the buffer layer BUF. At least a portion of the first electrode E1 is located in the via hole v. Optionally, the first electrode E1 extends to the via hole v to be connected to the signal line SL.

[0224] Reference Fig.34 In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) and a shading member LS located on the base substrate BS; a buffer layer BUF, which is located on a side of the signal line SL and the shading member LS away from the base substrate BS; a common electrode CE, a first electrode E1 (for example, a source of a transistor), a channel region CR, and a second electrode E2 (for example, a drain of a transistor), which are located on a side of the buffer layer BUF away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the common electrode CE away from the buffer layer BUF; a gate G, which is located on a side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1, which is located on a side of the gate G away from the insulating layer IN; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a pixel electrode PE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0225] Fig.35 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.35 The structure shown is Fig.34 The structure shown is similar, but with Fig.34 The structure shown differs at least in that the insulating layer IN does not extend substantially throughout the Fig.35 The array substrate depicted in FIG.

[0226] Fig.36 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.37 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.37 is along Fig.36 Cross-sectional view of line H-H' in FIG. Fig.36 and Fig.37In some embodiments, the array substrate includes: a base substrate BS; a signal line SL (for example, a data line providing a data signal to a transistor) located on the base substrate BS; a common electrode CE, a first electrode E1 (for example, a source of a transistor), a channel region CR, and a second electrode E2 (for example, a drain of a transistor), which are located on a side of the signal line SL away from the base substrate BS; an insulating layer IN (for example, a gate insulating layer), which is located on a side of at least the channel region CR and the common electrode CE away from the base substrate BS; a gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a pixel electrode PE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0227] Fig.38 is a plan view of an array substrate according to some embodiments of the present disclosure. Fig.39 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.39 is along Fig.38 The cross-sectional view of the line I-I' in FIG. Fig.38 and Fig.39 In some embodiments, the array substrate includes: a base substrate BS; a common electrode CE, a first electrode E1 (e.g., a source of a transistor), a channel region CR, and a second electrode E2 (e.g., a drain of a transistor) located on the base substrate BS; a signal line SL (e.g., a data line providing a data signal to the transistor), which is located on a side of at least the first electrode E1 away from the base substrate BS; an insulating layer IN (e.g., a gate insulating layer), which is located on a side of the signal line SL, the common electrode CE, the first electrode E1, the channel region CR, and the second electrode E2 away from the base substrate BS; a gate G, which is located on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1, which is located on a side of the gate G away from the base substrate BS; a planarization layer PLN, which is located on a side of the first passivation layer PVX1 away from the insulating layer IN; and a pixel electrode PE, which is located on a side of the planarization layer PLN away from the first passivation layer PVX1.

[0228] Reference Fig.36 , Fig.37 , Fig.38 and Fig.39 In some embodiments, the materials of the common electrode CE, the channel region CR, the first electrode E1 and the second electrode E2 include M1O a N bThe channel region CR, the first electrode E1 and the second electrode E2 are an integrated structure. Optionally, the common electrode CE, the first electrode E1 or the second electrode E2 is different from the channel region CR in that at least a portion of the pixel electrode, the first electrode E1 or the second electrode E2 undergoes a conductorization process.

[0229] Reference Fig.36 , Fig.37 , Fig.38 and Fig.39 In some embodiments, the signal line SL is in direct contact with the first electrode E1. Fig.38 and Fig.39 In the embodiment depicted in FIG, the entirety of the combination of the signal line SL, the common electrode CE, the channel region CR, the first electrode E1 and the second electrode E2 is located between the insulating layer IN and the base substrate BS. The signal line SL, the common electrode CE, the channel region CR, the first electrode E1 and the second electrode E2 all directly contact the surface (e.g., the upper surface) of the base substrate BS. Optionally, the signal line SL, the common electrode CE, the channel region CR, the first electrode E1 and the second electrode E2 all directly contact the surface (e.g., the lower surface) of the insulating layer IN.

[0230] Reference Fig.36 and Fig.37 , in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (eg Fig.37 ), the first electrode E1 covers at least a portion of the upper surface of the signal line SL, and optionally also covers at least one of the two side surfaces of the signal line SL, wherein the signal line SL extends along the length direction LD. The orthographic projection of the first electrode E1 on the substrate substrate BS at least partially overlaps with the orthographic projection of the signal line SL on the substrate substrate BS.

[0231] Reference Fig.38 and Fig.39 , in a cross section along a plane perpendicular to the substrate BS and perpendicular to the length direction LD and intersecting the signal line SL (for example, Fig.39 In the cross section shown in FIG. 1 , the signal line SL covers at least a portion of the upper surface of the first electrode E1, and optionally also covers at least a side surface of the first electrode E1, wherein the signal line SL extends along the length direction LD. The orthographic projection of the signal line SL on the substrate BS at least partially overlaps with the orthographic projection of the first electrode E1 on the substrate BS.

[0232] On the other hand, the present invention provides a display device, including an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is a liquid crystal display device. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device. In one example, the display device is a high transmittance advanced super-dimensional field conversion (ADS) type display device.

[0233] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of signal lines and a plurality of second signal lines that cross each other to define a plurality of sub-pixels. The method includes: forming a signal line on a substrate substrate; forming a buffer layer on a side of the signal line away from the substrate substrate; forming an active layer on a side of the buffer layer away from the substrate substrate; forming a second signal line on a side of the active layer away from the signal line; forming a first passivation layer on a side of the second signal line away from the substrate substrate; forming a planarization layer on a side of the second signal line away from the active layer; forming a pixel electrode on a side of the planarization layer away from the substrate substrate; forming a first via hole that at least extends through the buffer layer and exposes at least part of the signal line; and forming a second via hole that at least extends through the first passivation layer and exposes at least part of the signal line. Optionally, with respect to the same second signal line, the first minimum distance between the orthographic projection of the first via hole on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate is greater than the second minimum distance between the orthographic projection of the second via hole on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate.

[0234] FIG. 40A to FIG. 40H The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 40A to FIG. 40H Can be used to make e.g. Figure 2 The array substrate depicted in FIG. FIG. 40A to FIG. 40H, a signal line SL and a shading member LS are formed on the substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the shading member LS away from the substrate BS; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the buffer layer BUF; a gate G is formed on the side of the insulating layer IN away from the buffer layer BUF, thereby forming a channel region in the semiconductor material layer; an interlayer dielectric layer ILD is formed on the side of the gate G away from the insulating layer IN; a via v is formed to extend through the interlayer dielectric layer ILD, the insulating layer IN and the buffer layer to expose the surface of the signal line SL; a via v' is formed to extend through the interlayer dielectric layer ILD and the insulating layer IN to expose the surface of the semiconductor material layer outside the channel region CR; A conductive material is deposited in the hole v and the via v' to form a first electrode E1 and a second electrode E2; a first passivation layer PVX1 is formed on a side of the first electrode E1 and the second electrode E2 away from the substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; a common electrode CE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2 is formed on a side of the common electrode CE away from the planarization layer PLN; a via v'' is formed to extend through the second passivation layer PVX2, the planarization layer PLN and the first passivation layer PVX1 to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the second passivation layer PVX2 away from the planarization layer PLN, and the pixel electrode PE extends to the via v'' to be connected to the second electrode E2. FIG. 40A to FIG. 40H The process depicted in uses a total of nine masks.

[0235] FIG. 41A to FIG. 41H The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 41A to FIG. 41H Can be used to make e.g. Figure 4 Array substrate depicted in FIG. FIG. 41A to FIG. 41H The process described in FIG. 40A to FIG. 40H The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0236] FIG. 42A to FIG. 42G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 42A to FIG. 42G Can be used to make e.g. Figure 5 The array substrate depicted in FIG. FIG. 42A to FIG. 42G, forming a signal line SL and a light shielding member LS on a substrate BS; forming a buffer layer BUF on a side of the signal line SL and the light shielding member LS away from the substrate BS; forming a semiconductor material layer SML on a side of the buffer layer BUF away from the substrate BS; forming an insulating layer IN on a side of the semiconductor material layer SML away from the buffer layer BUF; forming a via v to extend through the insulating layer IN and the buffer layer to expose the surface of the signal line SL; depositing a conductive material and patterning it to form a gate G and a portion of the first electrode E1 extending to the via v to connect to the signal line SL; forming a via hole v on a side of the first electrode E1 and the gate G away from the substrate BS A first passivation layer PVX1 is formed; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; a common electrode CE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2 is formed on a side of the common electrode CE away from the planarization layer PLN; a via hole v'' is formed to extend through the second passivation layer PVX2, the planarization layer PLN and the first passivation layer PVX1 to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the second passivation layer PVX2 away from the planarization layer PLN, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. FIG. 42A to FIG. 42G The process depicted in uses a total of eight masks.

[0237] FIG. 43A to FIG. 43G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 43A to FIG. 43G Can be used to make e.g. Figure 7 Array substrate depicted in FIG. FIG. 43A to FIG. 43G The process described in FIG. 42A to FIG. 42G The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0238] FIG. 44A to FIG. 44G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 44A to FIG. 44G Can be used to make e.g. Figure 8 The array substrate depicted in FIG. FIG. 44A to FIG. 44G, a signal line SL and a light shielding member LS are formed on the substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the substrate BS; a via v is formed to extend through the buffer layer to expose the surface of the signal line SL; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS, and a part of the semiconductor material layer SML extends to the via v to be connected to the signal line SL; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the buffer layer BUF; a gate G is formed on the side of the insulating layer IN away from the buffer layer BUF; a first passivation layer is formed on the side of the gate G away from the substrate BS a planarization layer PVX1; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2 is formed on a side of the common electrode CE away from the planarization layer PLN; a via hole v'' is formed to extend through the second passivation layer PVX2, the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the second passivation layer PVX2 away from the planarization layer PLN, the pixel electrode PE extending to the via hole v'' to be connected to the second electrode E2. FIG. 40A to FIG. 40H The process depicted in uses a total of eight masks.

[0239] Figures 45A to 45G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 45A to 45G Can be used to make e.g. Fig. 9 Array substrate depicted in FIG. Figures 45A to 45G The process described in FIG. 44A to FIG. 44G The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0240] FIG. 46A to FIG. 46F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 46A to FIG. 46F Can be used to make e.g. Fig.11 The array substrate depicted in FIG. FIG. 46A to FIG. 46F, a signal line SL is formed on the base substrate BS; a semiconductor material layer SML is formed on the side of the signal line SL away from the base substrate BS; an insulating layer IN is formed on the side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on the side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on the side of the gate G away from the base substrate BS; a planarization layer PLN is formed on the side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on the side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2 is formed on the side of the common electrode CE away from the planarization layer PLN; a via hole v'' is formed to extend through the second passivation layer PVX2, the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on the side of the second passivation layer PVX2 away from the planarization layer PLN, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. FIG. 46A to FIG. 46F The process depicted in uses a total of seven masks.

[0241] FIG. 47A to FIG. 47F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 47A to FIG. 47F Can be used to make e.g. Fig.13 The array substrate depicted in FIG. FIG. 47A to FIG. 47F , a semiconductor material layer SML is formed on the base substrate BS; a signal line SL is formed on the side of the semiconductor material layer SML away from the base substrate BS; an insulating layer IN is formed on the side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on the side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on the side of the gate G away from the base substrate BS; a planarization layer PLN is formed on the side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on the side of the planarization layer PLN away from the first passivation layer PVX1; a second passivation layer PVX2 is formed on the side of the common electrode CE away from the planarization layer PLN; a via hole v'' is formed to extend through the second passivation layer PVX2, the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on the side of the second passivation layer PVX2 away from the planarization layer PLN, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. FIG. 47A to FIG. 47F The process depicted in uses a total of seven masks.

[0242] FIG. 48A to FIG. 48G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 48A to FIG. 48G Can be used to make e.g. Fig.15 The array substrate depicted in FIG. FIG. 48A to FIG. 48G, a signal line SL and a light shielding member LS are formed on the substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the substrate BS; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS, and the semiconductor material layer SML is formed so that the pixel electrode PE is formed as a part of the semiconductor material layer SML; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the buffer layer BUF; a gate G is formed on the side of the insulating layer IN away from the buffer layer BUF, thereby forming a channel region CR in the semiconductor material layer; an interlayer dielectric layer ILD is formed on the side of the gate G away from the insulating layer IN; a via v is formed to extend through the interlayer dielectric layer ILD, the insulating layer IN and the buffer layer to expose the signal line SL surface; forming a via v' to extend through the interlayer dielectric layer ILD and the insulating layer IN to expose the surface of the portion of the semiconductor material layer located outside the channel region CR; depositing a conductive material in the via v and the via v' to form a first electrode E1 and a second electrode E2; forming a first passivation layer PVX1 on a side of the first electrode E1 and the second electrode E2 away from the substrate BS; forming a planarization layer PLN on a side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; forming a via v", to extend through the first passivation layer PVX1 and the planarization layer PLN to expose the surface of the second electrode E2; forming a common electrode CE on a side of the planarization layer PLN away from the first passivation layer PVX1, and the common electrode CE extends to the via v", to be connected to the second electrode E2. FIG. 48A to FIG. 48G The process depicted in uses a total of eight masks.

[0243] FIG. 49A to FIG. 49G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 49A to FIG. 49G Can be used to make e.g. Fig.17 Array substrate depicted in FIG. FIG. 49A to FIG. 49G The process described in FIG. 48A to FIG. 48G The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0244] FIG. 50A to FIG. 50F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 50A to FIG. 50F Can be used to make e.g. Fig.18 The array substrate depicted in FIG. FIG. 50A to FIG. 50F, a signal line SL and a shading member LS are formed on a base substrate BS; a buffer layer BUF is formed on a side of the signal line SL and the shading member LS away from the base substrate BS; a semiconductor material layer SML is formed on a side of the buffer layer BUF away from the base substrate BS, and the semiconductor material layer SML is formed so that the pixel electrode PE is formed as a part of the semiconductor material layer SML; an insulating layer IN is formed on a side of the semiconductor material layer SML away from the buffer layer BUF; a via v is formed to extend through the insulating layer IN and the buffer layer to expose the surface of the signal line SL; a conductive material is deposited and patterned to form a gate G and a portion of the first electrode E1 extending to the via v to connect to the signal line SL; a first passivation layer PVX1 is formed on a side of the first electrode E1 and the gate G away from the base substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1. FIG. 50A to FIG. 50F The process depicted in uses a total of seven masks.

[0245] Figures 51A to 51F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 51A to 51F Can be used to make e.g. Fig. 20 Array substrate depicted in FIG. Figures 51A to 51F The process described in FIG. 50A to FIG. 50F The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0246] FIG. 52A to FIG. 52F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 52A to FIG. 52F Can be used to make e.g. Fig.21 The array substrate depicted in FIG. FIG. 52A to FIG. 52F , a signal line SL and a light shielding member LS are formed on the base substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the base substrate BS; a via v is formed to extend through the buffer layer to expose the surface of the signal line SL; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the base substrate BS, a portion of the semiconductor material layer SML extends to the via v to be connected to the signal line SL, and the semiconductor material layer SML is formed so that the pixel electrode PE is formed as a portion of the semiconductor material layer SML; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the buffer layer BUF; a gate G is formed on the side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1 is formed on the side of the gate G away from the base substrate BS; a planarization layer PLN is formed on the side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on the side of the planarization layer PLN away from the first passivation layer PVX1. FIG. 52A to FIG. 52FThe process depicted in uses a total of seven masks.

[0247] Figures 53A to 53F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 53A to 53F Can be used to make e.g. Fig. 22 Array substrate depicted in FIG. Figures 53A to 53F The process described in FIG. 52A to FIG. 52F The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0248] FIG. 54A to FIG. 54E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 54A to FIG. 54E Can be used to make e.g. Fig.24 The array substrate depicted in FIG. FIG. 54A to FIG. 54E A signal line SL is formed on the base substrate BS; a semiconductor material layer SML is formed on a side of the signal line SL away from the base substrate BS, and the semiconductor material layer SML is formed so that the pixel electrode PE is formed as a part of the semiconductor material layer SML; an insulating layer IN is formed on a side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on a side of the gate G away from the base substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a common electrode CE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1. FIG. 54A to FIG. 54E The process depicted in uses a total of six masks.

[0249] FIG. 55A to FIG. 55E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 55A to FIG. 55E Can be used to make e.g. Fig.26 The array substrate depicted in FIG. FIG. 55A to FIG. 55E A semiconductor material layer SML is formed on the base substrate BS, and the semiconductor material layer SML is formed so that the pixel electrode PE is formed as a part of the semiconductor material layer SML; a signal line SL is formed on the side of the semiconductor material layer SML away from the base substrate BS; an insulating layer IN is formed on the side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on the side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on the side of the gate G away from the base substrate BS; a planarization layer PLN is formed on the side of the first passivation layer PVX1 away from the insulating layer IN; and a common electrode CE is formed on the side of the planarization layer PLN away from the first passivation layer PVX1. FIG. 55A to FIG. 55E The process depicted in uses a total of six masks.

[0250] FIG. 56A to FIG. 56GThe invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 56A to FIG. 56G Can be used to make e.g. Fig.28 The array substrate depicted in FIG. FIG. 56A to FIG. 56G , a signal line SL and a light shielding member LS are formed on the substrate BS; a buffer layer BUF is formed on the side of the signal line SL and the light shielding member LS away from the substrate BS; a semiconductor material layer SML is formed on the side of the buffer layer BUF away from the substrate BS, and the semiconductor material layer SML is formed so that the common electrode CE is formed as a part of the semiconductor material layer SML; an insulating layer IN is formed on the side of the semiconductor material layer SML away from the buffer layer BUF; a gate G is formed on the side of the insulating layer IN away from the buffer layer BUF, thereby forming a channel region CR in the semiconductor material layer; an interlayer dielectric layer ILD is formed on the side of the gate G away from the insulating layer IN; a via v is formed to extend through the interlayer dielectric layer ILD, the insulating layer IN and the buffer layer to expose the surface of the signal line SL surface; forming a via hole v' to extend through the interlayer dielectric layer ILD and the insulating layer IN to expose the surface of the portion of the semiconductor material layer located outside the channel region CR; depositing a conductive material in the via hole v and the via hole v' to form a first electrode E1 and a second electrode E2; forming a first passivation layer PVX1 on a side of the first electrode E1 and the second electrode E2 away from the substrate BS; forming a planarization layer PLN on a side of the first passivation layer PVX1 away from the interlayer dielectric layer ILD; forming a via hole v", extending through the first passivation layer PVX1 and the planarization layer PLN to expose the surface of the second electrode E2; and forming a pixel electrode PE on a side of the planarization layer PLN away from the first passivation layer PVX1, the pixel electrode PE extending to the via hole v", to be connected to the second electrode E2. FIG. 56A to FIG. 56G The process depicted in uses a total of eight masks.

[0251] FIG. 57A to FIG. 57G The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. FIG. 57A to FIG. 57G Can be used to make e.g. Fig.30 Array substrate depicted in FIG. FIG. 57A to FIG. 57G The process described in FIG. 56A to FIG. 56G The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0252] Figures 58A to 58F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 58A to 58F Can be used to make e.g. Fig.31 The array substrate depicted in FIG. Figures 58A to 58F, forming a signal line SL and a light shielding member LS on a substrate BS; forming a buffer layer BUF on a side of the signal line SL and the light shielding member LS away from the substrate BS; forming a semiconductor material layer SML on a side of the buffer layer BUF away from the substrate BS, the semiconductor material layer SML being formed so that the common electrode CE is formed as a part of the semiconductor material layer SML; forming an insulating layer IN on a side of the semiconductor material layer SML away from the buffer layer BUF; forming a via hole v to extend through the insulating layer IN and the buffer layer to expose the surface of the signal line SL; depositing a conductive material and patterning it to form a gate electrode; A gate G and a portion of the first electrode E1 extending to the via hole v to be connected to the signal line SL; a first passivation layer PVX1 is formed on a side of the first electrode E1 and the gate G away from the substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a via hole v'' is formed to extend through the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. Figures 58A to 58F The process depicted in uses a total of seven masks.

[0253] Figures 59A to 59F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 59A to 59F Can be used to make e.g. Fig.33 Array substrate depicted in FIG. Figures 59A to 59F The process described in Figures 58A to 58F The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0254] Figures 60A to 60F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 60A to 60F Can be used to make e.g. Fig.34 The array substrate depicted in FIG. Figures 60A to 60F, a signal line SL and a light shielding member LS are formed on the substrate BS; a buffer layer BUF is formed on a side of the signal line SL and the light shielding member LS away from the substrate BS; a via v is formed to extend through the buffer layer to expose the surface of the signal line SL; a semiconductor material layer SML is formed on a side of the buffer layer BUF away from the substrate BS, a portion of the semiconductor material layer SML extends to the via v to be connected to the signal line SL, and the semiconductor material layer SML is formed so that the common electrode CE is formed as a portion of the semiconductor material layer SML; a via v is formed on the semiconductor material layer SML away from the buffer layer BUF An insulating layer IN is formed on one side of the insulating layer IN; a gate G is formed on a side of the insulating layer IN away from the buffer layer BUF; a first passivation layer PVX1 is formed on a side of the gate G away from the substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a via hole v'' is formed to extend through the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. Figures 60A to 60F The process depicted in uses a total of seven masks.

[0255] Figures 61A to 61F The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 61A to 61F Can be used to make e.g. Fig.35 Array substrate depicted in FIG. Figures 61A to 61F The process described in Figures 60A to 60F The process depicted in is similar, except that the insulating layer IN is patterned and does not extend throughout the array substrate.

[0256] Figures 62A to 62E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 62A to 62E It can be used to make, for example Fig.37 The array substrate depicted in FIG. Figures 62A to 62E, a signal line SL is formed on the base substrate BS; a semiconductor material layer SML is formed on a side of the signal line SL away from the base substrate BS, the semiconductor material layer SML is formed so that the common electrode CE is formed as a part of the semiconductor material layer SML; an insulating layer IN is formed on a side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on a side of the gate G away from the base substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a via hole v'' is formed to extend through the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1, the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. Figures 62A to 62E The process depicted in uses a total of six masks.

[0257] Figures 63A to 63E The invention shows a process of manufacturing an array substrate according to some embodiments of the present disclosure. Figures 63A to 63E Can be used to make e.g. Fig.39 The array substrate depicted in FIG. Figures 63A to 63E A semiconductor material layer SML is formed on a base substrate BS, and the semiconductor material layer SML is formed so that a common electrode CE is formed as a part of the semiconductor material layer SML; a signal line SL is formed on a side of the semiconductor material layer SML away from the base substrate BS; an insulating layer IN is formed on a side of the signal line SL and the semiconductor material layer SML away from the base substrate BS; a gate G is formed on a side of the insulating layer IN away from the base substrate BS; a first passivation layer PVX1 is formed on a side of the gate G away from the base substrate BS; a planarization layer PLN is formed on a side of the first passivation layer PVX1 away from the insulating layer IN; a via hole v'' is formed to extend through the planarization layer PLN, the first passivation layer PVX1 and the insulating layer IN to expose the surface of the second electrode E2; and a pixel electrode PE is formed on a side of the planarization layer PLN away from the first passivation layer PVX1, and the pixel electrode PE extends to the via hole v'' to be connected to the second electrode E2. Figures 63A to 63E The process depicted in uses a total of six masks.

[0258] Example 1: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer to form a shading member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to form a buffer layer with a thickness between 100 nm and 700 nm; Sputtering indium gallium zinc oxide to a thickness between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating layer on a side of the semiconductor material layer away from the substrate; sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the insulating layer and the buffer layer away from the substrate, the electrode material comprising a molybdenum-neodymium-copper stacking structure, an MTD-copper stacking structure, or a molybdenum-neodymium-copper-MTD stacking structure; patterning the electrode material layer; and depositing a conductive layer on the substrate (e.g., by plasma enhanced chemical vapor deposition). The method comprises the following steps: depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) by a deposition process to form an interlayer dielectric layer with a thickness between 200 nm and 400 nm; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on a substrate, wherein the electrode material comprises a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200 nm and 400 nm; A resin layer with a thickness between 2 μm and 3 μm is coated on the first passivation layer; a conductive material layer with a thickness between 40 nm and 100 nm is deposited on the first passivation layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100 nm and 300 nm; and a conductive material layer with a thickness between 40 nm and 135 nm is deposited on the second passivation layer using indium tin oxide or indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 1 corresponds to FIG. 40A to FIG. 40H The process described in .

[0259] Example 2: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum laminated structure, a molybdenum-neodymium-copper laminated structure, an MTD-copper laminated structure, or a molybdenum-neodymium-copper-MTD laminated structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to form a buffer layer with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm; The method comprises the following steps: patterning an InGaZn material to form a semiconductor material layer; forming an insulating material layer on a side of the semiconductor material layer away from the substrate by using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material; sputtering an electrode material layer with a thickness between 200nm and 1200nm on a side of the insulating layer and the buffer layer away from the substrate, wherein the electrode material includes a molybdenum-neodymium-copper stacking structure, an MTD-copper stacking structure or a molybdenum-neodymium-copper-MTD stacking structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate (for example, by a plasma enhanced chemical vapor deposition process) to form an interlayer dielectric with a thickness between 200nm and 400nm layer; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the substrate, the electrode material comprising a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer; patterning the insulating material layer to form an insulating layer, the insulating layer does not substantially extend throughout the array substrate, and the orthographic projection of the insulating layer on the substrate substrate does not at least partially overlap with the orthographic projection of the signal line on the substrate substrate, and does not at least partially overlap with the orthographic projection of the first electrode or the second electrode on the substrate substrate; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate (for example, by a plasma enhanced chemical vapor deposition process), To form a first passivation layer with a thickness between 200nm and 400nm; coating a resin layer with a thickness between 2μm and 3μm on the first passivation layer; using indium gallium zinc oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 100nm on the first passivation layer, and patterning the conductive material layer to form a common electrode; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; and using indium tin oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 135nm on the second passivation layer, and patterning the conductive material layer to form a pixel electrode. The process described in Example 2 corresponds to FIG. 41A to FIG. 41H The process described in .

[0260] Example 3: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100nm and 1000nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer to form a shading member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to form a buffer layer with a thickness between 100nm and 700nm; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10nm and 80nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on a side of the semiconductor material layer away from the base substrate; sputtering a layer with a thickness between 200nm and 1200nm on a side of the insulating layer and the buffer layer away from the base substrate. m, the electrode material layer including a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on a substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200nm and 400nm; coating a resin layer with a thickness between 2μm and 3μm on the first passivation layer; using indium gallium zinc oxide or indium zinc oxide to form a first passivation layer with a thickness between 2μm and 3μm; A conductive material layer with a thickness between 40nm and 100nm is deposited on the passivation layer, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; and a conductive material layer with a thickness between 40nm and 135nm is deposited on the second passivation layer using indium tin oxide or indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 3 corresponds to FIG. 42A to FIG. 42G The process described in .

[0261] Example 4: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to form a light shielding member LS and a signal line SL with a thickness between 100 nm and 700 nm; sputtering indium gallium zinc oxide on a substrate to a thickness between 10nm and 80nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material to form an insulating material layer on a side of the semiconductor material layer away from the substrate; sputtering an electrode material layer with a thickness between 200nm and 1200nm on a side of the insulating layer and the buffer layer away from the substrate, the electrode material comprising a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure or a molybdenum-neodymium-copper-MTD stacked structure ; patterning the electrode material layer; patterning the insulating material layer to form an insulating layer, the insulating layer does not extend substantially throughout the array substrate, the orthographic projection of the insulating layer on the substrate substrate does not overlap at least partially with the orthographic projection of the signal line on the substrate substrate, and does not overlap at least partially with the orthographic projection of the first electrode or the second electrode on the substrate substrate; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200 nm and 400 nm; coating a first passivation layer with a thickness between 2 μm and 1 μm on the first passivation layer; A resin layer with a thickness between 3 μm and 10 μm is deposited on the first passivation layer; a conductive material layer with a thickness between 40 nm and 100 nm is deposited on the first passivation layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100 nm and 300 nm; and a conductive material layer with a thickness between 40 nm and 135 nm is deposited on the second passivation layer using indium tin oxide or indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 4 corresponds to FIG. 43A to FIG. 43G The process described in .

[0262] Example 5: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to Forming a buffer layer with a thickness between 100nm and 700nm; forming a via extending through the buffer layer to expose the surface of the signal line; sputtering indium gallium zinc oxide to a thickness between 10nm and 80nm on the substrate, a portion of the indium gallium zinc oxide extending through the via in the buffer layer to connect to the signal line; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on a side of the semiconductor material layer away from the substrate; between the insulating layer and the buffer layer sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side away from the substrate, wherein the electrode material includes a molybdenum-neodymium-copper stacking structure, an MTD-copper stacking structure, or a molybdenum-neodymium-copper-MTD stacking structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200 nm and 400 nm; coating a resin layer with a thickness between 2 μm and 3 μm on the first passivation layer; using Depositing a conductive material layer with a thickness between 40nm and 100nm on the first passivation layer using indium gallium zinc oxide or indium zinc oxide, and patterning the conductive material layer to form a common electrode; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; and depositing a conductive material layer with a thickness between 40nm and 135nm on the second passivation layer using indium tin oxide or indium zinc oxide, and patterning the conductive material layer to form a pixel electrode. The process described in Example 5 corresponds to FIG. 44A to FIG. 44G The process described in .

[0263] Example 6: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the base substrate (for example, by a chemical vapor deposition process) to form a buffer layer with a thickness between 100 nm and 700 nm; forming A via extending through the buffer layer exposes the surface of the signal line; sputtering indium gallium zinc oxide to a thickness between 10nm and 80nm on the substrate, a portion of the indium gallium zinc oxide extending through the via in the buffer layer to connect to the signal line; patterning the indium gallium zinc oxide material to form a semiconductor material layer; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating material layer on a side of the semiconductor material layer away from the substrate; sputtering an electrode material layer with a thickness between 200nm and 1200nm on a side of the insulating layer and the buffer layer away from the substrate, the electrode material comprising a molybdenum-neodymium-copper stack structure, MTD-copper stacked structure or molybdenum-neodymium-copper-MTD stacked structure; patterning the electrode material layer; patterning the insulating material layer to form an insulating layer, the insulating layer does not substantially extend throughout the array substrate, the orthographic projection of the insulating layer on the substrate substrate does not overlap with the orthographic projection of the signal line on the substrate substrate at least partially, and does not overlap with the orthographic projection of the first electrode or the second electrode on the substrate substrate at least partially; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200nm and 400nm; A resin layer with a thickness between 2 μm and 3 μm is coated on the passivation layer; a conductive material layer with a thickness between 40 nm and 100 nm is deposited on the first passivation layer using indium gallium zinc oxide or indium zinc oxide, and the conductive material layer is patterned to form a common electrode; an insulating material (silicon oxide or silicon nitride / silicon oxide) is deposited on the substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100 nm and 300 nm; and a conductive material layer with a thickness between 40 nm and 135 nm is deposited on the second passivation layer using indium tin oxide or indium zinc oxide, and the conductive material layer is patterned to form a pixel electrode. The process described in Example 6 corresponds to Figures 45A to 45G The process described in .

[0264] Example 7: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm; patterning the indium gallium zinc oxide material to form a semiconductor material layer; patterning the electrode material layer to form a light shielding member LS and a signal line SL on the base substrate BS; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on a side of the semiconductor material layer and the signal line layer away from the base substrate; sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the insulating layer and the buffer layer away from the base substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD- Copper stack structure or molybdenum-neodymium-copper-MTD stack structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on a substrate substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200nm and 400nm; coating a resin layer with a thickness between 2μm and 3μm on the first passivation layer; using indium gallium zinc oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 100nm on the first passivation layer, and patterning the conductive material layer to form a common electrode; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on a substrate substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; and using indium tin oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 135nm on the second passivation layer, and patterning the conductive material layer to form a pixel electrode. The process described in Example 7 corresponds to FIG. 46A to FIG. 46F The process described in .

[0265] Example 8: In one example, a method for manufacturing an array substrate includes: cleaning a base substrate; sputtering indium gallium zinc oxide on the base substrate to a thickness between 10 nm and 80 nm; depositing an electrode material layer with a thickness between 100 nm and 1000 nm on the base substrate, the electrode material including a molybdenum-aluminum-aluminum stacked structure, a molybdenum-neodymium-copper stacked structure, an MTD-copper stacked structure, or a molybdenum-neodymium-copper-MTD stacked structure; patterning the indium gallium zinc oxide material to form a semiconductor material layer; patterning the electrode material layer to form a shading member LS and a signal line SL on the base substrate BS; using a chemical vapor deposition process or an atomic layer deposition process and using silicon oxide as an insulating material, forming an insulating layer on a side of the semiconductor material layer and the signal line layer away from the base substrate; sputtering an electrode material layer with a thickness between 200 nm and 1200 nm on a side of the insulating layer and the buffer layer away from the base substrate, the electrode material including a molybdenum-neodymium-copper stacked structure, an MTD- Copper stack structure or molybdenum-neodymium-copper-MTD stack structure; patterning the electrode material layer; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on a substrate substrate (for example, by a plasma enhanced chemical vapor deposition process) to form a first passivation layer with a thickness between 200nm and 400nm; coating a resin layer with a thickness between 2μm and 3μm on the first passivation layer; using indium gallium zinc oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 100nm on the first passivation layer, and patterning the conductive material layer to form a common electrode; depositing an insulating material (silicon oxide or silicon nitride / silicon oxide) on a substrate substrate (for example, by a chemical vapor deposition process) to form a second passivation layer with a thickness between 100nm and 300nm; and using indium tin oxide or indium zinc oxide to deposit a conductive material layer with a thickness between 40nm and 135nm on the second passivation layer, and patterning the conductive material layer to form a pixel electrode. The process described in Example 8 corresponds to FIG. 47A to FIG. 47F The process described in .

[0266] Fig.64 FIG. 2 shows the layout of signal lines in an array substrate according to some embodiments of the present disclosure. Fig.64 , the plurality of signal lines SL and the plurality of second signal lines SL2 cross each other, defining a plurality of sub-pixels sp.

[0267] Fig.65 1 shows the relative positions of via holes in an array substrate according to some embodiments of the present disclosure. Fig.65 and Figure 2In some embodiments, the array substrate includes a first via hole v1 extending at least through the buffer layer BUF. The first electrode E1 is at least partially in the first via hole v1. Optionally, the first electrode E1 extends through the first via hole v1 to be connected to the signal line SL. In some embodiments, the array substrate includes a second via hole v2 extending at least through the first passivation layer PVX1. At least a portion of the pixel electrode PE is located in the second via hole v2. Optionally, the pixel electrode PE extends to the second via hole v2 to be connected to the second electrode E2.

[0268] In some embodiments, with respect to the same second signal line, the first minimum distance between the orthographic projection of the first via v1 on the substrate substrate BS and the orthographic projection of the second signal line SL2 on the substrate substrate BS is represented as d1; the second minimum distance between the orthographic projection of the second via v2 on the substrate substrate BS and the orthographic projection of the second signal line SL2 on the substrate substrate BS is represented as d2, where d1 and d2 are greater than 0. In some embodiments, with respect to the same second signal line, the first minimum distance d1 is greater than the second minimum distance d2.

[0269] In some embodiments, the signal line SL includes a first portion P1 and a second portion P2. The first portion P1 is a portion of the signal line located in the first via v1. The second portion P2 is electrically connected to the first portion. In some embodiments, along the extension direction of the second signal line SL2, the first portion P1 has a first line width w1, and the second portion P2 has a second line width w2. Optionally, the first line width w1 is greater than the second line width w2.

[0270] Fig.66 The structure of the second signal line in the array substrate in some embodiments of the present disclosure is shown. Fig.66 In some embodiments, the second signal line SL2 includes a main body MB and a protrusion P, and the protrusion P protrudes away from the main body MB. The protrusion P and the main body MB are located in the same layer and are made of the same material. Optionally, the protrusion P and the main body MB are an integral structure. The main body MB extends along the extension direction of the second signal line SL2, and the protrusion P protrudes away from the main body MB in a direction different from the extension direction of the second signal line SL2.

[0271] In some embodiments, the orthographic projection of the body MB on the substrate separates the orthographic projection of the protrusion P on the substrate from the orthographic projection of the first via v1 on the substrate. Optionally, the orthographic projection of the protrusion P on the substrate separates the orthographic projection of the signal line SL on the substrate from the orthographic projection of the second via v2 on the substrate.

[0272] Fig.67 is a scanning electron microscopic image of a portion of an array substrate in some embodiments of the present disclosure. Fig.67, which shows the main body MB and the protrusion P of the second signal line. Fig.67 A second via v2 extending at least through the first passivation layer is depicted. Fig.66 and Fig.67 In some embodiments, the protrusion P has a shape that is wider in a portion close to the body MB and narrower in a portion far from the body MB.

[0273] Fig.68 is a plan view of an array substrate in some embodiments of the present disclosure. Fig.68 In some embodiments, an orthographic projection of the active layer on the substrate at least partially overlaps an orthographic projection of the protrusion on the substrate.

[0274] In some embodiments, the array substrate further includes a shading member LS. In some embodiments, the shading member LS is located on the same layer as the signal line SL. Optionally, the orthographic projection of the shading member LS on the base substrate overlaps at least partially with the orthographic projection of the second signal line SL2 on the base substrate. The inventors of the present disclosure have found that this unique structure helps to achieve a maximum aperture ratio in the array substrate.

[0275] In some embodiments, the orthographic projection of the shading member LS on the substrate at least partially overlaps with the orthographic projection of a portion of the second signal line SL2 on the substrate. Optionally, along the length direction LD (the extension direction of the signal line SL), at least one of the two boundaries of the orthographic projection of a portion of the second signal line SL2 on the substrate is completely located between the two boundaries of the orthographic projection of the shading member LS on the substrate.

[0276] In some embodiments, the minimum distance between the light shielding member LS and the signal line SL is in the range of 1.0 μm to 5.0 μm, for example, 1.0 μm to 2.0 μm, 2.0 μm to 3.0 μm, 3.0 μm to 4.0 μm, or 4.0 μm to 5.0 μm. In one example, the minimum distance is 3.0 μm. In another example, the minimum distance is 2.0 μm.

[0277] Fig.69 is a cross-sectional view of an array substrate in some embodiments of the present disclosure. Fig.69 and Fig.67In some embodiments, the array substrate includes: a first via v1 extending at least through the buffer layer BUF; a second via v2 extending at least through the first passivation layer PVX1; and a third via v3 extending at least through the planarization layer PLN. At least a portion of the first electrode E1 is located in the first via v1. Optionally, the first electrode E1 extends to the first via v1 to connect to the signal line SL. At least a portion of the pixel electrode PE is located in the second via v2. Optionally, the pixel electrode PE extends to the second via v2 to connect to the second electrode E2. At least a portion of the pixel electrode PE is located in the third via v3. Optionally, the pixel electrode PE extends to the third via v3 and enters the second via v2.

[0278] Fig.70 1 shows the relative positions of via holes in an array substrate according to some embodiments of the present disclosure. Fig.69 and Fig.70 In some embodiments, the orthographic projection of the third via v3 on the substrate substrate BS partially overlaps with the orthographic projection of the shading element LS on the substrate substrate BS. Optionally, at least 1% (e.g., at least 5%, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80% or at least 90%) of the orthographic projection of the third via v3 on the substrate substrate BS overlaps with the orthographic projection of the shading element LS on the substrate substrate BS. Optionally, no more than 90% (e.g., no more than 80%, no more than 70%, no more than 60%, no more than 50%, no more than 40%, no more than 30%, no more than 20%, no more than 10%, no more than 5% or no more than 1%) of the orthographic projection of the third via v3 on the substrate substrate BS overlaps with the orthographic projection of the shading element LS on the substrate substrate BS.

[0279] Fig.71 is a scanning electron microscopic image of a portion of an array substrate in some embodiments of the present disclosure. Fig.71 In some embodiments, the second via v2 has a first slope angle θ1 and the third via v3 has a second slope angle θ2. In some embodiments, the difference between the first slope angle θ1 and the second slope angle θ2 is in the range of 0 to 25 degrees. In one example, the first slope angle θ1 is greater than the second slope angle θ2. In an alternative example, the second slope angle θ2 is greater than the first slope angle θ1.

[0280] In some embodiments, the orthographic projection of the third via v3 on the substrate substrate BS at least partially overlaps with the orthographic projection of the second via v2 on the substrate substrate BS. Optionally, the orthographic projection of the third via v3 on the substrate substrate BS is larger than the orthographic projection of the second via v2 on the substrate substrate BS. Optionally, the orthographic projection of the third via v3 on the substrate substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the second via v2 on the substrate substrate BS.

[0281] Fig.72 is a scanning electron microscopic image of a portion of an array substrate in some embodiments of the present disclosure. Fig.72 In some embodiments, the buffer layer BUF includes a first portion PT1 and a second portion PT2. The first portion PT1 is a sidewall of the first via v1. The first portion PT1 separates the second portion PT2 from the first via v1. The orthographic projection of the first portion PT1 on the substrate BS at least partially overlaps with the orthographic projection of the signal line SL on the substrate BS. The orthographic projection of the second portion PT2 on the substrate BS does not overlap with the orthographic projection of the signal line SL on the substrate BS.

[0282] In some embodiments, a first height of the first portion PT1 relative to the surface S of the base substrate BS is greater than a second height of the second portion PT2 relative to the surface S of the base substrate BS.

[0283] In some embodiments, the average line width of the signal line SL is in the range of 0.7 μm to 3.5 μm, for example, 0.7 μm to 1.0 μm, 1.0 μm to 1.5 μm, 1.5 μm to 2.0 μm, 2.0 μm to 2.5 μm, 2.5 μm to 3.0 μm, or 3.0 μm to 3.5 μm. In one example, the average line width of the signal line SL is in the range of 1.0 μm to 2.5 μm.

[0284] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising a plurality of signal lines and a plurality of second signal lines, wherein the signal lines and the second signal lines cross each other to define a plurality of sub-pixels; The array substrate comprises: substrate substrate; A signal line located on the substrate; A buffer layer, located on a side of the signal line away from the substrate; An active layer, which is located on a side of the buffer layer away from the substrate; a second signal line located on a side of the active layer away from the signal line; A first passivation layer, which is located on a side of the second signal line away from the substrate; a planarization layer, located on a side of the second signal line away from the active layer; A pixel electrode, located on a side of the planarization layer away from the base substrate; a first via hole extending at least through the buffer layer and exposing at least a portion of the signal line; and a second via hole extending at least through the first passivation layer and exposing at least a portion of the pixel electrode; Among them, relative to the same second signal line, a first minimum distance between the orthographic projection of the first via on the base substrate and the orthographic projection of the second signal line on the base substrate is greater than a second minimum distance between the orthographic projection of the second via on the base substrate and the orthographic projection of the second signal line on the base substrate.

2. The array substrate according to claim 1, wherein: The signal line includes a first portion and a second portion; The first portion is a portion of the signal line located in the first via hole; The second portion is electrically connected to the first portion; Along the extending direction of the second signal line, the first portion has a first line width, and the second portion has a second line width, The first line width is greater than the second line width.

3. The array substrate according to claim 1, wherein: The second signal line includes a main body and a protruding portion protruding away from the main body; The main body extends along the extension direction of the second signal line; The protrusion protrudes away from the main body along a direction different from the extending direction of the second signal line; The orthographic projection of the main body on the base substrate separates the orthographic projection of the protrusion on the base substrate from the orthographic projection of the first via hole on the base substrate; as well as The orthographic projection of the protruding portion on the base substrate separates the orthographic projection of the signal line on the base substrate from the orthographic projection of the second via hole on the base substrate.

4. The array substrate according to claim 3, wherein: An orthographic projection of the active layer on the base substrate at least partially overlaps with the orthographic projection of the protrusion on the base substrate.

5. The array substrate according to claim 1, wherein: The active layer includes a first electrode region, a second electrode region, and a channel region located between the first electrode region and the second electrode region; the first electrode region includes a first electrode, and the second electrode region includes a second electrode; wherein the channel region, at least a portion of the first electrode, and at least a portion of the second electrode are an integrated structure; and The material of at least a portion of the first electrode and at least a portion of the second electrode is the same as the material of the channel region and is subjected to a conductorization process; The first electrode extends to the first via hole to be connected to the signal line; and The pixel electrode extends to the second via hole to be connected to the second electrode.

6. The array substrate according to claim 1, further comprising a light shielding member; in, The light shielding member and the signal line are located at the same layer; and The orthographic projection of the light shielding member on the base substrate at least partially overlaps with the orthographic projection of the second signal line on the base substrate.

7. The array substrate according to claim 1, further comprising a light shielding member; in, The orthographic projection of the light shielding member on the base substrate at least partially overlaps with the orthographic projection of a portion of the second signal line on the base substrate; as well as Along the extending direction of the signal line, at least one of two boundaries of the orthographic projection of the portion of the second signal line on the base substrate is completely located between two boundaries of the orthographic projection of the light shielding member on the base substrate.

8. The array substrate according to claim 1, further comprising a light shielding member; in, A minimum distance between the light shielding member and the signal line is in a range of 1.0 μm to 5.0 μm.

9. The array substrate according to claim 1, further comprising a third via hole extending at least through the planarization layer; in, An orthographic projection of the third via hole on the base substrate partially overlaps with an orthographic projection of the light shielding member on the base substrate.

10. The array substrate according to claim 1, wherein: The buffer layer includes a first portion and a second portion; The first portion is a sidewall of the first via hole; The first portion spaces the second portion apart from the first via; The orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; The orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the signal line on the substrate; as well as A first height of the first portion relative to the surface of the base substrate is greater than a second height of the second portion relative to the surface of the base substrate.

11. The array substrate according to claim 1, wherein: The average line width of the signal line is in the range of 0.7 μm to 3.5 μm.

12. The array substrate according to claim 5, wherein: The material of the channel region, at least a portion of the first electrode, and at least a portion of the second electrode includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0, and b≥0; and At least a portion of the first electrode and at least a portion of the second electrode are subjected to a lightly doped drain process.

13. The array substrate according to claim 5, wherein: The first electrode includes a first electrode portion and a second electrode portion electrically connected to each other; and The first electrode portion and the second electrode portion are made of different materials.

14. The array substrate according to claim 13, wherein: The material of the first electrode portion includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0, and b≥0; The second electrode portion includes a metal material; and The first electrode portion, at least a portion of the second electrode, and the channel region are an integrated structure.

15. The array substrate according to claim 13, wherein: At least a portion of the first electrode portion extends into the second electrode portion.

16. The array substrate according to claim 13, further comprising: An insulating layer, located on a side of the active layer away from the substrate; a gate, which is located on a side of the insulating layer away from the active layer; as well as a via extending through the insulating layer and the buffer layer to expose a surface of a portion of the signal line; Wherein, the first electrode portion and the gate are located in the same layer; The first electrode portion extends through the via hole to be connected to the signal line.

17. The array substrate according to claim 13, further comprising: An insulating layer, located on a side of the active layer away from the substrate; a gate, which is located on a side of the insulating layer away from the active layer; an interlayer dielectric layer, which is located on a side of the gate away from the insulating layer; as well as A via hole extending through the interlayer dielectric layer, the insulating layer and the buffer layer to expose a surface of a portion of the signal line; Wherein, the first electrode portion is in a layer located on a side of the interlayer dielectric layer away from the insulating layer; as well as The first electrode portion extends to the via hole to be connected to the signal line.

18. The array substrate according to claim 5, wherein: The second electrode includes a third electrode portion and a fourth electrode portion electrically connected to each other; and The third electrode portion and the fourth electrode portion are made of different materials.

19. The array substrate according to claim 18, wherein: The material of the third electrode portion includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0, and b≥0; The fourth electrode portion includes a metal material; and At least a portion of the first electrode, the channel region, and the third electrode portion are an integral structure.

20. The array substrate according to claim 18, further comprising: An insulating layer, located on a side of the active layer away from the substrate; a gate, which is located on a side of the insulating layer away from the active layer; an interlayer dielectric layer, which is located on a side of the gate away from the insulating layer; as well as a via hole extending through the interlayer dielectric layer and the insulating layer to expose a surface of a portion of the third electrode portion; Wherein, the fourth electrode portion is in a layer located on a side of the interlayer dielectric layer away from the insulating layer; as well as The fourth electrode portion extends to the via hole to be connected to the third electrode portion.

21. The array substrate according to claim 5, wherein: The channel region, the entire first electrode, and the entire second electrode are an integrated structure.

22. The array substrate according to claim 21, further comprising a via hole extending through the buffer layer to expose a surface of a portion of the signal line; in, The first electrode portion extends to the via hole to be connected to the signal line.

23. The array substrate according to claim 21, further comprising: an insulating layer located on the substrate, and A gate, which is located on a side of the insulating layer away from the substrate; Wherein, the signal line, the channel region, the first electrode and the second electrode are integrally located between the insulating layer and the base substrate; The signal line, the channel region, the first electrode and the second electrode all directly contact the surface of the base substrate; and The signal line, the channel region, the first electrode, and the second electrode all directly contact a surface of the insulating layer.

24. The array substrate according to claim 23, wherein: In a cross section along a plane perpendicular to the base substrate and perpendicular to the length direction and intersecting the signal line, the first electrode covers at least a portion of the upper surface of the signal line, wherein the signal line extends along the length direction; and An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the signal line on the base substrate.

25. The array substrate according to claim 23, wherein: In a cross section along a plane perpendicular to the base substrate and perpendicular to the length direction and intersecting the signal line, the signal line covers at least a portion of the upper surface of the first electrode, wherein the signal line extends along the length direction; and An orthographic projection of the signal line on the base substrate at least partially overlaps with an orthographic projection of the first electrode on the base substrate.

26. The array substrate according to claim 5, further comprising a pixel electrode electrically connected to the second electrode; in, The pixel electrode, the channel region, at least a portion of the first electrode, and at least a portion of the second electrode are located in the same layer and are an integrated structure.

27. The array substrate according to claim 26, further comprising: A gate, which is located on a side of the active layer away from the substrate; A passivation layer, located on a side of the gate away from the substrate; as well as A common electrode, which is located on a side of the passivation layer away from the substrate; The common electrode and the pixel electrode are configured to form an electric field in response to a voltage at the second electrode, thereby driving an image display in a sub-pixel.

28. The array substrate according to claim 5, further comprising a common electrode configured to be provided with a low voltage signal; in, The common electrode, the channel region, at least a portion of the first electrode, and at least a portion of the second electrode are located in a same layer and are made of the same material.

29. The array substrate according to claim 28, further comprising: A gate, which is located on a side of the active layer away from the substrate; A passivation layer, located on a side of the gate away from the substrate; A pixel electrode, which is located on a side of the passivation layer away from the base substrate; as well as a via hole extending at least through the passivation layer to expose a surface of a portion of the second electrode; Wherein, the pixel electrode extends to the via hole to be connected to the second electrode; as well as The common electrode and the pixel electrode are configured to form an electric field in response to a voltage at the second electrode, thereby driving an image display in a sub-pixel.

30. A display device comprising the array substrate according to any one of claims 1 to 29 and one or more integrated circuits connected to the array substrate.

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