Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate which is provided with a peripheral area located on the first side of a display area; the plurality of first electrode patterns, the plurality of second electrode patterns and the plurality of light-emitting layer patterns are arranged in the display area of the substrate in an array mode in the first direction and the second direction; the pixel defining layer is located on the side, away from the substrate, of the layer where the first electrode patterns are located, the pixel defining layer comprises a plurality of pixel openings, and the pixel openings expose at least one part of the first electrode patterns respectively; at least a part of the plurality of light-emitting layer patterns are respectively located in the plurality of pixel openings; orthographic projections of at least one part of the plurality of second electrode patterns on the substrate are mutually spaced in the first direction and the second direction; the plurality of electrode wires are located in at least one conductive layer between the substrate and the layer where the second electrode pattern is located, and at least one electrode wire is electrically connected with the second electrode pattern.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display devices are self-luminous devices with advantages such as high response, high contrast, and flexibility, and are widely used in the display field. In order to achieve the light transmittance of OLED, the top-emitting electrode on the light-emitting surface of the top-emitting OLED needs to have good light transmittance. Generally speaking, the top-emitting electrode used adopts an electrode set on the entire surface, and uses materials such as indium tin oxide and indium zinc oxide, and the top-emitting electrode is overlapped and connected to the power supply line VSS. Since the top-emitting electrode is set on the entire surface, and in order to improve the light transmittance, the thickness of the fixed emission is relatively thin, resulting in a high impedance of the top-emitting electrode, and a large voltage drop between the side area and the center area at the VSS overlap, resulting in poor brightness uniformity of the OLED product. When the area of ​​the OLED display device increases, it becomes particularly obvious.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0004] Summary of the Invention

[0005] In order to solve at least one aspect of the above problems, the embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device, which can at least reduce the voltage drop of the display panel and improve display uniformity.

[0006] In one aspect, a display panel is provided, comprising:

[0007] a base substrate, the base substrate comprising a display area and a peripheral area at least located on a first side of the display area;

[0008] a plurality of first electrode patterns, wherein the plurality of first electrode patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate;

[0009] a pixel defining layer, the pixel defining layer being located on a side of the layer where the plurality of first electrode patterns are located away from the base substrate, the pixel defining layer comprising a plurality of pixel openings, each of the plurality of pixel openings exposing at least a portion of the plurality of first electrode patterns;

[0010] a plurality of light-emitting layer patterns, the plurality of light-emitting layer patterns being arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and at least a portion of the plurality of light-emitting layer patterns being respectively located in the plurality of pixel openings;

[0011] a plurality of second electrode patterns, the plurality of second electrode patterns being located on a side of a layer where the plurality of light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns being arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and orthographic projections of at least a portion of the plurality of second electrode patterns on the base substrate being spaced apart from each other in the first direction and the second direction; and

[0012] a plurality of electrode traces, wherein the plurality of electrode traces are located in at least one conductive layer between the substrate and the layer where the second electrode pattern is located, and at least one of the electrode traces is electrically connected to at least one of the second electrode patterns through a second electrode via.

[0013] Wherein, the orthographic projection of the second electrode via on the base substrate is located in the display area.

[0014] In some exemplary embodiments of the present disclosure, the display panel includes a plurality of pixel units, which are arranged in an array along a first direction and a second direction in a display area of ​​the substrate, and at least one of the pixel units includes a plurality of sub-pixels;

[0015] At least one of the pixel units includes at least one second electrode pattern and at least one second electrode via hole; and / or at least one of the pixel units includes more than two second electrode patterns and more than two second electrode via holes.

[0016] In some exemplary embodiments of the present disclosure, in the same pixel unit, at least two sub-pixels share one second electrode pattern and one second electrode via hole, and another sub-pixel has a separate second electrode pattern and a separate second electrode via hole.

[0017] In some exemplary embodiments of the present disclosure, all of the multiple sub-pixels of at least one pixel unit share one second electrode pattern and one second electrode via hole.

[0018] In some exemplary embodiments of the present disclosure, all of the plurality of sub-pixels of at least one of the pixel units respectively have their own second electrode patterns and their own second electrode via holes.

[0019] In some exemplary embodiments of the present disclosure, at least one of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the plurality of electrode traces include a first electrode trace, a second electrode trace, and a third electrode trace;

[0020] The shared second electrode pattern is electrically connected to the first electrode trace and the second electrode trace through the shared second electrode via hole; the second electrode pattern of the other sub-pixel is electrically connected to the third electrode trace through the separate second electrode via hole;

[0021] The first electrode trace and the second electrode trace are connected to the same voltage signal, and the first electrode trace and the third electrode trace are connected to different voltage signals.

[0022] In some exemplary embodiments of the present disclosure, all of the multiple sub-pixels of at least one of the pixel units include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the multiple electrode traces include a first electrode trace, a second electrode trace, and a third electrode trace;

[0023] The second electrode pattern of the first sub-pixel is electrically connected to the second electrode via through the first electrode trace, the second electrode pattern of the second sub-pixel is electrically connected to the second electrode via through the second electrode trace, and the second electrode pattern of the third sub-pixel is electrically connected to the second electrode via through the third electrode trace;

[0024] At least two of the first electrode wiring, the second electrode wiring, and the third electrode wiring are connected to different voltage signals.

[0025] In some exemplary embodiments of the present disclosure, at least one of the pixel units includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the plurality of electrode traces include a first electrode trace, a second electrode trace, and a third electrode trace;

[0026] The shared second electrode pattern is electrically connected to the first electrode trace, the second electrode trace, and the third electrode trace through the shared second electrode via hole;

[0027] The first electrode wiring, the second electrode wiring, and the third electrode wiring are connected to the same voltage signal.

[0028] In some exemplary embodiments of the present disclosure, the display panel includes:

[0029] a buffer layer disposed on the base substrate;

[0030] A semiconductor layer disposed on a side of the buffer layer away from the substrate;

[0031] A first insulating layer provided on a side of the semiconductor layer away from the substrate;

[0032] A first conductive layer provided on a side of the first insulating layer away from the base substrate;

[0033] a second insulating layer disposed on a side of the first conductive layer away from the base substrate;

[0034] a second conductive layer disposed on a side of the second insulating layer away from the base substrate;

[0035] a third insulating layer disposed on a side of the second conductive layer away from the base substrate;

[0036] a third conductive layer disposed on a side of the third insulating layer away from the base substrate; and

[0037] a fourth insulating layer provided on a side of the third conductive layer away from the base substrate,

[0038] Part of the orthographic projection of each of the buffer layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer on the base substrate overlaps with the orthographic projection of the second electrode via on the base substrate.

[0039] In some exemplary embodiments of the present disclosure, the second electrode via hole penetrates a portion of the fourth insulating layer and the pixel defining layer; and

[0040] The electrode trace has a first portion and a second portion at the second electrode via hole. The first portion of the electrode trace is located in the third conductive layer, and the second portion of the electrode trace is located in the layer where the first electrode is located.

[0041] In some exemplary embodiments of the present disclosure, the display panel further includes:

[0042] a fifth insulating layer disposed between the third conductive layer and the fourth insulating layer; and

[0043] a fourth conductive layer disposed between the fifth insulating layer and the fourth insulating layer,

[0044] Part of the orthographic projection of each of the buffer layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer and the fifth insulating layer on the base substrate overlaps with the orthographic projection of the second electrode via on the base substrate.

[0045] In some exemplary embodiments of the present disclosure, the second electrode via hole penetrates a portion of the fourth insulating layer and the pixel defining layer; and

[0046] The electrode trace has a first portion and a second portion at the second electrode via hole. The first portion of the electrode trace is located in the fourth conductive layer, and the second portion of the electrode trace is located in the layer where the first electrode is located.

[0047] In some exemplary embodiments of the present disclosure, the first portion of the electrode traces is disposed at intervals in the second electrode vias, and the second portion of the electrode traces is disposed continuously in the second electrode vias.

[0048] In some exemplary embodiments of the present disclosure, the electrode trace includes a first sub-electrode trace and a second sub-electrode trace located in the fourth conductive layer, the main body of the first sub-electrode trace extends along the first direction, and the main body of the second sub-electrode trace extends along the second direction;

[0049] The first sub-electrode wiring and the second sub-electrode wiring cross at least in the second electrode via hole.

[0050] In some exemplary embodiments of the present disclosure, the display panel further includes a data signal line, the data signal line being used to provide a data signal to the pixel unit, the data signal line being located in the third conductive layer, and the main body of the data signal line extending along the second direction;

[0051] The orthographic projection of the second sub-electrode wiring on the base substrate at least partially overlaps with the orthographic projection of the data signal line on the base substrate.

[0052] In some exemplary embodiments of the present disclosure, the display panel further includes a voltage signal line, wherein the voltage signal line is used to provide a voltage signal to the first electrode pattern of the pixel unit; and

[0053] The voltage signal line includes a first voltage signal sub-line and a second voltage signal sub-line. The main body of the first voltage signal sub-line extends along a first direction, and the main body of the second voltage signal sub-line extends along a second direction.

[0054] In some exemplary embodiments of the present disclosure, the display panel includes a plurality of second voltage signal sub-lines, at least one of the second voltage signal sub-lines is located in the third conductive layer, and at least another of the second voltage signal sub-lines is located in the fourth conductive layer;

[0055] The orthographic projection of at least one of the second voltage signal sub-lines in the third conductive layer on the substrate and the orthographic projection of the second sub-electrode line on the substrate are spaced apart at least in the second electrode via, and the orthographic projection of at least another second voltage signal sub-line in the fourth conductive layer on the substrate and the orthographic projection of the second sub-electrode line on the substrate are spaced apart.

[0056] In some exemplary embodiments of the present disclosure, at least another second voltage signal sub-line located in the fourth conductive layer extends through a gap between the first portion of the electrode trace and the second electrode via.

[0057] In some exemplary embodiments of the present disclosure, the display panel includes a plurality of second sub-electrode traces, at least one of the second sub-electrode traces includes a winding portion, and at least one of the second sub-electrode traces extends through an area where the first electrode pattern is located through the winding portion; and

[0058] At least another second sub-electrode wiring is disconnected at the area where the first electrode pattern is located.

[0059] In some exemplary embodiments of the present disclosure, the winding portion includes a first sub-winding portion, a second sub-winding portion, and a third sub-winding portion, the first sub-winding portion and the third sub-winding portion extend along a first direction, and the second sub-winding portion extends along a second direction;

[0060] For the same second sub-electrode routing, the orthographic projection of the second sub-winding portion located in the area where the first electrode pattern is located on the base substrate is closer to the edge of the first electrode pattern than the orthographic projection of the portion of the second sub-electrode routing located outside the area where the first electrode pattern is located on the base substrate.

[0061] In some exemplary embodiments of the present disclosure, the first electrode pattern includes a first electrode main portion and a first electrode connecting portion, the display panel further includes a first electrode via hole, and an orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with an orthographic projection of the first electrode via hole on the base substrate;

[0062] The second electrode pattern includes a second electrode main portion and a second electrode connecting portion, and an orthographic projection of the second electrode connecting portion on the base substrate at least partially overlaps with an orthographic projection of the second electrode via on the base substrate;

[0063] The first electrode connecting portion protrudes outward from the first electrode main body portion, and the orthographic projection of a portion of the first electrode connecting portion on the base substrate does not overlap with the orthographic projection of the first electrode main body portion on the base substrate; the orthographic projection of the second electrode connecting portion on the base substrate falls within the orthographic projection of the second electrode main body portion on the base substrate.

[0064] In some exemplary embodiments of the present disclosure, the orthographic projection of the first electrode via on the base substrate falls within the orthographic projection of the second electrode pattern on the base substrate; and / or,

[0065] The orthographic projection of the second electrode via on the base substrate is spaced apart from the orthographic projection of the first electrode pattern on the base substrate.

[0066] In some exemplary embodiments of the present disclosure, the display panel further includes a hole transport layer pattern and an electron transport layer pattern, and the orthographic projection of each of the hole transport layer pattern and the electron transport layer pattern on the base substrate is spaced apart from the orthographic projection of the second electrode via on the base substrate.

[0067] In some exemplary embodiments of the present disclosure, the display panel includes a plurality of control chips arranged in the peripheral area, one of the plurality of control chips is used to provide a voltage signal to at least one of the voltage signal line, the first electrode line, the second electrode line, and the third electrode line, respectively, and another of the plurality of control chips is used to provide a voltage signal to at least another one of the voltage signal line, the first electrode line, the second electrode line, and the third electrode line, respectively; or,

[0068] The display panel includes a control chip arranged in the peripheral area, and the control chip is used to provide voltage signals to the voltage signal line, the first electrode wiring, the second electrode wiring, and the third electrode wiring respectively.

[0069] In some exemplary embodiments of the present disclosure, the orthographic projection of the second electrode via on the base substrate has a first via edge and a second via edge, the first via edge being close to the first electrode pattern, and the second via edge being close to an edge of the second electrode pattern;

[0070] The vertical distance between the edge of the first via hole and the closest edge of the first electrode pattern is greater than or equal to 30 microns; and / or the vertical distance between the edge of the second via hole and the closest edge of the second electrode pattern is greater than or equal to 30 microns.

[0071] Another aspect of the present disclosure provides a display device, wherein the display device includes the display panel as described above.

[0072] Another aspect of the present disclosure provides a method for manufacturing a display panel, wherein the method includes:

[0073] Providing a base substrate, the base substrate comprising a display area and a peripheral area at least located on a first side of the display area;

[0074] forming a plurality of first electrode patterns on the base substrate, wherein the plurality of first electrode patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate;

[0075] forming a pixel defining layer on a side of the layer where the plurality of first electrode patterns are located away from the base substrate, wherein the pixel defining layer comprises a plurality of pixel openings, each of the plurality of pixel openings exposing at least a portion of the plurality of first electrode patterns;

[0076] forming a plurality of second electrode via holes in the display area of ​​the base substrate;

[0077] forming a plurality of light-emitting layer patterns, the plurality of light-emitting layer patterns being arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, at least a portion of the plurality of light-emitting layer patterns being respectively located in the plurality of pixel openings, wherein orthographic projections of the plurality of light-emitting layer patterns on the base substrate are spaced apart from orthographic projections of the plurality of second electrode vias on the base substrate;

[0078] forming a plurality of electrode traces on the substrate; and

[0079] A plurality of second electrode patterns are formed on a side of the layer where the plurality of light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and orthographic projections of at least a portion of the plurality of second electrode patterns on the base substrate are spaced apart from each other in the first direction and the second direction.

[0080] The plurality of electrode traces are located in at least one conductive layer between the base substrate and the layer where the second electrode pattern is located, and at least one of the electrode traces is electrically connected to at least one of the second electrode patterns through a second electrode via. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0082] FIG1A is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure;

[0083] FIG1B is a schematic cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure;

[0084] FIG2A is a schematic planar structural diagram of a pixel unit of a display panel according to an exemplary embodiment of the present disclosure;

[0085] FIG2B is a schematic planar structural diagram of a pixel unit of a display panel according to another exemplary embodiment of the present disclosure;

[0086] FIG3A is a schematic planar structural diagram of electrode wiring included in a display panel according to an exemplary embodiment of the present disclosure;

[0087] FIG3B is a schematic planar structural diagram of electrode wiring included in a display panel according to another exemplary embodiment of the present disclosure;

[0088] FIG4A is a schematic planar structural diagram of a first conductive layer included in a display panel according to an exemplary embodiment of the present disclosure;

[0089] FIG4B is a schematic planar structural diagram of a second conductive layer included in a display panel according to an exemplary embodiment of the present disclosure;

[0090] FIG4C is a schematic planar structural diagram of a third conductive layer included in a display panel according to an exemplary embodiment of the present disclosure;

[0091] FIG4D is a schematic planar structural diagram of a fourth conductive layer included in a display panel according to an exemplary embodiment of the present disclosure;

[0092] FIG4E is a schematic plan view of a display panel including a first electrode pattern according to an exemplary embodiment of the present disclosure;

[0093] FIG4F is a schematic plan view of a display panel including a second electrode pattern according to an exemplary embodiment of the present disclosure;

[0094] FIG5A is a flow chart of a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure;

[0095] FIG5B is a schematic diagram of forming a second electrode via hole in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure;

[0096] 5C is a schematic diagram of an HTL material for forming a light-emitting layer pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure;

[0097] FIG5D is a schematic diagram of an EM material for forming a light-emitting layer pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure;

[0098] 5E-5F are schematic diagrams of forming a second electrode pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0100] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0101] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0102] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0103] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0104] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device, or the dimension along the Z direction in the accompanying drawings.

[0105] In this document, unless otherwise specified, the expression "patterning process" generally includes the steps of photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0106] It should be noted that the terms "same layer," "same layer arrangement," or similar expressions refer to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning this film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0107] In this document, unless otherwise specified, the expression "electrically connected" may mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and electrical signals can be transmitted between the two components; it may also mean that two components or elements are electrically connected through a conductive medium such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit electrical signals between the two components or elements; it may also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit electrical signals between the two components or elements.

[0108] The embodiments of the present disclosure provide at least one display panel, the display panel comprising: a substrate, the substrate comprising a display area and a peripheral area at least located on a first side of the display area; a plurality of first electrode patterns, the plurality of first electrode patterns being arranged in an array along a first direction and a second direction in the display area of ​​the substrate; a pixel defining layer, the pixel defining layer being located on a side of the layer where the plurality of first electrode patterns are located away from the substrate, the pixel defining layer comprising a plurality of pixel openings, the plurality of pixel openings respectively exposing at least a portion of the plurality of first electrode patterns; a plurality of light-emitting layer patterns, the plurality of light-emitting layer patterns being arranged in an array along a first direction and a second direction in the display area of ​​the substrate, at least a portion of the plurality of light-emitting layer patterns are respectively located in the multiple pixel openings; a plurality of second electrode patterns, the plurality of second electrode patterns are located on a side of the layer where the multiple light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns are arranged in an array along a first direction and a second direction in the display area of ​​the base substrate, and the orthographic projections of at least a part of the plurality of second electrode patterns on the base substrate are spaced apart from each other in the first direction and the second direction; and a plurality of electrode traces, the plurality of electrode traces are located in at least one conductive layer between the base substrate and the layer where the second electrode patterns are located, at least one of the electrode traces is electrically connected to at least one second electrode pattern through a second electrode via, and the orthographic projection of the second electrode via on the base substrate is located in the display area.

[0109] According to the display panel of the embodiment of the present disclosure, multiple first electrode patterns and multiple second electrode patterns are set to drive multiple light-emitting layer patterns, and multiple electrode traces are set in at least one conductive layer located between the base substrate and the layer of the second electrode pattern, at least one electrode trace is electrically connected to at least one second electrode pattern through a second electrode via. By avoiding the use of an overall designed second electrode pattern, the voltage drop caused by the overall design of the second electrode pattern is effectively reduced. At the same time, by setting multiple electrode traces, the electrode traces are connected to the second electrode pattern through the second electrode vias located in the display area, which can further improve the display effect.

[0110] The display panel according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 1A to FIG. 4F .

[0111] Fig. 1A is a schematic diagram of a planar structure of a display panel according to some exemplary embodiments of the present disclosure. Fig. 1B is a schematic diagram of a cross-sectional structure of a display panel according to some exemplary embodiments of the present disclosure.

[0112] The display panel 100 includes a base substrate 10 , a first electrode pattern 20 , a pixel defining layer 30 , a light emitting layer pattern 40 , a second electrode pattern 50 and a plurality of electrode traces 60 .

[0113] Exemplarily, as shown in FIG. 1A , the base substrate 10 includes a display area A and a peripheral area B located on a first side of the display area. For example, the peripheral area B is located below the display area A.

[0114] The first electrode pattern 20 may include a plurality of first electrode patterns 20 , and the plurality of first electrode patterns 20 are arranged in an array along the first direction X and the second direction Y in the display area A of the base substrate 10 .

[0115] The pixel defining layer 30 is arranged on the side of the layer where the multiple first electrode patterns 20 are located away from the base substrate 10. The pixel defining layer 30 defines multiple pixel openings, each pixel opening respectively exposing at least a portion of the corresponding first electrode pattern 20. By making each pixel opening respectively expose the corresponding first electrode pattern, it is convenient to drive the light-emitting layer pattern in the pixel opening to emit light or not.

[0116] A plurality of light-emitting layer patterns 40 are arranged in an array along a first direction X and a second direction Y in the display area A of the base substrate 10, and at least a portion of the plurality of light-emitting layer patterns 40 are respectively located in the plurality of pixel openings, that is, at least a portion of the light-emitting layer pattern 40 corresponding to each pixel opening is located within the pixel opening.

[0117] The plurality of second electrode patterns 50 are located on a side of the layer where the plurality of light-emitting layer patterns are located, away from the base substrate 10. The plurality of second electrode patterns 50 are arranged in an array along the first direction X and the second direction Y in the display area A of the base substrate 10. The orthographic projections of at least a portion of the plurality of second electrode patterns 50 on the base substrate 10 are spaced apart from each other in the first direction X and the second direction Y. Different second electrode patterns 50 are spaced apart from each other in the first direction X and the second direction Y. That is, a plurality of second electrode patterns 50 can be provided, and each second electrode pattern 50 can correspond to a sub-pixel in a pixel unit or multiple sub-pixels in a pixel unit.

[0118] For example, the first electrode pattern 20 , the pixel defining layer 30 , the light emitting layer pattern 40 , and the second electrode pattern 50 may be arranged in the same array in the first direction X and the second direction Y to form a display unit of the display panel to display corresponding images.

[0119] Multiple electrode traces 60 are located in at least one conductive layer between the base substrate 10 and the layer where the second electrode pattern 50 is located. For example, multiple electrode traces 60 are located in one conductive layer or multiple conductive layers. At least one electrode trace 60 is electrically connected to at least one second electrode pattern 50 through a second electrode via VH2. The positive projection of the second electrode via VH2 on the base substrate 10 is located in the display area A. By electrically connecting the second electrode pattern 50 to the electrode trace 60, the voltage drop generated by the second electrode pattern 50 can be avoided. At the same time, by setting the second electrode via VH2 in the display area A, the display quality can be improved while avoiding the voltage drop generated by the second electrode pattern.

[0120] In some exemplary embodiments, the display panel 100 includes a plurality of pixel units, as shown in FIG2A and FIG2B , respectively. The plurality of pixel units are arranged in an array along a first direction X and a second direction Y in the display area of ​​the substrate. At least one of the pixel units includes a plurality of sub-pixels. For example, a pixel unit includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. In other optional embodiments, for example, a pixel unit may include a greater or lesser number of sub-pixels, which can be arranged according to actual needs.

[0121] Among the plurality of pixel units, some or all of the pixel units may further include a second electrode pattern and at least one second electrode via hole. Some or all of the pixel units may further include two or more second electrode patterns and two or more second electrode via holes.

[0122] For example, a pixel unit may include a second electrode pattern and one or more second electrode vias.

[0123] For another example, a pixel unit may include a plurality of second electrode patterns and a plurality of electrode vias, and the number of the electrode patterns and the number of the electrode vias may correspond one to one or may not correspond.

[0124] In some embodiments, in the same pixel unit, at least two sub-pixels share a second electrode pattern and a second electrode via hole, and another sub-pixel has a separate second electrode pattern and a separate second electrode via hole.

[0125] In some further embodiments, in a pixel unit, all of the multiple sub-pixels of the pixel unit share one second electrode pattern and one second electrode via hole.

[0126] In some other embodiments, in a pixel unit, all the sub-pixels of the pixel unit have their own corresponding second electrode patterns, and each sub-pixel also has its own corresponding second electrode via hole.

[0127] FIG2A is a schematic planar structural diagram of a pixel unit of a display panel according to an exemplary embodiment of the present disclosure.

[0128] As shown in Figure 2A, a pixel unit may include three second electrode patterns (for example, second electrode pattern 50R, second electrode pattern 50G and second electrode pattern 50B) and three second electrode vias (second electrode via VH2R, second electrode via VH2G, second electrode via VH2B), and each sub-pixel corresponds to a second electrode pattern and a second electrode via.

[0129] FIG2B is a schematic planar structural diagram of a pixel unit of a display panel according to another exemplary embodiment of the present disclosure.

[0130] As shown in Figure 2B, a pixel unit may include two second electrode patterns (second electrode pattern 50R / G and second electrode pattern 50B) and two second electrode vias (second electrode via VH2R / G and second electrode via VH2B), the red sub-pixel R and the green sub-pixel G share the same second electrode pattern and the same second electrode via, and the blue sub-pixel B has another corresponding second electrode pattern and another second electrode via.

[0131] As shown in FIG3A , the pixel unit includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B, and the plurality of electrode traces include a first electrode trace 61, a second electrode trace 62, and a third electrode trace 63. The shared second electrode pattern is electrically connected to the first electrode trace 61 and the second electrode trace 62 through the shared second electrode via. The second electrode pattern of another sub-pixel is electrically connected to the third electrode trace 63 through the separate second electrode via.

[0132] In the pixel unit shown in Figures 3A and 2B, the second electrode pattern is connected to the same voltage signal, such as Vss(R / G), through the first electrode trace 61 and the second electrode trace 62, and the second electrode pattern of another sub-pixel is connected to a different voltage signal, such as Vss(B), through the third electrode trace 63.

[0133] FIG3B is a schematic planar structural diagram of electrode wiring included in a display panel according to another exemplary embodiment of the present disclosure.

[0134] As shown in FIG3B , each pixel unit also includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. The plurality of electrode wirings include a first electrode wiring 61 , a second electrode wiring 62 , and a third electrode wiring 63 .

[0135] For example, the second electrode pattern of the first sub-pixel is electrically connected to the second electrode via through the first electrode routing, the second electrode pattern of the second sub-pixel is electrically connected to the second electrode via through the second electrode routing, and the second electrode pattern of the third sub-pixel is electrically connected to the second electrode via through the third electrode routing.

[0136] At least two of the first electrode lines, the second electrode lines, and the third electrode lines are connected to different voltage signals. For example, the voltage signal connected to the first sub-pixel R through the first electrode line is Vss(R), the voltage signal connected to the second sub-pixel G through the second electrode line is Vss(G), and the voltage signal connected to the third sub-pixel B through the third electrode line is Vss(B). That is, the second electrode pattern corresponding to each sub-pixel in the pixel unit is connected to different electrode lines through the corresponding second electrode vias. Since the sub-pixels correspond to different sub-pixels, the light emission of different sub-pixels has different display effects on the display panel. To this end, the second electrode pattern corresponding to each sub-pixel is connected to different electrode lines through the corresponding second electrode vias, so that the electrical signals of different sub-pixels can be adjusted, thereby further improving the display uniformity of the display panel.

[0137] In another optional embodiment of the present disclosure, each pixel unit includes: a first sub-pixel, a second sub-pixel and a third sub-pixel, and the electrode wiring corresponding to each pixel unit includes a first electrode wiring, a second electrode wiring and a third electrode wiring. The shared second electrode pattern is electrically connected to the first electrode wiring, the second electrode wiring and the third electrode wiring through the shared second electrode via. The first electrode wiring, the second electrode wiring and the third electrode wiring are connected to the same voltage signal. That is, the sub-pixels corresponding to each pixel unit share the same second electrode pattern and second electrode via, and the voltage signal connected to each sub-pixel is the same. Therefore, by arranging multiple electrode wirings, the voltage drop of the voltage signal during transmission can be reduced, thereby improving the display quality of the display panel.

[0138] According to an embodiment of the present disclosure, the second electrode pattern is electrically connected through the second electrode via using an electrode trace and connected to the corresponding voltage signal, which can avoid the voltage drop caused by the voltage signal being conducted in the second electrode pattern, improve the uniformity of the display of the display panel, and effectively improve the display effect of the display panel.

[0139] Figure 4A is a schematic diagram of the planar structure of a first conductive layer included in a display panel of an exemplary embodiment of the present disclosure. Figure 4B is a schematic diagram of the planar structure of a second conductive layer included in a display panel of an exemplary embodiment of the present disclosure. Figure 4C is a schematic diagram of the planar structure of a third conductive layer included in a display panel of an exemplary embodiment of the present disclosure. Figure 4D is a schematic diagram of the planar structure of a fourth conductive layer included in a display panel of an exemplary embodiment of the present disclosure. Figure 4E is a schematic diagram of the planar structure of a first electrode pattern included in a display panel of an exemplary embodiment of the present disclosure. Figure 4F is a schematic diagram of the planar structure of a second electrode pattern included in a display panel of an exemplary embodiment of the present disclosure.

[0140] As shown in FIG. 1B , the display panel includes a buffer layer 11 , a semiconductor layer 12 , a first insulating layer 13 , a first conductive layer 14 , a second insulating layer 15 , a second conductive layer 16 , a third insulating layer 17 , a third conductive layer 21 and a fourth insulating layer 18 . Specifically, a buffer layer 11 is arranged on one side of the base substrate 10; a semiconductor layer 12 is arranged on a side of the buffer layer 11 away from the base substrate 10; a first insulating layer 13 is arranged on a side of the semiconductor layer 12 away from the base substrate 10; a first conductive layer 14 is arranged on a side of the first insulating layer 13 away from the base substrate 10; a second insulating layer 15 is arranged on a side of the first conductive layer 14 away from the base substrate 10; a second conductive layer 16 is arranged on a side of the second insulating layer 15 away from the base substrate 10; a third insulating layer 17 is arranged on a side of the second conductive layer 16 away from the base substrate 10; a third conductive layer 21 is arranged on a side of the third insulating layer 17 away from the base substrate 10; and a fourth insulating layer 18 is arranged on a side of the third conductive layer 21 away from the base substrate 10.

[0141] 4D , the display panel 100 further includes a fourth conductive layer 23 and a fifth insulating layer 22 . The fifth insulating layer 22 is disposed between the third conductive layer 21 and the fourth insulating layer 18 , and the fourth conductive layer is disposed between the fifth insulating layer 22 and the fourth insulating layer 18 .

[0142] In some embodiments, as shown in FIG1B and FIG4A to FIG4F , a portion of the orthographic projection of each of the buffer layer 11, the first insulating layer 13, the first conductive layer 14, the second insulating layer 15, the second conductive layer 16, and the third insulating layer 17 on the base substrate overlaps with the orthographic projection of the second electrode via on the base substrate. That is, the overlapping portion at the projection position of the second electrode via facilitates wiring connection and improves sub-pixel space utilization resulting from wiring layout.

[0143] The following describes in detail the film layer structures within a pixel unit with reference to FIG. 4A to FIG. 4F .

[0144] In the embodiments shown in FIG. 4A to FIG. 4F , a plurality of sub-pixel units within a pixel unit share a second electrode pattern, and the pixel unit includes three sub-pixels.

[0145] FIG4A shows a schematic planar structure diagram of the first conductive layer 14 included in a pixel unit. FIG4B shows a schematic planar structure diagram of the second conductive layer 16 included in a pixel unit. FIG4C shows a schematic planar structure diagram of the third conductive layer 21 included in a pixel unit.

[0146] As shown in FIG. 4C and FIG. 4D , the second electrode via hole VH2 penetrates the fourth insulating layer and a portion of the pixel defining layer.

[0147] In an optional embodiment of the present disclosure, an electrode trace 60 has a first portion 601 and a second portion 602 at the second electrode via VH2. The first portion of the electrode trace is located in the third conductive layer, and the second portion of the electrode trace is located in the layer where the first electrode pattern is located. An orthographic projection of a portion of each of the buffer layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer, and the fifth insulating layer on the base substrate partially overlaps with an orthographic projection of the second electrode via on the base substrate.

[0148] 1B , the second electrode via hole VH2 penetrates the fourth insulating layer 18 and a portion of the pixel defining layer 30. The electrode trace 60 has a first portion 60a and a second portion 60b at the second electrode via hole. The first portion 60a of the electrode trace is located in the fourth conductive layer, and the second portion 60b of the electrode trace is located in the layer where the first electrode pattern is located.

[0149] As shown in Figure 4D, the first parts 60a of the electrode traces are spaced apart in the second electrode via VH2, that is, in the second electrode via VH2, the first parts 60a of the electrode traces shown by the dotted lines are spaced apart in the first direction X. When the electrode traces include three traces, it can be concluded that the first parts 60a of each electrode trace are spaced apart from each other.

[0150] As shown in FIG. 4D , the second portion 60 b of the electrode trace is continuously disposed in the second electrode via hole VH2 .

[0151] As shown in Figure 4D, the electrode trace 60 includes a first sub-electrode trace 61a and a second sub-electrode trace 61b located in the fourth conductive layer, the main body of the first sub-electrode trace 61a extends along the first direction X, and the main body of the second sub-electrode trace 61b extends along the second direction Y; the first sub-electrode trace 61a and the second sub-electrode trace 61b cross at least in the second electrode via VH2.

[0152] As shown in FIG4D , the first sub-electrode wiring 61a includes multiple wirings, and the second sub-electrode wiring 61b also includes multiple wirings. For example, the first sub-pixel corresponds to the second sub-electrode wiring 61b1, the second sub-pixel corresponds to the second sub-electrode wiring 61b2, and the third sub-pixel corresponds to the second sub-electrode wiring 61b3.

[0153] As shown in Figures 4C and 4D , the display panel further includes a data signal line 62 for providing a data signal to the pixel unit. The data signal line 62 is located in the third conductive layer, and the main body of the data signal line 62 extends along the second direction Y. The orthographic projection of the second sub-electrode trace 61b on the base substrate at least partially overlaps with the orthographic projection of the data signal line 62 on the base substrate. Exemplarily, there are three data signal lines 62, and each data signal line 62 partially overlaps with the orthographic projection of each second sub-electrode trace 61b on the base substrate.

[0154] As shown in FIG4C , the display panel further includes voltage signal lines for providing voltage signals to the first electrode patterns of the pixel units. The voltage signal lines include a first voltage signal sub-line 63 a and a second voltage signal sub-line 63 b. The main body of the first voltage signal sub-line 63 a extends along a first direction X, and the main body of the second voltage signal sub-line 63 b extends along a second direction Y.

[0155] The display panel includes a plurality of second voltage signal sub-lines 63b, at least one of which is located in the third conductive layer, and at least another of which is located in the fourth conductive layer. As shown in Figures 4C and 4D, the second voltage signal sub-lines 63b located in the third conductive layer and the second voltage signal sub-lines 63b located in the fourth conductive layer have overlapping portions on the substrate.

[0156] As shown in FIG4D , the orthographic projection of at least one second voltage signal sub-line in the third conductive layer on the base substrate and the orthographic projection of the second sub-electrode line on the base substrate are spaced apart at least in the second electrode via.

[0157] The orthographic projection of at least another second voltage signal sub-line 63b in the fourth conductive layer on the base substrate is spaced apart from the orthographic projection of the second sub-electrode wiring 61b on the base substrate.

[0158] As shown in Figures 4C and 4D , the orthographic projection of the second voltage signal sub-line 63b on the substrate is spaced apart from the orthographic projection of the second sub-electrode trace 61b on the substrate. For example, the orthographic projections of the second voltage signal sub-line 63b on the substrate are located between adjacent orthographic projections of the second electrode trace 61b on the substrate, for example, between the second sub-electrode trace 61b1 corresponding to the first sub-pixel and the second sub-electrode trace 61b2 corresponding to the second sub-pixel, and between the second sub-electrode trace 61b2 corresponding to the second sub-pixel and the second electrode trace 61b3 corresponding to the third sub-pixel. This spacing allows for full utilization of space, enabling a rational routing arrangement, improving space utilization, and avoiding the need for oversized pixel units in the display panel.

[0159] Exemplarily, at least one second voltage signal sub-line 63b in the fourth conductive layer extends through the gap between the first portion of the electrode trace in the second electrode via. As shown in FIG4D , the first portion of the electrode trace in the fourth conductive layer has a gap K in the second electrode via, and the second voltage signal sub-line 63b in the fourth conductive layer extends in the second direction Y and passes through the gap K.

[0160] The display panel includes a plurality of second sub-electrode routings, at least one of the second sub-electrode routings includes a winding portion, at least one of the second sub-electrode routings extends through the area where the first electrode pattern is located through the winding portion; and at least another second sub-electrode routing is disconnected at the area where the first electrode pattern is located.

[0161] As shown in FIG4D , the second electrode wiring includes a second sub-electrode wiring 61 b ​​1 corresponding to the first sub-pixel, a second sub-electrode wiring 61 b ​​2 corresponding to the second sub-pixel, and a second electrode wiring 61 b ​​3 corresponding to the third sub-pixel.

[0162] The second sub-electrode trace 61b1 corresponding to the first sub-pixel includes a winding portion P. The second sub-electrode trace 61b1 extends through the region where the first electrode pattern is located via the winding portion P. That is, the second sub-electrode trace 61b1 extends in the second direction and passes through the region where the first electrode pattern is located along the edge of the region where the first electrode pattern is located.

[0163] The second sub-electrode routing 61b3 corresponding to the third sub-pixel is disconnected at the area where the first electrode pattern is located, that is, as shown in Figure 4D, the second sub-electrode routing 61b3 is disconnected at the area where the first electrode pattern is located, thereby avoiding the problem of increased manufacturing process costs and decreased yield caused by complex routing through the area where the first electrode pattern is located.

[0164] According to the embodiment of the present disclosure, by providing the winding portion P, the problem of complicated manufacturing process and increased cost caused by complex internal wiring can be prevented. At the same time, the winding portion P extends through the area where the first electrode pattern is located, which can avoid the problem of pixel unit size increase in the display panel due to the winding design 2.

[0165] As shown in FIG4D , the winding portion P includes a first sub-winding portion P1 , a second sub-winding portion P2 and a third sub-winding portion P3 . The first sub-winding portion P1 and the third sub-winding portion P3 extend along a first direction X, and the second sub-winding portion P2 extends along a second direction Y.

[0166] For example, for the same second sub-electrode trace 61b, the orthographic projection of the second sub-winding portion P2 located in the region where the first electrode pattern is located on the substrate is closer to the edge of the first electrode pattern than the orthographic projection of the portion of the second sub-electrode trace 61b located outside the region where the first electrode pattern is located on the substrate. That is, the second sub-winding portion P2 is closer to the periphery of the first electrode pattern than the second sub-electrode trace, thereby better achieving the winding function and avoiding the problem of complicated routing within the first electrode pattern region, which would lead to a complex manufacturing process and increased manufacturing costs.

[0167] As shown in Figure 4E, the first electrode pattern 20 includes a first electrode main body portion 20a and a first electrode connecting portion 20b, and the display panel also includes a first electrode via VH1, and the orthographic projection of the first electrode connecting portion 20b on the base substrate at least partially overlaps with the orthographic projection of the first electrode via VH1 on the base substrate.

[0168] As shown in FIG4F , the second electrode pattern 50 includes a second electrode main portion 50a and a second electrode connecting portion 50b , and the orthographic projection of the second electrode connecting portion 50b on the base substrate at least partially overlaps with the orthographic projection of the second electrode via VH2 on the base substrate.

[0169] As shown in FIG4E , the first electrode connecting portion 20b protrudes outward from the first electrode main portion 20a, i.e., protrudes toward the periphery of the first electrode main portion 20a. The orthographic projection of a portion of the first electrode connecting portion 20b on the base substrate does not overlap with the orthographic projection of the first electrode main portion 20a on the base substrate, i.e., the first electrode connecting portion 20b is located outside the first electrode main portion 20a.

[0170] 4F , the orthographic projection of the second electrode connecting portion 50b on the substrate falls within the orthographic projection of the second electrode main portion 50a on the substrate. The orthographic projections of the second electrode connecting portion 50b and the electrode main portion 50a on the substrate overlap.

[0171] Exemplarily, the orthographic projection of the first electrode via VH1 on the base substrate falls within the orthographic projection of the second electrode pattern on the base substrate, that is, the orthographic projection of the first electrode via VH1 on the base substrate and the orthographic projection of the second electrode pattern on the base substrate have an overlapping part.

[0172] Exemplarily, the orthographic projection of the second electrode via VH2 on the base substrate is spaced apart from the orthographic projection of the first electrode pattern on the base substrate, for example, spaced apart along the second direction Y. By spacing the first electrode pattern and the second electrode via VH2 apart, it is possible to avoid affecting the electrode routing within the second electrode via when forming the first electrode pattern.

[0173] The light-emitting layer pattern of the display panel includes multiple layers, such as a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, and an electron transport layer ETL.

[0174] Exemplarily, the display panel further includes a hole transport layer pattern HTL and an electron transport layer pattern ETL, and an orthographic projection of each of the hole transport layer pattern and the electron transport layer pattern on the base substrate is spaced apart from an orthographic projection of the second electrode via on the base substrate.

[0175] By arranging a gap between the above-mentioned pattern and the orthographic projection of the second electrode via on the base substrate, the problem of low product yield caused by process accuracy when forming the pattern and the second electrode via can be effectively avoided.

[0176] As shown in Figures 4C to 4F , the display panel includes first, second, and third electrode traces, as well as voltage signal lines corresponding to the pixel units, along the second direction Y. By controlling the electrical signals of each trace, the sub-pixels within the pixel units are controlled to achieve the display function of the display panel.

[0177] Exemplarily, the display panel includes a plurality of control chips arranged in the peripheral area B as shown in Figure 1A, one of the plurality of control chips is used to provide a voltage signal to at least one of the voltage signal line, the first electrode line, the second electrode line and the third electrode line, respectively, and another of the plurality of control chips is used to provide a voltage signal to at least another one of the voltage signal line, the first electrode line, the second electrode line and the third electrode line, respectively.

[0178] For example, two control chips are included, and the two control chips jointly provide five voltage control signals, such as AVDD / VDD / VSS(R) / VSS(G) / VSS(G), which are respectively input into the voltage signal line, the first electrode wiring, the second electrode wiring and the third electrode wiring.

[0179] The display panel includes a control chip arranged in the peripheral area, and the control chip is used to provide voltage signals to the voltage signal line, the first electrode wiring, the second electrode wiring, and the third electrode wiring respectively.

[0180] For another example, a control chip is selected, which can be a customized unconventional chip. One control chip can provide five control signals, which are respectively input into the voltage signal line, the first electrode trace, the second electrode trace and the third electrode trace.

[0181] In some exemplary embodiments, the orthographic projection of the second electrode via VH2 on the base substrate has a first via edge and a second via edge, wherein the first via edge is close to the first electrode pattern and the second via edge is close to the edge of the second electrode pattern.

[0182] As shown in Figure 4F, the vertical distance between the first edge and the nearest edge of the first electrode pattern is d1, and the vertical distance between the second edge and the nearest edge of the second electrode pattern is d2. The vertical distance d1 between the edge of the first via hole and the nearest edge of the first electrode pattern is greater than or equal to 30 microns. The vertical distance d2 between the edge of the second via hole and the nearest edge of the second electrode pattern is greater than or equal to 30 microns.

[0183] By setting the above distance, the problem of low product yield caused by the material forming the above patterns entering the second electrode via hole due to process accuracy during the formation of the first electrode pattern, the light-emitting layer pattern and the second electrode pattern can be avoided.

[0184] Another aspect of the present disclosure provides a display device, which includes the display panel described above. For example, the film layer structure of the display panel can refer to the description of the above embodiments and will not be repeated here.

[0185] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0186] Figure 5A is a flow chart of a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. Figure 5B is a schematic diagram of forming a second electrode via hole in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. Figure 5C is a schematic diagram of forming an HTL material for a light-emitting layer pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. Figure 5D is a schematic diagram of forming an EM material for a light-emitting layer pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure. Figures 5E-5F are schematic diagrams of forming a second electrode pattern in a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure.

[0187] Another aspect of the embodiments of the present disclosure provides a method for manufacturing a display panel.

[0188] The manufacturing method includes operations S1 to S7, as shown in FIG5A :

[0189] Operation S1: providing a base substrate, wherein the base substrate includes a display area and a peripheral area at least located on a first side of the display area.

[0190] Operation S2: forming a plurality of first electrode patterns on the base substrate, wherein the plurality of first electrode patterns are arranged in an array in a display area of ​​the base substrate along a first direction and a second direction.

[0191] Operation S3: forming a pixel defining layer on a side of the layer where the plurality of first electrode patterns are located away from the base substrate, wherein the pixel defining layer includes a plurality of pixel openings, each of the plurality of pixel openings exposing at least a portion of the plurality of first electrode patterns.

[0192] Operation S4: forming a plurality of second electrode via holes in the display area of ​​the base substrate.

[0193] As shown in Figure 5B, after multiple pixel openings M are formed in the pixel definition layer of the base substrate, the size of the formed pixel openings M can be adjusted according to design requirements, and a second electrode via VH2 is formed at the position corresponding to each pixel opening M so that each electrode via VH2 corresponds to the pixel opening M.

[0194] Operation S5: forming a plurality of light-emitting layer patterns, wherein the plurality of light-emitting layer patterns are arranged in an array along a first direction X and a second direction Y in the display area of ​​the base substrate, and at least a portion of the plurality of light-emitting layer patterns are respectively located in a plurality of pixel openings, wherein the orthographic projections of the plurality of light-emitting layer patterns on the base substrate are spaced apart from the orthographic projections of the plurality of second electrode vias on the base substrate.

[0195] As shown in FIG5C , the light-emitting layer pattern is continued to be formed in the pixel opening, wherein the materials forming the light-emitting layer pattern include hole transport layer (HTL) materials, electron transport layer (ETL) materials, and light-emitting layer (EML) materials, etc. The HTL material is formed by evaporation in the pixel opening. Specifically, the area where the HTL material is evaporated is larger than the pixel opening, while avoiding the second electrode via area, thereby ensuring the display quality of the display panel. Next, as shown in FIG5D , different EM materials are evaporated for different sub-pixels, so that the sub-pixels can emit light of different colors. Next, the ETL material is continued to be evaporated on the upper side of the EM material. Similarly, when evaporating the ETL material, it is evaporated in the pixel opening while avoiding the area where the second electrode via is located.

[0196] Operation S6: forming a plurality of electrode traces on the substrate.

[0197] Operation S7: forming a plurality of second electrode patterns on a side of a layer where a plurality of light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns are arranged in an array along a first direction and a second direction in the display area of ​​the base substrate, the orthographic projections of at least a portion of the plurality of second electrode patterns on the base substrate are spaced apart from each other in the first direction and the second direction, the plurality of electrode traces are located in at least one conductive layer between the base substrate and the layer where the second electrode patterns are located, and at least one electrode trace is electrically connected to at least one second electrode pattern through a second electrode via.

[0198] As shown in Figures 5E and 5F, a second electrode pattern is formed by evaporation in the upper area of ​​the pixel opening and the second electrode via hole. The second electrode pattern covers the sub-pixels of each pixel unit. As shown in Figure 5F, the upper side is the mask and the lower side is the formed second electrode pattern.

[0199] It should be understood that the display device according to the embodiment of the present disclosure has all the features and advantages of the above-mentioned display substrate (eg, the first substrate) and display panel, and details can be found in the above description.

[0200] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display panel, wherein: The display panel comprises: A base substrate, the base substrate comprising a display area and a peripheral area at least located on a first side of the display area; A plurality of first electrode patterns, wherein the plurality of first electrode patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate; A pixel defining layer, the pixel defining layer is located on a side of the layer where the plurality of first electrode patterns are located away from the base substrate, the pixel defining layer comprises a plurality of pixel openings, and the plurality of pixel openings respectively expose at least a portion of the plurality of first electrode patterns; A plurality of light-emitting layer patterns, wherein the plurality of light-emitting layer patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and at least a portion of the plurality of light-emitting layer patterns are respectively located in the plurality of pixel openings; a plurality of second electrode patterns, the plurality of second electrode patterns being located on a side of the layer where the plurality of light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns being arranged in an array along a first direction and a second direction in a display region of the base substrate, and orthographic projections of at least a portion of the plurality of second electrode patterns on the base substrate being spaced apart from each other in the first direction and the second direction; and a plurality of electrode traces, wherein the plurality of electrode traces are located in at least one conductive layer between the substrate and the layer where the second electrode pattern is located, and at least one of the electrode traces is electrically connected to at least one of the second electrode patterns through a second electrode via hole, Wherein, the orthographic projection of the second electrode via on the base substrate is located in the display area.

2. The display panel according to claim 1, wherein: The display panel comprises a plurality of pixel units, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction in a display area of ​​the substrate, and at least one of the pixel units comprises a plurality of sub-pixels; At least one of the pixel units includes at least one second electrode pattern and at least one second electrode via hole; and / or at least one of the pixel units includes more than two second electrode patterns and more than two second electrode via holes.

3. The display panel according to claim 2, wherein: In the same pixel unit, at least two sub-pixels share one second electrode pattern and one second electrode via hole, and another sub-pixel has a separate second electrode pattern and a separate second electrode via hole.

4. The display panel according to claim 2, wherein: All the sub-pixels of at least one of the pixel units share one second electrode pattern and one second electrode via hole.

5. The display panel according to claim 2, wherein: All the multiple sub-pixels of at least one of the pixel units respectively have their own second electrode patterns and their own second electrode via holes.

6. The display panel according to claim 3, wherein: At least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and the plurality of electrode wirings includes a first electrode wiring, a second electrode wiring and a third electrode wiring; The shared second electrode pattern is electrically connected to the first electrode wiring and the second electrode wiring through the shared second electrode via hole; the second electrode pattern of another sub-pixel is electrically connected to the third electrode wiring through the separate second electrode via hole; The first electrode routing and the second electrode routing are connected to the same voltage signal, and the first electrode routing and the third electrode routing are connected to different voltage signals.

7. The display panel according to claim 5, wherein: All the multiple sub-pixels of at least one of the pixel units include a first sub-pixel, a second sub-pixel and a third sub-pixel, and the multiple electrode wirings include a first electrode wiring, a second electrode wiring and a third electrode wiring; The second electrode pattern of the first sub-pixel is electrically connected to the second electrode via hole through the first electrode wiring, the second electrode pattern of the second sub-pixel is electrically connected to the second electrode via hole through the second electrode wiring, and the second electrode pattern of the third sub-pixel is electrically connected to the second electrode via hole through the third electrode wiring; At least two of the first electrode wiring, the second electrode wiring and the third electrode wiring are connected to different voltage signals.

8. The display panel according to claim 4, wherein: At least one of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and the plurality of electrode wirings includes a first electrode wiring, a second electrode wiring and a third electrode wiring; The shared second electrode pattern is electrically connected to the first electrode wiring, the second electrode wiring and the third electrode wiring through the shared second electrode via hole; The first electrode wiring, the second electrode wiring and the third electrode wiring are connected to the same voltage signal.

9. The display panel according to claim 1, wherein: The display panel comprises: A buffer layer disposed on the base substrate; A semiconductor layer disposed on a side of the buffer layer away from the substrate; A first insulating layer disposed on a side of the semiconductor layer away from the substrate; A first conductive layer disposed on a side of the first insulating layer away from the base substrate; A second insulating layer disposed on a side of the first conductive layer away from the base substrate; A second conductive layer disposed on a side of the second insulating layer away from the base substrate; A third insulating layer disposed on a side of the second conductive layer away from the base substrate; A third conductive layer disposed on a side of the third insulating layer away from the base substrate; and A fourth insulating layer is provided on a side of the third conductive layer away from the base substrate, The orthographic projection of a portion of each of the buffer layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer on the base substrate partially overlaps with the orthographic projection of the second electrode via on the base substrate.

10. The display panel according to claim 9, wherein: The second electrode via hole penetrates the fourth insulating layer and a portion of the pixel defining layer; as well as The electrode trace has a first portion and a second portion at the second electrode via hole, the first portion of the electrode trace is located in the third conductive layer, and the second portion of the electrode trace is located in the layer where the first electrode pattern is located.

11. The display panel according to claim 9, wherein: The display panel further includes: A fifth insulating layer disposed between the third conductive layer and the fourth insulating layer; and a fourth conductive layer disposed between the fifth insulating layer and the fourth insulating layer, The orthographic projection of a portion of each of the buffer layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer and the fifth insulating layer on the substrate overlaps with the orthographic projection of the second electrode via on the substrate. Stack.

12. The display panel according to claim 11, wherein: The second electrode via hole penetrates the fourth insulating layer and a portion of the pixel defining layer; as well as The electrode trace has a first portion and a second portion at the second electrode via hole, the first portion of the electrode trace is located in the fourth conductive layer, and the second portion of the electrode trace is located in the layer where the first electrode pattern is located.

13. The display panel according to claim 12, wherein: The first part of the electrode routing is arranged at intervals in the second electrode via hole, and the second part of the electrode routing is arranged continuously in the second electrode via hole.

14. The display panel according to claim 11, wherein: The electrode routing includes a first sub-electrode routing and a second sub-electrode routing located in the fourth conductive layer, the main body of the first sub-electrode routing extends along a first direction, and the main body of the second sub-electrode routing extends along a second direction; The first sub-electrode wiring and the second sub-electrode wiring cross at least in the second electrode via hole.

15. The display panel according to claim 14, wherein: The display panel further comprises a data signal line, the data signal line is used to provide a data signal to the pixel unit, the data signal line is located in the third conductive layer, and the main body of the data signal line extends along the second direction; The orthographic projection of the second sub-electrode wiring on the base substrate at least partially overlaps with the orthographic projection of the data signal line on the base substrate.

16. The display panel according to claim 15, wherein: The display panel further comprises a voltage signal line, wherein the voltage signal line is used to provide a voltage signal to the first electrode pattern of the pixel unit; and The voltage signal line includes a first voltage signal sub-line and a second voltage signal sub-line. The main body of the first voltage signal sub-line extends along a first direction, and the main body of the second voltage signal sub-line extends along a second direction.

17. The display panel according to claim 16, wherein: The display panel comprises a plurality of the second voltage signal sub-lines, at least one of the second voltage signal sub-lines is located in the third conductive layer, and at least another of the second voltage signal sub-lines is located in the fourth conductive layer; The orthographic projection of at least one of the second voltage signal sub-line located in the third conductive layer on the substrate and the orthographic projection of the second sub-electrode line on the substrate are spaced apart at least in the second electrode via, and the orthographic projection of at least another second voltage signal sub-line located in the fourth conductive layer on the substrate and the orthographic projection of the second sub-electrode line on the substrate are spaced apart.

18. The display panel according to claim 17, wherein: At least another second voltage signal sub-line in the fourth conductive layer extends through a gap of the first portion of the electrode trace in the second electrode via.

19. The display panel according to claim 18, wherein: The display panel includes a plurality of second sub-electrode routings, at least one of the second sub-electrode routings includes a winding portion, and at least one of the second sub-electrode routings extends through the region where the first electrode pattern is located through the winding portion; as well as At least another second sub-electrode wiring is disconnected at the area where the first electrode pattern is located.

20. The display panel according to claim 19, wherein: The winding portion includes a first sub-winding portion, a second sub-winding portion and a third sub-winding portion, the first sub-winding portion and the third sub-winding portion extend along a first direction, and the second sub-winding portion extends along a second direction; For the same second sub-electrode routing, the orthographic projection of the second sub-winding portion located in the area where the first electrode pattern is located on the substrate is closer to the edge of the first electrode pattern than the orthographic projection of the portion of the second sub-electrode routing located outside the area where the first electrode pattern is located on the substrate.

21. The display panel according to claim 1, wherein: The first electrode pattern includes a first electrode main body portion and a first electrode connecting portion, the display panel further includes a first electrode via hole, and an orthographic projection of the first electrode connecting portion on the base substrate at least partially overlaps with an orthographic projection of the first electrode via hole on the base substrate; The second electrode pattern comprises a second electrode main body portion and a second electrode connecting portion, and an orthographic projection of the second electrode connecting portion on the base substrate at least partially overlaps with an orthographic projection of the second electrode via on the base substrate; The first electrode connecting portion protrudes outward from the first electrode main body portion. The orthographic projection of a portion on the base substrate does not overlap with the orthographic projection of the first electrode main body on the base substrate; The orthographic projection of the second electrode connecting portion on the base substrate falls within the orthographic projection of the second electrode main body on the base substrate.

22. The display panel according to claim 21, wherein: The orthographic projection of the first electrode via on the base substrate falls within the orthographic projection of the second electrode pattern on the base substrate; and / or, The orthographic projection of the second electrode via on the base substrate is arranged at an interval from the orthographic projection of the first electrode pattern on the base substrate.

23. The display panel according to claim 1, wherein: The display panel further includes a hole transport layer pattern and an electron transport layer pattern, wherein an orthographic projection of each of the hole transport layer pattern and the electron transport layer pattern on the base substrate is spaced apart from an orthographic projection of the second electrode via on the base substrate.

24. The display panel according to claim 1, wherein: The display panel includes a plurality of control chips arranged in the peripheral area, one of the plurality of control chips is used to provide a voltage signal to at least one of the voltage signal line, the first electrode wiring, the second electrode wiring, and the third electrode wiring, and another of the plurality of control chips is used to provide a voltage signal to at least another one of the voltage signal line, the first electrode wiring, the second electrode wiring, and the third electrode wiring, respectively; or, The display panel includes a control chip arranged in the peripheral area, and the control chip is used to provide voltage signals to the voltage signal line, the first electrode wiring, the second electrode wiring and the third electrode wiring respectively.

25. The display panel according to claim 1, wherein: The orthographic projection of the second electrode via on the base substrate has a first via edge and a second via edge, the first via edge is close to the first electrode pattern, and the second via edge is close to the edge of the second electrode pattern; A vertical distance between an edge of the first via hole and an edge of the first electrode pattern that is closest to the first via hole is greater than or equal to 30 micrometers; and / or a vertical distance between an edge of the second via hole and an edge of the second electrode pattern that is closest to the first via hole is greater than or equal to 30 micrometers.

26. A display device, wherein: The display device includes the display panel according to any one of claims 1 to 25.

27. A method for manufacturing a display panel, wherein: The method comprises: Providing a base substrate, the base substrate comprising a display area and a peripheral area at least located on a first side of the display area; forming a plurality of first electrode patterns on the base substrate, wherein the plurality of first electrode patterns are arranged in an array in a display area of ​​the base substrate along a first direction and a second direction; forming a pixel defining layer on a side of the layer where the plurality of first electrode patterns are located away from the base substrate, wherein the pixel defining layer comprises a plurality of pixel openings, and the plurality of pixel openings respectively expose at least a portion of the plurality of first electrode patterns; forming a plurality of second electrode via holes in the display area of ​​the base substrate; Forming a plurality of light-emitting layer patterns, wherein the plurality of light-emitting layer patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and at least a portion of the plurality of light-emitting layer patterns are respectively located in the plurality of pixel openings, wherein the orthographic projections of the plurality of light-emitting layer patterns on the base substrate are spaced apart from the orthographic projections of the plurality of second electrode vias on the base substrate; forming a plurality of electrode traces on the substrate; and A plurality of second electrode patterns are formed on a side of the layer where the plurality of light-emitting layer patterns are located away from the base substrate, the plurality of second electrode patterns are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, and orthographic projections of at least a portion of the plurality of second electrode patterns on the base substrate are spaced apart from each other in the first direction and the second direction, The plurality of electrode traces are located in at least one conductive layer between the base substrate and the layer where the second electrode pattern is located, and at least one of the electrode traces is electrically connected to at least one of the second electrode patterns through a second electrode via.

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