Accelerometer signal acquisition chip and error compensation method

Abstract

The present invention discloses an accelerometer signal acquisition chip and an error compensation method. The signal acquisition device, temperature sensor, signal processing circuit, analog-to-digital converter bare chip and programmable logic device are integrated into a chip through system-level packaging technology. The accelerometer signal is acquired by the signal acquisition device, and the signal processing is performed by the signal processing circuit and the analog-to-digital converter bare chip. The analog-to-digital converter bare chip is connected to the programmable logic device, and the temperature value of the signal acquisition device is obtained by the temperature sensor. The programmable logic device synchronously reads the temperature value and the accelerometer signal, determines the acceleration compensation parameter according to the temperature value and the temperature compensation parameter, and corrects the accelerometer signal according to the acceleration compensation parameter, so as to solve the problem that the PCB size is large and the signal integrity and parameter consistency are difficult to ensure in the accelerometer acquisition circuit built by discrete devices. By correcting the accelerometer signal, the measurement accuracy of the accelerometer signal is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic devices, and in particular to an accelerometer signal acquisition chip and an error compensation method. Background Art

[0002] The accelerometer signal acquisition chip is a sensor chip used to measure and record acceleration changes. With the development of chip processing and packaging technology, the complexity of integrated circuits continues to increase. The diversified development of integrated circuits, especially large-scale integrated circuits, makes information extraction more difficult.

[0003] At present, the use of discrete devices to build traditional high-precision accelerometer acquisition circuits has problems such as large printed circuit board (PCB) size and difficulty in ensuring signal integrity and parameter consistency. Summary of the invention

[0004] The present invention provides an accelerometer signal acquisition chip and an error compensation method, which can solve the problems of large PCB size and difficulty in ensuring signal integrity and parameter consistency in building an accelerometer acquisition circuit using discrete devices.

[0005] According to one aspect of the present invention, an accelerometer signal acquisition chip is provided. The accelerometer signal acquisition chip is obtained by using a system-level package, and includes:

[0006] The signal acquisition device is electrically connected to the signal processing circuit, and is used to acquire the accelerometer signal and output the accelerometer signal to the signal processing circuit;

[0007] The temperature sensor is located within a preset distance range of the signal acquisition device and is used to obtain a temperature value of the signal acquisition device;

[0008] The signal processing circuit is electrically connected to the analog-to-digital converter bare chip, and is used to condition the accelerometer signal and then output it to the analog-to-digital converter bare chip;

[0009] The analog-to-digital converter bare chip is used to perform analog-to-digital conversion on the conditioned accelerometer signal;

[0010] The programmable logic device is electrically connected to the temperature sensor and the analog-to-digital converter bare chip, respectively, and is used to synchronously read the temperature value and the accelerometer signal under the control of a synchronization signal, determine the acceleration compensation parameter according to the temperature value and the temperature compensation parameter, correct the accelerometer signal according to the acceleration compensation parameter, and output a corrected accelerometer signal, wherein the temperature compensation parameter is determined by calibration based on the output value of the temperature sensor, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip.

[0011] According to another aspect of an embodiment of the present invention, there is provided an error compensation method for an accelerometer signal acquisition chip, which is applied to the accelerometer signal acquisition chip described in any embodiment of the present invention, comprising:

[0012] The programmable logic device reads the temperature value output by the temperature sensor and the accelerometer signal output by the analog-to-digital converter bare chip based on the synchronization signal;

[0013] The programmable logic device determines the acceleration compensation parameter according to the temperature value and the temperature compensation parameter, corrects the accelerometer signal according to the acceleration compensation parameter, and outputs the corrected accelerometer signal, wherein the temperature compensation parameter is determined by calibration based on the output value of the temperature sensor, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip.

[0014] The technical solution of the embodiment of the present invention integrates the signal acquisition device, temperature sensor, signal processing circuit, analog-to-digital converter bare chip and programmable logic device into a chip through system-level packaging technology, so as to achieve parameter consistency, signal integrity and chip miniaturization, and solve the problem that the PCB size is large and the signal integrity and parameter consistency are difficult to ensure when using discrete devices to build the accelerometer acquisition circuit. In addition, the accelerometer signal is corrected by compensating the parameters, thereby improving the measurement accuracy of the accelerometer signal.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A block diagram of an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of the structure of an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the structure of a signal conversion and temperature acquisition circuit in an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of the structure of a signal processing circuit in an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of the structure of an analog-to-digital conversion circuit in an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0022] Figure 6 A structure and logic relationship diagram of an FPGA bare chip in an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0023] Figure 7 A schematic diagram of the layout of an accelerometer signal acquisition chip provided by an embodiment of the present invention;

[0024] Figure 8 A flowchart of an error compensation method for an accelerometer signal acquisition chip is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Figure 1 The block diagram of an accelerometer signal acquisition chip provided by an embodiment of the present invention is shown in FIG. The present invention can be applied to a high-precision miniaturized accelerometer signal acquisition circuit. Figure 1As shown, the accelerometer signal acquisition chip 100 includes: a signal acquisition device 110, a temperature sensor 120, a signal processing circuit 130, an analog-to-digital converter bare chip 140 and a programmable logic device 150, etc. The above devices are integrated into a chip through the system-level packaging (System in Package, referred to as SIP) technology, which can achieve parameter consistency, signal integrity and miniaturization effects, thereby solving the problems of large PCB size, signal integrity and parameter consistency in building a traditional high-precision accelerometer acquisition circuit using discrete devices.

[0028] The signal acquisition device 110 is electrically connected to the signal processing circuit 130, and is used to collect accelerometer signals and output the accelerometer signals to the signal processing circuit 130. Optionally, the signal acquisition device 110 includes sampling resistors, and the number of the sampling resistors is determined based on the number of channels of the accelerometer signal. Generally, for the case of three-way accelerometer signals X, Y and Z, the accelerometer signal acquisition chip 100 includes sampling resistors for respectively collecting X-way accelerometer signals, sampling resistors for collecting Y-way accelerometer signals, and sampling resistors for collecting Z-way accelerometer signals. After passing through the sampling resistors, the three-way accelerometer signals X, Y and Z are output as voltage signals corresponding to the three-way accelerometer signals X, Y and Z.

[0029] The temperature sensor 120 is located within a preset distance range of the signal acquisition device 110, and is used to obtain the temperature value of the signal acquisition device 110. Optionally, the temperature sensor 120 is a semiconductor temperature sensor. For example, a semiconductor temperature sensor with a small linear measurement error and no special requirements for zero error can be selected. The preset distance range can be a preset value. In order to improve the accuracy of the temperature acquisition of the sampling resistor by the temperature sensor 120, a corresponding semiconductor temperature sensor is set for each sampling resistor, and the semiconductor temperature sensor can be as close to the sampling resistor as possible. For example, a semiconductor temperature sensor is set near each sampling resistor, and the semiconductor temperature sensor is connected to the programmable logic device 150 through the IO terminal.

[0030] The signal processing circuit 130 is electrically connected to the analog-to-digital converter chip 140, and is used to condition the accelerometer signal and output it to the analog-to-digital converter chip 140. Optionally, the signal processing circuit 130 includes a voltage reference core, an operational amplifier core, a low-pass filter, etc. The voltage reference core and the operational amplifier core are connected through an IO interface to form a voltage follower, and the output interface of the operational amplifier core is connected to the low-pass filter. Specifically, a voltage follower is constructed using an operational amplifier core and a voltage reference core to condition the accelerometer signal, and the input impedance is high and the output impedance is low, and the output stage is composed of a resistor and a capacitor to form a low-pass filter. For example, the signal processing circuit 130 includes a differential operational amplifier core, etc.

[0031] The analog-to-digital converter bare chip 140 is used to perform analog-to-digital conversion on the conditioned accelerometer signal. The analog-to-digital converter bare chip 140 is connected to the programmable logic device 150 via an IO terminal.

[0032] The programmable logic device 150 is electrically connected to the temperature sensor 120 and the analog-to-digital converter bare chip 140, respectively, and is used to synchronously read the temperature value and the accelerometer signal under the control of a synchronization signal, determine the acceleration compensation parameter according to the temperature value and the temperature compensation parameter, correct the accelerometer signal according to the acceleration compensation parameter, and output a corrected accelerometer signal, wherein the temperature compensation parameter is determined by calibration based on the output value of the temperature sensor 120, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip 140.

[0033] Optionally, the accelerometer signal acquisition chip further includes: a memory bare chip, the memory bare chip is used to store the temperature compensation parameters and the acceleration compensation parameters. The programmable logic device communicates with the memory bare chip through a bus interface, and is used to read the temperature compensation parameters and the acceleration compensation parameters into a local cache after power-on. For example, the memory bare chip includes a FLASH bare chip. Optionally, the FLASH bare chip includes a first FLASH bare chip that stores the temperature compensation parameters and the acceleration compensation parameters. It also includes a second FLASH bare chip that stores configuration information.

[0034] Figure 2 The schematic diagram of the structure of an accelerometer signal acquisition chip provided by an embodiment of the present invention is shown in FIG. The circuit composed of a sampling resistor and a semiconductor temperature sensor is recorded as a signal conversion and temperature acquisition circuit. Figure 2 As shown in FIG. 1 , the accelerometer signal acquisition chip includes three signal conversion and temperature acquisition circuits, three differential op amp bare cores, an analog-to-digital converter bare chip, a field programmable gate array (FPGA) bare chip, and a FLASH bare core. By using SIP technology, the signal conversion and temperature acquisition circuit, the differential op amp bare core, the analog-to-digital converter bare chip, and the digital logic implemented by the FPGA bare chip are integrated into a chip, avoiding long-distance routing and welding defects in the PCB, thereby improving the analog signal quality of the front end of the analog-to-digital converter bare chip, and improving the accuracy and synchronization of the acquisition of the three accelerometer signals of X, Y, and Z (including the X-axis acceleration signal, the Y-axis acceleration signal, and the Z-axis acceleration signal) through error correction and synchronous analog-to-digital conversion control.

[0035] The accelerometer signal acquisition chip mainly includes a signal conversion and temperature acquisition circuit, a signal processing circuit, an analog-to-digital conversion circuit, and an FPGA bare chip. For example, the accelerometer signal acquisition chip includes a semiconductor temperature sensor, a differential op amp bare chip, a high-precision analog-to-digital converter bare chip, a FLASH bare chip, an FPGA bare chip, and a number of chip resistors and capacitors. The above components are packaged on the substrate using the SIP method, and fanned out using the bottom ball grid array package (Ball Grid Array, BGA) solder balls.

[0036] Figure 3 The present invention provides a schematic diagram of a signal conversion and temperature acquisition circuit in an accelerometer signal acquisition chip. Figure 3 As shown, the signal conversion and temperature acquisition circuit includes a sampling resistor and a semiconductor temperature sensor. The accelerometer signal includes three accelerometer signals X, Y and Z. Correspondingly, the sampling resistor includes an X sampling resistor corresponding to the X accelerometer signal, a Y sampling resistor corresponding to the Y accelerometer signal, and a Z sampling resistor corresponding to the Z accelerometer signal. The semiconductor temperature sensor includes an X temperature sensor, a Y temperature sensor and a Z temperature sensor. The power supply of the semiconductor temperature sensor comes from the BGA fan-out pin of the accelerometer signal acquisition chip, and the temperature value is output to the IO end of the FPGA bare chip and is shared with the ground. Among them, the temperature value output by the semiconductor temperature sensor is a digital signal. The three accelerometer signals X, Y and Z pass through the corresponding sampling resistors respectively to obtain voltage signals X, voltage signals Y and voltage signals Z. The sampling resistor is connected to the analog signal ground.

[0037] Figure 4 The present invention provides a schematic diagram of a signal processing circuit in an accelerometer signal acquisition chip. Figure 4 As shown, the signal processing circuit includes an operational amplifier die, a voltage reference die and a low-pass filter. The voltage reference die is connected to the operational amplifier die through an IO terminal. Since there are three accelerometer signals, a corresponding operational amplifier die is set for each accelerometer signal. The X sampling resistor is connected to the IO terminal of the X operational amplifier die. The Y sampling resistor is connected to the IO terminal of the Y operational amplifier die. The Z sampling resistor is connected to the IO terminal of the Z operational amplifier die. Thus, the voltage signal X, the voltage signal Y and the voltage signal Z are input to the corresponding operational amplifier die. The output stage of each operational amplifier die is connected to a low-pass filter, and the IO terminal of the analog-to-digital converter die is connected to the low-pass filter to input the three conditioned accelerometer signals into the analog-to-digital converter die.

[0038] Figure 5 The present invention provides a schematic diagram of the structure of an analog-to-digital conversion circuit in an accelerometer signal acquisition chip. Figure 5As shown, the analog-to-digital conversion circuit includes a voltage reference bare chip and an analog-to-digital converter bare chip. Specifically, it includes an X analog-to-digital converter bare chip (abbreviated as AD bare chip), a Y analog-to-digital converter bare chip (abbreviated as AD bare chip) and a Z analog-to-digital converter bare chip (abbreviated as AD bare chip), which are respectively connected to the IO end of the FPGA bare chip to output the X-channel accelerometer signal, the Y-channel accelerometer signal and the Z-channel accelerometer signal after analog-to-digital conversion to the FPGA bare chip.

[0039] Figure 6 The structure and logic relationship diagram of the FPGA bare chip in an accelerometer signal acquisition chip provided by an embodiment of the present invention. Figure 6 As shown, the internal logic of the FPGA bare chip consists of temperature acquisition control logic, AD acquisition control logic, compensation and calibration logic, synchronization logic, and data latch and interface logic. The FPGA bare chip is connected to the X temperature sensor, the Y temperature sensor, and the Z temperature sensor through IO. Under the control of the synchronization logic, the temperature acquisition control logic reads the temperature value from the IO interface of the corresponding semiconductor temperature sensor. The FPGA bare chip is connected to 3 AD bare cores through the SPI interface. Under the control of the synchronization logic, the AD acquisition control logic reads the accelerometer signal after analog-to-digital conversion from the AD bare core. The FPGA bare chip reads the configuration information from the second FLASH bare core. After the chip is powered on, the compensation and calibration logic reads the temperature compensation parameters and acceleration compensation parameters from the first FLASH bare core and caches them to the RAM in the FPGA bare chip. The acceleration compensation parameters are determined based on the temperature value and the temperature compensation parameters, and the accelerometer signal is corrected according to the acceleration compensation parameters. If there is external synchronization, the synchronization logic samples the external synchronization clock and outputs the synchronization signal to the temperature acquisition control logic, the AD acquisition control logic, and the data latch and interface logic. If there is no external synchronization, the synchronization logic uses the local clock to generate a synchronization signal and outputs the synchronization signal to the temperature acquisition control logic, AD acquisition control logic and data latch and interface logic. The acquisition of the three accelerometer signals uses parallel logic, and the acquisition synchronization error is kept within 50ns.

[0040] Exemplarily, the FPGA bare chip is specifically used to: synchronously read the temperature value and the accelerometer signal under the control of a synchronization signal, determine a temperature compensation parameter based on the temperature value, determine a corrected temperature value based on the temperature value and the temperature compensation parameter, determine an acceleration compensation parameter based on the corrected temperature value, and determine a corrected accelerometer signal based on the accelerometer signal and the acceleration compensation parameter.

[0041] Under the control of the synchronization signal, the modified accelerometer signal is latched and outputted using an interface corresponding to an interface selection instruction, wherein the synchronization signal includes an external synchronization signal or a synchronization signal corresponding to a local clock.

[0042] Optionally, the data latch and interface logic can implement three interfaces: LVDS, AXI and SPI, for externally transmitting the corrected accelerometer signal latched in the FPGA bare chip. The interface selection can be performed through the enable terminal.

[0043] Optionally, the FPGA bare chip interface, control, JTAG, digital power, and external synchronization signals are connected to the BGA fan-out.

[0044] The carrier realized by the above chip can compensate for the zero position problem of the semiconductor temperature sensor by calibrating the temperature value collected by the semiconductor temperature sensor. Through the synchronization methods such as short-path equal-length routing strictly controlled by the SIP process and the timing constraints inside the FPGA bare chip, highly synchronized XYZ three-axis acceleration acquisition can be achieved, and the sampling data can be output in various ways such as LVDS, AXI bus or SPI with the FPGA bare chip. The overall BGA package is deleted to reduce the PCB size.

[0045] Optionally, the accelerometer signal acquisition chip adopts a digital-analog area division method to avoid interference caused by crossing signal lines. Figure 7 The following is a schematic diagram of the layout of an accelerometer signal acquisition chip provided by an embodiment of the present invention. Figure 7 As shown, in the analog area, D1-D3 are semiconductor temperature sensor bare cores, D4-D6 are operational amplifier bare cores, and D7-D9 are AD bare cores. In the digital area, D11-D12 are FLASH bare cores, and D10 is an FPGA bare chip.

[0046] The embodiment of the present invention uses system-level packaging technology to integrate signal acquisition devices, temperature sensors, signal processing circuits, analog-to-digital converter bare chips and programmable logic devices into chips, achieving parameter consistency, signal integrity and chip miniaturization, and solving the problem of large PCB size, signal integrity and parameter consistency in building accelerometer acquisition circuits using discrete devices. In addition, the accelerometer signal is corrected by compensating the parameters, thereby improving the measurement accuracy of the accelerometer signal.

[0047] Figure 8 A flowchart of an error compensation method for an accelerometer signal acquisition chip is provided for an embodiment of the present invention. This embodiment is applicable to a high-precision miniaturized accelerometer signal acquisition circuit. The method is applied to the accelerometer signal acquisition chip provided by any embodiment of the present invention.

[0048] like Figure 8 As shown, the method includes:

[0049] S810. The programmable logic device reads the temperature value output by the temperature sensor and the accelerometer signal output by the analog-to-digital converter bare chip based on the synchronization signal.

[0050] The synchronization signal includes a synchronization signal corresponding to external synchronization or a synchronization signal generated by a local clock of a programmable logic device.

[0051] Exemplarily, the synchronization logic inside the programmable logic device generates a synchronization signal, and sends the synchronization signal to the temperature acquisition control logic and the AD acquisition control logic to synchronously acquire the temperature value and the three-way accelerometer signal.

[0052] S820. The programmable logic device determines an acceleration compensation parameter according to the temperature value and the temperature compensation parameter, corrects the accelerometer signal according to the acceleration compensation parameter, and outputs a corrected accelerometer signal.

[0053] The temperature compensation parameter is determined by calibration based on the output value of the temperature sensor, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip.

[0054] Exemplarily, the temperature compensation parameter and the acceleration compensation parameter are determined by the following steps, including:

[0055] The accelerometer signal acquisition chip is set in a temperature-controlled test box, and a communication connection is established between the accelerometer signal acquisition chip and the chip test system. The calibration measurement temperature inside the temperature-controlled test box is adjusted by the chip test system. The chip test system determines multiple test accelerometer signals according to the range of the analog-to-digital converter bare chip, and outputs the multiple test accelerometer signals associated with different calibration measurement temperatures to the accelerometer signal acquisition chip. For different calibration measurement temperatures, the chip test system determines temperature compensation parameters and acceleration compensation parameters according to the calibrated measurement temperature corresponding to the accelerometer signal acquisition chip and the accelerometer signal to be calibrated, wherein the calibrated measurement temperature is the output value of the sensor, and the accelerometer signal to be calibrated is the output value of the accelerometer signal acquisition chip.

[0056] Furthermore, for different calibration measurement temperatures, the chip testing system determines the temperature compensation parameter and the acceleration compensation parameter according to the calibrated measurement temperature and the accelerometer signal to be calibrated corresponding to the accelerometer signal acquisition chip, including:

[0057] The temperature compensation parameter is determined by the chip test system according to the difference between the to-be-calibrated measurement temperature output by the temperature sensor in the accelerometer signal acquisition chip at different calibration measurement temperatures and the calibration measurement temperature. For different calibration measurement temperatures, the acceleration error vector is determined by the chip test system according to the difference between the test accelerometer signal input to the accelerometer signal acquisition chip and the to-be-calibrated accelerometer signal output by the accelerometer signal acquisition chip, and the acceleration compensation parameter is determined according to multiple acceleration error vectors associated with multiple test accelerometer signals.

[0058] Among them, the chip test system includes high-precision analog signal automatic test equipment (Automatic Test Equipment, referred to as ATE) or other special equipment with equivalent functions. For example, the ATE system simulates the input current to calibrate the characteristics of the sampling resistor in the accelerometer and the parameters of the AD bare core itself as they change with temperature, which can reduce the conversion error of the sampling.

[0059] The temperature control test chamber can be a natural convection temperature control test chamber. The accelerometer signal acquisition chip is placed inside the natural convection temperature control test chamber, and the natural convection temperature control test chamber is used for constant temperature control. The output of the semiconductor temperature sensor in the accelerometer signal acquisition chip is calibrated and the compensation parameters are extracted through the ATE system. The unsoldered accelerometer signal acquisition chip is connected to the ATE system through the tooling. For the accelerometer signal acquisition chip that has been welded on the board, the accelerometer signal input and output terminals in the board need to be connected to the ATE system. It does not matter whether the accelerometer signal acquisition chip is welded on the board, and the FPGA logic needs to be downloaded for calibration and compensation parameter extraction.

[0060] During the calibration and compensation parameter extraction process, the FPGA bare chip synchronously collects 3 temperature values ​​and 3 actual AD conversion output values ​​(i.e., accelerometer signals after analog-to-digital conversion). At each temperature point in the natural convection temperature control test chamber, 3 specific current signals are output to the accelerometer signal acquisition chip through the ATE system to simulate 3 accelerometer signals (i.e., test accelerometer signals) and calibrate the actual AD conversion output values. Among them, the 3 specific current signals are determined based on the maximum range of the AD bare core. For example, the 3 specific current signals can be 25% of the maximum range, 50% of the maximum range, and 75% of the maximum range, respectively. The maximum range refers to the maximum range of the current signal that the AD bare core can handle. The calibration parameters include 3 temperature values ​​and 3 accelerometer signals to be calibrated. The 3 accelerometer signals to be calibrated represent the accelerometer signals to be calibrated corresponding to the current signals of different gears of the accelerometer signal acquisition chip at different calibration measurement temperatures. The calibration parameters are transmitted to the host computer of the ATE system in the form of a message.

[0061] Optionally, the calibration parameter acquisition message includes a message header, 3-way temperature data, 3-way accelerometer signals after AD conversion, a check byte, and a message tail. The host computer of the ATE system calibrates once every degree Celsius and records the data to complete the calibration calculation process. After completing the calibration calculation, a response message is generated according to the obtained acceleration compensation parameters, and the response message is sent to the FPGA bare chip in the accelerometer signal acquisition chip through the asynchronous serial port, and written to the first FLASH bare core through the SIP interface. For example, for 25% of the maximum range, 50% of the maximum range, and 75% of the maximum range, a response message is generated according to the acceleration compensation parameters of each degree Celsius. The response message includes a message header, 25% of the maximum range, 50% of the maximum range, and 75% of the maximum range associated with each of the 3 accelerometer signals, acceleration compensation parameters at each degree Celsius, a check byte, and a message tail.

[0062] For example, according to the application scope, the calibration can be divided into two temperature ranges, the industrial calibration range can be -40°C to 85°C, and the wide temperature calibration range is -55°C to 125°C. The calibration methods of the two temperature ranges are the same.

[0063] Specifically, the temperature measurement calibration calculation is performed in the host computer of the ATE system. Each acceleration channel (including X-channel, Y-channel and Z-channel) is calibrated separately and the processing method is the same. Taking the X-channel acceleration channel as an example, the natural convection temperature control test box is controlled to gradually increase the temperature from the lowest temperature T0 of the temperature range to the highest temperature T max , record the temperature value T of the X temperature sensor corresponding to each degree Celsius c Calculate each calibration measurement temperature T x The corresponding T c The difference, T x ∈[T0,T max ], and measure the temperature T according to each calibration x The corresponding T c The difference between the temperature error vector ΔT is determined. After the temperature calibration is completed, the temperature error vector ΔT is stored in the first FLASH bare core. The acceleration data calibration is also performed on the host computer of the ATE system. Each acceleration channel (including X-channel, Y-channel and Z-channel) is calibrated separately and processed in the same way. Taking the X-channel accelerometer signal as an example, first, the temperature is gradually increased from the lowest temperature T0 of the temperature range to the highest temperature T in the natural convection temperature control test box. max During the process, record the given current value I of the ATE system at each degree Celsius (divided into three gears of 25% maximum range, 50% maximum range and 75% maximum range to test the accelerometer signal) combined with the actual AD conversion output value I of the X-channel accelerometer signal Ox , using the second-order function fitting method, at temperature points T0 to T maxA series of data points can be obtained (I O0 , I0), (I O1 , I1)... to (I Omax , I max ) calculate the difference and get the error vector matrix The above error vector matrix is ​​the error vector matrix of the accelerometer signal of the X-path. The error vector matrices of the accelerometer signal of the Y-path and the accelerometer signal of the Z-path can be identified in a similar form. After completing the accelerometer signal calibration process, the error vector matrix ΔI of each accelerometer signal is 25% , ΔI 50% and ΔI 75% Stored in the first FLASH bare core.

[0064] Exemplarily, the programmable logic device determines an acceleration compensation parameter according to the temperature value and the temperature compensation parameter, corrects the accelerometer signal according to the acceleration compensation parameter, and outputs a corrected accelerometer signal, including:

[0065] The programmable logic device determines at least one temperature compensation parameter corresponding to the temperature value according to a calibrated measurement temperature associated with the temperature value and the temperature compensation parameter, and determines a corrected temperature value according to the at least one temperature compensation parameter and the temperature value.

[0066] The programmable logic device determines at least one acceleration compensation parameter corresponding to the accelerometer signal based on the corrected temperature value, the calibrated measurement temperature associated with the temperature compensation parameter, and the accelerometer signal, determines a corrected accelerometer signal based on the at least one acceleration compensation parameter and the accelerometer signal, and outputs the corrected accelerometer signal.

[0067] Among them, the temperature error vector ΔT has a one-to-one correspondence with the calibration measurement temperature, and the temperature value output by the semiconductor temperature sensor near the sampling resistor can be matched with the calibration measurement temperature corresponding to the temperature error vector ΔT to obtain the temperature error vector related to the temperature value. Among them, the temperature error vector corresponding to the temperature value can be obtained. Alternatively, the temperature error vector corresponding to the temperature value and the temperature error vector corresponding to the next temperature value of the temperature value can also be obtained as the temperature error vector related to the temperature value.

[0068] Exemplarily, the programmable logic device compares the temperature value with the calibration measurement temperature to obtain a first calibration measurement temperature corresponding to the temperature value. The programmable logic device determines a first temperature compensation parameter and a second temperature compensation parameter according to the first calibration measurement temperature, wherein the first temperature compensation parameter is a temperature compensation parameter corresponding to the first calibration measurement temperature, and the second temperature compensation parameter is a temperature compensation parameter corresponding to a calibration measurement temperature associated with the first calibration measurement temperature. The programmable logic device determines the corrected temperature value according to the first temperature compensation parameter, the second temperature compensation parameter and the temperature value.

[0069] For example, the FPGA bare chip recognizes the temperature value T output by the semiconductor temperature sensor c The integer part of the calibration measurement temperature T x When the calibration temperature T x As the first calibration measurement temperature. Obtain the temperature error vector ΔT corresponding to the first calibration measurement temperature i The temperature error vector ΔT corresponding to the calibration measurement temperature associated with the first calibration measurement temperature is obtained. i+1 , which is the second temperature compensation parameter. Then, according to Calculate the corrected temperature value. Or, obtain T x The associated temperature error vector ΔT i and ΔT i-1 Then, according to Calculate the corrected temperature value. Or, obtain T x The associated temperature error vector ΔT i ,according to Calculate the corrected temperature value. The disclosed embodiment does not specifically limit the method of determining the corrected temperature value based on at least one temperature compensation parameter corresponding to the temperature value and the temperature value. For each accelerometer signal, the corrected temperature value of the signal is used as the input of the accelerometer compensation. If the temperature value T c More than T max Or lower than T0, a temperature error flag is output.

[0070] Exemplarily, the programmable logic device determines at least one acceleration compensation parameter corresponding to the accelerometer signal according to the corrected temperature value, the calibrated measurement temperature associated with the temperature compensation parameter, and the accelerometer signal, including:

[0071] The programmable logic device compares the corrected temperature value with the calibration measurement temperature to obtain a second calibration measurement temperature corresponding to the corrected temperature value. The programmable logic device determines a value interval of the accelerometer signal according to a proportion of the accelerometer signal in a range of the analog-to-digital converter bare chip, wherein the value interval is determined based on a proportion of the test accelerometer signal in the range of the analog-to-digital converter bare chip. The programmable logic device determines at least one acceleration compensation parameter according to the second calibration measurement temperature and the value interval.

[0072] Optionally, the programmable logic device determines at least one acceleration compensation parameter according to the second calibration measurement temperature and the value range, including:

[0073] For the first value interval or the last value interval, the programmable logic device determines the first acceleration compensation parameter and the second acceleration compensation parameter from the acceleration compensation parameters corresponding to the current value interval according to the second calibrated measurement temperature.

[0074] For any value interval in the remaining value interval, the programmable logic device determines the third acceleration compensation parameter and the fourth acceleration compensation parameter from the acceleration compensation parameters corresponding to the current value interval according to the second calibrated measurement temperature, and determines the fifth acceleration compensation parameter and the sixth acceleration compensation parameter from the acceleration compensation parameters corresponding to the previous value interval of the current value interval.

[0075] Among them, the first acceleration compensation parameter, the third acceleration compensation parameter and the fifth acceleration compensation parameter are acceleration compensation parameters corresponding to the second calibration measurement temperature in the acceleration compensation parameters corresponding to different value intervals, and the second acceleration compensation parameter, the fourth acceleration compensation parameter and the sixth acceleration compensation parameter are acceleration compensation parameters corresponding to the calibration measurement temperature associated with the second calibration measurement temperature in the acceleration compensation parameters corresponding to different value intervals.

[0076] For example, the FPGA bare chip recognizes that the integer part of the corrected temperature value is the same as the calibrated measured temperature T x When the calibration temperature T x As the second calibration measurement temperature corresponding to the correction temperature value. Since the calibration measurement temperature has a corresponding relationship with the error vector matrix of each accelerometer signal, the acquisition range of the acceleration compensation parameter can be determined according to the second calibration measurement temperature. O The proportion of the ADC bare chip in the range determines the accelerometer signal I OThe value interval can be divided by referring to the gear information of the test accelerometer signal. Optionally, 25%, 50% and 75% are used as the boundary values ​​of the value interval, and four value intervals of 0-25%, 25%-50%, 50%-75%, and 75%-100% are obtained. O The acceleration correction value is superimposed on the accelerometer signal I O , and obtain the corrected accelerometer signal.

[0077] Specifically, if the accelerometer signal I O If the accelerometer signal is within 0-25% of the range of the ADC bare chip, If the accelerometer signal I O If the proportion of the analog-to-digital converter bare chip is within 25%-50%, the accelerometer signal is corrected If the accelerometer signal I O If the ADC bare chip’s measurement range is between 50% and 75%, the accelerometer signal is corrected. If the accelerometer signal I O If the accelerometer signal is corrected when the ADC bare chip’s measurement range is between 75% and 100%, .

[0078] It should be noted that if the corrected accelerometer signal exceeds the measurement range of the analog-to-digital converter bare chip, an acceleration error flag is output.

[0079] Using the various forms of processes shown above, reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document is not limited here.

[0080] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An accelerometer signal acquisition chip, characterized in that: The accelerometer signal acquisition chip is obtained by adopting a system-level package, comprising: The signal acquisition device is electrically connected to the signal processing circuit, and is used to acquire the accelerometer signal and output the accelerometer signal to the signal processing circuit; The temperature sensor is located within a preset distance range of the signal acquisition device and is used to obtain a temperature value of the signal acquisition device; The signal processing circuit is electrically connected to the analog-to-digital converter bare chip, and is used to condition the accelerometer signal and then output it to the analog-to-digital converter bare chip; The analog-to-digital converter bare chip is used to perform analog-to-digital conversion on the conditioned accelerometer signal; The programmable logic device is electrically connected to the temperature sensor and the analog-to-digital converter bare chip respectively, and is used for synchronously reading the temperature value and the accelerometer signal under the control of a synchronization signal, determining an acceleration compensation parameter according to the temperature value and the temperature compensation parameter, correcting the accelerometer signal according to the acceleration compensation parameter, and outputting a corrected accelerometer signal, wherein the temperature compensation parameter is determined by calibration based on the output value of the temperature sensor, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip; Wherein, determining the acceleration compensation parameter according to the temperature value and the temperature compensation parameter comprises: The programmable logic device determines at least one temperature compensation parameter corresponding to the temperature value according to the temperature value and the calibrated measurement temperature corresponding to the temperature compensation parameter, and determines a corrected temperature value according to the at least one temperature compensation parameter and the temperature value; The programmable logic device determines at least one acceleration compensation parameter corresponding to the accelerometer signal according to the corrected temperature value, the calibrated measurement temperature corresponding to the temperature compensation parameter, and the accelerometer signal; The programmable logic device determines at least one temperature compensation parameter corresponding to the temperature value according to the temperature value and the calibrated measurement temperature corresponding to the temperature compensation parameter, and determines the corrected temperature value according to the at least one temperature compensation parameter and the temperature value, including: The programmable logic device compares the temperature value with the calibrated measurement temperature to obtain a first calibrated measurement temperature corresponding to the temperature value; The programmable logic device determines a first temperature compensation parameter and a second temperature compensation parameter according to the first calibration measurement temperature, wherein the first temperature compensation parameter is a temperature compensation parameter corresponding to the first calibration measurement temperature, and the second temperature compensation parameter is a temperature compensation parameter corresponding to a calibration measurement temperature associated with the first calibration measurement temperature, and the calibration measurement temperature associated with the first calibration measurement temperature includes a previous calibration measurement temperature adjacent to the first calibration measurement temperature or a subsequent calibration measurement temperature adjacent to the first calibration measurement temperature; The programmable logic device determines the corrected temperature value according to the first temperature compensation parameter, the second temperature compensation parameter and the temperature value.

2. The chip according to claim 1, characterized in that: The programmable logic device is specifically used for: Synchronously reading the temperature value and the accelerometer signal under the control of a synchronization signal, determining a temperature compensation parameter according to the temperature value, determining a corrected temperature value according to the temperature value and the temperature compensation parameter, determining an acceleration compensation parameter according to the corrected temperature value, and determining a corrected accelerometer signal according to the accelerometer signal and the acceleration compensation parameter; Under the control of the synchronization signal, the modified accelerometer signal is latched and outputted using an interface corresponding to an interface selection instruction, wherein the synchronization signal includes an external synchronization signal or a synchronization signal corresponding to a local clock.

3. The chip according to claim 1, characterized in that: The signal acquisition device includes sampling resistors, the number of which is determined based on the number of channels of the accelerometer signal, and the temperature sensor is a semiconductor temperature sensor.

4. The chip according to claim 2, characterized in that: The signal processing circuit includes a voltage reference core, an operational amplifier core and a low-pass filter; the voltage reference core and the operational amplifier core form a voltage follower, and the output interface of the operational amplifier core is connected to the low-pass filter.

5. The chip according to claim 1, characterized in that: Also includes: A memory bare chip, wherein the memory bare chip is used to store the temperature compensation parameter and the acceleration compensation parameter; The programmable logic device is communicatively connected to the memory bare chip, and is used to read the temperature compensation parameters and acceleration compensation parameters into a local cache after power-on.

6. An error compensation method for an accelerometer signal acquisition chip, characterized in that: The accelerometer signal acquisition chip used in any one of claims 1 to 5 comprises: The programmable logic device reads the temperature value output by the temperature sensor and the accelerometer signal output by the analog-to-digital converter bare chip based on the synchronization signal; The programmable logic device determines an acceleration compensation parameter according to the temperature value and the temperature compensation parameter, corrects the accelerometer signal according to the acceleration compensation parameter, and outputs a corrected accelerometer signal, wherein the temperature compensation parameter is determined by calibration based on the output value of the temperature sensor, and the acceleration compensation parameter is determined by calibration based on the output value of the analog-to-digital converter bare chip; The programmable logic device determines the acceleration compensation parameter according to the temperature value and the temperature compensation parameter, including: The programmable logic device determines at least one temperature compensation parameter corresponding to the temperature value according to the temperature value and the calibrated measurement temperature corresponding to the temperature compensation parameter, and determines a corrected temperature value according to the at least one temperature compensation parameter and the temperature value; The programmable logic device determines at least one acceleration compensation parameter corresponding to the accelerometer signal according to the corrected temperature value, the calibrated measurement temperature corresponding to the temperature compensation parameter, and the accelerometer signal; The programmable logic device determines at least one temperature compensation parameter corresponding to the temperature value according to the temperature value and the calibrated measurement temperature corresponding to the temperature compensation parameter, and determines the corrected temperature value according to the at least one temperature compensation parameter and the temperature value, including: The programmable logic device compares the temperature value with the calibrated measurement temperature to obtain a first calibrated measurement temperature corresponding to the temperature value; The programmable logic device determines a first temperature compensation parameter and a second temperature compensation parameter according to the first calibration measurement temperature, wherein the first temperature compensation parameter is a temperature compensation parameter corresponding to the first calibration measurement temperature, and the second temperature compensation parameter is a temperature compensation parameter corresponding to a calibration measurement temperature associated with the first calibration measurement temperature, and the calibration measurement temperature associated with the first calibration measurement temperature includes a previous calibration measurement temperature adjacent to the first calibration measurement temperature or a subsequent calibration measurement temperature adjacent to the first calibration measurement temperature; The programmable logic device determines the corrected temperature value according to the first temperature compensation parameter, the second temperature compensation parameter and the temperature value.

7. The method according to claim 6, characterized in that The temperature compensation parameter and the acceleration compensation parameter are determined by the following steps, including: Placing the accelerometer signal acquisition chip in a temperature-controlled test box, and establishing a communication connection between the accelerometer signal acquisition chip and a chip testing system; Adjusting the calibration measurement temperature inside the temperature control test box through the chip testing system; Determining, by the chip testing system, a plurality of test accelerometer signals according to the measuring range of the analog-to-digital converter bare chip, and outputting the plurality of test accelerometer signals associated with different calibration measurement temperatures to the accelerometer signal acquisition chip; For different calibration measurement temperatures, the chip testing system determines the temperature compensation parameters and the acceleration compensation parameters according to the measurement temperature to be calibrated and the accelerometer signal to be calibrated corresponding to the accelerometer signal acquisition chip, wherein the measurement temperature to be calibrated is the output value of the sensor, and the accelerometer signal to be calibrated is the output value of the accelerometer signal acquisition chip.

8. The method according to claim 7, characterized in that For different calibration measurement temperatures, the chip testing system determines the temperature compensation parameter and the acceleration compensation parameter according to the to-be-calibrated measurement temperature and the to-be-calibrated accelerometer signal corresponding to the accelerometer signal acquisition chip, including: Determine the temperature compensation parameter by the chip testing system according to the difference between the to-be-calibrated measurement temperature output by the temperature sensor in the accelerometer signal acquisition chip at different calibration measurement temperatures and the calibration measurement temperature; For different calibration measurement temperatures, the chip testing system determines the acceleration error vector based on the difference between the test accelerometer signal input into the accelerometer signal acquisition chip and the accelerometer signal to be calibrated output by the accelerometer signal acquisition chip, and determines the acceleration compensation parameter based on multiple acceleration error vectors associated with multiple test accelerometer signals.

9. The method according to claim 7, characterized in that: The step of correcting the accelerometer signal according to the acceleration compensation parameter and outputting the corrected accelerometer signal comprises: A modified accelerometer signal is determined according to the at least one acceleration compensation parameter and the accelerometer signal, and the modified accelerometer signal is output.

10. The method according to claim 6, characterized in that The programmable logic device determines at least one acceleration compensation parameter corresponding to the accelerometer signal according to the corrected temperature value, the calibrated measurement temperature corresponding to the temperature compensation parameter, and the accelerometer signal, including: The programmable logic device compares the corrected temperature value with the calibrated measurement temperature to obtain a second calibrated measurement temperature corresponding to the corrected temperature value; The programmable logic device determines a value interval of the accelerometer signal according to a proportion of the accelerometer signal in a measurement range of the analog-to-digital converter bare chip, wherein the value interval is determined based on a proportion of the test accelerometer signal in the measurement range of the analog-to-digital converter bare chip; The programmable logic device determines at least one acceleration compensation parameter according to the second calibration measurement temperature and the value range.

11. The method according to claim 10, characterized in that The programmable logic device determines at least one acceleration compensation parameter according to the second calibration measurement temperature and the value range, including: For the first value interval or the last value interval, the programmable logic device determines the first acceleration compensation parameter and the second acceleration compensation parameter from the acceleration compensation parameters corresponding to the current value interval according to the second calibrated measurement temperature; For any value interval in the remaining value intervals, the programmable logic device determines a third acceleration compensation parameter and a fourth acceleration compensation parameter from the acceleration compensation parameters corresponding to the current value interval according to the second calibrated measurement temperature, and determines a fifth acceleration compensation parameter and a sixth acceleration compensation parameter from the acceleration compensation parameters corresponding to the previous value interval of the current value interval; Among them, the first acceleration compensation parameter, the third acceleration compensation parameter and the fifth acceleration compensation parameter are acceleration compensation parameters corresponding to the second calibration measurement temperature in the acceleration compensation parameters corresponding to different value intervals, the second acceleration compensation parameter, the fourth acceleration compensation parameter and the sixth acceleration compensation parameter are acceleration compensation parameters corresponding to the calibration measurement temperature associated with the second calibration measurement temperature in the acceleration compensation parameters corresponding to different value intervals, and the calibration measurement temperature associated with the second calibration measurement temperature is the next calibration measurement temperature adjacent to the second calibration measurement temperature.

Images