Current-limiting protection circuit, low-dropout linear voltage stabilizing circuit and radio frequency module

Abstract

The invention relates to a current-limiting protection circuit, a low-dropout linear voltage stabilizing circuit and a radio frequency module. The current-limiting protection circuit provided by the embodiment of the invention comprises a switch detection module which is configured to connect or disconnect a current detection path under the control of the output voltage of the low-dropout linear voltage stabilizing circuit so as to open or close the output of the detection voltage; the current-limiting control module is configured to output a current-limiting control signal to the control end of the output transistor under the condition that the detection voltage is obtained and the detection voltage is higher than a third reference voltage, so that the low-dropout linear voltage stabilizing circuit enters a closed state; under the condition that the detection voltage is not obtained, the output of the current limiting control signal is closed, so that the low-dropout linear voltage stabilizing circuit is recovered to a normal working state; wherein the current-limiting protection circuit is used as a peripheral circuit of the low-dropout linear voltage stabilizing circuit. The output current of the low-dropout linear voltage stabilizing circuit can be limited, and the low-dropout linear voltage stabilizing circuit has the advantage of being low in power consumption.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a current limiting protection circuit, a low voltage difference linear voltage regulator circuit and a radio frequency module. Background Art

[0002] LDO (low dropout regulator) circuit, or low voltage difference linear regulator, usually uses output transistor to output stable voltage. The output transistor is a high-power load device with limited current capacity. Therefore, when the load current of the LDO circuit is too large or the output is short-circuited, the current flowing through the output transistor is too large, which is prone to avalanche breakdown and device burnout.

[0003] Therefore, in order to prevent this from happening, it is crucial to design a current limiting protection circuit to limit the output current of the LDO circuit, thereby avoiding excessive current flowing through the output transistor. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a current limiting protection circuit, a low voltage difference linear voltage regulator circuit and a radio frequency module to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a current limiting protection circuit, the current limiting protection circuit comprising:

[0006] A switch detection module, configured to turn on or off a current detection path under the control of the output voltage of the low-voltage difference linear voltage regulator circuit, so as to turn on or off the output of the detection voltage; wherein the current detection path is used to use a detection transistor to copy the current flowing through the output transistor of the low-voltage difference linear voltage regulator circuit according to a preset ratio to obtain a detection current, and determine the detection voltage according to the detection current;

[0007] a current limiting control module, configured to output a current limiting control signal to the control end of the output transistor to make the low voltage difference linear voltage regulator circuit enter a closed state when the detection voltage is obtained and the detection voltage is higher than a third reference voltage; and to turn off the output of the current limiting control signal to restore the low voltage difference linear voltage regulator circuit to a normal working state when the detection voltage is not obtained;

[0008] Wherein, the current limiting protection circuit serves as a peripheral circuit of the low voltage difference linear voltage stabilization circuit.

[0009] In combination with the first aspect, in an optional implementation manner, the switch detection module is configured to, when the output voltage is lower than a first threshold voltage, be controlled by the output voltage to turn on the current detection path so as to turn on the output of the detection voltage;

[0010] When the output voltage is higher than a second threshold voltage, the current detection path is disconnected under the control of the output voltage, so that the output of the detection voltage is turned off;

[0011] The first threshold voltage is smaller than the second threshold voltage.

[0012] In combination with the first aspect, in an optional implementation manner, the switch detection module includes a hysteresis comparator, a second switch transistor, a detection transistor and a detection resistor;

[0013] The first input terminal of the hysteresis comparator is configured to obtain the output voltage, the second input terminal of the hysteresis comparator is configured to obtain the second reference voltage, and the output terminal of the hysteresis comparator is connected to the control terminal of the second switch transistor;

[0014] The control end of the detection transistor is connected to the control end of the output transistor; the first signal end of the detection transistor is connected to the first power supply end, and the second signal end of the detection transistor is connected to the second signal end of the second switch transistor; the first signal end of the second switch transistor is connected to the first end of the detection resistor and is configured to provide the detection voltage; the second end of the detection resistor is connected to the second power supply end;

[0015] Wherein, the second switch transistor, the detection transistor and the detection resistor connected between the first power supply terminal and the second power supply terminal constitute the current detection path;

[0016] The first threshold voltage is lower than the second reference voltage, and the second threshold voltage is higher than the second reference voltage.

[0017] In combination with the first aspect, in an optional implementation manner, the current limiting control module includes:

[0018] a comparator configured to output a first switch control signal of a first level when the detection voltage is higher than the third reference voltage; and to output a first switch control signal of a second level when the detection voltage is lower than the third reference voltage;

[0019] The first switch transistor is configured to be turned on under the control of a first switch control signal of a first level to output the current limiting control signal; and to be turned off under the control of a first switch control signal of a second level to turn off the output of the current limiting control signal.

[0020] In combination with the first aspect, in an optional implementation manner, the output transistor is a PMOS transistor; the detection transistor is a PMOS transistor; the first switch transistor is a PMOS transistor; and the second switch transistor is an NMOS transistor;

[0021] The negative input terminal of the hysteresis comparator is configured to obtain the output voltage, the positive input terminal of the hysteresis comparator is configured to obtain the second reference voltage, the output terminal of the hysteresis comparator is connected to the gate of the second switch transistor; the source of the second switch transistor is respectively connected to the first end of the detection resistor and the negative input terminal of the comparator, and the drain of the second switch transistor is connected to the drain of the detection transistor; the second end of the detection resistor is connected to the second power supply terminal; the source of the detection transistor is connected to the first power supply terminal, and the gate of the detection transistor is connected to the gate of the output transistor;

[0022] The positive input terminal of the comparator is configured to obtain the third reference voltage, the output terminal of the comparator is connected to the control terminal of the first switching transistor; the source of the first switching transistor is connected to the first power supply terminal; the drain of the first switching transistor is connected to the gate of the output transistor for transmitting the current limiting control signal.

[0023] In combination with the first aspect, in an optional implementation manner, the current limiting protection circuit further includes a digital filtering module;

[0024] The input end of the digital filter module is connected to the output end of the low voltage difference linear voltage regulator circuit, and the output end of the digital filter module is configured to output the output voltage of the low voltage difference linear voltage regulator circuit;

[0025] The digital filtering module is configured to sample the voltage value at the output end of the low voltage difference linear voltage regulator circuit multiple times within a preset time, and determine and output the output voltage of the low voltage difference linear voltage regulator circuit according to all the voltage values;

[0026] Wherein, when all the voltage values ​​are lower than a first threshold voltage, the output voltage is lower than the first threshold voltage;

[0027] In a case where any one of all the voltage values ​​is higher than the first threshold voltage, the output voltage is higher than the first threshold voltage.

[0028] In combination with the first aspect, in an optional implementation manner, the hysteresis comparator includes a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second PMOS transistor, a twenty-third NMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth PMOS transistor, a thirtieth NMOS transistor, a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor, and a thirty-fourth NMOS transistor;

[0029] The gate of the twentieth NMOS transistor is configured as the first input terminal of the hysteresis comparator; the gate of the twenty-first NMOS transistor is configured as the second input terminal of the hysteresis comparator;

[0030] The drain of the 20th NMOS transistor is respectively connected to the gate of the 22nd PMOS transistor, the drain of the 24th PMOS transistor, the gate of the 24th PMOS transistor, the gate of the 25th PMOS transistor and the drain of the 26th PMOS transistor, and the drain of the 21st NMOS transistor is respectively connected to the gate of the 29th PMOS transistor, the drain of the 27th PMOS transistor, the gate of the 27th PMOS transistor, the gate of the 26th PMOS transistor and the drain of the 25th PMOS transistor; the source of the 20th NMOS transistor and the source of the 21st NMOS transistor are respectively connected to the drain of the 28th NMOS transistor, the source of the 28th NMOS transistor is connected to the second power supply terminal, and the gate of the 28th NMOS transistor is configured to obtain a first low-bit bias signal;

[0031] A source of the twenty-fourth PMOS transistor, a source of the twenty-fifth PMOS transistor, a source of the twenty-sixth PMOS transistor, and a source of the twenty-seventh PMOS transistor are respectively connected to the first power supply terminal;

[0032] The source of the twenty-second PMOS transistor and the source of the twenty-ninth PMOS transistor are respectively connected to the first power supply terminal, the drain of the twenty-second PMOS transistor is respectively connected to the drain of the twenty-third NMOS transistor, the gate of the twenty-third NMOS transistor and the gate of the thirtieth NMOS transistor, the source of the twenty-third NMOS transistor and the source of the thirtieth NMOS transistor are respectively connected to the second power supply terminal; the drain of the twenty-ninth PMOS transistor is respectively connected to the drain of the thirtieth NMOS transistor, the gate of the thirty-first PMOS transistor and the gate of the thirty-second NMOS transistor;

[0033] The drain of the thirty-first PMOS transistor is respectively connected to the drain of the thirty-second NMOS transistor, the gate of the thirty-third PMOS transistor and the gate of the thirty-fourth NMOS transistor, and the drain of the thirty-third PMOS transistor is connected to the drain of the thirty-fourth NMOS transistor and configured as the output end of the hysteresis comparator;

[0034] The source of the thirty-first PMOS transistor and the source of the thirty-third PMOS transistor are respectively connected to the first power supply terminal, and the source of the thirty-second NMOS transistor and the source of the thirty-fourth NMOS transistor are respectively connected to the second power supply terminal.

[0035] In combination with the first aspect, in an optional implementation manner, the comparator includes a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth NMOS transistor and an eighteenth PMOS transistor;

[0036] The gate of the twelfth NMOS transistor is configured as the negative input terminal of the comparator; the gate of the thirteenth NMOS transistor is configured as the positive input terminal of the comparator;

[0037] The drain of the twelfth NMOS transistor is connected to the drain of the fifteenth PMOS transistor, the gate of the fifteenth PMOS transistor and the gate of the sixteenth PMOS transistor respectively, the drain of the thirteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and the gate of the eighteenth PMOS transistor respectively; the source of the fifteenth PMOS transistor, the source of the sixteenth PMOS transistor and the source of the eighteenth PMOS transistor are connected to the first power supply terminal respectively;

[0038] The source of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor are respectively connected to the drain of the fourteenth NMOS transistor, and the gate of the fourteenth NMOS transistor and the gate of the seventeenth NMOS transistor are respectively configured to obtain the first low-bit bias signal; the source of the fourteenth NMOS transistor and the source of the seventeenth NMOS transistor are respectively connected to the second power supply terminal;

[0039] A drain of the seventeenth NMOS transistor is connected to a drain of the eighteenth PMOS transistor and is configured as an output terminal of the comparator.

[0040] In a second aspect, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, wherein the low voltage difference linear voltage regulator circuit includes an error amplifier, an output transistor, a feedback circuit, and a current limiting protection circuit as described in the first aspect;

[0041] The first input terminal of the error amplifier is configured to obtain a first reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the control terminal of the output transistor; the first signal terminal of the output transistor is connected to the first power supply terminal, and the second signal terminal of the output transistor is connected to the input terminal of the feedback circuit and is configured to provide the output voltage of the low voltage difference linear voltage regulator circuit.

[0042] In combination with the second aspect, in an optional implementation manner, the error amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor and a compensation capacitor;

[0043] The gate of the first PMOS transistor is configured as the first input terminal of the error amplifier; the gate of the second PMOS transistor is configured as the second input terminal of the error amplifier;

[0044] The drain of the first PMOS transistor is respectively connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor and the gate of the fifth NMOS transistor, the drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor and the gate of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the eighth NMOS transistor; the drain of the seventh NMOS transistor is respectively connected to the drain of the ninth PMOS transistor, the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor, the drain of the eighth NMOS transistor is connected to the drain of the tenth PMOS transistor and is configured as the output end of the error amplifier;

[0045] The gate of the seventh NMOS transistor and the gate of the eighth NMOS transistor are respectively configured to obtain a second low-bit bias signal; the source of the third NMOS transistor, the source of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor are respectively connected to the second power supply terminal; the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the drain of the eleventh PMOS transistor, and the gate of the eleventh PMOS transistor is configured to obtain a first high-bit bias signal; the source of the eleventh PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are respectively connected to the first power supply terminal;

[0046] A first end of the compensation capacitor is connected to the drain of the sixth NMOS transistor and the source of the eighth NMOS transistor respectively, and a second end of the compensation capacitor is connected to the output end of the low voltage difference linear voltage regulator circuit;

[0047] And / or, the feedback circuit includes a first resistor and a second resistor;

[0048] The second input terminal of the error amplifier is connected to the second terminal of the first resistor and the first terminal of the second resistor respectively. The first terminal of the first resistor is connected to the second signal terminal of the output transistor. The second terminal of the second resistor is connected to the second power supply terminal.

[0049] In a third aspect, an embodiment of the present application provides a radio frequency module, wherein the radio frequency module includes the low voltage difference linear voltage regulator circuit as described in the second aspect.

[0050] The beneficial effects of the technical solution provided by the embodiment of the present application include: through the switch detection module, the on-off control of the current detection path is added, and the current detection path can be turned on or off under the control of the output voltage of the low-voltage difference linear voltage regulator circuit, so that when the output is overloaded, such as when the load current is too large or the output is short-circuited, the current detection path can be controlled to be turned on so that it starts to work, and when the output voltage of the low-voltage difference linear voltage regulator circuit is normal, that is, the low-voltage difference linear voltage regulator circuit is in a normal working state, the current detection path can be controlled to be disconnected, no current flows in the path, no energy is consumed, and the current limiting protection circuit does not work at this time. Therefore, the power consumption of the current protection circuit is greatly reduced. In addition, by turning on or off the output of the detection voltage, combined with the current limiting control module, the output overcurrent of the low-voltage difference linear voltage regulator circuit is limited, which can avoid the occurrence of avalanche breakdown, heating and device burning due to the large current flowing through the output transistor when the output of the low-voltage difference linear voltage regulator circuit is overloaded. Furthermore, by using the current limiting protection circuit as a peripheral circuit of the low voltage difference linear voltage regulator circuit, the stability problem of the low voltage difference linear voltage regulator circuit will not be caused, thereby improving the circuit stability.

[0051] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0053] Figure 1 A circuit diagram of a specific example of an LDO current limiting circuit in the related art;

[0054] Figure 2 A circuit diagram of a specific example of a current limiting protection circuit in an embodiment of the present application;

[0055] Figure 3A circuit diagram of another specific example of a current limiting protection circuit in an embodiment of the present application;

[0056] Figure 4 A circuit diagram of a specific example of a hysteresis comparator in an embodiment of the present application;

[0057] Figure 5 A circuit diagram of a specific example of a comparator in an embodiment of the present application;

[0058] Figure 6 Schematic diagram of a circuit of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0060] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0061] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0062] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0063] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0064] In the embodiments of the present application, "plurality" refers to two or more.

[0065] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0066] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0067] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0068] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0069] In this application, the LDO circuit can be referred to by different names, such as LDO, low-dropout voltage regulator circuit, low-dropout voltage regulator, low-dropout linear voltage regulator circuit, etc., and the names are not limited here. The high level and the low level can be relative values, not limited to absolute values.

[0070] In the process of implementing the present invention, the inventors found that the related art has the following problems:

[0071] Figure 1 A circuit diagram of a specific example of an LDO current limiting circuit in the related art is shown. As shown in the figure, the overall architecture of the LDO current limiting circuit includes two parts: an LDO main circuit consisting of an error amplifier EA01, an output transistor MP01 and a feedback circuit; and a current limiting circuit consisting of a detection transistor MS01, a detection resistor RS01, a comparator COM01 and a control transistor MC01.

[0072] The first input terminal of the error amplifier EA01 is configured to obtain the zeroth reference voltage vref01, the output terminal of the error amplifier EA01 is connected to the control terminal of the output transistor MP01, the first terminal of the output transistor MP01 is configured to obtain the input power supply vin, and the second terminal of the output transistor MP01 is configured to provide an output voltage vout and is connected to the second input terminal of the error amplifier EA01 through a feedback circuit. The feedback circuit includes a zeroth resistor R01 and a zeroth resistor R02, which are connected in series between the second terminal of the output transistor MP01 and the ground terminal, and the connection node between the zeroth resistor R01 and the zeroth resistor R02 is connected to the second input terminal of the error amplifier EA01. The first input terminal of the error amplifier EA01 is a negative input terminal, and the second input terminal of the error amplifier EA01 is a positive input terminal.

[0073] The control end of the detection transistor MS01 is connected to the control end of the output transistor MP01, the first end of the detection transistor MS01 is configured to obtain the input power vin, the second end of the detection transistor MS01 is respectively connected to the first input end of the comparator COM01 and the first end of the detection resistor RS01, and the second end of the detection resistor RS01 is connected to the ground end; the second input end of the comparator COM01 is configured to obtain the 02nd reference voltage vref02, the output end of the comparator COM01 is connected to the control end of the control transistor MC01; the first end of the control transistor MC01 is configured to obtain the input power vin, and the second end of the control transistor MC01 is connected to the control end of the output transistor MP01. The first input end of the comparator COM01 is a negative input end, and the second input end of the comparator COM01 is a positive input end. The input power vin can be provided by the circuit power supply end, and the ground end can be grounded to 0V.

[0074] The ratio of the width to length of the output transistor MP01 and the detection transistor MS01 is N:1 (N is much greater than 1). When the load current of the LDO main circuit is too large or the output is short-circuited, a large current (exceeding the rated current) flows through the output transistor MP01. At this time, the current flowing through the detection transistor MS01 also increases, and the voltage drop across the detection resistor RS01 increases. The voltage at the negative input terminal of the comparator COM01 increases and is greater than the 02nd reference voltage vref02. Therefore, the comparator COM01 outputs a low level, controls the transistor MC01 to turn on, and then pulls up the control terminal (such as the gate terminal) of the output transistor MP01, so that the LDO main circuit is turned off, thereby playing a role in current limiting.

[0075] When the load current of the LDO main circuit drops, the current flowing through the output transistor MP01 decreases, and the current of the detection transistor MS01 also decreases. When the current flowing through the output transistor MP01 returns to below the limit current, the negative input voltage of the comparator COM01 is less than the positive input voltage, and the comparator COM01 outputs a high level, thereby turning off the control transistor MC01, and the LDO main circuit resumes the output under normal working conditions.

[0076] Then, when current flows through the output transistor MP01, current also flows through the detection transistor MS01. Therefore, when the LDO main circuit is in normal working state, the detection transistor MS01 is always consuming energy, resulting in an increase in the power consumption of the LDO current limiting circuit.

[0077] To this end, an embodiment of the present application provides a current limiting protection circuit. Figure 2 A circuit diagram of a specific example of a current limiting protection circuit in an embodiment of the present application is shown. As shown in the figure, the current limiting protection circuit includes:

[0078] The switch detection module 10 is configured to turn on or off the current detection path under the control of the output voltage vout of the low voltage difference linear voltage regulator circuit, so as to turn on or off the output of the detection voltage vs; wherein the current detection path is used to use the detection transistor MS to copy the current flowing through the output transistor MP of the low voltage difference linear voltage regulator circuit according to a preset ratio to obtain the detection current, and determine the detection voltage vs according to the detection current;

[0079] The current limiting control module 20 is configured to output a current limiting control signal to the control end of the output transistor MP to make the low voltage difference linear voltage regulator circuit enter a closed state when the detection voltage vs is obtained and the detection voltage vs is higher than the third reference voltage vref3; and to turn off the output of the current limiting control signal to restore the low voltage difference linear voltage regulator circuit to a normal working state when the detection voltage vs is not obtained;

[0080] Wherein, the current limiting protection circuit serves as a peripheral circuit of the low voltage difference linear voltage stabilization circuit.

[0081] In this way, the embodiment of the present application adds an on-off control of the current detection path through the switch detection module, and can turn on or off the current detection path under the control of the output voltage of the low-voltage difference linear voltage regulator circuit, so that when the output is overloaded, such as when the load current is too large or the output is short-circuited, the current detection path can be controlled to be turned on so that it starts to work, and when the output voltage of the low-voltage difference linear voltage regulator circuit is normal, that is, the low-voltage difference linear voltage regulator circuit is in a normal working state, the current detection path can be controlled to be disconnected, no current flows in the path, no energy is consumed, and the current limiting protection circuit does not work at this time. Therefore, the power consumption of the current protection circuit is greatly reduced. In addition, by turning on or off the output of the detection voltage, combined with the current limiting control module, the output overcurrent of the low-voltage difference linear voltage regulator circuit is limited, and it can be avoided that when the output of the low-voltage difference linear voltage regulator circuit is overloaded, the current flowing through the output transistor is large, and avalanche breakdown, heating and device burning occur. In addition, the current limiting protection circuit is used as a peripheral circuit of the low-voltage difference linear voltage regulator circuit, so it will not cause the stability problem of the low-voltage difference linear voltage regulator circuit, and the circuit stability is improved.

[0082] In the embodiment of the present application, the output transistor MP can be a single transistor; or it can be a plurality of transistors connected in series and / or in parallel, having a control terminal, a first signal terminal and a second signal terminal corresponding to the single transistor, and its working principle is that under the control of the control signal input at the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal.

[0083] Likewise, the detection transistor MS may be a single transistor; or a plurality of transistors connected in series and / or in parallel, and have a control terminal, a first signal terminal, and a second signal terminal corresponding to the single transistor.

[0084] The output transistor MP and the detection transistor MS may include at least one of the following: MOSFET (metal oxide semiconductor field effect transistor, referred to as MOS transistor); BJT (bipolar junction transistor, referred to as triode); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor).

[0085] Exemplarily, the output transistor MP may be a PMOS transistor (P-type MOS transistor). Accordingly, the detection transistor MS may be a PMOS transistor. Alternatively, the output transistor MP may be an NMOS transistor (N-type MOS transistor). Accordingly, the detection transistor MS may be an NMOS transistor.

[0086] In some possible implementations, the on-off of any connection node in the current detection path can be controlled to realize the on-off control of the current detection path based on the output voltage vout, so that when the current detection path is disconnected, the current flowing through the output transistor MP is not copied, and no current flows through the detection transistor MS, thereby turning off the output of the detection voltage vs. For example, the on-off of the control terminal of the detection transistor MS can be controlled; or the on-off of the output terminal (such as the first signal terminal or the second signal terminal) of the detection transistor MS can also be controlled, and so on.

[0087] In the embodiment of the present application, the current detection path uses the detection transistor MS to replicate the current flowing through the output transistor MP at a preset ratio, wherein the preset ratio can be set according to actual needs. For example, the ratio of the width to length of the output transistor MP and the detection transistor MS can be N:1 (N is much greater than 1), thereby achieving scaled-down replication of the current.

[0088] In some possible implementations, the method of determining the detection voltage vs according to the detection current in the switch detection module 10 may include at least one of the following: using a resistor; using a current-voltage converter; using a transimpedance amplifier.

[0089] In some possible implementations, the method for performing voltage comparison between the detection voltage vs and the third reference voltage vref3 in the current limiting control module 20 may include at least one of the following: using one or more voltage comparators; using different logical operations of gate circuits (AND, OR, NOT, etc.) to directly implement the comparison circuit.

[0090] Exemplarily, when the low voltage difference linear voltage regulator circuit is in normal working state, the output voltage vout is within the normal voltage value range, the current detection path can be controlled to be disconnected, the output of the detection voltage vs can be turned off, and the current limiting protection circuit does not work, so the power consumption can be reduced.

[0091] When the low voltage difference linear voltage regulator circuit is overloaded and its output current exceeds the rated current, the output voltage vout is reduced, and the current detection path can be controlled to be turned on, and the output of the detection voltage vs is turned on, and the current limiting protection circuit starts to work. When the detection voltage vs is higher than the third reference voltage vref3, the current limiting control module 20 can output a current limiting control signal to the control end of the output transistor MP to reduce the current flowing through the output transistor MP01, so that the low voltage difference linear voltage regulator circuit is turned off, thereby playing a role in current limiting.

[0092] When the overload of the low voltage difference linear voltage regulator circuit is eliminated, the output voltage vout returns to the normal voltage value range. At this time, the current detection path can be controlled to be disconnected, and the output of the detection voltage vs can be turned off, so that the low voltage difference linear voltage regulator circuit returns to normal working state, and the current limiting protection circuit stops working.

[0093] In some possible implementations, the high level or low level voltage value of the current limiting control signal can be determined according to actual needs to achieve control of the current flowing through the output transistor, such as achieving control of the on and off of the output transistor. For example, the output transistor is a PMOS transistor, and when the current limiting control signal is at a high level, the output transistor can be controlled to be cut off so that the low voltage difference linear voltage regulator circuit is turned off, and the high level can be determined according to the power supply voltage.

[0094] In an optional implementation, the switch detection module 10 is configured to be controlled by the output voltage to turn on the current detection path when the output voltage is lower than the first threshold voltage, so as to turn on the output of the detection voltage;

[0095] When the output voltage is higher than a second threshold voltage, the current detection path is disconnected under the control of the output voltage, so that the output of the detection voltage is turned off;

[0096] The first threshold voltage is smaller than the second threshold voltage.

[0097] In the embodiment of the present application, the first threshold voltage and the second threshold voltage can be set according to actual needs.

[0098] In some possible implementations, the method of comparing the output voltage vout with the first threshold voltage and the second threshold voltage respectively may include at least one of the following: using one or more voltage comparators; using different logical operations of gate circuits (AND, OR, NOT, etc.) to directly implement the comparison circuit.

[0099] In this way, the embodiment of the present application sets the first threshold voltage and the second threshold voltage, so that the current limiting protection circuit starts to work only after the output voltage vout is reduced by a certain voltage capacity, thereby ensuring the self-regulation capability of the low voltage difference linear voltage regulator circuit; and it is achieved that the current limiting protection circuit stops working only after the output voltage vout recovers a sufficient voltage capacity, and the low voltage difference linear voltage regulator circuit can start working again, thereby improving the safety of the low voltage difference linear voltage regulator circuit.

[0100] In an optional implementation, the switch detection module 10 includes a hysteresis comparator COM2, a second switch transistor MC2, a detection transistor MS and a detection resistor RS;

[0101] The first input terminal of the hysteresis comparator COM2 is configured to obtain the output voltage vout, the second input terminal of the hysteresis comparator COM2 is configured to obtain the second reference voltage vref2, and the output terminal of the hysteresis comparator COM2 is connected to the control terminal of the second switch transistor MC2;

[0102] The control end of the detection transistor MS is connected to the control end of the output transistor MP; the first signal end of the detection transistor MS is connected to the first power supply end vdda, and the second signal end of the detection transistor MS is connected to the second signal end of the second switch transistor MC2; the first signal end of the second switch transistor MC2 is connected to the first end of the detection resistor RS and is configured to provide the detection voltage vs; the second end of the detection resistor RS is connected to the second power supply end vssa;

[0103] The second switch transistor MC2, the detection transistor MS and the detection resistor RS connected between the first power supply terminal vdda and the second power supply terminal vssa constitute the current detection path;

[0104] The first threshold voltage is less than the second reference voltage vref2 , and the second threshold voltage is greater than the second reference voltage vref2 .

[0105] In the embodiment of the present application, the first power supply terminal vdda can provide a power supply voltage, and the second power supply terminal vsa can be grounded.

[0106] The second switch transistor MC2 can be a single transistor; it can also be a plurality of transistors connected in series and / or in parallel, having a control terminal, a first signal terminal and a second signal terminal corresponding to a single transistor. Its working principle can refer to the working principle of the output transistor MP, which will not be repeated here.

[0107] The second switch transistor MC2 may include at least one of the following: MOSFET (metal oxide semiconductor field effect transistor, MOS transistor for short); BJT (bipolar junction transistor, triode for short); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor). Exemplarily, the second switch transistor MC2 may be a PMOS transistor, or may be an NMOS transistor.

[0108] The detection resistor RS may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0109] The first threshold voltage and the second threshold voltage may be determined according to the second reference voltage vref2 of the input hysteresis comparator COM2. The hysteresis comparator may be used to compare the output voltage vout with the first threshold voltage and the second threshold voltage, but the present invention is not limited thereto.

[0110] In some possible implementations, the first input terminal of the hysteresis comparator COM2 may be a negative input terminal, and the second input terminal may be a positive input terminal. If the low voltage difference linear voltage regulator circuit outputs normally, and the output voltage vout is higher than the second threshold voltage, the hysteresis comparator COM2 may output a second switch control signal of a low level, and the second switch transistor may be controlled to be disconnected. At this time, almost no current flows through the detection transistor MS, and there is no voltage drop on the detection resistor RS, that is, the output of the detection voltage vs is turned off, thereby turning off the output of the current limiting control signal.

[0111] If the low voltage difference linear voltage regulator circuit is overloaded, the output voltage vout decreases. When the output voltage vout is lower than the first threshold voltage, the hysteresis comparator COM2 can output a high-level second switch control signal, which can control the second switch transistor to be turned on, and the detection transistor MS flows through a detection current that is in a preset proportion to the current flowing through the output transistor MP, which is reflected in the voltage (detection voltage vs) on the detection resistor RS. The voltage increases to a high voltage, that is, the output of the detection voltage vs is turned on. Then, when the detection voltage vs is higher than the third reference voltage vref3, the current limiting control module 20 can output a current limiting control signal to the control end of the output transistor MP to control the low voltage difference linear voltage regulator circuit to be turned off and perform current limiting.

[0112] Of course, the first input terminal of the hysteresis comparator COM2 can be a positive input terminal, and the second input terminal can be a negative input terminal. Then, when the output voltage vout is lower than the first threshold voltage, the hysteresis comparator COM2 can output a low-level second switch control signal, and a second switch transistor adapted to the low-level second switch control signal can be set to control the current detection path to be turned on. The specific control principle can be obtained by referring to the above, and will not be repeated here.

[0113] In this way, the embodiment of the present application forms a current detection path that can be controlled to be on and off through the hysteresis comparator COM2, the second switching transistor MC2, the detection transistor MS and the detection resistor RS, and the low voltage difference linear voltage regulator circuit can start working again only after the output voltage vout needs to restore sufficient voltage capacity.

[0114] In an optional implementation, the current limiting control module 20 includes:

[0115] The comparator COM1 is configured to output a first switch control signal of a first level when the detection voltage vs is higher than the third reference voltage vref3; and to output a first switch control signal of a second level when the detection voltage vs is lower than the third reference voltage vref3;

[0116] The first switch transistor MC1 is configured to be turned on under the control of a first switch control signal of a first level to output the current limiting control signal; and to be turned off under the control of a first switch control signal of a second level to turn off the output of the current limiting control signal.

[0117] In the embodiment of the present application, the first switching transistor MC1 can be a single transistor; it can also be a plurality of transistors connected in series and / or in parallel, having a control terminal, a first signal terminal and a second signal terminal corresponding to a single transistor. Its working principle can refer to the working principle of the output transistor MP, which will not be repeated here.

[0118] The first switch transistor MC1 may include at least one of the following: MOSFET (metal oxide semiconductor field effect transistor, MOS transistor for short); BJT (bipolar junction transistor, triode for short); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor). Exemplarily, the first switch transistor MC1 may be a PMOS transistor, or may also be an NMOS transistor.

[0119] In some possible implementations, the negative input terminal of the comparator COM1 can be configured to obtain the detection voltage vs, and the positive input terminal can be configured to obtain the third reference voltage vref3. When the detection voltage vs is higher than the third reference voltage vref3, the comparator COM1 can output a low-level first switch control signal, which can control the first switch transistor to be turned on and output a current limiting control signal. On the contrary, when the detection voltage vs is lower than the third reference voltage vref3, the comparator COM1 can output a high-level first switch control signal, which can control the first switch transistor to be turned off and turn off the output of the current limiting control signal.

[0120] Of course, the detection voltage vs can also be input from the positive input terminal of the comparator COM1, so that when the detection voltage vs is higher than the third reference voltage vref3, the comparator COM1 can output a high-level first switch control signal, and a first switch transistor adapted to the high-level first switch control signal can be set to control the output current limiting control signal. The specific control principle can be obtained by referring to the above, and will not be repeated here.

[0121] In this way, the embodiment of the present application can control the output of the current limiting control signal or shut down the output by simply detecting whether the voltage is higher or lower than the third reference voltage through the comparator and the first switch transistor. Since the low voltage difference linear voltage regulator circuit can start working again after the output voltage recovers sufficient voltage capacity, it has been realized at the hysteresis comparator COM2, so there is no need to increase the hysteresis of the comparator COM1, thereby simplifying the circuit structure and facilitating miniaturization.

[0122] In an optional implementation, the output transistor MP is a PMOS transistor; the detection transistor MS is a PMOS transistor; the first switch transistor MC1 is a PMOS transistor; the second switch transistor MC2 is an NMOS transistor;

[0123] The negative input terminal of the hysteresis comparator COM2 is configured to obtain the output voltage vout, the positive input terminal of the hysteresis comparator COM2 is configured to obtain the second reference voltage vref2, the output terminal of the hysteresis comparator COM2 is connected to the gate of the second switch transistor MC2; the source of the second switch transistor MC2 is respectively connected to the first end of the detection resistor RS and the negative input terminal of the comparator COM1, and the drain of the second switch transistor MC2 is connected to the drain of the detection transistor MS; the second end of the detection resistor RS is connected to the second power supply terminal vssa; the source of the detection transistor MS is connected to the first power supply terminal vdda, and the gate of the detection transistor MS is connected to the gate of the output transistor MP;

[0124] The positive input terminal of the comparator COM1 is configured to obtain the third reference voltage vref3, the output terminal of the comparator COM1 is connected to the control terminal of the first switch transistor MC1; the source of the first switch transistor MC1 is connected to the first power supply terminal vdda; the drain of the first switch transistor MC1 is connected to the gate of the output transistor MP for transmitting the current limiting control signal.

[0125] In the embodiment of the present application, when the low voltage difference linear voltage regulator circuit outputs normally, the second threshold voltage determined based on the second reference voltage vref2 is less than the output voltage vout, so the hysteresis comparator COM2 outputs a low level, and the MC2 of the NMOS is cut off, so almost no current flows through the MS of the PMOS.

[0126] When the output of the low voltage difference linear voltage regulator circuit is overloaded, that is, when the output current of the low voltage difference linear voltage regulator circuit exceeds the rated current, the output voltage vout decreases at this time. When the output voltage vout is lower than the first threshold voltage determined based on the second reference voltage vref2, the hysteresis comparator COM2 outputs a high level, so that the MC2 of the NMOS is turned on, and the current flows through the MS of the PMOS, which is reflected as a high voltage on the detection resistor RS (the detection voltage vs increases), and the detection voltage vs input to the negative input terminal of the comparator COM1 increases. When the detection voltage vs is greater than the third reference voltage vref3, the comparator COM1 outputs a low level, the MC1 of the PMOS is turned on, and the drain terminal of MC1 outputs a high level, pulling up the gate of the MP of the PMOS, so that the low voltage difference linear voltage regulator circuit is turned off, thereby playing a role in current limiting.

[0127] Figure 3 A circuit diagram of another specific example of a current limiting protection circuit in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the current limiting protection circuit further includes a digital filter module (Digital Filter) 30;

[0128] The input end of the digital filter module 30 is connected to the output end of the low voltage difference linear voltage regulator circuit, and the output end of the digital filter module 30 is configured to output the output voltage of the low voltage difference linear voltage regulator circuit;

[0129] The digital filter module 30 is configured to sample the voltage value at the output end of the low voltage difference linear voltage regulator circuit multiple times within a preset time, and determine and output the output voltage of the low voltage difference linear voltage regulator circuit according to all the voltage values;

[0130] Wherein, when all the voltage values ​​are lower than a first threshold voltage, the output voltage is lower than the first threshold voltage;

[0131] In a case where any one of all the voltage values ​​is higher than the first threshold voltage, the output voltage is higher than the first threshold voltage.

[0132] In the embodiment of the present application, the digital filter module (Digital Filter) can sample the signal in the digital domain. By sampling, the continuous analog signal can be converted into a discrete digital signal, and then different types of processing such as low pass, high pass, band pass and band stop are performed in the digital filter. The digital filter module can process the input signal through digital hardware or software. The implementation of the digital filter module may include assembling a special hardware device according to a mathematical model or a signal flow graph, or directly using a general-purpose computer to perform programming.

[0133] When the LDO draws a large current, vout will also decrease at this moment, but the LDO is not overloaded at this time, and vout will return to normal after a period of time. Therefore, in order to avoid the comparator (such as the hysteresis comparator COM2) from making a misjudgment due to the instantaneous decrease of vout in this situation and directly shutting down the LDO, a digital filter module is added to the comparison end of the comparator to sample the LDO output voltage vout multiple times within a preset time (for example, after sampling once, sample it again after a period of time) and then output it, ensuring that when multiple samples are low level, a low level vout is output again, indicating that the LDO is overloaded. At this time, MC2 is controlled to be turned on, and finally the LDO is turned off.

[0134] Exemplarily, the output terminal of the digital filter module 30 is connected to the negative input terminal of the hysteresis comparator COM2.

[0135] The embodiment of the present application utilizes a digital filter module to perform multiple sampling of the voltage at the output end of the low-voltage difference linear voltage regulator circuit within a preset time, which can realize the confirmation of whether an overload occurs and whether the reduction of the output voltage vout can be automatically restored. In this way, it can be ensured that when the voltage values ​​obtained by multiple samplings are all lower than the first threshold voltage, it is confirmed that the low-voltage difference linear voltage regulator circuit has an overload. At this time, the digital filter module outputs the low-level output voltage vout (such as lower than the first threshold voltage) obtained by sampling, and finally controls the low-voltage difference linear voltage regulator circuit to shut down, which plays a role in current limiting. The preset time can be set according to actual needs.

[0136] And if the digital filtering module finds through multiple sampling that the voltage at the output end of the low-voltage difference linear voltage regulator circuit has recovered within the preset time, then the output voltage vout lower than the first threshold voltage will not be output (it can be determined based on the voltage value obtained by multiple sampling. The determination method can be set according to actual needs. For example, it can be the average value of all voltage values ​​obtained by multiple sampling within the preset time, or it can be the voltage value obtained by the last sampling within the preset time, etc.), and the current limiting protection circuit will not work.

[0137] Figure 4A circuit diagram of a specific example of a hysteresis comparator in an embodiment of the present application is shown. Among them, the specific circuit structure of the hysteresis comparator can be set according to actual needs and is not limited thereto. In an optional implementation, the hysteresis comparator includes a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21, a twenty-second PMOS transistor M22, a twenty-third NMOS transistor M23, a twenty-fourth PMOS transistor M24, a twenty-fifth PMOS transistor M25, a twenty-sixth PMOS transistor M26, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth PMOS transistor M29, a thirtieth NMOS transistor M30, a thirty-first PMOS transistor M31, a thirty-second NMOS transistor M32, a thirty-third PMOS transistor M33 and a thirty-fourth NMOS transistor M34;

[0138] The gate of the twentieth NMOS transistor M20 is configured as the first input terminal (such as the negative input terminal) of the hysteresis comparator COM2; the gate of the twenty-first NMOS transistor M21 is configured as the second input terminal (such as the positive input terminal) of the hysteresis comparator COM2;

[0139] The drain of the twentieth NMOS transistor M20 is respectively connected to the gate of the twenty-second PMOS transistor M22, the drain of the twenty-fourth PMOS transistor M24, the gate of the twenty-fourth PMOS transistor M24, the gate of the twenty-fifth PMOS transistor M25 and the drain of the twenty-sixth PMOS transistor M26, and the drain of the twenty-first NMOS transistor M21 is respectively connected to the gate of the twenty-ninth PMOS transistor M29, the drain of the twenty-seventh PMOS transistor M27, the gate of the twenty-sixth PMOS transistor M26 and the drain of the twenty-fifth PMOS transistor M25; the source of the twentieth NMOS transistor M20 and the source of the twenty-first NMOS transistor M21 are respectively connected to the drain of the twenty-eighth NMOS transistor M28, the source of the twenty-eighth NMOS transistor M28 is connected to the second power supply terminal vssa, and the gate of the twenty-eighth NMOS transistor M28 is configured to obtain the first low-bit bias signal vbn1;

[0140] A source of the twenty-fourth PMOS transistor M24, a source of the twenty-fifth PMOS transistor M25, a source of the twenty-sixth PMOS transistor M26, and a source of the twenty-seventh PMOS transistor M27 are respectively connected to the first power supply terminal vdda;

[0141] The source of the twenty-second PMOS transistor M22 and the source of the twenty-ninth PMOS transistor M29 are respectively connected to the first power supply terminal vdda, the drain of the twenty-second PMOS transistor M22 is respectively connected to the drain of the twenty-third NMOS transistor M23, the gate of the twenty-third NMOS transistor M23 and the gate of the thirtieth NMOS transistor M30, the source of the twenty-third NMOS transistor M23 and the source of the thirtieth NMOS transistor M30 are respectively connected to the second power supply terminal vssa; the drain of the twenty-ninth PMOS transistor M29 is respectively connected to the drain of the thirtieth NMOS transistor M30, the gate of the thirty-first PMOS transistor M31 and the gate of the thirty-second NMOS transistor M32;

[0142] The drain of the thirty-first PMOS transistor M31 is respectively connected to the drain of the thirty-second NMOS transistor M32, the gate of the thirty-third PMOS transistor M33 and the gate of the thirty-fourth NMOS transistor M34, and the drain of the thirty-third PMOS transistor M33 is connected to the drain of the thirty-fourth NMOS transistor M34 and is configured as the output terminal COM2out of the hysteresis comparator;

[0143] The source of the thirty-first PMOS transistor M31 and the source of the thirty-third PMOS transistor M33 are respectively connected to the first power supply terminal vdda, and the source of the thirty-second NMOS transistor M32 and the source of the thirty-fourth NMOS transistor M34 are respectively connected to the second power supply terminal vsa.

[0144] In the embodiment of the present application, the main structure of the hysteresis comparator is formed by the twentieth NMOS transistor M20, the twenty-first NMOS transistor M21, the twenty-second PMOS transistor M22, the twenty-third NMOS transistor M23, the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, the twenty-sixth PMOS transistor M26, the twenty-seventh PMOS transistor M27, the twenty-eighth NMOS transistor M28, the twenty-ninth PMOS transistor M29 and the thirtieth NMOS transistor M30. The twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 are input pairs of transistors of the hysteresis comparator, the gate input vout of the twentieth NMOS transistor M20, and the gate input vref2 of the twenty-first NMOS transistor M21. The thirty-first PMOS transistor and the thirty-second NMOS transistor form a first inverter, and the thirty-third PMOS transistor and the thirty-fourth NMOS transistor form a second inverter, so as to realize waveform shaping, realize localization of the output signal of the hysteresis comparator, and improve the output stability.

[0145] Figure 5A circuit diagram of a specific example of a comparator in an embodiment of the present application is shown. The specific circuit structure of the comparator can be set according to actual needs and is not limited thereto. In an optional implementation, the comparator includes a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth NMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth NMOS transistor M17 and an eighteenth PMOS transistor M18;

[0146] The gate of the twelfth NMOS transistor M12 is configured as the negative input terminal of the comparator COM1; the gate of the thirteenth NMOS transistor M13 is configured as the positive input terminal of the comparator COM1;

[0147] The drain of the twelfth NMOS transistor M12 is connected to the drain of the fifteenth PMOS transistor M15, the gate of the fifteenth PMOS transistor M15 and the gate of the sixteenth PMOS transistor M16 respectively, and the drain of the thirteenth NMOS transistor M13 is connected to the drain of the sixteenth PMOS transistor M16 and the gate of the eighteenth PMOS transistor M18 respectively; the source of the fifteenth PMOS transistor M15, the source of the sixteenth PMOS transistor M16 and the source of the eighteenth PMOS transistor M18 are connected to the first power supply terminal vdda respectively;

[0148] The source of the twelfth NMOS transistor M12 and the source of the thirteenth NMOS transistor M13 are respectively connected to the drain of the fourteenth NMOS transistor M14, and the gate of the fourteenth NMOS transistor M14 and the gate of the seventeenth NMOS transistor M17 are respectively configured to obtain the first low-bit bias signal vbn1; the source of the fourteenth NMOS transistor M14 and the source of the seventeenth NMOS transistor M17 are respectively connected to the second power supply terminal vssa;

[0149] A drain of the seventeenth NMOS transistor M17 is connected to a drain of the eighteenth PMOS transistor M18 and configured as an output terminal COM1out of the comparator.

[0150] In the embodiment of the present application, the twelfth NMOS transistor M12 and the thirteenth NMOS transistor M13 are an input pair of transistors of the comparator, the gate of the twelfth NMOS transistor M12 inputs the detection voltage vs, and the gate of the thirteenth NMOS transistor M13 inputs vref3.

[0151] The embodiment of the present application also provides a low voltage difference linear voltage stabilization circuit, Figure 6A circuit diagram of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application is shown. As shown in the figure, the low voltage difference linear voltage regulator circuit includes an error amplifier EA, an output transistor MP, a feedback circuit 40 and a current limiting protection circuit as described in the above embodiment;

[0152] The first input terminal (negative input terminal) of the error amplifier EA is configured to obtain a first reference voltage vref1, the second input terminal (positive input terminal) of the error amplifier EA is connected to the output terminal of the feedback circuit 40, and the output terminal of the error amplifier EA is connected to the control terminal of the output transistor MP; the first signal terminal of the output transistor MP is connected to the first power supply terminal vdda, and the second signal terminal of the output transistor MP is connected to the input terminal of the feedback circuit 40 and is configured to provide the output voltage vout of the low voltage difference linear voltage regulator circuit.

[0153] The specific circuit structure of the error amplifier can be set according to actual needs and is not limited to Figure 6 In an optional implementation, the error amplifier EA includes a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11 and a compensation capacitor Cc;

[0154] The gate of the first PMOS transistor M1 is configured as the first input terminal of the error amplifier EA; the gate of the second PMOS transistor M2 is configured as the second input terminal of the error amplifier EA;

[0155] The drain of the first PMOS transistor M1 is respectively connected to the drain of the third NMOS transistor M3, the gate of the third NMOS transistor M3 and the gate of the fifth NMOS transistor M5, the drain of the second PMOS transistor M2 is respectively connected to the drain of the fourth NMOS transistor M4, the gate of the fourth NMOS transistor M4 and the gate of the sixth NMOS transistor M6; the drain of the fifth NMOS transistor M5 is connected to the source of the seventh NMOS transistor M7, the drain of the sixth NMOS transistor M6 is connected to the source of the eighth NMOS transistor M8; the drain of the seventh NMOS transistor M7 is respectively connected to the drain of the ninth PMOS transistor M9, the gate of the ninth PMOS transistor M9 and the gate of the tenth PMOS transistor M10, the drain of the eighth NMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10 and is configured as the output end of the error amplifier EA;

[0156] The gate of the seventh NMOS transistor M7 and the gate of the eighth NMOS transistor M8 are respectively configured to obtain the second low-bit bias signal vbn2; the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, the source of the fifth NMOS transistor M5 and the source of the sixth NMOS transistor M6 are respectively connected to the second power supply terminal vssa; the source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are respectively connected to the drain of the eleventh PMOS transistor M11, and the gate of the eleventh PMOS transistor M11 is configured to obtain the first high-bit bias signal vbp1; the source of the eleventh PMOS transistor M11, the source of the ninth PMOS transistor M9 and the source of the tenth PMOS transistor M10 are respectively connected to the first power supply terminal vdda;

[0157] A first end of the compensation capacitor Cc is connected to the drain of the sixth NMOS transistor M6 and the source of the eighth NMOS transistor M8 respectively, and a second end of the compensation capacitor Cc is connected to the output end of the low voltage difference linear voltage regulator circuit.

[0158] In the embodiment of the present application, the first PMOS transistor M1 and the second PMOS transistor M2 are input pairs of the error amplifier EA. The gate of the first PMOS transistor M1 can be configured to receive a first reference voltage vref1. The gate of the second PMOS transistor M2 can be configured to obtain a feedback signal vfb and can be connected to a connection node between the first resistor R1 and the second resistor R2. The gate of the output transistor MP can be connected to the drain of the eighth NMOS transistor M8 and the drain of the tenth PMOS transistor M10, respectively.

[0159] In the embodiment of the present application, the compensation capacitor Cc can be a single capacitor, or a plurality of capacitors connected in series and / or in parallel, or a passive capacitor network or an active capacitor network including resistors, capacitors, inductors, etc. The compensation capacitor Cc provides the function of a Miller compensation capacitor, which can improve the stability of the output voltage vout.

[0160] In this way, the low voltage difference linear voltage regulator circuit of the embodiment of the present application can reduce power consumption through the current limiting protection circuit of the above embodiment, and can limit the output overcurrent of the low voltage difference linear voltage regulator circuit through the current limiting protection circuit of the hysteresis comparator, and the low voltage difference linear voltage regulator circuit can start working again after the current capacity drops to a certain level.

[0161] In the embodiment of the present application, the specific circuit structure of the feedback circuit 40 can be set according to actual needs and is not limited to Figure 6 In an optional embodiment, the feedback circuit 40 includes a first resistor R1 and a second resistor R2;

[0162] The second input terminal of the error amplifier EA is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2 respectively. The first terminal of the first resistor R1 is connected to the second signal terminal of the output transistor MP. The second terminal of the second resistor R2 is connected to the second power supply terminal vsa.

[0163] In the embodiment of the present application, the first resistor R1 and the second resistor R2 can be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0164] In the embodiment of the present application, the first low-bit bias signal vbn1, the second low-bit bias signal vbn2 and the first high-bit bias signal vbp1 can all be provided by external bias circuits, and these bias circuits can be controlled by logic control circuits. These are not the inventive points of the invention, and the bias circuits and logic control circuits are both prior art, and the present invention will not be described in detail.

[0165] The transistor in the embodiment of the present application may be a single transistor or a plurality of transistors may be connected in series and / or in parallel.

[0166] An embodiment of the present application also provides a radio frequency module, which includes a low voltage difference linear voltage regulator circuit as described in the above embodiment, thereby reducing power consumption and effectively reducing heating and burning of the module / chip.

[0167] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A current limiting protection circuit, characterized in that: The current limiting protection circuit comprises: A switch detection module, configured to turn on or off a current detection path under the control of the output voltage of the low-voltage difference linear voltage regulator circuit, so as to turn on or off the output of the detection voltage; wherein the current detection path is used to use a detection transistor to copy the current flowing through the output transistor of the low-voltage difference linear voltage regulator circuit according to a preset ratio to obtain a detection current, and determine the detection voltage according to the detection current; a current limiting control module, configured to output a current limiting control signal to the control end of the output transistor to make the low voltage difference linear voltage regulator circuit enter a closed state when the detection voltage is obtained and the detection voltage is higher than a third reference voltage; and to turn off the output of the current limiting control signal to restore the low voltage difference linear voltage regulator circuit to a normal working state when the detection voltage is not obtained; Wherein, the current limiting protection circuit serves as a peripheral circuit of the low voltage difference linear voltage stabilization circuit.

2. The current limiting protection circuit according to claim 1, characterized in that: The switch detection module is configured to, when the output voltage is lower than a first threshold voltage, be controlled by the output voltage to turn on the current detection path so as to turn on the output of the detection voltage; When the output voltage is higher than a second threshold voltage, the current detection path is disconnected under the control of the output voltage, so that the output of the detection voltage is turned off; The first threshold voltage is smaller than the second threshold voltage.

3. The current limiting protection circuit according to claim 2, characterized in that: The switch detection module includes a hysteresis comparator, a second switch transistor, a detection transistor and a detection resistor; The first input terminal of the hysteresis comparator is configured to obtain the output voltage, the second input terminal of the hysteresis comparator is configured to obtain the second reference voltage, and the output terminal of the hysteresis comparator is connected to the control terminal of the second switch transistor; The control end of the detection transistor is connected to the control end of the output transistor; the first signal end of the detection transistor is connected to the first power supply end, and the second signal end of the detection transistor is connected to the second signal end of the second switch transistor; the first signal end of the second switch transistor is connected to the first end of the detection resistor and is configured to provide the detection voltage; the second end of the detection resistor is connected to the second power supply end; Wherein, the second switch transistor, the detection transistor and the detection resistor connected between the first power supply terminal and the second power supply terminal constitute the current detection path; The first threshold voltage is lower than the second reference voltage, and the second threshold voltage is higher than the second reference voltage.

4. The current limiting protection circuit according to claim 3, characterized in that: The current limiting control module comprises: a comparator configured to output a first switch control signal of a first level when the detection voltage is higher than the third reference voltage; and to output a first switch control signal of a second level when the detection voltage is lower than the third reference voltage; The first switch transistor is configured to be turned on under the control of a first switch control signal of a first level to output the current limiting control signal; and to be turned off under the control of a first switch control signal of a second level to turn off the output of the current limiting control signal.

5. The current limiting protection circuit according to claim 4, characterized in that: The output transistor is a PMOS transistor; the detection transistor is a PMOS transistor; the first switch transistor is a PMOS transistor; and the second switch transistor is an NMOS transistor; The negative input terminal of the hysteresis comparator is configured to obtain the output voltage, the positive input terminal of the hysteresis comparator is configured to obtain the second reference voltage, the output terminal of the hysteresis comparator is connected to the gate of the second switch transistor; the source of the second switch transistor is respectively connected to the first end of the detection resistor and the negative input terminal of the comparator, and the drain of the second switch transistor is connected to the drain of the detection transistor; the second end of the detection resistor is connected to the second power supply terminal; the source of the detection transistor is connected to the first power supply terminal, and the gate of the detection transistor is connected to the gate of the output transistor; The positive input terminal of the comparator is configured to obtain the third reference voltage, the output terminal of the comparator is connected to the control terminal of the first switching transistor; the source of the first switching transistor is connected to the first power supply terminal; the drain of the first switching transistor is connected to the gate of the output transistor for transmitting the current limiting control signal.

6. The current limiting protection circuit according to any one of claims 1 to 5, characterized in that: The current limiting protection circuit also includes a digital filtering module; The input end of the digital filter module is connected to the output end of the low voltage difference linear voltage regulator circuit, and the output end of the digital filter module is configured to output the output voltage of the low voltage difference linear voltage regulator circuit; The digital filtering module is configured to sample the voltage value at the output end of the low voltage difference linear voltage regulator circuit multiple times within a preset time, and determine and output the output voltage of the low voltage difference linear voltage regulator circuit according to all the voltage values; Wherein, when all the voltage values ​​are lower than a first threshold voltage, the output voltage is lower than the first threshold voltage; In a case where any one of all the voltage values ​​is higher than the first threshold voltage, the output voltage is higher than the first threshold voltage.

7. The current limiting protection circuit according to claim 6, characterized in that: The hysteresis comparator includes a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second PMOS transistor, a twenty-third NMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth PMOS transistor, a thirtieth NMOS transistor, a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor and a thirty-fourth NMOS transistor; The gate of the twentieth NMOS transistor is configured as the first input terminal of the hysteresis comparator; the gate of the twenty-first NMOS transistor is configured as the second input terminal of the hysteresis comparator; The drain of the 20th NMOS transistor is respectively connected to the gate of the 22nd PMOS transistor, the drain of the 24th PMOS transistor, the gate of the 24th PMOS transistor, the gate of the 25th PMOS transistor and the drain of the 26th PMOS transistor, and the drain of the 21st NMOS transistor is respectively connected to the gate of the 29th PMOS transistor, the drain of the 27th PMOS transistor, the gate of the 27th PMOS transistor, the gate of the 26th PMOS transistor and the drain of the 25th PMOS transistor; the source of the 20th NMOS transistor and the source of the 21st NMOS transistor are respectively connected to the drain of the 28th NMOS transistor, the source of the 28th NMOS transistor is connected to the second power supply terminal, and the gate of the 28th NMOS transistor is configured to obtain a first low-bit bias signal; A source of the twenty-fourth PMOS transistor, a source of the twenty-fifth PMOS transistor, a source of the twenty-sixth PMOS transistor, and a source of the twenty-seventh PMOS transistor are respectively connected to the first power supply terminal; The source of the twenty-second PMOS transistor and the source of the twenty-ninth PMOS transistor are respectively connected to the first power supply terminal, the drain of the twenty-second PMOS transistor is respectively connected to the drain of the twenty-third NMOS transistor, the gate of the twenty-third NMOS transistor and the gate of the thirtieth NMOS transistor, the source of the twenty-third NMOS transistor and the source of the thirtieth NMOS transistor are respectively connected to the second power supply terminal; the drain of the twenty-ninth PMOS transistor is respectively connected to the drain of the thirtieth NMOS transistor, the gate of the thirty-first PMOS transistor and the gate of the thirty-second NMOS transistor; The drain of the thirty-first PMOS transistor is respectively connected to the drain of the thirty-second NMOS transistor, the gate of the thirty-third PMOS transistor and the gate of the thirty-fourth NMOS transistor, and the drain of the thirty-third PMOS transistor is connected to the drain of the thirty-fourth NMOS transistor and configured as the output end of the hysteresis comparator; The source of the thirty-first PMOS transistor and the source of the thirty-third PMOS transistor are respectively connected to the first power supply terminal, and the source of the thirty-second NMOS transistor and the source of the thirty-fourth NMOS transistor are respectively connected to the second power supply terminal.

8. The current limiting protection circuit according to claim 7, characterized in that: The comparator includes a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth NMOS transistor and an eighteenth PMOS transistor; The gate of the twelfth NMOS transistor is configured as the negative input terminal of the comparator; the gate of the thirteenth NMOS transistor is configured as the positive input terminal of the comparator; The drain of the twelfth NMOS transistor is connected to the drain of the fifteenth PMOS transistor, the gate of the fifteenth PMOS transistor and the gate of the sixteenth PMOS transistor respectively, the drain of the thirteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and the gate of the eighteenth PMOS transistor respectively; the source of the fifteenth PMOS transistor, the source of the sixteenth PMOS transistor and the source of the eighteenth PMOS transistor are connected to the first power supply terminal respectively; The source of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor are respectively connected to the drain of the fourteenth NMOS transistor, and the gate of the fourteenth NMOS transistor and the gate of the seventeenth NMOS transistor are respectively configured to obtain the first low-bit bias signal; the source of the fourteenth NMOS transistor and the source of the seventeenth NMOS transistor are respectively connected to the second power supply terminal; A drain of the seventeenth NMOS transistor is connected to a drain of the eighteenth PMOS transistor and is configured as an output terminal of the comparator.

9. A low voltage difference linear voltage regulator circuit, characterized in that: The low voltage difference linear voltage regulator circuit comprises an error amplifier, an output transistor, a feedback circuit and a current limiting protection circuit as claimed in any one of claims 1 to 8; The first input terminal of the error amplifier is configured to obtain a first reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the control terminal of the output transistor; the first signal terminal of the output transistor is connected to the first power supply terminal, and the second signal terminal of the output transistor is connected to the input terminal of the feedback circuit and is configured to provide the output voltage of the low voltage difference linear voltage regulator circuit.

10. The low voltage difference linear voltage regulator circuit according to claim 9, characterized in that: The error amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor and a compensation capacitor; The gate of the first PMOS transistor is configured as the first input terminal of the error amplifier; the gate of the second PMOS transistor is configured as the second input terminal of the error amplifier; The drain of the first PMOS transistor is respectively connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor and the gate of the fifth NMOS transistor, the drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor and the gate of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the eighth NMOS transistor; the drain of the seventh NMOS transistor is respectively connected to the drain of the ninth PMOS transistor, the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor, the drain of the eighth NMOS transistor is connected to the drain of the tenth PMOS transistor and is configured as the output end of the error amplifier; The gate of the seventh NMOS transistor and the gate of the eighth NMOS transistor are respectively configured to obtain a second low-bit bias signal; The source of the third NMOS transistor, the source of the fourth NMOS transistor, the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are respectively connected to the second power supply terminal; the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the drain of the eleventh PMOS transistor, and the gate of the eleventh PMOS transistor is configured to obtain a first high bias signal; The source of the eleventh PMOS transistor, the source of the ninth PMOS transistor and the source of the tenth PMOS transistor are respectively connected to the first power supply terminal; A first end of the compensation capacitor is connected to the drain of the sixth NMOS transistor and the source of the eighth NMOS transistor respectively, and a second end of the compensation capacitor is connected to the output end of the low voltage difference linear voltage regulator circuit; And / or, the feedback circuit includes a first resistor and a second resistor; The second input terminal of the error amplifier is connected to the second terminal of the first resistor and the first terminal of the second resistor respectively. The first terminal of the first resistor is connected to the second signal terminal of the output transistor. The second terminal of the second resistor is connected to the second power supply terminal.

11. A radio frequency module, characterized in that: The radio frequency module includes the low voltage drop linear voltage regulator circuit as described in claim 9 or 10.

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