Current-limiting protection circuit of direct-current solid-state circuit breaker and control method thereof

Abstract

The invention provides a current-limiting protection circuit of a direct-current solid-state circuit breaker and a control method of the current-limiting protection circuit. The current-limiting protection circuit comprises a first current-limiting circuit, a second current-limiting circuit, a third current-limiting circuit, a first driving resistor, a second driving resistor, a first power switch, a second power switch, a third power switch, a first sampling module, a second sampling module and a third sampling module, the first current limiting circuit is used for comparing the sampling voltage output by the first sampling module with the reference voltage and reducing the current turn-off speed of the first power switch according to the comparison result; the second current limiting module is used for comparing the sampling voltage output by the second sampling module with the reference voltage and slowing down the current turn-off speed of a branch where the second power switch is located according to the comparison result; and the third current limiting circuit is used for comparing the sampling voltage output by the third sampling module with the reference voltage, and slowing down the current turn-off speed of the branch where the third power switch is located according to the comparison result. And the current overshoot degree of the parallel switching device can be greatly reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of direct current distribution systems, and in particular, relates to a current limiting protection circuit of a direct current solid-state circuit breaker and a control method thereof. Background Art

[0002] With the development of distributed power sources and energy storage technology, DC microgrids have received widespread attention because they can reliably and efficiently accommodate distributed power generation systems, energy storage units, and DC power loads. The low impedance and low inertia characteristics of DC microgrids result in a fast rise speed and high amplitude of short-circuit fault current. In addition, the DC microgrid has a small power supply radius and is more likely to become unstable after a fault occurs, so a protection method that can quickly clear the fault is required. Unfortunately, since traditional mechanical DC circuit breakers use mechanical switches as the main switches, the slow movement of the contacts results in the time it takes to cut off the fault current being generally in milliseconds, which may burn out the power conversion device and cause safety accidents, making it difficult to directly use them in DC microgrids. Fortunately, DC solid-state circuit breakers (SSCBs) based on power semiconductor devices can effectively solve problems such as slow shutdown speed and difficulty in arc extinguishing.

[0003] As the main switch of SSCB, power semiconductor devices are the key part of SSCB to achieve fault current removal. They are mainly divided into traditional silicon-based devices and wide bandgap (WBG) semiconductor devices represented by silicon carbide (SiC) materials. Compared with silicon-based devices, WBG semiconductors have the advantages of low on-resistance and high maximum allowable junction temperature, making them very suitable for SSCB applications. Unfortunately, due to the limitations of the WBG semiconductor chip production process, the current-carrying capacity of commercial WBG discrete devices is generally average and cannot be directly applied to high-current DC fault isolation scenarios. Parallel power devices are the most direct, simple and effective way to increase the current level of SSCB.

[0004] Current balance is the main challenge when multiple devices are connected in parallel. Even if devices with the same parameters and models are selected, there will still be current unevenness during the actual current shutdown process due to the influence of the internal parasitic parameters of the device and the parasitic parameters of the line. This may cause overcurrent in one or more devices in several parallel device groups, thereby affecting the service life of the device or even causing damage, affecting the normal function of the SSCB. Therefore, solving the overcurrent problem caused by uneven current between parallel devices is the key to ensuring the reliable operation of the power device parallel module. Summary of the invention

[0005] The main purpose of the embodiment of the present invention is to provide a current limiting protection circuit of a DC solid-state circuit breaker and a control method thereof, which can adjust the shutdown speed of the switching device through a closed-loop control method, slow down the current change rate of the device with a faster shutdown speed, and greatly reduce the current overshoot of the parallel switching device.

[0006] In a first aspect, a current limiting protection circuit for a DC solid-state circuit breaker is provided, comprising: a first current limiting circuit, a second current limiting circuit, a third current limiting circuit, a first driving resistor, a second driving resistor, a third driving resistor, a first power switch, a second power switch, a third power switch, a first sampling module, a second sampling module and a third sampling module; the gate of the first power switch is connected to a first control signal through the first driving resistor, the gate of the second power switch is connected to a second control signal through the second driving resistor, the gate of the third power switch is connected to a third control signal through the third driving resistor, the drain of the first power switch, the drain of the second power switch and the drain of the third power switch are connected to an input end, and the source of the first power switch, the source of the second power switch and the source of the third power switch are connected to an input end through the first sampling module, the second sampling module and the third sampling module respectively. The output end is connected; the first current limiting circuit is connected to the first sampling module and the gate and source of the first power switch, and is used to compare the sampled voltage output by the first sampling module with the reference voltage, and slow down the current shutdown speed of the first power switch according to the comparison result; the second current limiting module is connected to the second sampling module and the gate and source of the second power switch, and is used to compare the sampled voltage output by the second sampling module with the reference voltage, and slow down the current shutdown speed of the branch where the second power switch is located according to the comparison result; the third current limiting module is connected to the third sampling module and the gate and source of the third power switch, and is used to compare the sampled voltage output by the third sampling module with the reference voltage, and slow down the current shutdown speed of the branch where the third power switch is located according to the comparison result, and the reference voltage is the arithmetic mean of the sampled voltages output by the first sampling module, the second sampling module and the third sampling module.

[0007] In another possible implementation, the first current limiting circuit includes: a first comparator, a first switch tube and a first capacitor; the non-inverting input terminal of the first comparator is connected to the first sampling module, the inverting input terminal is connected to the reference voltage, the output terminal of the first comparator is connected to the first end of the first switch tube, the second end of the first switch tube is connected to the gate of the first power switch through the first capacitor, and the third end of the first switch tube is connected to the source of the first power switch.

[0008] In another possible implementation, the second current limiting circuit includes: a second comparator, a second switch tube and a second capacitor; the non-inverting input terminal of the second comparator is connected to the second sample module, the inverting input terminal is connected to the reference voltage, the output terminal of the second comparator is connected to the first end of the second switch tube, the second end of the second switch tube is connected to the gate of the second power switch through the second capacitor, and the third end of the second switch tube is connected to the source of the second power switch.

[0009] In another possible implementation, the third current limiting circuit includes: a third comparator, a third switch tube and a third capacitor; the non-inverting input terminal of the third comparator is connected to the third sample module, the inverting input terminal is connected to the reference voltage, the output terminal of the third comparator is connected to the first end of the third switch tube, the second end of the third switch tube is connected to the gate of the third power switch through the third capacitor, and the third end of the third switch tube is connected to the source of the third power switch.

[0010] In another possible implementation, the first switch tube, the second switch tube and the third switch tube are P-MOSFETs, the first end is a gate, the second end is a drain, and the third end is a source.

[0011] In another possible implementation, when a short circuit fault occurs in the solid-state circuit breaker line, if the current of the first branch where the first power switch is located is lower than the average current of the first branch, the second branch and the third branch, the first comparator outputs a low level, drives the first switch tube to turn on, and the first capacitor is connected between the gate and the source of the first power switch to provide a discharge circuit for the gate capacitor of the first power switch, thereby slowing down the shutdown speed of the first power switch; if the current of the second branch where the second power switch is located is lower than the average current, the second comparator outputs a low level, drives the second switch tube to turn on, the second capacitor is connected between the gate and the source of the second power switch to provide a discharge circuit for the gate capacitor of the second power switch, thereby slowing down the shutdown speed of the second power switch; if the current of the third branch where the third power switch is located is lower than the average current, the third comparator outputs a low level, drives the third switch tube to turn on, the third capacitor is connected between the gate and the source of the third power switch to provide a discharge circuit for the gate capacitor of the third power switch, thereby slowing down the shutdown speed of the third power switch.

[0012] In a possible implementation, the current limiting protection circuit also includes a reference voltage generating circuit, which includes a fourth comparator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; the non-inverting input terminal of the fourth comparator is connected to the sampled voltage sampled and output by the first sampling module through the fifth resistor, the sampled voltage sampled and output by the second sampling module through the sixth resistor, the sampled voltage sampled and output by the third sampling module through the seventh resistor, and is also grounded through the eighth resistor; the inverting input terminal of the fourth comparator is grounded through the ninth resistor, and is connected to the output terminal of the fourth comparator through the tenth resistor, and the output terminal of the fourth comparator outputs the reference voltage to the first current limiting circuit, the second current limiting circuit and the third current limiting circuit.

[0013] In a second aspect, a control method for a current limiting protection circuit of the aforementioned DC solid-state circuit breaker is provided, comprising: if a short circuit fault occurs in the line, in a first stage, the current of a first branch where a first power switch is located, a second branch where a second power switch is located, and a third branch where a third power switch is located are controlled to rise, and the currents of the three branches are equal; in a second stage, after the currents of the three branches rise to a current threshold, the gates of the first power switch, the second power switch, and the third power switch receive a first control signal, a second control signal, and a third control signal indicating shutdown through a first drive resistor, a second drive resistor, and a third drive resistor, respectively; in a third stage, if the first drive resistor is the smallest among the first drive resistor, the second drive resistor, and the third drive resistor, control The gate-source voltage of the first power switch decreases the fastest; in the fourth stage, the gate-source voltage of the first power switch reaches the Miller platform voltage first, and the first power switch is controlled to start shutting down, the current of the first branch decreases, the current is switched, the currents of the second branch and the third branch increase, the current of the first branch is lower than the average current of the first branch, the second branch and the third branch, and the first current limiting circuit is controlled to work, providing a discharge loop for the gate-source voltage of the first power switch, and slowing down the shutdown speed of the first power switch; in the fifth stage, the Miller platform of the first power switch ends, the current of the first branch is less than the average current, and the first current limiting circuit is connected between the gate and source of the first power switch to control the shutdown speed of the first power switch to slow down until the gate-source voltage of the first power switch reaches the preset shutdown voltage.

[0014] In a third aspect, a DC solid-state circuit breaker is provided, comprising: a solid-state switch, a sampling module, an isolation unit, a controller, a drive circuit and an energy absorption circuit, wherein the solid-state switch is specifically the aforementioned current limiting protection circuit; the solid-state switch is connected in series to the DC bus, the energy absorption circuit is connected in parallel to both ends of the solid-state switch, the sampling module is connected to the DC bus and the isolation unit, the controller is connected to the isolation unit and the drive circuit, and the drive circuit is connected to the solid-state switch.

[0015] In another possible implementation, the energy absorption circuit includes: a varistor, a fourth capacitor and a fourth resistor; the varistor is connected in parallel across the solid-state switch, and a branch in which the fourth capacitor and the fourth resistor are connected in series is connected in parallel across the solid-state switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in describing the embodiments of the present application are briefly introduced below.

[0017] Figure 1 A topological schematic diagram of a DC solid-state circuit breaker provided by an embodiment of the present invention; Figure 2 A schematic structural diagram of a current limiting protection circuit for a DC solid-state circuit breaker provided by an embodiment of the present invention; Figure 3 A schematic diagram of a simulation circuit of a current limiting protection circuit of a DC solid-state circuit breaker provided by an embodiment of the present invention; Figure 4 is a schematic diagram of a reference voltage generating circuit in an embodiment of the present invention; Figure 5 A schematic diagram of waveforms during the shutdown process of a DC solid-state circuit breaker according to an embodiment of the present invention; Figure 6 It is a schematic diagram of simulation results of the current limiting protection circuit of the DC solid-state circuit breaker under current limiting control according to an embodiment of the present invention; Figure 7 It is a schematic diagram of simulation results of a current limiting protection circuit of a DC solid-state circuit breaker in an embodiment of the present invention when there is no current limiting control; Figure 8 A schematic flow chart of a control method for a current limiting protection circuit of a DC solid-state circuit breaker provided by the present invention. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present invention.

[0019] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, modules and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, modules, components and / or groups thereof. It should be understood that when we refer to a module as being "connected" or "coupled" to another module, it may be directly connected or coupled to the other modules, or there may be intermediate modules. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any modules and all combinations of one or more associated listed items.

[0020] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation method of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0021] The technical solution of the present application and how to solve the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0022] Figure 1 A topological diagram of a DC solid-state circuit breaker provided in one embodiment of the present invention. A DC solid-state circuit breaker 1 is connected in series to a DC bus. Specifically, the input end of the DC solid-state circuit breaker 1 is connected to the bus voltage V via an inductor L. DC The output end of the DC solid-state circuit breaker 1 is connected through a load resistor R load Ground.

[0023] A DC solid-state circuit breaker (SSCB) 1 includes: a solid-state switch 11, a sampling module 12, an isolation unit 13, a controller 14, a drive circuit 15, and an energy absorption circuit 16. The solid-state switch 11 is a key part of the solid-state circuit breaker to realize fault current shutdown, specifically a current limiting protection circuit to limit the overshoot of the shutdown current. The current limiting protection circuit is a current limiting parallel module including SiC JFET based on capacitor buffer, and its specific structure is described later. The solid-state switch 11 is connected in series to the DC bus, the energy absorption circuit 16 is connected in parallel to both ends of the solid-state switch 11, the sampling module 12 is connected to the DC bus and the isolation unit 13, the controller 14 is connected to the isolation unit 13 and the drive circuit 15, and the drive circuit 15 is connected to the solid-state switch 11. The sampling module 12, the isolation unit 13, the controller 14, and the drive circuit 15 are connected in sequence to form a control circuit of the solid-state switch 11 to control the conduction and shutdown of the solid-state switch.

[0024] The energy absorption circuit 16 includes: a varistor MOV, a fourth capacitor C and a fourth resistor R; the varistor MOV is connected in parallel at both ends of the solid-state switch 11, and a branch formed by the fourth capacitor C and the fourth resistor R being connected in series is connected in parallel at both ends of the solid-state switch 11.

[0025] In the embodiment of the present invention, the sampling module 12 adopts the principle of current sampling to collect the current flowing through the SSCB. i line . The isolation module 13 transmits information through optical fiber to prevent interference between strong and weak electricity and ensure the safety of the equipment. The controller 14 uses a high-speed FPGA to improve the running speed of the fault algorithm. The drive module 15 has a negative voltage drive capability and can well drive the silicon carbide junction field effect transistor (SiC JFET) device in the current limiting protection circuit. The metal oxide varistor (MOV) and the RC buffer absorption loop are connected in parallel at both ends of the solid-state switch 11 to clamp the overvoltage of the device, protect the solid-state switch 11 from damage by transient overvoltage, and slow down the current shutdown process. dv / dt , absorbing the remaining energy in the line inductance.

[0026] Figure 2 A schematic diagram of a current limiting protection circuit for a DC solid-state circuit breaker provided by an embodiment of the present invention is provided. Figure 3 For a specific circuit diagram. Figure 2 and Figure 3 As shown, the current limiting protection circuit of the DC solid-state circuit breaker includes: a first current limiting circuit 111, a second current limiting circuit 112, a third current limiting circuit 113, a first driving resistor , the second driving resistor , the third driving resistor , a first power switch J1, a second power switch J2, a third power switch J3, a first sampling module 114, a second sampling module 115 and a third sampling module 116. The gate of the first power switch J1 is connected to the first driving resistor Connect the first control signal V GS1 The gate of the second power switch J2 is connected to the second driving resistor Connect the second control signal V GS2 The gate of the third power switch J3 is connected to the third driving resistor Connect the third control signal V GS3The drain of the first power switch J1, the drain of the second power switch J2 and the drain of the third power switch J3 are connected to the input terminal P, and the source of the first power switch J1, the source of the second power switch J2 and the source of the third power switch J3 are connected to the output terminal N through the first sampling module 114, the second sampling module 115 and the second sampling module 116 respectively. The first current limiting circuit 111 is connected to the gate and source of the first sampling module 114 and the first power switch J1, and is used to compare the sampling voltage v1 output by the first sampling module 114 with the reference voltage v ref The second current limiting module 112 is connected to the second sampling module 115 and the gate and source of the second power switch J2, and is used to compare the sampling voltage v2 output by the second sampling module 115 with the reference voltage v ref The third current limiting module 113 is connected to the third sampling module 116 and the gate and source of the third power switch J3, and is used to compare the sampling voltage v3 output by the third sampling module 116 with the reference voltage v ref , and according to the comparison result, the current shut-off speed of the branch where the third power switch J3 is located is slowed down, and the reference voltage v ref It is the arithmetic mean of the sampling voltages v1 , v2 , and v3 output by the first sampling module 114 , the second sampling module 115 , and the third sampling module 116 .

[0027] The first power switch J1, the second power switch J2 and the third power switch J3 are silicon carbide junction field effect transistors SiC JFET. gd , C gs and C ds They are the parasitic capacitances between the gate-drain, gate-source, and drain-source inside the SiC JFET. The first two have a significant impact on the switching speed, while the latter has a smaller impact on the switching speed. In order to reduce the impact of the parasitic inductance inside the power device and the parasitic inductance of the line in the PCB on the current sharing effect, the circuit design ensures symmetry while widening the connection line as much as possible. Figure 2In the table below, Jn (J1, J2, J3) represents SiC JFET, and n represents the ordinal number of the cascaded SiC JFET. The driving resistor Rgn (Rg1, Rg2, Rg3) is used to adjust the turn-off speed of the SiC JFET. The difference between the two currents at turn-off can be achieved by changing the size of the driving resistor Rgn. The JFET driving side capacitor Cn (C1, C2, C3), low-voltage MOSFET Qn (Q1, Q2, Q3) and high-speed comparator Un (U1, U2, U3) are used to adjust the voltage drop speed across the gate and source of the SiC JFET, and control the turn-off speed of the JFET to limit the turn-off current overshoot. The input of the comparator's non-inverting input terminal is the sampled voltage of the corresponding side branch current after passing through the sampling resistor. The input of the comparator's inverting input terminal is the sampled voltage of the other side branch current after passing through the sampling resistor. The output of the comparator controls the on and off of the MOSFET. When the MOSFET Qn is turned on, Cn is connected in parallel across the gate and source of the SiC JFET Jn to slow down v gs When MOSFET Qn is turned off, the gate-source voltage v gs Maintain normal falling speed. All the above devices work together to form a SiC JFET parallel current limiting module.

[0028] In the embodiment of the present invention, the first current limiting circuit 111 includes: a first comparator U1, a first switch tube Q1 and a first capacitor C1. The non-inverting input terminal of the first comparator U1 is connected to the first sampling module 114, and the inverting input terminal is connected to the reference voltage v ref The output end of the first comparator U1 is connected to the first end of the first switch tube Q1, the second end of the first switch tube Q1 is connected to the gate of the first power switch J1 through the first capacitor C1, and the third end of the first switch tube Q1 is connected to the source of the first power switch J1.

[0029] The second current limiting circuit 112 includes: a second comparator U2, a second switch tube Q2 and a second capacitor C2. The non-inverting input terminal of the second comparator U2 is connected to the second sampling module 115, and the inverting input terminal is connected to the reference voltage v ref The output end of the second comparator U2 is connected to the first end of the second switch tube Q2, the second end of the second switch tube Q2 is connected to the gate of the second power switch J2 through the second capacitor C2, and the third end of the second switch tube Q2 is connected to the source of the second power switch J2.

[0030] The third current limiting circuit 113 includes: a third comparator U3, a third switch tube Q3 and a third capacitor C3. The third comparator U3 has a non-inverting input terminal connected to the third sampling module 116, and an inverting input terminal connected to a reference voltage v refThe output end of the third comparator U2 is connected to the first end of the third switch tube Q3, the second end of the third switch tube Q3 is connected to the gate of the third power switch J3 through the third capacitor C3, and the third end of the third switch tube Q3 is connected to the source of the third power switch J3.

[0031] The first switch tube Q1, the second switch tube Q2 and the third switch tube Q3 are P-MOSFETs, the first end of which is a gate, the second end is a drain, and the third end is a source. Figure 3 The first current limiting circuit 111 includes a first resistor R1, and the third end of the first switch tube Q1 and the output end of the first sampling module 114 are grounded through the first resistor R1. The second current limiting circuit 112 includes a second resistor R2, and the third end of the second switch tube Q2 and the output end of the second sampling module 115 are grounded through the second resistor R2. The third current limiting circuit 113 includes a third resistor R3, and the third end of the third switch tube Q3 and the output end of the third sampling module 116 are grounded through the third resistor R3.

[0032] The current of the current limiting protection circuit flows from the input terminal P to the output terminal N. The input terminal P is Figure 1 The first control signal V gs1 , the second control signal V gs2 and the second control signal V gs3 Generated by the driving circuit 15, and used to control the on and off of the first power switch J1, the second power switch J2 and the third power switch J3 respectively.

[0033] See also Figure 4 The current limiting protection circuit of the DC solid-state circuit breaker also includes a reference voltage generating circuit, which is connected to the first current limiting circuit 111, the second current limiting circuit 112, the third current limiting circuit 113, the first sampling module 114, the second sampling module 115 and the third sampling module 116, and is used to generate a reference voltage v according to the sampled voltages v1, v2, and v3 sampled and output by the first sampling module 114, the second sampling module 115 and the third sampling module 116. ref, and transmitted to the first current limiting circuit 111, the second current limiting circuit 112 and the third current limiting circuit 113. The reference voltage generating circuit includes a fourth comparator U4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10. The non-inverting input terminal of the fourth comparator U4 is connected to the sampled voltage v1 sampled and output by the first sampling module 114 through the fifth resistor R5, to the sampled voltage v2 sampled and output by the second sampling module 115 through the sixth resistor R6, to the sampled voltage v3 sampled and output by the third sampling module 116 through the seventh resistor R7, and is also grounded through the eighth resistor R8. The inverting input terminal of the fourth comparator U4 is grounded through the ninth resistor R9, and is connected to the output terminal of the fourth comparator U4 through the tenth resistor R10. The output terminal of the fourth comparator U4 outputs the reference voltage v ref To the first current limiting circuit 111 , the second current limiting circuit 112 and the third current limiting circuit 113 .

[0034] When a short circuit fault occurs in the solid-state circuit breaker 1, if the current of the first branch where the first power switch J1 is located is lower than the average current of the first branch, the second branch and the third branch, the first comparator U1 outputs a low level, drives the first switch tube Q1 to turn on, and the first capacitor C1 is connected between the gate and the source of the first power switch J1 to provide a discharge loop for the gate capacitor of the first power switch J1, thereby slowing down the turn-off speed of the first power switch J1. If the current of the first branch where the second power switch J2 is located is lower than the average current, the second comparator U2 outputs a low level, drives the second switch tube Q2 to turn on, and the second capacitor C2 is connected between the gate and the source of the second power switch J2 to provide a discharge loop for the gate capacitor of the second power switch J2, thereby slowing down the turn-off speed of the second power switch J2.

[0035] If the current of the third branch where the third power switch J3 is located is lower than the average current, the third comparator U3 outputs a low level to drive the third switch tube Q3 to be turned on, and the third capacitor C3 is connected between the gate and the source of the third power switch J3 to provide a discharge loop for the gate capacitor of the third power switch J3, thereby slowing down the turn-off speed of the third power switch J3.

[0036] The shutdown process of the current limiting protection circuit of the DC solid-state circuit breaker is divided into multiple stages and analyzed in detail. Assuming that the resistance of the first drive resistor Rg1 is less than the resistance of the second drive resistor Rg2 and less than the resistance of the third drive resistor Rg3, the transient shutdown process of the SSCB is analyzed as follows: Here, it is assumed that the second power switch J2 and the third power switch J3 will have an overcurrent condition, then the current limiting control circuit of the first power switch J1 will start to work, while the current limiting control circuits of the second power switch J2 and the third power switch J3 will not work. Ignore the delays of the first sampling module 114, the second sampling module 115, the third sampling module 116, the first comparator U1, the second comparator U2 and the third comparator U3. The transient shutdown process is as follows, Figure 3 It is the waveform related to the transient shutdown process.

[0037] Phase I (0-t0): DC system operates normally, line operating current I rated If it is within the safety threshold range, SSCB operation will not be triggered.

[0038] Phase II (t0-t1): When a short circuit occurs, the SiC JFET on-state internal resistance R ON It is very small and can be basically ignored. The current in the line rises rapidly. The currents of the first branch where the first power switch J1 is located, the second branch where the second power switch J2 is located, and the third branch where the third power switch J3 is located share the line fault current. According to Kirchhoff's Voltage Law (KVL): (1) The above differential equation has the initial condition: t=t0, The solution of , after first-order Taylor expansion, is: (2) The currents in the two branches are: (3) Phase III (t1-t2): When the short-circuit current reaches the preset threshold I th After that, the current sampled by the sampling module 12 reaches the controller 14 through the isolation unit 13, and then is processed by the controller 14, and a shutdown signal is sent to the drive circuit 15 of the first power switch J1, the second power switch J2 and the third power switch J3. The drive circuit 15 sends a first control signal V indicating shutdown to the gate of the first power switch J1, the gate of the second power switch J2 and the gate of the third power switch J3 respectively. GS1 , the second control signal V GS2 and the third control signal V GS3. The gate-source voltage of the first power switch J1, the second power switch J2 and the third power switch J3 begins to drop. Since the gate-source voltage of the first power switch J1, the second power switch J2 and the third power switch J3 does not reach the turn-off threshold voltage at this time, the SSCB does not turn off the fault current, and the parallel branch currents are the same. Therefore, the first comparator U1, the second comparator U2 and the third comparator U3 output 1, that is, output a high level, and control the first switch tube Q1, the second switch tube Q2 and the third switch tube Q3 to turn off. The first capacitor C1, the second capacitor C2 and the third capacitor C3 on the driving side are not connected to the corresponding circuit, and the parasitic capacitance C of the gate-source side of the first power switch J1, the second power switch J2 and the third power switch J3 is gs1 , C gs2 , C gs3 The corresponding branches drive the electric discharge respectively. According to the KVL law: (4) In the formula, , , is the driving resistance of the first power switch J1, the second power switch J2 and the third power switch J3, , , is the gate-source parasitic capacitance of the first power switch J1, the second power switch J2 and the third power switch J3, , is the gate-source voltage of the first power switch J1, the second power switch J2 and the third power switch J3, , , is the turn-off voltage of the first power switch J1 , the second power switch J2 and the third power switch J3 , preferably -15V.

[0039] Due to the driving resistance ,therefore Decline faster than , .

[0040] Stage IV (t2-t3): First, the Miller platform voltage is reached, and JFET1 starts to turn off. The current changes phase when the , Rise. When the current is less than the average current, the first comparator U1 is controlled to output a low level, and the first switch tube Q1 is controlled to be turned on. At this time, the first capacitor C1 is connected to both sides of the gate source of the first power switch J1 to provide a discharge circuit for the gate capacitor, thereby slowing down the turn-off speed of the first power switch J1.

[0041] (5) Wherein, C1 is the first capacitor connected in parallel to the driving side of the first power switch J1, is the voltage across the first capacitor C1.

[0042] Phase V (t3-t4): At t4, the Miller platform of the first power switch J1 ends, C gs2 Continue charging. Since the current of the first branch where the first power switch J1 is located is less than the current of the second branch where the second power switch J2 is located, the first comparator U1 of the first branch where the first power switch J1 is located outputs a low level, and the first capacitor C1 on the driving side of the first power switch J1 is connected. At this time, C1 is connected to both sides of the gate source of the first power switch J1, providing a discharge circuit for the gate capacitor, slowing down the turn-off speed of the second power switch J1, The decreasing situation is the same as formula (5). Until the gate-source voltage of the first power switch Down to V GS .

[0043] The present invention can timely cut off the short-circuit fault when the SSCB responds to the line short-circuit fault, and ensures that during the fault cutting stage of the SSCB, if the current between branches is overcurrent, the current cut-off rate can be adjusted in time to limit the unevenness of the branch current.

[0044] In the process of the switch device turning off the fault current, the difference in the turning-off speed between the parallel devices due to various other factors is the main reason for the uneven turning-off transient current. The current limiting protection circuit of the DC solid-state circuit breaker in the embodiment of the present invention can effectively reduce the overcurrent of the parallel switching devices. When a short circuit fault occurs, the connection and disconnection of the capacitor on the driving side of the switching device are realized through a closed-loop control method, thereby adjusting the turning-off speed of the switching device, slowing down the current change rate of the device with a faster turning-off speed, and limiting the current overshoot of the switching device. Compared with most of the developed DC solid-state circuit breaker topologies, the present invention effectively increases the capacity of the SSCB by connecting SiC JFETs in parallel; and compared with the topology using a passive current limiting control method, the addition of active devices in the present invention greatly reduces the current overshoot of the parallel switching devices.

[0045] In order to verify the effectiveness of the SSCB current limiting control scheme proposed in the embodiment of the present invention, the feasibility of the current limiting protection circuit of the DC solid-state circuit breaker will be verified through PSpice simulation. Figure 4 To simulate the circuit, the current limiting protection circuit of the DC solid-state circuit breaker is connected to the test circuit and turned on and off through the VPULSE driving topology. The specific structure of the current limiting protection circuit can be found in Figure 2, VPULSE is the VPULSE pulse voltage source inside PSpice, and DC uses the VDC direct current voltage source built into PSpice.

[0046] The device parameters in the simulation circuit are shown in Table 1. The simulation model of SiC JFET comes from UnitedSiC, USA. The bus voltage V DC Set to 450 V. Output a control signal to both ends of the GS of the current limiting protection circuit through VPULSE to drive the parallel JFET to turn off. Observe the turn-off waveform of the current limiting control topology to verify the turn-off effect of the topology in the test circuit and verify the feasibility of the topology circuit.

[0047] Table 1 Device parameters of current limiting protection circuit

[0048] The simulation results of the shutdown process of the current limiting protection circuit are as follows: Figure 6 , 7 As shown, Figure 6 This is a schematic diagram of the simulation results for limited flow control. Figure 7 This is a schematic diagram of the simulation results when the infinite current is controlled. The simulation is performed by adjusting the driving resistance , , To cause uneven branch current. Among them, I1, I2, and I3 are the currents flowing through the three branches of the current limiting protection circuit.

[0049] pass Figure 7 It can be seen that when the driving resistor , , When they are not equal, the currents distributed among the three branches will deviate. During the shutdown process, J1 is shut down first, resulting in current phase change. The current distributed by J1 will be smaller than the current distributed by J2. Figure 6 It can be seen that after adding current limiting control, the shutdown speed of J1 slows down and the current unevenness is greatly reduced, which verifies the feasibility of the current limiting control method proposed in this paper.

[0050] like Figure 8 The flowchart of a control method of a current limiting protection circuit of a DC solid-state circuit breaker provided by an embodiment of the present invention is shown, and the method includes: Step S11, if a short circuit fault occurs in the line, in the first stage, the currents of the first branch where the first power switch is located, the second branch where the second power switch is located, and the third branch where the third power switch is located are controlled to increase, and the currents of the three branches are equal.

[0051] In the embodiment of the present invention, the DC system of the DC solid-state circuit breaker operates normally, and the line operating current I ratedIf it is within the safety threshold range, SSCB operation will not be triggered.

[0052] If a short circuit occurs in the line, the current in the line rises rapidly, and the first branch where the first power switch J1 is located, the second branch where the second power switch J2 is located, and the second branch where the third power switch J3 is located evenly share the line fault current. The currents in the first branch, the second branch, and the third branch are equal.

[0053] Step S12, in the second stage, after the current of the three branches rises to the current threshold, the gates of the first power switch, the second power switch and the third power switch receive the first control signal, the second control signal and the third control signal indicating shutdown through the first drive resistor, the second drive resistor and the third drive resistor respectively.

[0054] In the second stage, when the short-circuit current reaches the preset threshold value I th After that, the driving circuit 15 sends a first control signal V indicating shutdown to the gate of the first power switch J1, the gate of the second power switch J2, and the gate of the third power switch J3 respectively. GS1 and the second control signal V GS2 and the third control signal V GS3 . The gate-source voltage of the first power switch J1, the second power switch J2 and the third power switch J3 begins to drop. Since the gate-source voltage of the first power switch J1, the second power switch J2 and the third power switch J3 does not reach the turn-off threshold voltage at this time, the SSCB does not turn off the fault current, and the parallel branch currents are the same. Therefore, the outputs of the first comparator U1, the second comparator U2 and the third comparator U32 are 0, and the first switch tube Q1, the second switch tube Q2 and the third switch tube Q3 are controlled to be turned off. The first capacitor C1, the second capacitor C2 and the third capacitor C3 on the driving side are not connected to the corresponding circuit, and the gate-source side parasitic capacitances Cgs1, Cgs2 and Cgs3 of the first power switch J1, the second power switch J2 and the third power switch J3 are respectively discharged through the corresponding branch driving circuit.

[0055] Step S13, in the third stage, if the first driving resistor is the smallest among the first driving resistor, the second driving resistor, and the third driving resistor, the gate-source voltage of the first power switch is controlled to drop fastest.

[0056] Assuming the driving resistance , so the gate-source voltage of the first power switch Falling faster than the gate-source voltage of the second power switch and the gate-source voltage of the third power switch The gate-source voltage of the first power switch The decline rate is the fastest, C gs1 Charging stop, C gd1 Start charging.

[0057] Step S14, in the fourth stage, the gate-source voltage of the first power switch first reaches the Miller platform voltage, the first power switch is controlled to start to shut down, the current of the first branch starts to decrease, the current is switched, the currents of the second branch and the third branch increase, the current of the first branch is lower than the average current of the first branch, the second branch and the third branch, the first current limiting circuit is controlled to work, a discharge loop is provided for the gate-source voltage of the first power switch, and the shutdown speed of the first power switch is slowed down.

[0058] In the fourth stage, the gate-source voltage of the first power switch J1 is The Miller platform voltage is reached first, and the first power switch J1 starts to turn off. The current flowing through the first branch where the first power switch J1 is located is The current starts to decrease, the current changes phase, and the current in the second branch and the current of the third branch At this time, the current of the first branch is lower than the average current of the first branch, the second branch and the third branch, the first current limiting circuit is controlled to work, the first comparator U1 outputs a low level, and the first switch tube Q1 is controlled to be turned on. At this time, the first capacitor C1 is connected to both sides of the gate source of the first power switch J1 to provide a discharge circuit for the gate capacitor, thereby slowing down the turn-off speed of the first power switch J1.

[0059] Step S15, in the fifth stage, the Miller platform of the first power switch ends, the current of the first branch is less than the average current, the first current limiting circuit is connected between the gate and source of the first power switch, and the shutdown speed of the first power switch is controlled to slow down until the gate-source voltage of the first power switch reaches the preset shutdown voltage.

[0060] In the fifth stage, the Miller platform of the first power switch J1 ends, C gd1 Charging is completed, C gs1 Continue charging. Since the current of the first branch where the first power switch J1 is located is lower than the average current, the first comparator U1 of the first branch where the first power switch J1 is located outputs a low level, and the first capacitor C1 on the driving side of the first power switch J1 is connected. At this time, the first capacitor C1 is connected to both sides of the gate source of the first power switch J1 to provide a discharge loop for the gate capacitor, slowing down the turn-off speed of the first power switch J1 until the gate-source voltage of the first power switch J1 reaches the preset turn-off voltage, i.e., -15V.

[0061] The embodiment of the present invention effectively increases the capacity of the SSCB by connecting SiC JFETs in parallel; and compared with the topology structure using a passive current limiting control method, the addition of active devices greatly reduces the current overshoot of the parallel switch devices. When a short circuit fault occurs, the connection and disconnection of the drive side capacitor of the switch device is achieved through a closed-loop control method, thereby adjusting the turn-off speed of the switch device, slowing down the current change rate of the device with a faster turn-off speed, and limiting the current overshoot of the switch device.

[0062] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0063] The above is only a partial implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A current limiting protection circuit for a DC solid-state circuit breaker, characterized in that: The current limiting protection circuit of the DC solid-state circuit breaker includes: a first current limiting circuit, a second current limiting circuit, a third current limiting circuit, a first driving resistor, a second driving resistor, a third driving resistor, a first power switch, a second power switch, a third power switch, a first sampling module, a second sampling module and a third sampling module; The gate of the first power switch is connected to a first control signal through the first driving resistor, the gate of the second power switch is connected to a second control signal through the second driving resistor, and the gate of the third power switch is connected to a third control signal through the third driving resistor. The drain of the first power switch, the drain of the second power switch, and the drain of the third power switch are connected to the input end, and the source of the first power switch, the source of the second power switch, and the source of the third power switch are connected to the output end through the first sampling module, the second sampling module, and the third sampling module, respectively; the first current limiting circuit is connected to the first sampling module, the gate and source of the first power switch, and is used to compare the sampled voltage output by the first sampling module with the reference voltage. The second current limiting module is connected to the second sampling module and the gate and source of the second power switch, and is used to compare the sampled voltage output by the second sampling module with the reference voltage, and to slow down the current shutdown speed of the branch where the second power switch is located according to the comparison result; the third current limiting module is connected to the third sampling module and the gate and source of the third power switch, and is used to compare the sampled voltage output by the third sampling module with the reference voltage, and to slow down the current shutdown speed of the branch where the third power switch is located according to the comparison result, and the reference voltage is the arithmetic mean of the sampled voltages output by the first sampling module, the second sampling module and the third sampling module.

2. The current limiting protection circuit according to claim 1, characterized in that: The first current limiting circuit includes: a first comparator, a first switch tube and a first capacitor; the non-inverting input end of the first comparator is connected to the first sampling module, the inverting input end is connected to the reference voltage, the output end of the first comparator is connected to the first end of the first switch tube, the second end of the first switch tube is connected to the gate of the first power switch through the first capacitor, and the third end of the first switch tube is connected to the source of the first power switch.

3. The current limiting protection circuit according to claim 2, characterized in that: The second current limiting circuit includes: a second comparator, a second switch tube and a second capacitor; the non-inverting input end of the second comparator is connected to the second sampling module, the inverting input end is connected to the reference voltage, the output end of the second comparator is connected to the first end of the second switch tube, the second end of the second switch tube is connected to the gate of the second power switch through the second capacitor, and the third end of the second switch tube is connected to the source of the second power switch.

4. The current limiting protection circuit according to claim 3, characterized in that: The third current limiting circuit includes: a third comparator, a third switch tube and a third capacitor; the non-inverting input end of the third comparator is connected to the third sampling module, the inverting input end is connected to the reference voltage, the output end of the third comparator is connected to the first end of the third switch tube, the second end of the third switch tube is connected to the gate of the third power switch through the third capacitor, and the third end of the third switch tube is connected to the source of the third power switch.

5. The current limiting protection circuit according to claim 4, characterized in that: The first switch tube, the second switch tube and the third switch tube are P-MOSFETs, with a first end being a gate, a second end being a drain, and a third end being a source.

6. The current limiting protection circuit according to claim 5, characterized in that: When a short circuit fault occurs in the solid-state circuit breaker line, if the current of the first branch where the first power switch is located is lower than the average current of the first branch, the second branch and the third branch, the first comparator outputs a low level to drive the first switch tube to turn on, and the first capacitor is connected between the gate and the source of the first power switch to provide a discharge circuit for the gate capacitor of the first power switch, thereby slowing down the turn-off speed of the first power switch; If the current of the second branch where the second power switch is located is lower than the average current, the second comparator outputs a low level to drive the second switch tube to turn on, and the second capacitor is connected between the gate and the source of the second power switch to provide a discharge loop for the gate capacitor of the second power switch, thereby slowing down the turn-off speed of the second power switch; If the current of the third branch where the third power switch is located is lower than the average current, the third comparator outputs a low level to drive the third switch tube to turn on, and the third capacitor is connected between the gate and source of the third power switch to provide a discharge loop for the gate capacitor of the third power switch, thereby slowing down the shutdown speed of the third power switch.

7. The current limiting protection circuit according to claim 1, characterized in that: The current limiting protection circuit also includes a reference voltage generating circuit, which includes a fourth comparator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; the non-inverting input terminal of the fourth comparator is connected to the sampled voltage sampled and output by the first sampling module through the fifth resistor, is connected to the sampled voltage sampled and output by the second sampling module through the sixth resistor, is connected to the sampled voltage sampled and output by the third sampling module through the seventh resistor, and is also grounded through the eighth resistor; the inverting input terminal of the fourth comparator is grounded through the ninth resistor, and is connected to the output terminal of the fourth comparator through the tenth resistor, and the output terminal of the fourth comparator outputs a reference voltage to the first current limiting circuit, the second current limiting circuit and the third current limiting circuit.

8. A method for controlling a current limiting protection circuit of a DC solid-state circuit breaker according to any one of claims 1 to 7, characterized in that: The control method comprises: If a short circuit fault occurs in the line, in the first stage, the currents of the first branch where the first power switch is located, the second branch where the second power switch is located, and the third branch where the third power switch is located are controlled to increase, and the currents of the three branches are equal; In the second stage, after the currents of the three branches rise to the current threshold, the gates of the first power switch, the second power switch and the third power switch receive the first control signal, the second control signal and the third control signal indicating shutdown through the first drive resistor, the second drive resistor and the third drive resistor respectively; In the third stage, if the first driving resistor is the smallest among the first driving resistor, the second driving resistor, and the third driving resistor, the gate-source voltage of the first power switch is controlled to drop fastest; In the fourth stage, the gate-source voltage of the first power switch reaches the Miller platform voltage first, the first power switch is controlled to start turning off, the current of the first branch starts to decrease, the current phase is changed, the current of the second branch and the third branch increases, the current of the first branch is lower than the average current of the first branch, the second branch and the third branch, the first current limiting circuit is controlled to work, a discharge loop is provided for the gate-source voltage of the first power switch, and the turn-off speed of the first power switch is slowed down; In the fifth stage, the Miller platform of the first power switch ends, the current of the first branch is less than the average current, and the first current limiting circuit is connected between the gate and source of the first power switch to control the shutdown speed of the first power switch to slow down until the gate-source voltage of the first power switch reaches a preset shutdown voltage.

9. A DC solid-state circuit breaker, characterized in that: The DC solid-state circuit breaker comprises: a solid-state switch, a sampling module, an isolation unit, a controller, a drive circuit and an energy absorption circuit, wherein the solid-state switch is specifically a current limiting protection circuit as described in any one of claims 1 to 7; The solid-state switch is connected in series to the DC bus, the energy absorption circuit is connected in parallel to both ends of the solid-state switch, the sampling module is connected to the DC bus and the isolation unit, the controller is connected to the isolation unit and the drive circuit, and the drive circuit is connected to the solid-state switch.

10. The DC solid-state circuit breaker according to claim 9, characterized in that: The energy absorption circuit includes: a varistor, a fourth capacitor and a fourth resistor; the varistor is connected in parallel at both ends of the solid-state switch, and a branch formed by the fourth capacitor and the fourth resistor being connected in series is connected in parallel at both ends of the solid-state switch.

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