Compilation processing method and device for optimizing multiplication function execution

Abstract

The invention provides a compilation processing method for optimizing multiplication function execution. The compilation processing method is applied to a compiler comprising a front-end module and a rear-end module. The front-end module converts a large-number multiplication function called in the high-level language code into an intermediate expression IR code through a preset compiling template; the IR code indicates that the segment multiplication functions are called for multiple times, and results of the segment multiplication functions are accumulated; wherein each segment multiplication function is used for executing multiplication operation of two data segments which are obtained by segmenting and dividing parameters of the large number multiplication function and have preset lengths. The back-end module converts the segment multiplication function in the IR code into hardware instructions suitable for execution by the accelerator. By means of the framework of the compiler, parallel optimization of the rear end and advanced parameter decoupling of the front end can be achieved, and therefore automatic generation of optimized large number multiplication codes suitable for various environments can be achieved through a compiling template.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the field of computer application technology, and more particularly, to a compilation processing method and device for optimizing the execution of a multiplication function. Background Art

[0002] With the development of data privacy technology, more and more privacy protection technologies are widely used. In privacy protection technology, more encryption operations need to be performed, and encryption operations generally use at least 2048-bit keys to protect security. This means that each encryption operation involves multiple large number multiplications.

[0003] For large number multiplication, the prior art lacks an effective solution that can be executed by an accelerator device. Summary of the invention

[0004] In view of this, one or more embodiments of the present specification provide a compilation processing method and apparatus for optimizing the execution of a multiplication function.

[0005] According to a first aspect of one or more embodiments of this specification, a compilation processing method for optimizing the execution of a multiplication function is proposed, which is applied to a compiler, wherein the compiler includes a front-end module and a back-end module; the method includes:

[0006] The front-end module extracts a large number multiplication function from a high-level language code, and converts the large number multiplication function into an intermediate expression IR code according to a preset compilation template; the IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function;

[0007] The back-end module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

[0008] According to a second aspect of one or more embodiments of this specification, a compilation processing device for optimizing the execution of a multiplication function is provided, which is applied to a compiler, and the device includes:

[0009] A front-end module is used to extract a large number multiplication function from a high-level language code, and convert the large number multiplication function into an intermediate expression IR code according to a preset compilation template; the IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function;

[0010] The back-end module is used to convert the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

[0011] According to a third aspect of the embodiments of this specification, a computer-readable storage medium is provided, on which computer instructions are stored. When the instructions are executed by a processor, the compilation processing method for optimizing the execution of a multiplication function as described in the first aspect of the embodiments of this specification is implemented.

[0012] According to a fourth aspect of an embodiment of this specification, a computer device is provided, the computer device comprising:

[0013] processor;

[0014] a memory for storing processor-executable instructions;

[0015] The processor executes the executable instructions to implement the compilation processing method for optimizing the execution of the multiplication function as described in the first aspect of the embodiment of this specification.

[0016] According to a fifth aspect of the embodiments of this specification, a computer program product is provided, which, when executed by a processor, implements the compilation processing method for optimizing the execution of a multiplication function as described in the first aspect of the embodiments of this specification.

[0017] The present specification provides a compilation processing method for optimizing the execution of a multiplication function, which is applied to a compiler including a front-end module and a back-end module. The front-end module converts a large number multiplication function called in a high-level language code into an intermediate representation (IR) code through a preset compilation template; the IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated; wherein each segment multiplication function is used to perform a multiplication operation of two data segments of a preset length obtained by segmenting the parameters of the large number multiplication function. The back-end module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

[0018] In the above method, the large number multiplication operation in the high-level language is encapsulated as a function that can be called directly, and the segment multiplication operation is encapsulated in the segment multiplication function through the IR based on the segmented integer multiplication. The large number multiplication in the high-level language is encapsulated in a high-level language function that is independent of various high-level parameters, and the back-end segment multiplication is implemented based on the parameterized hardware instructions suitable for the accelerator core converted from the segment multiplication function. Through the framework of the above compiler, the parallel optimization of the back-end and the decoupling of the high-level parameters of the front-end can be realized, so that the compilation template can be used to realize the automatic generation of optimized large number multiplication code suitable for various environments.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0021] Figure 1 It is a schematic diagram of a compiler shown in this specification according to an exemplary embodiment.

[0022] Figure 2 The flowchart of a compiling method for optimizing the execution of a multiplication function is shown in this specification according to an exemplary embodiment.

[0023] Figure 3 It is a schematic diagram of a calculation graph shown in this specification.

[0024] Figure 4 It is a schematic diagram of another computational graph shown in this specification.

[0025] Figure 5 It is a schematic diagram of another calculation graph shown in this specification.

[0026] Figure 6 It is a block diagram of a compiling processing device for optimizing the execution of a multiplication function according to an exemplary embodiment of the present specification.

[0027] Figure 7 It is a hardware structure diagram of a computer device shown in this specification according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of this specification. Instead, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0029] It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may be combined into a single step for description in other embodiments.

[0030] In order to ensure security, encryption algorithms generally require the use of a key of at least 2048 bits. During the encryption process, due to the limitation of the number of key bits, the large integer multiplication used for key calculations in the encryption process requires at least 4096 32-bit integer multiplication instructions, which will be referred to as large number multiplication in the following text. The complexity of the encryption process means that the encryption process may involve thousands of large number multiplications, which makes the encryption process slower.

[0031] In the large number multiplication in high-level languages, the large number multiplication algorithm can be adapted to parameters of different lengths by adjusting the loop bounds, and by changing the control flow to adapt to different multiplication variants (such as eliminating redundant calculations in square operations). That is, optimization at the high-level language algorithm level can be performed. In addition, in order to speed up the encryption process in the related art, an accelerator (such as GPU, FPGA, etc.) that is good at parallel integer processing is generally used to accelerate the encryption process. In order to better play the performance advantages of the accelerator, the integer multiplication code executed by the accelerator device can be manually adjusted to balance various factors that affect the speed of parallel processing (such as chip resource usage, communication costs, workload balance, memory access patterns, etc.).

[0032] However, if you need to optimize both high-level languages ​​and parallel operations at the same time, you will encounter difficulties. For example, an optimization that is effective in one environment may not perform well in another environment. Therefore, it is necessary to customize different environments for different bit lengths, different accelerator devices, and different combinations of multiplication variants, which will consume more optimization time.

[0033] Based on this, this specification provides a compilation processing method for optimizing the execution of multiplication functions and a corresponding compiler framework. The compiler framework includes a front-end module and a back-end module. The overall architecture of the compiler is as follows: Figure 1 shown. Figure 1 The solid-line boxes represent the compiler or modules in the compiler, and the dotted-line boxes represent the code.

[0034] like Figure 1As shown, the front-end module converts the large number multiplication function called in the high-level language code into an intermediate representation (IR) code through a preset compilation template; the IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated. Exemplarily, in the following, the segment multiplication function is represented as UNIT_MUL. Each segment multiplication function UNIT_MUL is used to perform the multiplication operation of two data segments of a preset length obtained by segmenting the parameters of the large number multiplication function. The back-end module converts the segment multiplication function in the IR code into a parameterized hardware platform instruction code suitable for the accelerator core according to the specification parameter information of the accelerator. In the scenario of the GPU accelerator, that is, the kernel function that CUDA can process, the kernel function is a function that can be executed by the accelerator processing core. In the FPGA accelerator scenario, it can be an assembly, machine code, and other hardware instruction codes that the FPGA IP can receive. In the back-end processing, the back-end module provides optimized execution and implementation of the segment multiplication function based on the hardware characteristics of the accelerator and the multi-threaded parallel execution capability of the accelerator.

[0035] In the above method, the large number multiplication operation is encapsulated as a function that can be called directly in the high-level language, and the segment multiplication operation is encapsulated in the segment multiplication function through the IR based on the segmented integer multiplication, which is independent of the high-level parameters. The back-end module only performs parallel optimization on the implementation of the segment multiplication function itself. Through the framework of the above compiler, the parallel optimization of the back-end and the decoupling of the high-level parameters of the front-end can be realized, so that the compilation template can be used to realize the automatic generation of large number multiplication optimization code suitable for various environments.

[0036] Next, a compilation processing method for optimizing the execution of a multiplication function shown in this specification will be described.

[0037] The method shown in this specification is applied to a compiler, and the compiler includes a front-end module and a back-end module. Through the cooperation of the front-end module and the back-end module, the conversion from high-level language to machine code can be achieved. The machine code can be a code that can be directly executed by an accelerator device. The accelerator device can be a field programmable gate array (FieldProgrammable Gate Array, FPGA), a graphics processing unit (graphics processing unit, GPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), etc.

[0038] The method of this specification is an optimization method proposed for the characteristics of large number multiplication used in cryptography (such as the length of large numbers, the modulus in the calculation process, etc.). It can be understood that if large number multiplication in other fields has similar calculation characteristics to the large number multiplication commonly used in the cryptography field, the method shown in this specification can also be used to optimize large number multiplication.

[0039] like Figure 2 As shown, Figure 2 1 is a flowchart of a compilation processing method for optimizing the execution of a multiplication function shown in this specification, including:

[0040] Step 201: The front-end module extracts a large number multiplication function from a high-level language code, and converts the large number multiplication function into an IR code according to a preset compilation template.

[0041] The IR code indicates that the segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of preset lengths, and the data segments are obtained by segmenting the parameters of the large number multiplication function.

[0042] The compiler in this manual adopts a front-end-IR-back-end structure. The front-end module is responsible for converting the large number multiplication function code in the high-level language into IR code.

[0043] The large number multiplication function is a function that encapsulates the large number multiplication operation in the high-level language code, for example, it is recorded as Mul(). The high-level language is a programming language that is closer to a natural language, such as C language. Compared with the method in the related art, in the method of this specification, there is no need to use a high-level language to write the implementation code of large number multiplication. In the program code of the high-level language, the large number multiplication function Mul(A, B) can be directly called to realize the multiplication of two large integers. The parameters in the large number multiplication function may include two integers A and B that need to be multiplied.

[0044] The compilation template is a pre-written IR code that can be used for the large number multiplication function. The compilation template can directly and easily convert the large number multiplication function of the high-level language into the IR code.

[0045] Among them, for the specific length of the data segment Ns, the above-mentioned preset length can be determined according to the specification parameter information of the accelerator. Since different accelerator devices have different most suitable operation bit widths when performing parallel operations, the number of parallel calculations that can be processed simultaneously is different. Therefore, the specific length of the data segment can be determined according to the specification parameter information of different accelerator devices to achieve a better acceleration effect.

[0046] The integer multiplication process reflected in the IR code can be based on the following logic: first, the integers A and B to be calculated by the large number multiplication function Mul can be divided into multiple data segments, SegA[i] and SegB[j], and then the segment multiplication between the data segments from the two integers is used to obtain the segment multiplication result, and the segment multiplication results are accumulated to obtain the final integer multiplication result. The specific implementation of the segment multiplication is encapsulated in the segment multiplication function UNIT_MUL, which facilitates the backend to independently optimize the parallelization of the segment multiplication.

[0047] As for how to use the accumulation of segment multiplication to obtain the final calculation result, you can use simulated vertical multiplication, divide and conquer method, etc. For example, when using the implementation logic of simulated vertical multiplication, you can use the nesting of double loops to implement large number multiplication. Specifically, the outer loop traverses each segment pair of the integer value of the large number multiplication parameter, and the inner loop accumulates some intermediate results calculated by the segment multiplication function, and then the multiplication calculation can be completed by simulating vertical multiplication.

[0048] Through the above method, the large number multiplication function of the high-level language can be converted into a series of segment multiplication function calls, so that the front-end can manage various high-level parameters without having to worry about the complex parallelization strategy implemented by the back-end. The high-level parameters mentioned here are the variables defined by the specific cryptographic algorithm when the high-level language code of the application layer is writing the cryptographic code.

[0049] Furthermore, in addition to taking the large number multiplication function as input, the front end can also identify the bit length of the integer in the large number multiplication function parameter, and take the bit length of the integer as a parameter for input to the front end module. The bit length can affect the number of times the loop is executed. After the bit length is input to the front end module, it can be determined according to the bit length of the integer that the integer needs to be divided into several data segments, thereby generating an IR code that is compatible with the bit length of the integer.

[0050] In addition, in the field of cryptography, the required large number multiplication may not only be the multiplication of two large numbers, but may also utilize various multiplication variants, such as exponential function, Montgomery multiplication, etc. For these multiplication variants, the front end can also further optimize the multiplication variants.

[0051] For example, the front-end module can determine the multiplication variant form corresponding to the large number multiplication function according to the encryption method implemented by calling the large number multiplication function in the high-level language code; and determine the compilation template corresponding to the multiplication variant form from the template library as the preset compilation template.

[0052] Since the multiplication variant used by each encryption algorithm is fixed, the front end can determine the specific multiplication variant that the current large number multiplication code needs to implement based on the context in the high-level language code, and automatically determine the corresponding compilation template based on the multiplication variant used.

[0053] In addition, in different multiplication variants, the characteristics of different multiplication variants can be used to optimize the compilation templates corresponding to different multiplication variants, so as to reduce the number of segment multiplication functions called in the IR code, thereby reducing the accelerator devices.

[0054] Here we will use power multiplication, Montgomery modular multiplication, and constant multiplication as examples to illustrate the optimizations involved in multiplication variants.

[0055] First, for the multiplication variants with redundant calculations, the redundant calculations can be removed in the IR code.

[0056] For example, when the multiplication variant is power multiplication, the preset coding template indicates that the first data segment and the second data segment of the multiplier are processed by the segment multiplication function, and the obtained result is multiplexed as the result of multiplying the second data segment by the first data segment.

[0057] Specifically, power multiplication can also be called exponential operation. During the operation, power multiplication can be split into several square operations to save redundant operations. For example, if you need to calculate the eighth power of A, you can first calculate the square of A, then calculate the square of the square of A, and so on, until you get the eighth power of A.

[0058] This requires the calculation of square operations. Assume that the two data to be calculated for large number multiplication are A and B, and the two data are split into multiple data segments, marked as segA[i] and segB[i]. For the square operation, segA[i] and segB[i] are the same. Correspondingly, segA[i]*segB[j] is equivalent to segA[j]*segB[i]. Therefore, the segment multiplication results of the data segments can be reused, that is, the calculation results of the first data segment and the second data segment are reused as the result of multiplying the second data segment by the first data segment, so as to reduce the call of hardware instructions and improve the calculation efficiency of the acceleration device.

[0059] For another example, in the case where the multiplication variant is Montgomery modular multiplication, the multiplication variant is Montgomery modular multiplication, and the preset compilation template indicates that the segment multiplication function is only executed on a specific number of bits in the parameters of the large number multiplication, and the specific number of bits is the first several high bits or the first several low bits.

[0060] For Montgomery modular multiplication, Montgomery modular multiplication generally includes multiplication of only low bits (Multiply-low) and multiplication of only high bits (Multiply-high). For example, when two 8-bit numbers are multiplied, only the low bits are multiplied to get the low 8 bits of the result, and only the high bits are multiplied to get the high 8 bits of the result. For these multiplications, the segment multiplication that is useless for the result can be omitted.

[0061] Specifically, for multiplication that only calculates the low-order bits, the result is the accumulation of several segment multiplication function operation results that affect the low-order bits, that is, the accumulation of several low-order operation results of the parameters. For other segment multiplication functions, they can be removed from the IR code. For example, if the operation result obtained by multiplying the first data segment and the second data segment is used to calculate the accumulated result of the high-order bits, then the segment multiplication function for multiplying the first data segment and the second data segment can be omitted in the IR code.

[0062] For multiplication that only calculates high bits, since the carry may affect the operation results of the high bits in the result, we can analyze whether the low-bit operation will produce a carry that affects the high-bit operation result based on the number of 0s in the two parameters involved in the large number multiplication function, and based on this, only calculate the segment multiplication function used to accumulate the high bits in the result.

[0063] Secondly, in the field of cryptography, some parameters involved in large number multiplication are fixed values. Therefore, these fixed constant values ​​can be written into the corresponding IR code or stored in constant memory to reduce data access of accelerator devices and reduce the use of on-chip storage space for storage cache.

[0064] Through the above compilation template and various parameters that may be required by the front-end module, IR codes suitable for the bit length of the integer and the multiplication variant used can be generated.

[0065] In addition, the functions implemented by each module of the compiler in this application can be integrated into a multi-level intermediate representation (MLIR) as a dialect. MLIR provides an extensible compiler framework. Dialect is a variant of an IR language that allows new operations, attributes, and types to be defined. By integrating the above compiler as a dialect in MLIR, high-level parameters and back-end architecture details can be decoupled more efficiently to achieve the purpose of the method of this specification.

[0066] Step 203: The backend module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

[0067] After obtaining the IR code, the IR code can be converted into machine code that can be executed by the accelerator device. For the segment multiplication function, it needs to be converted into hardware instructions suitable for accelerator execution, such as a kernel function that can be directly executed in the CUDA GPU acceleration environment. When the accelerator is an FPGA, it can be converted into assembly instruction code that can be directly executed by the FPGA. The above hardware instructions can be parameterized. For example, under the GPU platform, various parameters in the kernel function can be adjusted to adapt to various hardware. For example, the workload size of each thread can be adjusted, the number of threads working in parallel can be adjusted, and so on.

[0068] The back-end module can convert the segment multiplication function into a hardware instruction according to the specification parameter information of the accelerator, and the hardware instruction is transmitted through the first number N T Threads are executed in parallel to perform operations.

[0069] Specifically, hardware instructions suitable for each accelerator can be generated according to the specification parameter information of each accelerator. Moreover, the generated hardware instructions fully utilize the parallel capability of the accelerator device. T threads execute in parallel. In addition, N T The size of can be determined according to the specification parameter information of the accelerator device. In the case where the accelerator is a GPU, the specification parameter information of the accelerator can be obtained through GPU info.

[0070] In addition to the above methods, hardware instructions can also be optimized during the hardware platform code generation process in the backend to achieve better parallel effects and improve execution efficiency. The optimization of hardware instructions will be explained below.

[0071] First, optimize the parallelization strategy.

[0072] like Figure 3 As shown, Figure 3 It is a schematic diagram of a computational graph. The computational graph can represent the execution of hardware instructions, and the factors affecting the parallel speed of hardware instructions can be analyzed through the computational graph. Figure 3 In the example, each aibj represents a word multiplication operation. A word can be 32-bit data, and the specific word length can also change with the specification parameter information of the accelerator device. The data segments of the two parameters of the large number multiplication function are A and B, ai is each word in the specific data segment of parameter A, and bj represents each word in the specific data segment of parameter B.

[0073] In addition, the arrows between the aibj elements represent the accumulation of the intermediate results obtained by the wide-multiply instruction, which represents the data flow during the accumulation process. The yellow outer frame represents the workload of each thread. That is, the area occupied by the parallel work responsible for each thread in the calculation graph. The intersection between the arrow and the yellow frame indicates the need for cross-thread communication.

[0074] Related technologies include Figure 4 The four parallel strategies shown will be combined in the following Figure 4 The computational graph of is used to analyze the four parallel strategies.

[0075] Figure 4 The parallel strategy shown in (a) is that each thread is responsible for a word multiplication operation. This requires more threads, and each thread is allocated some resources, which will lead to more on-chip resources consumption and more communication consumption between threads. Moreover, more threads will bring more initialization consumption, and the smaller workload borne by each thread is not enough to offset the consumption brought by the initialization thread.

[0076] Figure 4 The parallel strategy shown in (b) is: each thread is responsible for calculating a certain bit in the result of the hardware instruction. Although this can reduce the communication between threads, due to the different workloads of different threads, some threads only perform one word multiplication operation, but some threads need to perform more word multiplication operations, and different threads are executed in parallel, this will lead to warp divergence, affecting the resource utilization of the accelerator.

[0077] Figure 4 The parallel strategy shown in (c) is: N T The number is 1, that is, one thread is responsible for the execution of one hardware instruction. Although this can reduce thread bundle divergence, reduce on-chip resource consumption, and reduce communication between threads, it will reduce the level of parallelization and reduce loop unrolling.

[0078] Figure 4 The parallel strategy shown in (d) is: one-bit parallelization strategy. That is, each thread is responsible for calculating one or several rows in the graph ( Figure 4 This approach can balance the above factors, such as the impact of on-chip resource consumption, parallelization level, and communication between threads on computing efficiency.

[0079] In addition, Figure 4 In addition to the parallelization strategy of (d) in the specification, this specification also proposes a two-dimensional parallelization strategy such as Figure 5As shown. In this strategy, each thread is responsible for a rectangular area. The range of this rectangle includes N b1 ×N b2 word multiplication operations. The communication cost between threads is close to N b1 +N b2 According to the mean inequality, when N b1 =N b2 The communication consumption can be minimized. That is, each thread is responsible for a square area, which can achieve better results.

[0080] In other words, Figure 5 The hardware instructions corresponding to the computational graph shown are as follows: T The threads execute the first operation in parallel to obtain several intermediate results respectively; the first operation executed by each thread includes a word multiplication operation of a rectangular range in the calculation diagram, and the accumulation of the word multiplication operation results within the rectangular range; the words involved in the word multiplication operation include a preset number of bytes in the data segment; a single thread performs an accumulation operation of the intermediate results across threads to obtain a segment multiplication result.

[0081] Compared to Figure 4 The scheme in Figure 5 The two-dimensional parallelization strategy shown can further balance various factors that affect parallel speed, such as on-chip resource usage, cross-thread communication consumption, parallelism, workload balance, and memory access pattern. Specifically, the number of threads is compared to Figure 4 The solution (a) in the above example has fewer threads and will not cause excessive resource consumption due to allocating too many threads. It also ensures a certain degree of parallelism. Some data exchanges occur within threads, and some occur between threads. Figure 4 The solution (d) reduces the communication consumption across threads, thereby better balancing the various factors that affect the parallel speed.

[0082] also, Figure 5 In the solution shown, the workloads of different threads can be the same, so that the workloads of different threads can be basically the same, and the problem of thread bundle divergence can be better avoided.

[0083] exist Figure 5 In the scheme shown, N T The size of the data segment is affected by the size of N b1 and N b2 Therefore, the preset length Ns of the data segment can be determined based on the accelerator specification parameter information. b1 =N b2 In the case of , the side length Nb of the workload that is more suitable for each thread is determined according to the accelerator specification parameter information, and then the number of threads assigned to each edge in the calculation graph TPS = Ns / Nb can be calculated. Then NT The size of is the square of TPS.

[0084] Second, carry delay.

[0085] In each word multiplication operation, a carry may be generated, and each accumulation of carries will bring additional cross-thread communication consumption. Therefore, in order to reduce the communication consumption caused by the accumulation of carries, during the execution of hardware instructions, the first operation performed by each thread also includes storing the carry of the word multiplication operation result into the register corresponding to the thread. The accumulation operation includes: a single thread sums the first result of the accumulation of the intermediate results with the carries stored in each register.

[0086] That is, during the word multiplication operation, the carry is first stored in the register without accumulation, and after all accumulations are completed, the carry stored in the register is summed with the first result obtained by accumulation to obtain the final hardware instruction operation result. The accumulation of the carry can be achieved through the warp data shuffle operation.

[0087] Moreover, carries are generally infrequent and small data, so communication-intensive carry propagation can be reduced without consuming more on-chip resources.

[0088] Third, customized storage strategy.

[0089] Specifically, during the execution of the hardware instruction, the data segment is stored in a register, and the intermediate result generated by the word multiplication operation is stored in a shared memory.

[0090] First, considering the irregular access pattern, the data segments can be stored in registers instead of shared memory. This can avoid bank conflicts and non-coalesced memory access caused by storing data in shared memory under irregular access patterns.

[0091] In addition, when storing data segments into registers, the data can be first stored in shared memory, and then the data in shared memory can be stored in registers, which can reduce global memory accesses.

[0092] Secondly, the intermediate results generated by word multiplication can be transferred through shared memory instead of warp shuffle operation. Since the data segments are stored in registers, the intermediate results can be stored in other on-chip resources besides registers, which can balance the usage peaks of various on-chip resources. In addition, when using index transposition, this choice is also necessary due to the complex memory access pattern brought by index transposition.

[0093] Fourth, Index Transposing.

[0094] Different words in the hardware instruction operation result require different numbers of word multiplication results to be accumulated. For example, the last bit of the segment multiplication result may only need to be obtained based on one word multiplication result, while the second to last bit of the segment multiplication result may need to be accumulated by two word multiplication results. The effective allocation of the initial task can avoid thread bundle divergence during the word multiplication process, but it cannot avoid thread bundle divergence during global accumulation. To solve this problem, index transposition is performed before accumulation after the word multiplication is completed.

[0095] Before index transposition, N T Threads are responsible for executing hardware instructions, and each thread is assigned Figure 5 The workload shown in Figure 1 is as follows. After the index is transposed, only Nb threads are responsible for executing hardware instructions, and each thread manages Nb columns of data. Transposing the index can effectively reduce the thread bundle divergence caused by global accumulation.

[0096] Corresponding to the embodiments of the aforementioned method, this specification also provides embodiments of an apparatus and a computer device to which it is applied.

[0097] like Figure 6 As shown, Figure 6 1 is a block diagram of a compiling processing device for optimizing the execution of a multiplication function according to an exemplary embodiment of the present specification, wherein the device is applied to a compiler and includes:

[0098] The front-end module 610 is used to extract a large number multiplication function from a high-level language code, and convert the large number multiplication function into an intermediate expression IR code according to a preset compilation template; the IR code indicates that the segment multiplication function is called multiple times, and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform the multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function;

[0099] The back-end module 620 is used to convert the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

[0100] In an optional embodiment, the front-end module 610 is also used to determine the multiplication variant form corresponding to the large number multiplication function according to the encryption method implemented by calling the large number multiplication function in the high-level language code; and determine the compilation template corresponding to the multiplication variant form from the template library as the preset compilation template.

[0101] In an optional embodiment, the multiplication variant is a power multiplication; the preset coding template indicates that the first data segment and the second data segment of the multiplier are processed using the segment multiplication function, and the obtained result is reused as the result of multiplying the second data segment by the first data segment.

[0102] In an optional embodiment, wherein the multiplication variant is Montgomery modular multiplication, the preset compilation template indicates that the segment multiplication function is performed only on a specific number of bits in the parameters of the large number multiplication, and the specific number of bits is the first several high bits or the first several low bits.

[0103] In an optional embodiment, the preset length is determined according to specification parameter information of the accelerator.

[0104] In an optional embodiment, the back-end module 620, specifically used for the back-end module, converts the segment multiplication function into hardware instructions according to the specification parameter information of the accelerator, and the hardware instructions are implemented by parallel execution of a first number NT of threads.

[0105] In an optional embodiment, the hardware instruction indicates: the NT threads execute the first operation in parallel to obtain several intermediate results respectively; the first operation executed by each thread includes a word multiplication operation of a rectangular range in the calculation diagram, and the accumulation of the word multiplication operation results within the rectangular range; the words involved in the word multiplication operation include a preset number of bytes in the data segment; a single thread performs an accumulation operation of intermediate results across threads to obtain a segment multiplication result.

[0106] In an optional embodiment, the first operation performed by each thread also includes storing the carry of the word multiplication operation result in a register corresponding to the thread; the accumulation operation includes: a single thread sums the first result of the accumulation of the intermediate results with the carry stored in each register.

[0107] In an optional embodiment, during the execution of the hardware instruction, the data segment is stored in a register, and the intermediate result generated by the word multiplication operation is stored in a shared memory.

[0108] The implementation process of the functions and effects of each module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, which will not be repeated here.

[0109] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. A person of ordinary skill in the art can understand and implement it without paying creative labor.

[0110] like Figure 7 As shown, Figure 7 A hardware structure diagram of a computer device used by the above compiler is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0111] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification. The processor implements the above method by running executable instructions.

[0112] The memory 1020 for storing processor executable instructions can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020.

[0113] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0114] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0115] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0116] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0117] The embodiments of the present specification also provide a computer program product, which, when executed by a processor, implements the above-mentioned compilation processing method for optimizing the execution of a multiplication function.

[0118] The embodiments of the present specification also provide a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned compilation processing method for optimizing the execution of a multiplication function is implemented.

[0119] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0120] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0121] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0122] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

Claims

1. A compilation processing method for optimizing the execution of a multiplication function, applied to a compiler, the compiler comprising a front-end module and a back-end module; the method comprising: The front-end module extracts the large number multiplication function from the high-level language code, and converts the large number multiplication function into an intermediate expression IR code according to a preset compilation template; The IR code indicates that a segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function; The back-end module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

2. The method according to claim 1, further comprising: The front-end module determines the multiplication variant form corresponding to the large number multiplication function according to the encryption method implemented by calling the large number multiplication function in the high-level language code; And determine the compilation template corresponding to the multiplication variant form from the template library as the preset compilation template.

3. The method according to claim 2, wherein: The multiplication variant is a power multiplication; the preset coding template indicates that the first data segment and the second data segment of the multiplier are processed by the segment multiplication function, and the obtained result is multiplexed as the result of multiplying the second data segment by the first data segment.

4. The method according to claim 2, wherein: The multiplication variant is Montgomery modular multiplication, and the preset compilation template indicates that the segment multiplication function is only performed on a specific number of bits in the parameters of the large number multiplication, and the specific number of bits is the first several high bits or the first several low bits.

5. The method according to claim 1, wherein: The preset length is determined according to specification parameter information of the accelerator.

6. The method according to claim 1, wherein: The backend module converts the segment multiplication function in the IR code into a hardware instruction suitable for execution by the accelerator, including: The back-end module converts the segment multiplication function into a hardware instruction according to the specification parameter information of the accelerator, and the hardware instruction is transmitted through a first number N T Threads are executed in parallel to perform operations.

7. The method according to claim 6, wherein: The hardware instructions indicate: The N T The threads execute the first operation in parallel to obtain several intermediate results respectively; the first operation executed by each thread includes a word multiplication operation of a rectangular range in the calculation graph and accumulation of word multiplication operation results within the rectangular range; The words involved in the word multiplication operation include a preset number of bytes in the data segment; A single thread performs the accumulation operation of the intermediate results across threads to obtain the segment multiplication result.

8. The method according to claim 7, wherein: The first operation performed by each thread further includes storing the carry of the word multiplication operation result into a register corresponding to the thread; The accumulation operation includes: a single thread sums a first result of the intermediate result accumulation with a carry stored in each register.

9. The method according to claim 7, wherein: During the execution of the hardware instruction, the data segment is stored in a register, and the intermediate result generated by the word multiplication operation is stored in a shared memory.

10. A compiling and processing device for optimizing the execution of a multiplication function, the device comprising: The front-end module is used to extract the large number multiplication function from the high-level language code and convert the large number multiplication function into an intermediate expression IR code according to a preset compilation template; The IR code indicates that a segment multiplication function is called multiple times and the results of each segment multiplication function are accumulated; the segment multiplication function is used to perform multiplication of two data segments of a preset length, and the data segments are obtained by segmenting the parameters of the large number multiplication function; The back-end module is used to convert the segment multiplication function in the IR code into a hardware instruction suitable for execution by an accelerator.

11. A computer program product, wherein when the computer program product is executed by a processor, the computer program product implements the method according to any one of claims 1 to 9.

12. A computer device comprising: processor; a memory for storing processor-executable instructions; The processor implements the method according to any one of claims 1 to 9 by running the executable instructions.

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