A method for optimizing AVX instruction simulation execution based on loop dependency analysis

Abstract

The present invention discloses an AVX instruction simulation execution optimization method based on loop dependency analysis. When an executable file is executed for the first time in a dynamic instruction conversion mode, a jump instruction, a comparison instruction and an increment instruction close to a data read instruction are determined by semantic analysis of the instruction. A single-layer loop body where the data read instruction is located is determined according to a relationship between the instruction address and the operands between the data read instruction and these instructions to determine a prefetch instruction adding mode. Then, an execution exception is introduced in the dynamic instruction conversion process to obtain a prefetch instruction adding mode of the data read instruction in the multi-layer loop body. A prefetch instruction insertion strategy list is formed by the prefetch instruction adding mode and the address of the data read instruction. Subsequently, the executable file can be executed again according to the prefetch instruction insertion strategy list, thereby effectively reducing the instruction conversion and instruction execution time and improving the efficiency of AVX instruction simulation execution.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to an AVX instruction simulation execution optimization method based on loop dependency analysis. Background Art

[0002] AVX (Advanced Vector Extensions) is a SIMD (Single Instruction Multiple Data) instruction set introduced by Intel in its processors, which aims to improve the performance of floating-point operations and integer operations. The AVX instruction set allows the processor to process more data at a time, thereby improving the parallelism and throughput of the processing process. The key features of the AVX instruction set include: the use of larger registers, AVX can use 256-bit or even 512-bit wide YMM registers, which can process more data at a time than the 128-bit wide XMM registers used by the SSE instruction set; operand fusion, AVX instructions can operate on two 128-bit operands at the same time and store the results in a 256-bit register, effectively reducing the number of instructions required and potential delays; mixed precision, AVX supports mixed precision operations, that is, it allows single-precision (32-bit) and double-precision (64-bit) floating-point numbers to be processed in the same instruction. The SIMD instruction set of the ARM64 architecture, commonly known as Neon, also known as Advanced SIMD, is an instruction set extension introduced in the ARMv7 architecture and later versions. It is used to accelerate applications such as multimedia and signal processing that require large amounts of data processing, providing support for high-performance computing.

[0003] In practice, when industrial computing software based on the x86 architecture is efficiently executed on the ARM64 platform, it is necessary to use the ARM64 SIMD instructions to efficiently simulate the execution of AVX instructions. Since AVX instructions support 256-bit or 512-bit data vectors and Neon instructions mainly support 128-bit data vectors, when using Neon instructions to simulate the execution of AVX instructions to process AVX data vectors, they need to be split and reorganized before processing. The existing processing method is mainly to read data directly from the memory to the NEON register on demand and then perform the corresponding operation. However, based on the memory hierarchy of modern processors, there is usually a certain delay in reading data from the memory to the register, especially when reading in a loop, this delay will be significantly amplified, resulting in a significant increase in the instruction conversion process and instruction execution time, further reducing the efficiency of AVX instruction simulation execution. Summary of the invention

[0004] In view of this, the present invention provides an AVX instruction simulation execution optimization method based on circular dependency analysis, which determines the way to add prefetch instructions before data read instructions through circular dependency analysis of data read instructions, thereby realizing efficient simulation execution of AVX instructions.

[0005] The present invention provides an AVX instruction simulation execution optimization method based on loop dependency analysis, which specifically includes the following steps:

[0006] Step 1: If the executable file has a corresponding prefetch instruction insertion strategy list, the execution of the executable file is completed according to the prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is loaded and executed through dynamic instruction conversion;

[0007] Step 2: If the current AVX instruction to be converted is not a data read instruction, convert it into a Neon instruction and then execute step 9; otherwise, record the current AVX instruction to be converted as the first AVX instruction, and record the address of the first AVX instruction as the first AVX instruction address; obtain the instructions of the first AVX instruction forward by a set number to form a first instruction set, and perform pre-conversion on the instructions in the first instruction set to obtain the syntax and semantics of the instructions;

[0008] Step 3: According to the obtained syntax and semantics, find the jump instruction closest to the address of the first AVX instruction. If it exists, execute step 4; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 9;

[0009] Step 4, record the jump instruction as the first jump instruction, record its address as the first jump instruction address, record the target address set as the first target address, if the first target address is less than the first AVX instruction address, execute step 5; if the first target address is greater than the first AVX instruction address, delete the first jump instruction from the first instruction set and execute step 8;

[0010] Step 5: Form a second instruction set from the instructions between the first jump instruction address and the first AVX instruction address. If the second instruction set contains comparison and increment or decrement instructions with data in the register as operands, the first jump instruction is a loop jump instruction and step 6 is executed; otherwise, the first AVX instruction is dynamically converted into a Neon instruction and step 9 is executed.

[0011] Step 6: record the data in the register corresponding to the first AVX instruction address as the first data address, and form a third instruction set from the instructions from the first target address to the first jump instruction address. If there is an instruction in the third instruction set that uses an immediate number to modify the first data address, then record the immediate number in the instruction closest to the first AVX instruction address as the data read step length, record the address of the instruction as the modified instruction address, and execute step 7; otherwise, dynamically convert the first AVX instruction into a Neon instruction and execute step 9;

[0012] Step 7, adding the correspondence between the added prefetch instruction name, address and operand and the first AVX instruction address to the prefetch instruction insertion strategy list, and then executing step 9;

[0013] Step 8: If there is a jump instruction in the first instruction set, execute step 3; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 9;

[0014] Step 9: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process.

[0015] Further, the set number is the number of instructions between the end instruction and the first AVX instruction, and the end instruction is determined by reverse analysis.

[0016] Furthermore, the set number is a smaller value between the number of instructions existing between the end instruction and the first AVX instruction and an empirical value.

[0017] Furthermore, the experience value is 200.

[0018] Furthermore, in step 6, the immediate value in the instruction closest to the first AVX instruction address is recorded as the data read step length, and the address of the instruction is recorded as the modified instruction address, and then the following is executed:

[0019] Step 6.1, forming a fourth instruction set from the first jump instruction address to the forward set number of instructions, if there is no loop jump instruction in the fourth instruction set, executing step 7; otherwise, executing step 6.2;

[0020] Step 6.2, in the memory area pointed to by the first data address, traverse the memory pages starting from the first memory page, modify the memory pages with readable attributes to unreadable, and form an instruction memory area mapping table based on the correspondence between the first AVX instruction address and the first data address; convert the first AVX instruction into a Neon instruction and execute the executable file sequentially, when a memory access exception occurs, for the exception address existing in the instruction memory area mapping table, record the exception address, clear the exception and resume the execution of the executable file; if the multiple exception addresses corresponding to the same first AVX instruction address are an arithmetic progression, use the address before the exception address as the address of the prefetch instruction, and use the memory page corresponding to the exception address as the operand of the prefetch instruction, and execute step 7.

[0021] Furthermore, the method of adding the correspondence between the added prefetch instruction name, address and operand and the first AVX instruction address to the prefetch instruction insertion strategy list in step 7 is:

[0022] If the modified instruction address is less than the first AVX instruction address, a prefetch instruction is added between the first AVX instruction address and the first jump instruction address, and the operand of the prefetch instruction is the sum of the first data address and the data reading step; if the modified instruction address is greater than the first AVX instruction address, a prefetch instruction is added between the modified instruction address and the first jump instruction address, and the operand of the prefetch instruction is the current first data address.

[0023] Furthermore, the data reading instruction in step 2 is vmovaps, vmovups, vmovapd, vmovupd, vbroadcastss or vbroadcastsd. Beneficial Effects

[0024] When the present invention executes the executable file for the first time in the dynamic instruction conversion mode, the jump instruction, comparison instruction and self-increment instruction close to the data reading instruction are determined by semantic analysis of the instruction, and the single-layer loop body where the data reading instruction is located is determined according to the relationship between the instruction address and the operand between the data reading instruction and these instructions to determine the adding mode of the prefetch instruction, and then the prefetch instruction adding mode of the data reading instruction in the multi-layer loop body is obtained by introducing an execution exception in the dynamic instruction conversion process, and a prefetch instruction insertion strategy list is formed by the prefetch instruction adding mode and the address of the data reading instruction. Subsequently, the executable file can be executed again according to the prefetch instruction insertion strategy list, which effectively reduces the time of instruction conversion and instruction execution and improves the efficiency of AVX instruction simulation execution. DETAILED DESCRIPTION

[0025] The present invention is described in detail with reference to the following embodiments.

[0026] In order to solve the problem of delay in reading data from memory to registers, existing processors provide a data prefetch mechanism, which can load data from memory to cache in advance, so that it can be retrieved faster when the data is actually used later, thus reducing waiting time. Therefore, when simulating the execution of AVX instructions on the ARM64 architecture, if the AVX data vectors can be prefetched to the cache in advance before data segmentation, the overall efficiency can be improved when the data is subsequently segmented and loaded into NEON registers.

[0027] The present invention provides an AVX instruction simulation execution optimization method based on loop dependency analysis, the core idea of ​​which is: when an executable file is executed for the first time in a dynamic instruction conversion mode, the jump instructions, comparison instructions and self-increment instructions close to the data reading instructions are determined by semantic analysis of the instructions, and the single-layer loop body where the data reading instructions are located is determined according to the relationship between the instruction addresses and operands between the data reading instructions and these instructions to determine the adding method of the prefetch instructions, and then the prefetch instruction adding method of the data reading instructions in the multi-layer loop body is obtained by introducing an execution exception in the dynamic instruction conversion process, and a prefetch instruction insertion strategy list is formed by the prefetch instruction adding method and the address of the data reading instruction, and the executable file can be executed again later according to the prefetch instruction insertion strategy list.

[0028] The present invention provides an AVX instruction simulation execution optimization method based on loop dependency analysis, which specifically includes the following steps:

[0029] Step 1: If the executable file has a corresponding prefetch instruction insertion strategy list, the execution of the executable file is completed by dynamic instruction conversion loading and execution according to the prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is executed by dynamic instruction conversion loading and execution.

[0030] Step 2: If the current AVX instruction to be converted is not a data read instruction, convert it to a Neon instruction and then execute step 11; otherwise, record the current AVX instruction to be converted as the first AVX instruction, and record the address of the first AVX instruction as the first AVX instruction address; obtain the instructions of the first AVX instruction forward by a set number to form a first instruction set, and perform a pre-conversion on the instructions in the first instruction set to obtain the syntax and semantics of the instructions. Wherein, obtaining the instructions of the first AVX instruction forward by a set number refers to obtaining a set number of instructions, and the addresses of these instructions are all greater than the first AVX instruction address.

[0031] When obtaining the set number of instructions from the first AVX instruction forward to form the first instruction set, the set number can be set based on experience, or the set number can be set to the number of instructions between the end instruction and the first AVX instruction after obtaining the end instruction. In addition, the smaller value of the number of instructions between the end instruction and the first AVX instruction and the experience value can be used as the set number.

[0032] Step 3: According to the syntax and semantics of the instructions in the first instruction set, find the jump instruction closest to the address of the first AVX instruction. If it exists, execute step 4; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 11.

[0033] Step 4, record the jump instruction as the first jump instruction, obtain the instruction address of the first jump instruction and record it as the first jump instruction address, obtain the target address of the first jump instruction and record it as the first target address. If the first target address is smaller than the first AVX instruction address, it means that the first target address is before the first AVX instruction, then execute step 5; if the first target address is greater than the first AVX instruction address, delete the first jump instruction from the first instruction set and then execute step 10.

[0034] Step 5: Form a second instruction set by instructions from the first jump instruction address to the first AVX instruction address. If the second instruction set contains comparison and increment or decrement instructions with register data as operands, the first jump instruction is determined to be a loop jump instruction, and step 6 is executed; otherwise, it is indicated that the first jump instruction is not a loop jump instruction, and the first AVX instruction is dynamically converted into a Neon instruction and step 11 is executed.

[0035] Step 6, obtain the data in the register corresponding to the first AVX instruction address and record it as the first data address, and form a third instruction set by the instructions from the first target address to the first jump instruction address. If there is an instruction in the third instruction set that uses an immediate number to modify the first data address, select the instruction closest to the first AVX instruction address, and record the immediate number in the instruction as the data read step, and record the address of the instruction as the modified instruction address, and then execute step 7; otherwise, it means that the first AVX instruction does not read data in a loop, then dynamically convert the first AVX instruction into a Neon instruction and execute step 11.

[0036] Step 7, form a fourth instruction set from the first jump instruction address to the set number of instructions. If there is no loop jump instruction in the fourth instruction set, it means that the current loop is a single-layer loop code, and execute step 8; otherwise, it means that it is a multi-layer loop code, and execute step 9.

[0037] The loop jump instruction is determined in the same manner as in step 5.

[0038] Step 8. If the modified instruction address is less than the first AVX instruction address, a prefetch instruction is added between the first AVX instruction address and the first jump instruction address, and the operand of the prefetch instruction is the sum of the first data address and the data reading step size; if the modified instruction address is greater than the first AVX instruction address, a prefetch instruction is added between the modified instruction address and the first jump instruction address, and the operand of the prefetch instruction is the current first data address; the correspondence between the added prefetch instruction name, address and operand and the first AVX instruction address is added to the prefetch instruction insertion strategy list, and then execute step 11.

[0039] For example, the prefetch instruction used is PST [R1], where R1 points to the memory address of the data to be prefetched.

[0040] Step 9, in the memory area pointed to by the current first data address, traverse the memory pages starting from the first memory page, modify the memory pages with readable attributes to unreadable, and add the correspondence between the first AVX instruction address and the first data address to the instruction memory area mapping table; convert the first AVX instruction into the corresponding Neon instruction and execute the executable file sequentially, when a memory access exception occurs, for the exception address existing in the instruction memory area mapping table, record the exception address, clear the exception and resume the execution of the executable file; establish a correspondence between the exception address and the first AVX instruction address based on searching the instruction memory area mapping table for the first AVX instruction address that is the same as the exception address, if the exception address corresponding to the same first AVX instruction address is an arithmetic progression, indicating that the first AVX instruction address is located in a multi-layer loop body, then the set position before the exception address is used as the address of the prefetch instruction, and the memory page corresponding to the exception address is used as the operand of the prefetch instruction, and the correspondence between the prefetch instruction name, address and operand and the first AVX instruction address is added to the prefetch instruction insertion strategy list.

[0041] Step 10: If there is a jump instruction in the first instruction set, execute step 3; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 11.

[0042] Step 11: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process. Example

[0043] In this embodiment, an AVX instruction simulation execution optimization method based on loop dependency analysis provided by the present invention is used to add prefetch instructions to AVX data reading instructions in the loop body, and complete the simulation execution of AVX instructions on the ARM platform. Specifically, when the executable file is executed for the first time, the AVX data reading instructions (such as vmovaps, vmovups, vmovapd, vmovupd, vbroadcastss, vbroadcastsd, etc.) are reversed to determine whether the AVX data reading instruction is located in the loop body, and whether the loop body is a single-layer loop or a nested multi-layer loop, including the following steps:

[0044] S1. For an AVX data read instruction, the address of the current AVX data read instruction is currentInstrAddress, and the current AVX data read instruction is recorded as currentInstr.

[0045] S2. Reverse a set number of instructions from currentInstrAddress in advance, and record the set number as maxInstrCount. For example, because the number of AVX instructions in a program usually does not exceed 100, the set number can be set to 200.

[0046] This embodiment is described by taking the following simplified loop assembly code for loop reading of an array with a length of 8M bytes as an example:

[0047] mov rcx, array_size / 32 ; process 32 bytes each time and calculate the number of loops

[0048] mov rsi, array ; source address

[0049] loop_start:

[0050] vmovaps ymm0, [rsi] ; Use vmovaps to read 32 bytes from memory to the ymm0 register, assuming the memory address is aligned; here you can process the read data, such as storing the data in ymm0 to another location or performing calculations

[0051] ......; AVX data processing process, the specific content is omitted

[0052] add rsi, 32 ; move to the next 32-byte memory location

[0053] sub rcx, 1 ; counter decrement by 1 ()

[0054] cmp rcx, 0 ; compare loop count

[0055] jb loop_start ; If not 0, jump to the loop head and continue looping

[0056] S3. Find the first jump instruction, record the instruction address of the jump instruction as jumpInstrAddress, record the jump instruction as jumpInstr, and record the target address of the jump instruction as jumpDestAddress. If jumpDestAddress is less than currentInstrAddress, that is, it jumps to before currentInstrAddress, then execute S4; otherwise, execute S8.

[0057] S4. From jumpInstrAddress to currentInstrAddress, if there is an rcx / rdx comparison instruction and an rcx / rdx decrement instruction behind jumpInstrAddress, then jumpInstr is a loop jump instruction and S5 is executed; otherwise, S8 is executed.

[0058] S5. Extract the register value in currentInstrAddress and record it as sourceReg. Find the first instruction that modifies sourceReg with an immediate value from currentInstrAddress to jumpInstrAddress. If it exists, record the immediate value as readStep. The immediate value is the step size of each increase of the data address when reading data, and execute S6; otherwise, execute S8.

[0059] S6. Continue forward and reverse from jumpInstrAddress for no more than maxInstrCount instructions, and check whether there is a loop jump instruction with a similar pattern to jumpInstr. If not, it means that the current loop is a single-layer loop, and the address growth of data access in the single-layer loop body is linear. The corresponding relationship between currentInstrAddress and readStep is added to the prefetch instruction insertion strategy list, and the prefetch instruction is inserted before the target instruction converted by currentInstr with readStep as the parameter to complete the processing of the current instruction; if it exists, it means that currentInstr executes S7 in a nested multi-layer loop body.

[0060] The inserted prefetch instruction, for example, `prfmpldl1keep, %addr`, where %addr is the memory address pointing to the required prefetch data, specifically the sum of the value of the address operand in the currentInstr instruction and readStep. The value of the address operand in the currentInstr instruction is the value of sourceReg.

[0061] S7. Add a memory monitoring mechanism, analyze the growth pattern of the data access address, access the memory area pointed to by sourceReg one by one, that is, traverse the memory pages starting from the first memory page pointed to by sourceReg, set the accessible memory pages to unreadable, and record the mapping relationship between currentInstrAddress and the memory area; complete the dynamic conversion of currentInstrAddress and then continue to reverse forward. When an exception occurs during the execution of the converted code, in the memory access exception handling function, when there is a corresponding currentInstrAddress according to the current exception address, record the current exception address, clear the exception and resume the execution of the executable file; when the executable file ends execution, traverse the recorded exception address sequence and AVX data read instruction mapping, if the exception address related to the same AVX data read instruction is an arithmetic progression, record the currentInstrAddress and the step size of the arithmetic progression in the prefetch instruction insertion strategy list.

[0062] S8. Dynamically convert currentInstrAddress without inserting prefetch instructions.

[0063] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing AVX instruction simulation execution based on loop dependency analysis, characterized in that: The specific steps include: Step 1: If the executable file has a corresponding prefetch instruction insertion strategy list, the execution of the executable file is completed according to the prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is loaded and executed through dynamic instruction conversion; Step 2: If the current AVX instruction to be converted is not a data read instruction, convert it to a Neon instruction and then execute step 9; otherwise, record the current AVX instruction to be converted as the first AVX instruction, and record the address of the first AVX instruction as the first AVX instruction address; Obtaining a set number of instructions forward of the first AVX instruction to form a first instruction set, and performing pre-conversion on the instructions in the first instruction set to obtain syntax and semantics of the instructions; Step 3: According to the obtained syntax and semantics, find the jump instruction closest to the address of the first AVX instruction. If it exists, execute step 4; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 9; Step 4, record the jump instruction as the first jump instruction, record its address as the first jump instruction address, record the target address set as the first target address, if the first target address is less than the first AVX instruction address, execute step 5; if the first target address is greater than the first AVX instruction address, delete the first jump instruction from the first instruction set and execute step 8; Step 5: Form a second instruction set from the instructions between the first jump instruction address and the first AVX instruction address. If the second instruction set contains comparison and increment or decrement instructions with data in the register as operands, the first jump instruction is a loop jump instruction and step 6 is executed; otherwise, the first AVX instruction is dynamically converted into a Neon instruction and step 9 is executed. Step 6: record the data in the register corresponding to the first AVX instruction address as the first data address, and form a third instruction set from the instructions from the first target address to the first jump instruction address. If there is an instruction in the third instruction set that uses an immediate number to modify the first data address, then record the immediate number in the instruction closest to the first AVX instruction address as the data read step length, record the address of the instruction as the modified instruction address, and execute step 7; otherwise, dynamically convert the first AVX instruction into a Neon instruction and execute step 9; Step 7, adding the correspondence between the added prefetch instruction name, address and operand and the first AVX instruction address to the prefetch instruction insertion strategy list, and then executing step 9; Step 8: If there is a jump instruction in the first instruction set, execute step 3; otherwise, dynamically convert the first AVX instruction into a Neon instruction and then execute step 9; Step 9: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process.

2. The AVX instruction simulation execution optimization method according to claim 1, characterized in that: The set number is the number of instructions between the end instruction and the first AVX instruction, and the end instruction is determined by reverse analysis.

3. The AVX instruction simulation execution optimization method according to claim 2, characterized in that: The set number is the smaller value of the number of instructions between the end instruction and the first AVX instruction and the empirical value.

4. The AVX instruction simulation execution optimization method according to claim 3, characterized in that: The experience value is 200.

5. The AVX instruction simulation execution optimization method according to claim 1, characterized in that: In step 6, the immediate value in the instruction closest to the first AVX instruction address is recorded as the data read step length, and the address of the instruction is recorded as the modified instruction address, and then the following is executed: Step 6.1, forming a fourth instruction set from the first jump instruction address to the forward set number of instructions, if there is no loop jump instruction in the fourth instruction set, executing step 7; Otherwise, proceed to step 6.2; Step 6.2, in the memory area pointed to by the first data address, traverse the memory pages starting from the first memory page, modify the memory pages with readable attributes to unreadable, and form an instruction memory area mapping table based on the correspondence between the first AVX instruction address and the first data address; convert the first AVX instruction into a Neon instruction and execute the executable file sequentially, when a memory access exception occurs, for the exception address existing in the instruction memory area mapping table, record the exception address, clear the exception and resume the execution of the executable file; if the multiple exception addresses corresponding to the same first AVX instruction address are an arithmetic progression, use the address before the exception address as the address of the prefetch instruction, and use the memory page corresponding to the exception address as the operand of the prefetch instruction, and execute step 7.

6. The AVX instruction simulation execution optimization method according to claim 1, characterized in that: The method of adding the correspondence between the added prefetch instruction name, address and operand and the first AVX instruction address to the prefetch instruction insertion strategy list in step 7 is: If the modification instruction address is less than the first AVX instruction address, a prefetch instruction is added between the first AVX instruction address and the first jump instruction address, and the operand of the prefetch instruction is the sum of the first data address and the data read step length; If the modification instruction address is greater than the first AVX instruction address, a prefetch instruction is added between the modification instruction address and the first jump instruction address, and the operand of the prefetch instruction is the current first data address.

7. The AVX instruction simulation execution optimization method according to claim 1, characterized in that: The data reading instruction in step 2 is vmovaps, vmovups, vmovapd, vmovupd, vbroadcastss or vbroadcastsd.