Interrupt resource pooling processing method and device, computer equipment and medium

Abstract

The invention relates to an interrupt resource pooling processing method and device, computer equipment, a computer readable storage medium and a computer program product, and can be applied to the technical field of computers. The method comprises the following steps: receiving an interrupt configuration request for target equipment sent by a driving program; the interrupt configuration request comprises interrupt configuration information of the target equipment; determining an interrupt arrangement mode of the target equipment according to the interrupt configuration information; mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table according to the interrupt arrangement mode; according to the mapped management interrupt table and the mapped queue interrupt table, generating a target virtual interrupt table corresponding to the target equipment, and outputting the target virtual interrupt table to a driving program; the drive program is used for obtaining the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table. By adopting the method, the efficiency of acquiring the interrupt information can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, apparatus, computer device, computer-readable storage medium, and computer program product for processing interrupt resource pooling. Background Art

[0002] With the rapid development of computer technology, device interrupt processing has become a key technology to improve system performance. In device interrupt processing, the processing of interrupt tables is crucial to ensure stable system operation and improve processing efficiency. Therefore, how to efficiently implement the access configuration of interrupt tables has become an important research direction.

[0003] Conventional technology usually configures interrupt table access through a fixed interrupt table mapping method; however, configuring the interrupt table through this method lacks flexibility and requires the driver to request access to various types of interrupt tables separately, resulting in low efficiency in obtaining interrupt information. Summary of the invention

[0004] Based on this, it is necessary to provide an interrupt resource pooling processing method, apparatus, computer equipment, computer-readable storage medium and computer program product that can improve the efficiency of obtaining interrupt information in response to the above technical problems.

[0005] In a first aspect, the present application provides a method for processing interrupt resource pooling. The method comprises:

[0006] Receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0007] Determining an interrupt arrangement mode of the target device according to the interrupt configuration information;

[0008] According to the interrupt arrangement mode, mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table;

[0009] According to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0010] In one embodiment, the method further comprises:

[0011] Receiving an interrupt access request sent by the driver;

[0012] Obtaining a target access address from the interrupt access request;

[0013] According to the target access address, target interrupt information is obtained from the mapped management interrupt table or the mapped queue interrupt table.

[0014] In one embodiment, obtaining target interrupt information from the mapped management interrupt table or the mapped queue interrupt table according to the target access address includes:

[0015] Determine the interrupt table type according to the target access address;

[0016] When the interrupt table type is the mapped managed interrupt table, acquiring the target interrupt information from the mapped managed interrupt table;

[0017] In a case where the interrupt table type is the mapped queue interrupt table, the target interrupt information is acquired from the mapped queue interrupt table.

[0018] In one embodiment, the method further comprises:

[0019] Generate an interrupt message according to the target interrupt information;

[0020] The interrupt message is sent to a target address.

[0021] In one embodiment, determining the interrupt arrangement mode of the target device according to the interrupt configuration information includes:

[0022] Identifying location information of the management interrupt in the interrupt configuration information;

[0023] The interrupt arrangement mode is determined according to the location information of the management interrupt.

[0024] In one embodiment, determining the interrupt arrangement mode according to the location information of the management interrupt includes:

[0025] In a case where the position information of the management interrupt indicates a first position, determining the interrupt arrangement mode to be a first interrupt arrangement mode;

[0026] In a case where the position information of the managed interrupt indicates the last position, the interrupt arrangement mode is determined to be the second interrupt arrangement mode.

[0027] In a second aspect, the present application also provides an interrupt resource pooling processing device. The device comprises:

[0028] A request receiving module, used for receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0029] A mode determination module, used to determine the interrupt arrangement mode of the target device according to the interrupt configuration information;

[0030] An address mapping module, used for mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table according to the interrupt arrangement mode;

[0031] A target generation module is used to generate a target virtual interrupt table corresponding to the target device according to the mapped management interrupt table and the mapped queue interrupt table, and output the target virtual interrupt table to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0032] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0033] Receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0034] Determining an interrupt arrangement mode of the target device according to the interrupt configuration information;

[0035] According to the interrupt arrangement mode, mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table;

[0036] According to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0037] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0038] Receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0039] Determining an interrupt arrangement mode of the target device according to the interrupt configuration information;

[0040] According to the interrupt arrangement mode, mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table;

[0041] According to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0042] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0043] Receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0044] Determining an interrupt arrangement mode of the target device according to the interrupt configuration information;

[0045] According to the interrupt arrangement mode, mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table;

[0046] According to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0047] The above-mentioned interrupt resource pooling processing method, device, computer equipment, computer-readable storage medium and computer program product receive an interrupt configuration request for a target device sent by a driver; the interrupt configuration request contains the interrupt configuration information of the target device; according to the interrupt configuration information, the interrupt arrangement mode of the target device is determined; according to the interrupt arrangement mode, the access address of the virtual interrupt table is mapped to the access address of the management interrupt table and the access address of the queue interrupt table; according to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table. This scheme realizes the separate storage of management interrupts and queue interrupts by mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table, which is beneficial for the driver to directly access the corresponding interrupt table through the target virtual interrupt table to obtain interrupt information, thereby avoiding the complex process of first locating the interrupt table of the device and then searching for the corresponding entry under the traditional method, thereby improving the efficiency of obtaining interrupt information; at the same time, by determining the interrupt arrangement mode according to the interrupt configuration information and performing address mapping accordingly, the driver can accurately locate the required interrupt information, further improving the efficiency of obtaining interrupt information. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A schematic diagram of a flow chart of an interrupt resource pooling processing method in one embodiment;

[0050] Figure 2 A schematic diagram of the structure of a message signal interruption extension table in one embodiment;

[0051] Figure 3 is a schematic diagram of the hierarchical structure of devices and queues in one embodiment;

[0052] Figure 4 A schematic diagram of a process of a driver accessing a table in one embodiment;

[0053] Figure 5 A schematic diagram of a process flow of a driver accessing a table in one embodiment;

[0054] Figure 6 A flowchart of the steps of obtaining interruption information in one embodiment;

[0055] Figure 7 A schematic flow chart of the steps of interrupting transmission in one embodiment;

[0056] Figure 8 It is a structural block diagram of an interrupt resource pooling processing device in one embodiment;

[0057] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0060] In an exemplary embodiment, Figure 1 As shown, a method for processing interrupt resource pooling is provided. This embodiment uses the method applied to a terminal (computer) as an example for illustration; it is understandable that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, etc.; the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. In this embodiment, the method includes the following steps:

[0061] Step S101, receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device.

[0062] Step S102: determining the interrupt arrangement mode of the target device according to the interrupt configuration information.

[0063] Step S103 , mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table according to the interrupt arrangement mode.

[0064] Step S104, generating a target virtual interrupt table corresponding to the target device according to the mapped management interrupt table and the mapped queue interrupt table, and outputting the target virtual interrupt table to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0065] The driver may be a program for configuring and controlling a hardware device, for example, a program for configuring a PF (physical function device) / VF (virtual function device) interrupt.

[0066] The target device may be a hardware device for which interrupts need to be configured, for example, a PF (physical function device) or a VF (virtual function device).

[0067] The interrupt configuration information may include relevant parameter information for configuring the target device interrupt, for example, information on the number of interrupts required by the target device, including a management interrupt and the number of interrupts of a network or storage queue.

[0068] The interrupt arrangement mode may be an arrangement mode of interrupts in the interrupt table, for example, mode 1 in which the management interrupt is in Entry 0 followed by queue interrupts, or mode 2 in which the queue interrupt is in the front and the last Entry is the management interrupt.

[0069] The virtual interrupt table may be a standard MSI-X (Message Signal Interrupt Extension) table seen by the driver, for example, a Msix_tbl (Message Signal Interrupt Extension Table) formed by splicing a management interrupt table and a queue interrupt table.

[0070] The management interrupt table may be a table storing all PF (physical function device) / VF (virtual function device) management interrupt information, for example, may be pvf_msix_tbl (physical / virtual function message signal interrupt extension table).

[0071] The queue interrupt table may be a table storing all network queues and queue interrupt information, for example, q_msix_tbl (queue message signal interrupt extension table).

[0072] Optionally, the terminal (computer) receives an interrupt configuration request for a target device sent by a driver, wherein the target device may be a PF (physical function device) or a VF (virtual function device), and the interrupt configuration request includes information on the number of interrupts required by the target device, wherein the information on the number of interrupts includes one management interrupt and the number of interrupts of a network or storage queue; the terminal determines whether the interrupt arrangement mode of the target device is mode 1 or mode 2 according to the interrupt configuration information, wherein mode 1 is a mode in which the management interrupt is in Entry 0 followed by queue interrupts, and mode 2 is a mode in which the queue interrupt is in front and the last Entry is a management interrupt; the terminal maps the access address of the virtual interrupt table Msix_tbl (message signal interrupt extension table) to The access address of pvf_msix_tbl (physical / virtual function message signal interrupt extension table) and the access address of q_msix_tbl (queue message signal interrupt extension table); the terminal generates the target virtual interrupt table Msix_tbl (message signal interrupt extension table) corresponding to the target device according to the mapped pvf_msix_tbl (physical / virtual function message signal interrupt extension table) and the mapped q_msix_tbl (queue message signal interrupt extension table), and outputs the target virtual interrupt table Msix_tbl (message signal interrupt extension table) to the driver (Driver), so that the driver (Driver) can obtain management interrupt information and queue interrupt information through the target virtual interrupt table Msix_tbl (message signal interrupt extension table).

[0073] In the above interrupt resource pooling processing method, an interrupt configuration request for a target device sent by a driver is received; the interrupt configuration request contains the interrupt configuration information of the target device; according to the interrupt configuration information, the interrupt arrangement mode of the target device is determined; according to the interrupt arrangement mode, the access address of the virtual interrupt table is mapped to the access address of the management interrupt table and the access address of the queue interrupt table; according to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table. The scheme realizes the separate storage of management interrupts and queue interrupts by mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table, which is conducive to the driver to directly access the corresponding interrupt table through the target virtual interrupt table to obtain interrupt information, thereby avoiding the complex process of first locating the interrupt table of the device and then searching for the corresponding entry in the traditional method, and improving the efficiency of obtaining interrupt information; at the same time, by determining the interrupt arrangement mode according to the interrupt configuration information and performing address mapping accordingly, the driver can accurately locate the required interrupt information, further improving the efficiency of obtaining interrupt information.

[0074] In an exemplary embodiment, the method further includes: receiving an interrupt access request sent by a driver; obtaining a target access address from the interrupt access request; and obtaining target interrupt information from a mapped management interrupt table or a mapped queue interrupt table according to the target access address.

[0075] The interrupt access request may be an access request sent by a driver to obtain interrupt information, for example, a request to access Msix_tbl (message signal interrupt extension table) sent by the driver to obtain management interrupt information or queue interrupt information.

[0076] The target access address may be address information for accessing an interrupt table, for example, a pvf_id (physical / virtual function identifier) ​​address for accessing a management interrupt table or a qid (queue identifier) ​​address for accessing a queue interrupt table.

[0077] The target interrupt information may be interrupt-related parameter information stored in the interrupt table, such as Vector Control, Msg Data, Msg Upper Addr, and / or Msg Addr, which are parameter information used to assemble MSIX (Message Signaled Interrupt Extension) interrupt messages.

[0078] Optionally, the terminal receives an interrupt access request sent by a driver (Driver), and obtains a target access address from the interrupt access request; the terminal determines whether the interrupt access request is for a management interrupt or a queue interrupt. If it is a management interrupt request, the target access address is parsed into pvf_id (physical / virtual function identifier), and the target interrupt information is obtained from the mapped pvf_msix_tbl (physical / virtual function message signal interrupt extension table) according to the pvf_id (physical / virtual function identifier); if it is a queue interrupt request, the target access address is parsed into qid (queue identifier), and the target interrupt information is obtained from the mapped q_msix_tbl (queue message signal interrupt extension table) according to the qid (queue identifier); the target interrupt information includes Vector Control (vector control), Msg Data (message data), Msg UpperAddr (message high address) and Msg Addr (message address), which are parameter information used to assemble MSIX (message signal interrupt extension) interrupt messages.

[0079] The technical solution provided in this embodiment obtains the target access address from the interrupt access request, and directly obtains the target interrupt information from the mapped management interrupt table or queue interrupt table according to the target access address, which is conducive to simplifying the process of obtaining the interrupt information and avoiding the complex process of first locating the interrupt table of the PF / VF device and then searching for the corresponding entry in the traditional way, thereby helping to improve the access efficiency of the interrupt information; at the same time, this method of directly obtaining the interrupt information through the target access address makes the access to the interrupt information more convenient and efficient.

[0080] In an exemplary embodiment, according to the target access address, the target interrupt information is obtained from the mapped management interrupt table or the mapped queue interrupt table, which specifically includes the following contents: according to the target access address, the interrupt table type is determined; when the interrupt table type is the mapped management interrupt table, the target interrupt information is obtained from the mapped management interrupt table; when the interrupt table type is the mapped queue interrupt table, the target interrupt information is obtained from the mapped queue interrupt table.

[0081] The interrupt table type may be a type identifier used to distinguish whether the interrupt table is a management interrupt table or a queue interrupt table.

[0082] Optionally, the terminal determines the interrupt table type according to the target access address: if it is interrupt arrangement mode 1 and the target access address is Entry0 (entry 0), or if it is interrupt arrangement mode 2 and the target access address is the last Entry (entry), the interrupt table type is determined to be the mapped pvf_msix_tbl (physical / virtual function message signal interrupt extension table), the terminal resolves the target access address into pvf_id (physical / virtual function identifier), and obtains Vector Control (vector control), Msg Data (message data), Msg Upper Addr (message high address) and Msg from the mapped pvf_msix_tbl (physical / virtual function message signal interrupt extension table) according to pvf_id (physical / virtual function identifier). Addr (message address) and other target interrupt information; if it is other cases, the interrupt table type is determined to be the mapped q_msix_tbl (queue message signal interrupt extension table), the terminal resolves the target access address to qid (queue identifier), and obtains the target interrupt information from the mapped q_msix_tbl (queue message signal interrupt extension table) according to qid (queue identifier).

[0083] The technical solution provided in this embodiment determines the interrupt table type according to the target access address, and directly obtains the target interrupt information from the corresponding management interrupt table or queue interrupt table according to the determined interrupt table type, which is conducive to storing and managing different types of interrupt information separately, avoiding the complicated process of searching for different types of interrupt information in the same interrupt table, thereby simplifying the interrupt information acquisition process and improving the access efficiency of the interrupt information; at the same time, this method of classified management based on the interrupt table type makes the storage structure of the interrupt information clearer and more efficient.

[0084] In an exemplary embodiment, the method further includes: generating an interrupt message according to target interrupt information; and sending the interrupt message to a target address.

[0085] Among them, the interrupt message can be a message signal interrupt extension message assembled according to the parameters in the interrupt information, for example, it can be an MSIX (message signal interrupt extension) interrupt message assembled according to the parameters of Vector Control, Msg Data, Msg Upper Addr and Msg Addr.

[0086] The target address may be a destination address to which the interrupt message needs to be sent, for example, a complete interrupt message target address composed of Msg UpperAddr (message upper address) and Msg Addr (message address).

[0087] Optionally, the terminal extracts parameter information such as Vector Control, Msg Data, MsgUpper Addr and Msg Addr in the target interrupt information according to the target interrupt information obtained from the mapped management interrupt table or the mapped queue interrupt table, and assembles and generates an MSIX (message signal interrupt extension) interrupt message according to the parameter information; the terminal combines Msg Upper Addr and MsgAddr to form a complete target address, and sends the generated MSIX (message signal interrupt extension) interrupt message to the target address.

[0088] The technical solution provided in this embodiment, by generating an interrupt message according to the target interrupt information and sending it to the target address, is conducive to converting the obtained interrupt parameter information into a standard interrupt message format and ensuring that the interrupt message can be accurately delivered to the specified target, thereby facilitating efficient conversion of interrupt information to actual interruption and ensuring accurate execution of the interrupt mechanism.

[0089] In an exemplary embodiment, determining the interrupt arrangement mode of the target device according to the interrupt configuration information specifically includes the following contents: identifying the location information of the management interrupt in the interrupt configuration information; and determining the interrupt arrangement mode according to the location information of the management interrupt.

[0090] The interrupt arrangement mode may be the arrangement of management interrupts and queue interrupts in Entry when the driver configures interrupts, for example, interrupt arrangement mode 1 (management interrupts are in Entry 0, followed by queue interrupts) or interrupt arrangement mode 2 (queue interrupts are in front, and the last entry is the management interrupt).

[0091] The location information of the management interrupt may be an Entry location of the management interrupt in a MSIX (Message Signaled Interrupt Extension) table, for example, the location of Entry 0 or the location of the last Entry.

[0092] Among them, the interrupt configuration information may also include information written by the driver when configuring the PF (physical function device) / VF (virtual function) interrupt, for example, it may include parameter information such as Vector Control, Msg Data, Msg Upper Addr, and MsgAddr written by the driver to the MSIX (message signaled interrupt extension) table.

[0093] Optionally, after receiving the interrupt configuration information, the terminal first parses the Entry arrangement order in the interrupt configuration information, and identifies the location information of the management interrupt by scanning the content of each Entry in the interrupt configuration information: if the management interrupt is located at the Entry0, it means that the management interrupt is configured at the starting position of the MSIX (Message Signaled Interrupt Extension) table; if the management interrupt is located at the last Entry, it means that the management interrupt is configured at the end of the MSIX (Message Signaled Interrupt Extension) table; the terminal determines whether the target device adopts interrupt arrangement mode 1 or interrupt arrangement mode 2 based on the identified management interrupt location information.

[0094] The technical solution provided in this embodiment, by identifying the position information of the management interrupt in the interrupt configuration information and determining the interrupt arrangement mode according to the position information, is helpful for accurately judging which interrupt arrangement mode is currently adopted, thereby facilitating the subsequent correct access to the information of the management interrupt and queue interrupt; at the same time, this method of determining the arrangement mode based on the management interrupt position makes the judgment process of the interrupt arrangement mode simpler and more intuitive, without the need for complex judgment logic.

[0095] In an exemplary embodiment, the interrupt arrangement mode is determined based on the position information of the managed interrupt, which specifically includes the following contents: when the position information of the managed interrupt indicates the first position, the interrupt arrangement mode is determined to be the first interrupt arrangement mode; when the position information of the managed interrupt indicates the last position, the interrupt arrangement mode is determined to be the second interrupt arrangement mode.

[0096] The first position may be a starting position in a MSIX (Message Signaled Interrupt Extension) table, for example, the position of Entry 0.

[0097] The last position may be the end position in the MSIX (Message Signaled Interrupt Extension) table, for example, the position of the last Entry.

[0098] Among them, the first interrupt arrangement mode (i.e., interrupt arrangement mode 1) may be an arrangement mode in which the management interrupt is located at the starting position of the MSIX (Message Signaled Interrupt Extension) table, for example, the management interrupt may be in Entry 0, followed by the interrupt Entry 1 of the first queue, and the interrupt Entry 2 of the second queue.

[0099] Among them, the second interrupt arrangement mode (i.e., interrupt arrangement mode 2) may be an arrangement mode in which the management interrupt is located at the end of the MSIX (Message Signaled Interrupt Extension) table, for example, the interrupts of each queue may start from Entry 0, and the last Entry is an arrangement mode for the management interrupt.

[0100] Optionally, after obtaining the interrupt configuration information, the terminal first checks the location information of the management interrupt in the MSIX (message signal interrupt extension) table: if the location information of the management interrupt shows that the management interrupt is configured at the position of Entry0, the terminal determines the interrupt arrangement mode as the first interrupt arrangement mode, and the terminal maps the management interrupt to pvf_msix_tbl (physical / virtual function message signal interrupt extension table), and maps Entry1 and subsequent queue interrupts to q_msix_tbl (queue message signal interrupt extension table) in sequence; if the location information of the management interrupt shows that the management interrupt is configured at the position of the last Entry, the terminal determines the interrupt arrangement mode as the second interrupt arrangement mode, and the terminal maps the queue interrupts from Entry0 to the second to last Entry in sequence to q_msix_tbl (queue message signal interrupt extension table), and maps the management interrupt of the last Entry to pvf_msix_tbl (physical / virtual function message signal interrupt extension table).

[0101] The technical solution provided in this embodiment establishes a corresponding relationship between the location information of the management interrupt and the interrupt arrangement mode, which is conducive to quickly determining the currently used interrupt arrangement mode through simple location judgment, thereby facilitating rapid identification of the interrupt arrangement mode.

[0102] The following is an application example to illustrate the interrupt resource pooling processing method provided by the present application. This application example uses the method applied to a terminal as an example.

[0103] This application example is used to manage the internal interrupt resources of the DPU (data processing unit) in a pooled manner.

[0104] Name explanation:

[0105] DPU (Data Processing Unit) is a hardware device used in large-scale computing scenarios such as data centers. It serves cloud computing and its main function is to improve the efficiency of computing infrastructure such as data centers, reduce energy waste, and thus reduce costs. It is responsible for carrying infrastructure layer services such as network virtualization and hardware resource pooling to release the computing power of the CPU (central processing unit) to upper-layer applications.

[0106] A PF (Physical Function) is a physical device that has the ability to fully configure or control PCIe device resources.

[0107] A VF (Virtual Function) is a lightweight PCIe function that is associated with a PF and can share one or more physical resources with a physical function and other VFs associated with the same physical function.

[0108] FPGA (Field-programmable Gate Array) is a semiconductor device consisting of a matrix of configurable logic blocks (CLBs) connected by programmable interconnects. After manufacturing, FPGAs can be reprogrammed according to the desired application or functional requirements.

[0109] PCIe (Peripheral Component Interconnect Express) is an important branch of the computer bus. It uses the existing PCI programming concepts and signal standards and builds a higher-speed serial communication system standard. Currently, this standard is formulated and maintained by the PCI-SIG organization. PCIe is only used for internal interconnection. Since PCIe is based on the existing PCI system, the existing PCI system can be converted to PCIe by modifying the physical layer without modifying the software.

[0110] MSI / MSIx (Message Signaled Interrupt / Message Signaled Interrupt Extended) is an improved interrupt mechanism of the subsequent PCI / PCI-X bus, among which MSI-X is an upgraded version proposed in PCI-X.

[0111] This application example can be applied to cloud computing, data centers, networks, storage, chips, FPGA (field programmable gate array) and other technical fields.

[0112] Currently, there are one or more PF and VF devices inside PCIe bus network cards, smart network cards, and DPUs, and each PF or VF device also requires a management interrupt. Each PF or VF device has one or more network / storage queues, and each queue also requires its own queue interrupt.

[0113] The management of these interrupt resources is mostly static. That is, each network queue or storage queue has its own queue interrupt resource. At the same time, each PF or VF device also needs to reserve management interrupts.

[0114] This static management method is relatively simple and efficient, and is more suitable for situations where there are not many PF and VF devices and not many network and storage queues.

[0115] With the increase in the number of PF, VF devices and network and storage queues of smart network cards, DPUs and other products, many existing DPU network cards can already support 2K-level PF and VF devices, and network and storage queues support up to 8K / 16K levels. The corresponding number of interrupts has also reached the level of several K or tens of K. At this time, if the traditional static management method is used, it is necessary to manage independent interrupt resources for each PF / VF, which is not only inefficient, but also very complex in structure and difficult to implement on the chip.

[0116] At the same time, smart network cards and DPUs generally support dynamic adjustment of the number of queues under PF / VF. This requires flexible adjustment of the number of queue interrupts under PF / VF. However, the static management method does not have the ability to flexibly adjust the number of interrupts. It is necessary to reserve the number of interrupts according to the maximum number of network and storage queues supported by each PF / VF. However, in many scenarios, the number of queues under PF and VF will not be allocated to the maximum value, which will cause a lot of waste.

[0117] For example, a DPU supports 1K PFs and VFs and 4K network queues. Each PF and VF has a maximum of 64 network queues, so each PF and VF needs a maximum of one management interrupt and 64 queue interrupts, for a total of 65 interrupts. Static management requires 65K interrupts to manage 1K PF and VF devices, but in fact this DPU only has 4K queues, and only 5K interrupt resources are needed when all are working. Using static management will result in a huge waste of resources.

[0118] This requires a new interrupt management method with the following functions and features: Support dynamic adjustment of the number of interrupts under each PF and VF. Centrally manage interrupt resources according to the number of PFs, VFs and the total number of network and storage queues to reduce waste. Ensure the quick acquisition of interrupt resources without affecting overall performance. Simple and convenient management.

[0119] In this application example, the MSI / MSIx (Message Signaled Interrupt / Extended Message Signaled Interrupt) interrupt mechanism of PCIe (Peripheral Component Interconnect) is:

[0120] 1. In the bar (base address register) space under each PF (physical function device) and VF (virtual function) device, there is a continuous address to store the MSIX (extended message signal interrupt) table. MSIX consists of several rows of entries. One interrupt corresponds to one entry, and there are as many entries as the number of interrupts supported by the current PF / VF device.

[0121] refer to Figure 2 , Figure 2 The structure of the MSI-X (Message Signaled Interrupt Extension) table is shown. The table consists of multiple entries, each of which contains four DWORD (double word) data (including DWORD 0, DWORD 1, DWORD 2, DWORD 3), which can be read (RD) and written (WR). They are: Vector Control, Msg Data, Msg Upper Addr, and Msg Addr. The figure shows the complete structure from Entry 0, Entry 1, Entry 2 to Entry N-1.

[0122] 2. When the PF / VF device wants to send an interrupt, it goes to the corresponding Entry, takes out the parameters of Vector Control / Msg Data / Msg Upper Addr / Msg Addr, and then assembles them into an MSIX (extended message signal interrupt) interrupt message. When it is sent out, the interrupt is sent.

[0123] 3. The MSIX (Extended Message Signaled Interrupt) table is maintained by the software on the CPU (Central Processing Unit) side, and PF / VF is read-only. So from the perspective of the CPU, the current PF / VF device has n network and storage queues, plus the management interrupt of PF / VF, so this PF / VF device must support n+1 interrupts, and the number of entries in the MSIX table is also equal to n+1.

[0124] The structure between the PF / VF and network storage queues of the smart NIC DPU (data processor) is: multiple PF / VF devices can be supported under the PCIe EP (endpoint) device, each PF / VF device has its own Msix_tbl (extended message signal interrupt table), each PF / VF device has one or more network and storage queues Q0-Qx, each PF / VF device has a management interrupt, and each Q (queue) has its own Q interrupt. Under the smart NIC or DPU, after the PF / VF is pooled, there will be a unified index pvf_id (physical / virtual function identifier). The number of network and storage Q queues under each PF / VF can be adjusted. In actual implementation, in order to facilitate the management of all network and storage queues, there will be a unified index Qid (queue identifier). It is also called the number Qid (queue identifier) ​​that is uniformly managed after the network and storage queues are pooled.

[0125] refer to Figure 3 , Figure 3 The figure shows the hierarchical structure of PF / VF devices and queues under a PCIe EP (PCIe endpoint, PCIe can be expressed as a peripheral component interconnect standard) device. There are multiple PVF (physical / virtual function) devices under the PCIe EP device, and the figure shows three devices: PVF0, PVF1, and PVF2. Each PVF device has its own Msix tbl (message signal interrupt extension table). At the queue level, PVF0 has four queues: Q0, Q1, Q2, and Q3; PVF1 has eight queues: Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7; and PVF2 has two queues: Q0 and Q1. These queues are assigned queue identifiers in a unified numbering method, from qid0 to qid13. The specific correspondence is: the four queues of PVF0 correspond to qid0, qid1, qid2, and qid3; the eight queues of PVF1 correspond to qid4, qid5, qid6, qid7, qid8, qid9, qid10, and qid11; the two queues of PVF2 correspond to qid12 and qid13.

[0126] Achievement purpose:

[0127] The structure of Msix_tbl is specified by the PCIe standard and must be implemented according to this structure. The structure of Msix_tbl seen by the driver must be standard. However, if we strictly follow this structure during implementation, the following problems will occur:

[0128] 1. The number of network and storage queues for each PF / VF is different, which leads to a different number of interrupts for each PF / VF. It is necessary to design msix_tbl of different depths for each PF / VF, which makes the structure very complicated and difficult to maintain.

[0129] 2. The network and storage queues under PF / VF support dynamic adjustment, so the number of interrupts under each PF / VF must also support dynamic adjustment, resulting in the depth of msix_table also needing to support dynamic adjustment. In chip / FPGA (field programmable gate array) design, msix_table cannot achieve such flexible design whether using SRAM (static random access memory) resources or other logic resources. It can only be designed to support the maximum number of interrupts. This will cause a lot of waste when there are relatively few network and storage queues under PF / VF.

[0130] 3. After PF / VF and network and storage queues are pooled, they can obtain their own interrupt resources, which cannot be uniformly addressed, causing difficulties in use.

[0131] Solution:

[0132] 1. Comply with PCIe regulations. The Msix_tbl of each PF / VF device seen by the driver must be standard.

[0133] 2. The depth of Msix_tbl should be adjusted dynamically according to the changes in the number of network and storage queues under PF / VF.

[0134] 3. All interrupt resources should be pooled and managed in a unified manner.

[0135] 4. All queues can obtain their own queue interrupt resources according to their Qid (queue identifier).

[0136] 5. All PF / VFs can obtain their own management interrupt resources according to their own pvf_id (physical / virtual function identifier).

[0137] In this application example, the standard interrupt configuration process is:

[0138] The process of driver configuring interrupt for PF (physical function device) / VF (virtual function) is:

[0139] 1. The driver obtains the number of interrupts required by the PF / VF: n = 1 management interrupt + the number of network or storage queues.

[0140] 2. The driver writes n interrupt information into Msix_tbl (message signal interrupt extension table). One entry stores the information of one interrupt, so the driver needs to write n entries.

[0141] 3. The driver establishes the connection between the interrupt and queue and the PF / VF management module, which is to inform the hardware which queue should use the interrupt information in which Entry, and the PF / VF management module which Entry should use the interrupt information in.

[0142] There is a key point here: the PF / VF management interrupt is shared by the entire PF / VF device, and there is only one for each PF / VF. The queue interrupt is used by each queue separately, and there is one for each queue.

[0143] The above are two different types of interrupts. After PF / VF and queues are pooled separately, these two types of interrupts cannot be managed in a unified addressing manner and must be separated. Management interrupts must be addressed with pvf_id (physical / virtual function identifier), and queue interrupts must be addressed with qid (queue identifier). But there is a problem here. Before the driver is configured, it is impossible to know which entry's interrupt is for management interrupts and which entry is for queue interrupts.

[0144] But in fact, there are traces to follow. The process of driver configuration interrupt has certain rules. There are only two ways:

[0145] (1) Interrupt Arrangement Mode 1: The management interrupt is Entry 0, followed by the interrupt Entry 1 of the first queue, the interrupt Entry 2 of the second queue, and so on.

[0146] (2) Interrupt Arrangement Mode 2: Entry 0 is the interrupt of the first queue, Entry 1 is the interrupt of the second queue, and the last Entry is the management interrupt.

[0147] Based on these two modes, we can manage all interrupt resources in a pooled manner.

[0148] refer to Figure 4 , Figure 4 A schematic diagram showing the process of a driver accessing a table, specifically a schematic diagram showing the process of a driver accessing Msix_tbl (message signal interrupt extension table) / PBA_tbl ​​(pending bit array table).

[0149] from Figure 4 A complete interrupt table structure and its access process can be seen in the figure. This figure mainly contains three key table structures:

[0150] 1. The table seen by the driver: Msix_tbl (message signal interrupt extension table), which contains multiple entries from Entry0, Entry1, Entry2 to Entry_(q_num-1) (entry_(queue number-1)). Each entry contains four Dwords (double words), namely Dword3, Dword2, Dword1, and Dword0, corresponding to Vector_Ctl (vector control), Msg Data (message data), Msg Up Addr (message high address), and Msg LowAdr (message low address).

[0151] 2. pvf_msix_tbl (physical / virtual function message signal interrupt extension table): contains entries from pvf0, pvf1, pvf2 to pvf1023, each entry also contains four parts: Vector_Ctl (vector control), Msg Data (message data), MsgUp Addr (message high address) and Msg Low Adr (message low address).

[0152] 3.q_msix_tbl (queue message signal interrupt extension table): contains entries from qid0, qid1, qid2 to qid2047, and its structure is the same as the above two tables.

[0153] The access process is as follows:

[0154] 1. The driver reads / writes Msix_tbl (Message Signal Interrupt Extension Table).

[0155] 2. After address resolution.

[0156] 3. Process according to interrupt arrangement mode 1 or interrupt arrangement mode 2:

[0157] For interrupt queuing mode 1: start from q_off (queue offset) = 0.

[0158] For interrupt queuing mode 2: start from q_off (queue offset) = 1 (then to q_off = 2), and continue until q_off (queue offset) = q_num-2 (queue number - 2).

[0159] 4. Access pvf_msix_tbl (Physical / Virtual Function Message Signaled Interrupt Extension Table).

[0160] 5. Get the queue offset.

[0161] 6. Get the QID (queue ID).

[0162] 7. Access q_msix_tbl (queue message signal interrupt extension table).

[0163] Among them, the English translation is: Msix_tbl (message signal interrupt extension table), Entry (entry), Dword (double word), Vector_Ctl (vector control), Msg Data (message data), Msg Up Addr (message high address), Msg LowAdr (message low address), pvf_msix (physical / virtual function message signal interrupt extension), pvf_msix_tbl (physical / virtual function message signal interrupt extension table), q_msix_tbl (queue message signal interrupt extension table), driver (driver), q_off (queue offset), QID (queue identifier).

[0164] refer to Figure 5 ,according to Figure 5 The process handles the driver's access to msix_tbl (message signal interrupt extension table) and PBA_tbl ​​(pending bit array table).

[0165] from Figure 5 In the figure, you can see the complete process of driver accessing msix_tbl (message signal interrupt extension table) and PBA_tbl ​​(to-be-processed bit array table). The process starts with "driver accessing msix_tbl and PBA_tbl ​​process", and enters the step of accessing Msix_tbl after address resolution. Then determine whether it is interrupt arrangement mode 1. If it is (Y), determine whether to access Entry0. If so, manage interrupt access, access pvf_msix_tbl, address: pvf_id, end, if not (N), queue interrupt access to obtain relative q_off=(addr-1), obtain qid according to q_off, access q_msix_tbl, address: qid, end; if it is interrupt arrangement mode 2, determine whether to access the last Entry. If so, manage interrupt access, access pvf_msix_tbl, address: pvf_id, end, if not, queue interrupt access to obtain relative q_off=addr, and jump to the step of obtaining qid according to q_off.

[0166] Among them, the English translation is: driver (driver), msix_tbl (message signal interrupt extension table), PBA_tbl ​​(pending bit array table), Entry (entry), q_off (queue offset), pvf_msix_tbl (physical / virtual function message signal interrupt extension table), pvf_id (physical / virtual function identifier), qid (queue identifier), q_msix_tbl (queue message signal interrupt extension table), addr (address).

[0167] In this way, the driver still sees the standard Msix_tbl (message signal interrupt extension table). This table is virtual, and is actually spliced ​​from pvf_msix_tbl (physical / virtual function message signal interrupt extension table) and q_msix_tbl (queue message signal interrupt extension table). The benefits of this implementation are:

[0168] 1. The actual depth of Msix_tbl (message signal interrupt extension table) is: the number of pvfs + the number of queues. Save a lot of storage space: For example: if pvf_num (number of physical / virtual functions) = 512, q_num (number of queues) = 2048, each pvf supports up to 64 queues, msix_tbl_width (message signal interrupt extension table width) = 128 bits. The traditional static management method needs to consume: (1 management interrupt + 64 queue interrupts) * pvf_num (number of physical / virtual functions) * msix_tbl_width (message signal interrupt extension table width) = 4259840 bits ≈ 4.26Mbits storage space. The implementation of the method in this application example consumes: (pvf_num+q_num)*msix_tbl_width (message signal interrupt extension table width) = 327680 bits (bits) ≈ 0.33 Mbits (megabits) storage space, where q_num represents the number of queues, saving 92.3% of storage space.

[0169] 2.Support dynamic adjustment of the number of supported PF / VF:

[0170] The number of interrupts can be adjusted together with the number of queues supported by PF / VF. No additional configuration or adjustment is required. If the number of queues changes, the number of interrupts is automatically adjusted to the number of queues + 1.

[0171] 3. Support more interrupts under PF / VF:

[0172] The number of interrupts supported by PF / VF is limited by the total number of queues. That is to say, a single PF / VF can support up to q_num (number of queues) = 2048 + 1 interrupts without increasing resource consumption. This is a necessary condition for PF / VF to support more queues.

[0173] The process of using interrupts:

[0174] 1. Get interrupt information;

[0175] 2. Send an interrupt based on the interrupt information.

[0176] The process of using interrupts has also become simpler.

[0177] refer to Figure 6 , Figure 6 Shows the process of obtaining interrupt information, from Figure 6 In the figure, you can see two parallel interrupt table structures and their access methods, pvf msix tbl (physical / virtual function message signal interrupt extension table) and qid_msix_tbl (queue identification message signal interrupt extension table).

[0178] Each table contains four Dwords (double words), from Dword3, Dword2, Dword1 to Dword0, corresponding to Vector Ctl (vector control), Msg Data (message data), Msg Up Addr (message high address) and Msg LowAdr (message low address).

[0179] In terms of access mechanism, pvf msix tbl is addressed by pvf_id (physical / virtual function identifier), while qid_msix_tbl is addressed by qid (queue identifier). In the figure, rd msix tbl (read message signal interrupt extension table) and get msix (get message signal interrupt) represent the entire reading process.

[0180] refer to Figure 6 :If you want to send a management interrupt, use pvf_id (physical / virtual function identifier) ​​as the address, read pvf_msix_tbl (physical / virtual function message signal interrupt extension table) to obtain the interrupt information. If you want to send a queue interrupt, use qid (queue identifier) ​​as the address, read q_msix_tbl (queue message signal interrupt extension table) to obtain the interrupt information.

[0181] refer to Figure 7 , Figure 7A complete interrupt sending process is shown. The process starts with applying for sending interrupts. First, determine whether it is a management interrupt. If it is a management interrupt (Y branch), access pvf_msix_tbl (physical / virtual function message signal interrupt extension table), where addr (address) = pvf_id (physical / virtual function identifier); if it is not a management interrupt (N branch), access q_msix_tbl (queue message signal interrupt extension table), where addr (address) = qid (queue identifier). Finally, the process ends.

[0182] This greatly simplifies the process of obtaining interrupt information when sending an interrupt. In the static method, you need to first find the msix_tbl (message signal interrupt extension table) under PF / VF and then find the corresponding Entry, which is a complicated process.

[0183] This application example includes at least the following technical effects:

[0184] 1. Unified pool management of all interrupt resources:

[0185] The traditional static management method is to implement the msix_tbl (message signal interrupt extension table) of each PF (physical function device) / VF (virtual function) device one by one. For the case that the smart network card DPU (data processing unit) often has 512 / 1K / 2K or even more PF / VF devices, this implementation method is not only complex and consumes a lot of resources, but is also almost impossible to implement in chip design.

[0186] By adopting the method of this application example, only two table entries are needed: pvf_msix_tbl (physical / virtual function message signal interrupt extension table) and q_msix_tbl (queue message signal interrupt extension table) to support all PF / VF devices, simplifying the structure and reducing resource consumption to less than 4%.

[0187] This application example uses a mapping method to map the standard Msix_tbl (message signal interrupt extension table) to pvf_msix_tbl (physical / virtual function message signal interrupt extension table) and q_msix_tbl (queue message signal interrupt extension table). The driver sees the standard msix_tbl (message signal interrupt extension table), but the underlying implementation is pvf_msix_tbl and q_msix_tbl. When the driver accesses msix_tbl, it only needs to map the access address from msix_tbl to pvf_msix_tbl and q_msix_tbl.

[0188] 2. The number of interrupts supported by PF / VF devices can be adjusted dynamically:

[0189] The traditional static management method is to implement the msix_tbl (message signal interrupt extension table) of each PF / VF device one by one. If the number of queues under PF / VF is variable, this method must implement msix_tbl according to the maximum number of queues supported, which has a large resource overhead.

[0190] The method of this application example does not care about the maximum number of queues supported by PF / VF, but is limited by the total number of queues supported by the SmartNIC DPU (data processor).

[0191] 3. The driver side sees the virtual Msix_tbl (message signal interrupt extension table):

[0192] This application example does not implement a physical msix_tbl (message signal interrupt extension table), but instead uses pvf_msix_tbl (physical / virtual function message signal interrupt extension table) / q_msix_tbl (queue message signal interrupt extension table) to create a msix_tbl.

[0193] 4. The way to get interrupt information when sending an interrupt is very simplified:

[0194] In the static method, you need to first find the msix_tbl (message signal interrupt extension table) under PF / VF and then find the corresponding Entry, which is a complicated process.

[0195] In this application example, the corresponding entry can be obtained by only checking the pvf_msix_tbl (physical / virtual function message signal interrupt extension table) / q_msix_tbl (queue message signal interrupt extension table) table entry once.

[0196] The technical solution provided by this application example realizes the separate storage of management interrupts and queue interrupts by mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table, which is beneficial for the driver to directly access the corresponding interrupt table through the target virtual interrupt table to obtain interrupt information, thereby avoiding the complex process of first locating the interrupt table of the device and then searching for the corresponding entry under the traditional method, thereby improving the efficiency of obtaining interrupt information; at the same time, by determining the interrupt arrangement mode according to the interrupt configuration information and performing address mapping accordingly, the driver can accurately locate the required interrupt information, further improving the efficiency of obtaining interrupt information.

[0197] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0198] Based on the same inventive concept, the embodiment of the present application also provides an interrupt resource pooling processing device for implementing the interrupt resource pooling processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more interrupt resource pooling processing device embodiments provided below can refer to the limitations of the interrupt resource pooling processing method above, and will not be repeated here.

[0199] In an exemplary embodiment, Figure 8 As shown, an interrupt resource pooling processing device is provided, and the interrupt resource pooling processing device 800 may include:

[0200] The request receiving module 801 is used to receive an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device;

[0201] A mode determination module 802 is used to determine the interrupt arrangement mode of the target device according to the interrupt configuration information;

[0202] An address mapping module 803, used to map the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table according to the interrupt arrangement mode;

[0203] The target generation module 804 is used to generate a target virtual interrupt table corresponding to the target device according to the mapped management interrupt table and the mapped queue interrupt table, and output the target virtual interrupt table to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

[0204] In an exemplary embodiment, the device 800 also includes: an information acquisition module, which is used to receive an interrupt access request sent by a driver; obtain a target access address from the interrupt access request; and obtain target interrupt information from a mapped management interrupt table or a mapped queue interrupt table according to the target access address.

[0205] In an exemplary embodiment, the information acquisition module is also used to determine the interrupt table type based on the target access address; when the interrupt table type is a mapped management interrupt table, the target interrupt information is obtained from the mapped management interrupt table; when the interrupt table type is a mapped queue interrupt table, the target interrupt information is obtained from the mapped queue interrupt table.

[0206] In an exemplary embodiment, the apparatus 800 further includes: a message sending module, configured to generate an interrupt message according to target interrupt information; and send the interrupt message to a target address.

[0207] In an exemplary embodiment, the mode determination module 802 is further configured to identify location information of the management interrupt in the interrupt configuration information; and determine the interrupt arrangement mode according to the location information of the management interrupt.

[0208] In an exemplary embodiment, the mode determination module 802 is further used to determine the interrupt arrangement mode as the first interrupt arrangement mode when the position information of the management interrupt indicates the first position; and to determine the interrupt arrangement mode as the second interrupt arrangement mode when the position information of the management interrupt indicates the last position.

[0209] Each module in the above interrupt resource pooling processing device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0210] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Fig. 9As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for processing interrupt resource pooling is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0211] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0212] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0213] In an exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0214] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0215] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0216] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0217] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for processing interrupt resource pooling, characterized in that: The method comprises: Receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device; Determining an interrupt arrangement mode of the target device according to the interrupt configuration information; According to the interrupt arrangement mode, mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table; According to the mapped management interrupt table and the mapped queue interrupt table, a target virtual interrupt table corresponding to the target device is generated, and the target virtual interrupt table is output to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

2. The method according to claim 1, characterized in that The method further comprises: Receiving an interrupt access request sent by the driver; Obtaining a target access address from the interrupt access request; According to the target access address, target interrupt information is obtained from the mapped management interrupt table or the mapped queue interrupt table.

3. The method according to claim 2, characterized in that The step of acquiring target interrupt information from the mapped management interrupt table or the mapped queue interrupt table according to the target access address includes: Determine the interrupt table type according to the target access address; When the interrupt table type is the mapped managed interrupt table, acquiring the target interrupt information from the mapped managed interrupt table; In a case where the interrupt table type is the mapped queue interrupt table, the target interrupt information is acquired from the mapped queue interrupt table.

4. The method according to claim 2, characterized in that: The method further comprises: Generate an interrupt message according to the target interrupt information; The interrupt message is sent to a target address.

5. The method according to claim 1, characterized in that Determining the interrupt arrangement mode of the target device according to the interrupt configuration information includes: Identifying location information of the management interrupt in the interrupt configuration information; The interrupt arrangement mode is determined according to the location information of the management interrupt.

6. The method according to claim 5, characterized in that The determining the interrupt arrangement mode according to the location information of the management interrupt includes: In a case where the position information of the management interrupt indicates a first position, determining the interrupt arrangement mode to be a first interrupt arrangement mode; In a case where the position information of the managed interrupt indicates the last position, the interrupt arrangement mode is determined to be the second interrupt arrangement mode.

7. An interrupt resource pooling processing device, characterized in that: The device comprises: A request receiving module, used for receiving an interrupt configuration request for a target device sent by a driver; the interrupt configuration request includes interrupt configuration information of the target device; A mode determination module, used to determine the interrupt arrangement mode of the target device according to the interrupt configuration information; An address mapping module, used for mapping the access address of the virtual interrupt table to the access address of the management interrupt table and the access address of the queue interrupt table according to the interrupt arrangement mode; A target generation module is used to generate a target virtual interrupt table corresponding to the target device according to the mapped management interrupt table and the mapped queue interrupt table, and output the target virtual interrupt table to the driver; the driver is used to obtain the interrupt information in the mapped management interrupt table and the interrupt information in the mapped queue interrupt table through the target virtual interrupt table.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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