A data processing system, method, product, device and storage medium

Abstract

Embodiments of the present application relate to the technical field of data processing, in particular to a data processing system, method, product, device and storage medium, aiming to improve the data transmission speed between central processors and graphic processors. The data processing system comprises: a central processor cluster comprising a plurality of central processor cores and a first cluster shared cache; a graphic processor cluster comprising a plurality of graphic processor cores and a second cluster shared cache; a shared memory; each central processor core in the central processor cluster is provided with a second-level private cache; each graphic processor core in the graphic processor cluster is provided with a first-level private cache; in the case that the address contained in the received data write request of any central processor core in the central processor cluster is a graphic processor address, the corresponding data is written into the second cluster shared cache.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data processing, in particular, to a data processing system, method, product, device and storage medium. BACKGROUND

[0002] Heterogeneous multi-core processors integrate different types of computing units such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units) to provide a more flexible and efficient computing platform. This architecture takes advantage of the sequential processing capabilities of CPUs and the parallel processing capabilities of GPUs to adapt to various computing loads. In related technologies, the CPU is usually responsible for generating data and writing it back to the shared memory, and the GPU reads these data from the shared memory for calculation, generates a large amount of result data, and writes it back to the memory again.

[0003] In related technologies, this data transmission mode has a significantly increased transmission delay under high load due to frequent data transfer between the CPU and the GPU. In particular, if the required data cannot be obtained in time from the cache during GPU processing, a high cache miss rate will be caused, forcing the GPU to read data from the main memory, which slows down the processing speed and affects the overall system running speed of the heterogeneous multi-core processor. SUMMARY

[0004] Embodiments of the present application provide a data processing method, product, device and storage medium, aiming to improve the data transmission speed between the central processor and the graphics processor of a heterogeneous processor.

[0005] A first aspect of embodiments of the present application provides a data processing system, which comprises:

[0006] a central processor cluster comprising a first central processor core, a second central processor core, a third central processor core, a fourth central processor core and a first cluster shared cache;

[0007] a graphics processor cluster comprising a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core and a second cluster shared cache;

[0008] a shared memory for storing data readable by the central processor cluster and the graphics processor cluster;

[0009] each central processor core in the central processor cluster is provided with a two-level private cache;

[0010] each graphics processor core in the graphics processor cluster is provided with a one-level private cache;

[0011] In a case where the address included in the received data write request is a graphics processor address, the central processor core of any of the central processor clusters writes corresponding data to the second cluster shared cache.

[0012] Optionally, in a case where the storage space of the first-level private cache of each central processor core is insufficient, the cache line data that has not been accessed for the longest time in the first-level private cache is sent to the second-level private cache for storage.

[0013] In a case where the storage space of the second-level private cache is insufficient, the cache line data that has not been accessed for the longest time in the second-level private cache is sent to the first cluster shared cache for storage.

[0014] In a case where the storage space of the first cluster shared cache is insufficient, the cache line data that has not been accessed for the longest time in the first cluster shared cache is sent to the shared memory for storage.

[0015] Optionally, in a case where the storage space of the private cache of each graphics processor core is insufficient, the cache line data that has not been accessed for the longest time in the private cache is sent to the second cluster shared cache for storage.

[0016] In a case where the storage space of the second cluster shared cache is insufficient, the cache line data that has not been accessed for the longest time in the second cluster shared cache is sent to the shared memory for storage.

[0017] Optionally, in a case where each central processor core or graphics processor core writes data in the private cache, the cache state of the private cache is an exclusive state.

[0018] The second aspect of the embodiment of the application provides a data processing method, which is based on any of the data processing systems provided in the first aspect of the embodiment of the application, and comprises the following steps:

[0019] In a case where a first data read request sent by any central processor core in the central processor cluster is received, a first target address corresponding to the first data read request is determined.

[0020] In a case where the first target address is a central processor address, corresponding caches are sequentially queried in the central processor cluster according to the first target address.

[0021] In a case where the corresponding cache is queried, data corresponding to the first data read request is read from the cache.

[0022] Optionally, the method further comprises the following steps:

[0023] In the case that the corresponding cache is not queried, reading the data from the shared memory.

[0024] Optionally, the method further comprises:

[0025] In the case that the first target address is a graphics processor address, determining that the first target address is in a miss state in the central processor cluster;

[0026] Reading the data corresponding to the first target address in the shared memory.

[0027] Optionally, the step of querying the corresponding cache in the central processor cluster according to the first target address comprises:

[0028] Determining whether the first target address hits in a first-level private cache in each central processor core in the central processor cluster;

[0029] In the case that the first target address hits in the first-level private cache, determining that the first-level private cache is the cache corresponding to the first target address;

[0030] In the case that the first target address does not hit in the first-level private cache, determining whether the first target address hits in a second-level private cache in the central processor core;

[0031] In the case that the first target address hits in the second-level private cache, determining that the second-level private cache is the cache corresponding to the first target address;

[0032] In the case that the first target address does not hit in the second-level private cache, determining whether the first target address hits in a first cluster shared cache;

[0033] In the case that the first target address hits in the first cluster shared cache, determining that the first cluster shared cache is the cache corresponding to the first target address.

[0034] Optionally, the method further comprises:

[0035] In the case that a second data read request sent by any graphics processor core in a graphics processor cluster is received, determining a second target address corresponding to the second data read request;

[0036] According to the second target address, querying the corresponding cache in the graphics processor cluster;

[0037] In a case where the corresponding cache is queried, reading data corresponding to the second data read request from the cache.

[0038] Optionally, the method further comprises:

[0039] In a case where the corresponding cache is not queried, reading the data from shared memory.

[0040] Optionally, the step of querying the corresponding cache in the graphics processor cluster according to the second target address comprises:

[0041] determining whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster;

[0042] in a case where the second target address hits in the private cache, determining that the private cache is the cache corresponding to the second target address;

[0043] in a case where the second target address does not hit in the private cache, determining whether the second target address hits in a second cluster shared cache;

[0044] in a case where the second target address hits in the second cluster shared cache, determining that the second cluster shared cache is the cache corresponding to the second target address.

[0045] Optionally, the method further comprises:

[0046] in a case where the first data write request sent by the central processor core is received, determining a third target address corresponding to the first data write request;

[0047] in a case where the third target address is a central processor address, determining whether the third target address hits in a first-level private cache of a central processor core of the central processor cluster;

[0048] in a case where the third target address hits in the first-level private cache, determining whether a cache line state of the first-level private cache is an exclusive state;

[0049] in a case where the cache line state is not the exclusive state, changing the cache line state to the exclusive state;

[0050] in a case where the cache line state is the exclusive state, writing data corresponding to the first data write request into the first-level private cache.

[0051] Optionally, the method further comprises:

[0052] In a case where the third target address is not hit, cache replacement is performed, including:

[0053] storing cache line data in the first level private cache which has not been accessed for the longest time into a second level private cache;

[0054] writing the data corresponding to the first data write request into the first level private cache.

[0055] Optionally, the method further includes:

[0056] In a case where the third target address is a graphics processor address, determining whether the third target address is hit in a second cluster shared cache;

[0057] In a case where the third target address is hit, writing the data corresponding to the first data write request into the second cluster shared cache.

[0058] Optionally, the method further includes:

[0059] In a case where the third target address is not hit, cache replacement is performed, including:

[0060] storing cache line data in the second cluster shared cache which has not been accessed for the longest time into a shared memory;

[0061] writing the data corresponding to the first data write request into the second cluster shared cache.

[0062] Optionally, the method further includes:

[0063] In a case where a second data write request sent by any graphics processor core in a graphics processor cluster is received, determining a fourth target address corresponding to the second data write request;

[0064] determining whether the fourth target address is hit in a private cache of the graphics processor core;

[0065] In a case where the fourth target address is hit in the private cache, determining whether a cache line state of the private cache is an exclusive state;

[0066] In a case where the cache line state is not the exclusive state, changing the cache line state of the private cache to the exclusive state;

[0067] In a case where the cache line state is the exclusive state, writing the data corresponding to the second data write request into the private cache.

[0068] Optionally, the method further includes:

[0069] In the case that the fourth target address is not hit, cache replacement is performed, including:

[0070] storing the cache line data in the private cache which is not accessed for the longest time into a second cluster shared cache;

[0071] writing the second data write request into the private cache.

[0072] A third aspect of the embodiments of the present application provides a data processing apparatus, the apparatus comprising:

[0073] a first target address determination module configured to determine a first target address corresponding to a first data read request in the case that the first data read request is received from any central processor core in a central processor cluster;

[0074] a first cache query module configured to query a corresponding cache in the central processor cluster according to the first target address in the case that the first target address is a central processor address;

[0075] a first data read module configured to read data corresponding to the first data read request from the cache in the case that the corresponding cache is queried.

[0076] Optionally, the apparatus further comprises:

[0077] a second data read module configured to read the data from a shared memory in the case that the corresponding cache is not queried.

[0078] Optionally, the apparatus further comprises:

[0079] a first miss state determination module configured to determine that the first target address is in a miss state in the central processor cluster in the case that the first target address is a graphics processor address;

[0080] a third data read module configured to read the data corresponding to the first target address from a shared memory.

[0081] Optionally, the first cache query module comprises:

[0082] a first hit state determination submodule configured to determine whether the first target address hits in a first level private cache in each central processor core in the central processor cluster;

[0083] a first cache determination submodule configured to determine that the first level private cache is the cache corresponding to the first target address in the case that the first target address hits in the first level private cache.

[0084] a second hit status determining submodule, configured to determine whether the first target address hits in a second private cache in the central processor core in a case that the first target address does not hit in the first private cache;

[0085] a second cache determining submodule, configured to determine that the second private cache is the cache corresponding to the first target address in a case that the first target address hits in the second private cache;

[0086] a third hit status determining submodule, configured to determine whether the first target address hits in a first cluster shared cache in a case that the first target address does not hit in the second private cache;

[0087] a third cache determining submodule, configured to determine that the first cluster shared cache is the cache corresponding to the first target address in a case that the first target address hits in the first cluster shared cache.

[0088] Optionally, the apparatus further includes:

[0089] a second target address determining module, configured to determine a second target address corresponding to a second data read request sent by any of the graphics processor cores in the graphics processor cluster in a case that the second data read request is received;

[0090] a second cache querying module, configured to query a corresponding cache in the graphics processor cluster level by level according to the second target address;

[0091] a fourth data reading module, configured to read data corresponding to the second data read request from the cache in a case that the corresponding cache is queried.

[0092] Optionally, the apparatus further includes:

[0093] a fifth data reading module, configured to read the data from a shared memory in a case that the corresponding cache is not queried.

[0094] Optionally, the second cache querying module includes:

[0095] a fourth hit status determining submodule, configured to determine whether the second target address hits in a private cache in each of the graphics processor cores in the graphics processor cluster;

[0096] a fourth cache determining submodule, configured to determine that the private cache is the cache corresponding to the second target address in a case that the second target address hits in the private cache;

[0097] a fifth hit status determining submodule, configured to determine whether the second target address hits in a second cluster shared cache in a case that the second target address does not hit in the private cache;

[0098] a fifth cache determining submodule, configured to determine that the second cluster shared cache is the cache corresponding to the second target address in a case that the second target address hits in the second cluster shared cache.

[0099] Optionally, the apparatus further includes:

[0100] a third address determining module, configured to determine a third target address corresponding to a first data write request in a case that the first data write request is received;

[0101] a first hit status determining module, configured to determine whether the third target address hits in a first-level private cache of a central processing unit core of the central processing unit cluster in a case that the third target address is a central processing unit address;

[0102] a first cache line status determining module, configured to determine whether a cache line status of the first-level private cache is an exclusive state in a case that the third target address hits in the first-level private cache;

[0103] a first status changing module, configured to change the cache line status to the exclusive state in a case that the cache line status is not the exclusive state;

[0104] a first data writing module, configured to write the data corresponding to the first data write request into the first-level private cache in a case that the cache line status is the exclusive state.

[0105] Optionally, the apparatus further includes:

[0106] a first cache replacement module, configured to perform cache replacement in a case that the third target address does not hit, including:

[0107] storing cache line data of the first-level private cache that has not been accessed for the longest time into a second-level private cache;

[0108] a second data writing module, configured to write the data corresponding to the first data write request into the first-level private cache.

[0109] Optionally, the apparatus further includes:

[0110] a second hit status determining module, configured to determine whether the third target address hits in a second cluster shared cache in a case that the third target address is a graphics processing unit address;

[0111] The third data writing module is configured to write the data corresponding to the first data writing request into the second cluster shared cache in the case that the third target address hits.

[0112] Optionally, the apparatus further comprises:

[0113] The second cache replacement module is configured to perform cache replacement in the case that the third target address misses, including:

[0114] storing the cache line data which has not been accessed for the longest time in the second cluster shared cache into shared memory;

[0115] The fourth data writing module is configured to write the data corresponding to the first data writing request into the second cluster shared cache.

[0116] Optionally, the apparatus further comprises:

[0117] The fourth target address determination module is configured to determine a fourth target address corresponding to a second data writing request sent by any graphics processor core in a graphics processor cluster in the case that the second data writing request is received;

[0118] The third hit state determination module is configured to determine whether the fourth target address hits in a private cache of the graphics processor core;

[0119] The second cache line state determination module is configured to determine whether a cache line state of the private cache is in an exclusive state in the case that the fourth target address hits in the private cache;

[0120] The second state changing module is configured to change the cache line state of the private cache to the exclusive state in the case that the cache line state is not the exclusive state;

[0121] The fifth data writing module is configured to write the data corresponding to the second data writing request into the private cache in the case that the cache line state is the exclusive state.

[0122] Optionally, the apparatus further comprises:

[0123] The second cache replacement module is configured to perform cache replacement in the case that the fourth target address misses, including:

[0124] storing the cache line data which has not been accessed for the longest time in the private cache into a second cluster shared cache;

[0125] The sixth data writing module is configured to write the data corresponding to the second data writing request into the private cache.

[0126] The fourth aspect of the embodiments of the present application provides a product including computer programs / instructions, which, when executed by a processor, implement the steps in any of the methods provided in the first aspect of the present application.

[0127] The fifth aspect of the embodiments of the present application provides a readable storage medium having computer programs stored thereon, which, when executed by a processor, implement the steps in the method described in the first aspect of the present application.

[0128] The sixth aspect of the embodiments of the present application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps in the method described in the first aspect of the present application.

[0129] The data processing system provided in the present application includes a central processor cluster, a graphics processor cluster, and a shared memory. The central processor cluster includes a first central processor core, a second central processor core, a third central processor core, a fourth central processor core, and a first cluster shared cache. The graphics processor cluster includes a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core, and a second cluster shared cache. The shared memory is used to store data readable by the central processor cluster and the graphics processor cluster. Each central processor core in the central processor cluster is provided with a three-level cache, including a first-level private cache, a second-level private cache, and the first cluster shared cache. Each graphics processor core in the graphics processor cluster is provided with a two-level cache, including a private cache and the second cluster shared cache. In a case where an address included in a received data write request is a graphics processor address, any central processor core in the central processor cluster writes corresponding data to the second cluster shared cache, and the data is dirty data.

[0130] In the present application, the central processor cluster and the graphics processor cluster are provided. The central processor cluster includes two-level private memory and a first cluster shared cache, and the graphics processor cluster includes one-level private memory and a second cluster shared cache. In data storage, any central processor core can directly store graphics processor corresponding data to the second cluster shared cache, and the graphics processor core can directly obtain data from the second cluster shared cache, without the need to first store the data to the shared memory and then obtain the data from the shared memory by the graphics processor core, which significantly improves the performance and data access speed of the graphics processor, and further improves the efficiency of the entire system. BRIEF DESCRIPTION OF DRAWINGS

[0131] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0132] Figure 1 is a schematic diagram of a data processing system architecture according to an embodiment of the present application;

[0133] Figure 2 is a schematic diagram of an address space according to an embodiment of the present application;

[0134] Figure 3 is a schematic diagram of a second cluster shared cache structure according to an embodiment of the present application;

[0135] Figure 4 is a schematic diagram of a central processor data write according to an embodiment of the present application;

[0136] Figure 5 is a flowchart of a data processing method according to an embodiment of the present application;

[0137] Figure 6 is a flowchart of a central processor data read according to an embodiment of the present application;

[0138] Figure 7 is a flowchart of a graphics processor core data read according to an embodiment of the present application;

[0139] Figure 8 is a flowchart of a central processor data write according to an embodiment of the present application;

[0140] Figure 9 is a flowchart of a graphics processor data write according to an embodiment of the present application;

[0141] Figure 10 is a schematic diagram of a data processing device according to an embodiment of the present application;

[0142] Figure 11 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0143] The technical solutions of the embodiments of the present application will be described clearly and completely in the following description with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0144] Reference Figure 1 , Figure 1 is a data processing system architecture diagram proposed by an embodiment of the present application, as shown in the figure, the system comprises: Figure 1

[0145] a central processor cluster comprising a first central processor core, a second central processor core, a third central processor core, a fourth central processor core, and a first cluster shared cache; a graphics processor cluster comprising a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core, and a second cluster shared cache; a shared memory for storing data readable by the central processor cluster and the graphics processor cluster; each central processor core in the central processor cluster is provided with a three-level cache; each graphics processor core in the graphics processor cluster is provided with a two-level cache; in the case that an address contained in a data write request received by any central processor core in the central processor cluster is a graphics processor address, the corresponding data is written into the second cluster shared cache, and the data is dirty data.

[0146] in the case that the storage space of the first-level private cache of each central processor core is insufficient, the cache line data in the first-level private cache that has not been accessed for the longest time is sent to the second-level private cache for storage; in the case that the storage space of the second-level private cache is insufficient, the cache line data in the second-level private cache that has not been accessed for the longest time is sent to the first cluster shared cache for storage; in the case that the storage space of the first cluster shared cache is insufficient, the cache line data in the first cluster shared cache that has not been accessed for the longest time is sent to the shared memory for storage.

[0147] in the case that the storage space of the private cache of each graphics processor core is insufficient, the cache line data in the private cache that has not been accessed for the longest time is sent to the second cluster shared cache for storage; in the case that the storage space of the second cluster shared cache is insufficient, the cache line data in the second cluster shared cache that has not been accessed for the longest time is sent to the shared memory for storage.

[0148] in the case that each central processor core or graphics processor core writes data in the private cache, the cache state of the private cache is exclusive.

[0149] ​In this embodiment, the proposed data processing system is essentially a multi-core heterogeneous processor architecture. The central processor cluster (CPU cluster) is composed of 4 central processor cores, each of which contains a three-level cache, including a first-level private cache (L1), a second-level private cache (L2), and a first cluster shared cache. The graphics processor cluster is composed of 4 graphics processor cores, containing a two-level cache, including a private cache and a second cluster shared cache. The architecture also includes a shared memory (DRAM), and all central processor cores and graphics processor cores can store or read data in the shared memory.

[0150] In this embodiment, the central processor cluster follows the cache consistency principle when reading data. When a core wants to read data, it first queries the first-level private cache. If the first-level private cache is not hit, it queries the second-level private cache. If the second-level private cache is not hit, it reads data from the first cluster shared cache. If the first cluster shared cache has no data, it reads data from the shared memory.

[0151] In this embodiment, the central processor cluster also follows the cache consistency principle when writing data. When a core wants to write data, it first acquires an exclusive state to ensure that the cache behavior of the corresponding level in the remaining cores is invalid, and then executes the write operation, thus ensuring the cache consistency of each core in the cluster.

[0152] In this embodiment, the graphics processor cluster follows the cache consistency principle when reading data. When a core wants to read data, it first queries the first-level private cache. If the first-level private cache is not hit, it queries the second cluster shared cache. If the second cluster shared cache is not hit, it reads data from the shared memory.

[0153] In this embodiment, the graphics processor cluster writes data similarly to the central processor cluster. When a core wants to write data, it invalidates the data of the same cache line in the cache of other cores, so that the private cache of the core is in an exclusive state, and then executes the write operation.

[0154] In this embodiment, the second cluster shared cache is a cache that can be accessed by all graphics processor cores. In addition, data generated by the central processor cores can be directly written into the second cluster shared cache. Thus, the graphics processor cores do not need to obtain data from the shared memory when reading data, but can directly obtain data from the second cluster shared cache, thereby increasing the data reading speed.

[0155] Reference Figure 2 , Figure 2 is an address space diagram proposed by an embodiment of the present application, as Figure 2As shown, the address of the data is composed of the central processor address space and the graphics processor address space, and when receiving a data read or data write request, it is necessary to determine whether the target address is the central processor address or the graphics processor address, and according to the actual use scene, the proportion of the two spaces can be flexibly adjusted.

[0156] Reference Figure 3 , Figure 3 is a second cluster shared cache structure schematic diagram proposed by an embodiment of the application, as Figure 3 As shown, the second cluster shared cache includes data written by the central processor cluster and data written by the graphics processor cluster, and the graphics processor cluster can read any data in the second cluster shared cache. When the central processor core identifies the address as the graphics processor address, the data can be directly sent to the second cluster shared cache for caching.

[0157] In this embodiment, the data processing system uses CHI protocol to maintain cache consistency, and five states are defined to describe the cache line state in the cache.

[0158] Among them, I is invalid state, indicating that the data is invalid.

[0159] SC state is shared state, and the cache line data is clean (clean state data), that is, the data in the cache is the same as that in the memory, and there may be a cache line copy in other cores.

[0160] SD is a shared state, and the cache line data is dirty (dirty state data), that is, the data in the cache is different from that in the memory, and there may be a cache line copy in other cores.

[0161] UC is an exclusive state, and the cache line data is clean, and there is no cache line copy in other cores.

[0162] UD is an exclusive state, and the cache line data is clean, and there is no cache line copy in other cores.

[0163] In order to ensure the cache consistency of the system, the cache of the core writing data first acquires the exclusive state (UC state or UD state), so that when a core writes data in the cache, the corresponding cache line in the cache of the remaining cores is in invalid state, and when the data is finally sent to the shared memory for storage, only the cache line written by this core is stored, thereby ensuring the cache consistency of the system.

[0164] Reference Figure 4 , Figure 4 is a central processor data write schematic diagram, as Figure 4As shown, when the data generated by the central processor cluster wants to be written into the graphics processor cluster, the central processor core first checks the address domain segment on the address, if the address is the central processor address, the data is written into the cache corresponding to the central processor, if the address is the graphics processor address, the data is directly written into the second cluster shared cache, a core of the central processor cluster directly writes data into the second cluster shared cache, the written data is UD state, when the graphics processor core wants to read data, it is directly obtained from the second cluster shared cache.

[0165] In this embodiment, in the central processor cluster, two levels of private caches are included in the central processor core, the first level of private cache is the fastest and has the smallest space, the second level of private cache has larger space than the first level of private cache but slightly lower speed, and the first cluster shared cache has slower speed but larger space. In the graphics processor cluster, the private cache has the fastest speed and the smallest space, the second cluster shared cache has slower speed but larger space. The shared memory has the largest space but the slowest data access speed. When storing data, it is first stored into the first level of private cache, and the data not frequently used is stored into the second level of private cache, and so on. The storage order of the central processor core data is first level of private cache-second level of private cache-first cluster shared cache-shared memory, and the storage order of the graphics processor core data is private cache-second cluster shared cache-shared memory.

[0166] Reference Figure 5 , Figure 5 is a flowchart of a data processing method according to an embodiment of the present application. As shown in Figure 5 , the method comprises the following steps:

[0167] S11: In the case of receiving a first data read request sent by any central processor core in the central processor cluster, determining a first target address corresponding to the first data read request.

[0168] In this embodiment, the first data read request is a data read request sent by the central processor core, and the first target address is a data storage address contained in the data read request sent by the central processor core.

[0169] In this embodiment, reference Figure 6 , Figure 6 is a central processor data read flowchart according to an embodiment of the present application, as shown in Figure 6 , in the case of receiving a data read request sent by any central processor core, determining a first target address corresponding to the data read request.

[0170] S12: In a case where the first target address is a central processor address, a corresponding cache is queried in the central processor cluster according to the first target address.

[0171] In this embodiment, the central processor address is an address corresponding to data stored in the central processor cluster.

[0172] In this embodiment, as shown in FIG. 6, in a case where the first target address is a central processor address, a corresponding cache is queried in the central processor cluster according to the first target address, and specific steps include: Figure 6

[0173] S12-1: Whether the first target address hits in the first-level private cache in each central processor core in the central processor cluster is determined.

[0174] In this embodiment, the first target address hit means that the target address is found in the cache.

[0175] In this embodiment, the first target address is first found in the first-level private cache in each central processor core in the central processor cluster.

[0176] S12-2: In a case where the first target address hits in the first-level private cache, the first-level private cache is determined as the cache corresponding to the first target address.

[0177] In this embodiment, in a case where the first target address hits, that is, the first target address is found in the first-level private cache, the data required by the first data reading request is stored in the first-level private cache, and the first-level private cache is determined as the cache corresponding to the first target address.

[0178] S12-3: In a case where the first target address does not hit in the first-level private cache, whether the first target address hits in the second-level private cache in the central processor core is determined.

[0179] In this embodiment, in a case where the first target address does not hit, that is, the first target address is not found in the first-level private cache, the data required by the first data reading request is not stored in the first private cache, the data reading request is sent to the cache controller of the second-level private cache, and whether the first target address hits in the second-level private cache in the central processor core is determined.

[0180] ​In this embodiment, because the first-level private cache is closest to the core and has the fastest speed but the smallest storage space, the first-level private cache sends data to the second-level private cache in the case of insufficient storage space, the second-level private cache has larger space, and so on, and the shared memory has the largest space, so the query is performed in the order of the first private cache, the second private cache, the shared cache, and the shared memory in turn.

[0181] S12-4: In the case where the first target address hits in the second-level private cache, the second-level private cache is determined as the cache corresponding to the first target address.

[0182] In this embodiment, in the case where the first target address hits, that is, the first target address is found in the second-level private cache, the data required by the first data read request is stored in the second-level private cache, and the second-level private cache is determined as the cache corresponding to the second target address.

[0183] S12-5: In the case where the first target address does not hit in the second-level private cache, it is determined whether the first target address hits in the first cluster shared cache.

[0184] In this embodiment, in the case where the first target address does not hit, that is, the first target address is not found in the second-level private cache, the data required by the first data read request is not stored in the second-level private cache, and it is determined whether the first target address hits in the first cluster shared cache.

[0185] S12-6: In the case where the first target address hits in the first cluster shared cache, the first cluster shared cache is determined as the cache corresponding to the first target address.

[0186] In this embodiment, in the case where the first target address hits, the data required by the first data read request is stored in the first cluster shared cache, and the first cluster shared cache is determined as the cache corresponding to the first target address.

[0187] S13: In the case where the corresponding cache is found, the data corresponding to the data read request is read from the cache.

[0188] In this embodiment, in the case where the first target address hits and the corresponding cache is found, the data requested by the data read request is read from the corresponding cache.

[0189] In this embodiment, the method further includes:

[0190] S14: In the case where the corresponding cache is not found, the data is read from the shared memory.

[0191] In this embodiment, as shown in Figure 6 In the case where the corresponding cache is not queried, the data is directly read from the shared memory.

[0192] In this embodiment, the method further comprises:

[0193] S15: In the case where the first target address is a graphics processor address, it is determined that the first target address is in a miss state in the central processor cluster.

[0194] In this embodiment, in the case where the first target address is a graphics processor address, it is explained that the data required by the first data read request is stored in the cache corresponding to the graphics processor cluster and is not stored in the cache corresponding to the central processor cluster, and at this time, it is directly determined that the first target address is in a miss state in the central processor cluster.

[0195] S16: The data corresponding to the first target address is read in the shared memory.

[0196] In this embodiment, at this time, the data read request is directly sent to the shared memory controller, and the data corresponding to the first target address is read from the shared memory.

[0197] For example, a central processor core sends a read data request, first judges whether the address is a central processor address domain segment or a graphics processor address domain segment. If the address is a graphics processor address domain segment, the central processor core displays cache miss, and directly reads data from the memory. If the central processor first private cache hits, the data is directly read from the first private cache. If the first private cache misses, the read data request is sent to the second private cache controller, the second private cache hits, and the data is read from the hit core. If the first private cache and the second private cache both miss, the read data request is sent to the first cluster shared cache, and if the first cluster shared cache misses, the read data request is sent to the shared memory controller, and the data is directly read from the shared memory.

[0198] In another embodiment of the present application, the method further comprises:

[0199] S21: In the case where the second data read request sent by any graphics processor core in the graphics processor cluster is received, a second target address corresponding to the second data read request is determined.

[0200] In this embodiment, the second data read request is a data read request sent by a graphics processor core, and the second target address is a data storage address contained in the data read request sent by the graphics processor core.

[0201] In this embodiment, reference is made to Figure 7 ,Figure 7 is a data reading flowchart of a graphics processor core according to an embodiment of the present application, as shown in Figure 7 In a case where a second data reading request is received from any graphics processor core in the graphics processor cluster, a second target address corresponding to the second data reading request is determined.

[0202] S22: According to the second target address, a corresponding cache in the graphics processor cluster is queried step by step.

[0203] In this embodiment, according to the second target address, a corresponding cache in the graphics processor cluster is queried step by step, and the specific steps include:

[0204] S22-1: It is determined whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster.

[0205] In this embodiment, it is determined whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster, that is, whether the second target address is found in the private cache.

[0206] S22-2: In a case where the second target address hits in the private cache, the private cache is determined as the cache corresponding to the second target address.

[0207] In this embodiment, in a case where the second target address hits, that is, in a case where the second target address is found in the private cache, it is indicated that the data required to be read by the second data reading request is stored in the private cache of the graphics processor, and the private cache is determined as the cache corresponding to the second target address.

[0208] S22-3: In a case where the second target address does not hit in the private cache, it is determined whether the second target address hits in a second cluster shared cache.

[0209] In this embodiment, in a case where the second target address does not hit, that is, in a case where the second target address is not found in the private cache, it is indicated that the data required to be read by the second data reading request is not stored in the private cache of the graphics processor, and it is thus required to determine whether the second target address hits in the second cluster shared cache.

[0210] S22-4: In a case where the second target address hits in the second cluster shared cache, the second cluster shared cache is determined as the cache corresponding to the second target address.

[0211] In the embodiment, in the case that the second target address hits, i.e. in the case that the second target address is found in the second cluster shared cache, it is determined that the data required by the second data read request is stored in the second cluster shared cache, and the second cluster shared cache is the cache corresponding to the second target address.

[0212] S23: In the case that the corresponding cache is found, the data corresponding to the second data read request is read from the cache.

[0213] In the embodiment, in the case that the cache corresponding to the second target address is found, the data corresponding to the second data read request is read from the cache.

[0214] For example, a certain graphics processor core sends a read data request without determining the address domain segment. If the private cache (L1) does not hit, the data is directly read. If the private cache does not hit, the request is sent to the second cluster shared cache controller. If the second cluster shared cache hits, the data is directly returned. If the private cache and the second cluster shared cache both do not hit, the request is directly sent to the shared memory, and the data is read from the memory.

[0215] In another embodiment of the application, the method further comprises:

[0216] S31: In the case that the first data write request sent by the central processor core is received, a third target address corresponding to the first data write request is determined.

[0217] In the embodiment, the first data write request is a data write request sent by the central processor core, and the third target address is an address included in the data write request sent by the central processor core and required to write data into the storage.

[0218] In the embodiment, reference is made to Figure 8 , Figure 8 is a central processor data writing flowchart proposed by an embodiment of the application, as shown in Figure 8 In the case that the first data write request sent by the central processor core is received, a third target address corresponding to the first data write request is determined.

[0219] S32: In the case that the third target address is a central processor address, it is determined whether the third target address hits in a first-level private cache of a central processor core of the central processor cluster.

[0220] In the embodiment, as shown in Figure 8 In the case that the third target address is a central processor address, it is determined whether the third target address hits in a first-level private cache of a central processor core of the central processor cluster.

[0221] S33: determining whether the cache line state of the first level private cache is in the exclusive state in the case that the third target address is hit in the first level private cache.

[0222] In this embodiment, as shown in the figure, in the case that the third target address is hit, i.e. the third target address exists in the first level private cache, it is determined whether the running state of the first level private cache is in the exclusive state. Figure 8

[0223] S34: changing the cache line state to the exclusive state in the case that the cache line state is not the exclusive state.

[0224] In this embodiment, as shown in the figure, in the case that the cache line state is not the exclusive state, the cache line state is changed to the exclusive state in order to ensure cache consistency. At this time, the first private cache acquires the exclusive state from the processor, and the processor modifies the corresponding cache line in the remaining cores to the invalid state in the case that the request is received. Figure 8

[0225] S35: writing the data corresponding to the first data write request into the first level private cache in the case that the cache line state is the exclusive state.

[0226] In this embodiment, in the case that the cache line state is the exclusive state, the data corresponding to the first data write request is written into the first level private cache.

[0227] In this embodiment, the method further comprises:

[0228] S36: performing cache replacement in the case that the third target address is not hit, comprising:

[0229] storing the cache line data which has not been accessed for the longest time in the first level private cache into the second level private cache.

[0230] In this embodiment, in the case that the third target address is not hit, i.e. the third target address is not found in the first level private cache, cache replacement is performed. When cache replacement is performed, the cache line data which has not been accessed for the longest time in the first level private cache is stored into the second level private cache.

[0231] In this embodiment, a counter is set in each cache. Each time there is a data read request, the number corresponding to each cache line is incremented by one. When a data read request reads the data of a certain row, the number corresponding to the cache line is cleared. When it is necessary to release cache space, the cache line data corresponding to the largest number is determined as the cache line data which has not been accessed for the longest time, and the data is sent to the next level of cache for storage until it is sent to the shared memory. ​​

[0232] S37: write the data corresponding to the first data write request into the first level private cache.

[0233] In this embodiment, after sending the cache line data which has not been accessed for the longest time to the second level private cache, the data corresponding to the first data write request is written into the first level private cache.

[0234] In this embodiment, the method further comprises:

[0235] S38: in the case where the third target address is a graphics processor address, determining whether the third target address hits in the second cluster shared cache.

[0236] In this embodiment, as shown in Figure 8 In the case where the third target address is a graphics processor address, it is determined whether the third target address hits in the second cluster shared cache, i.e. whether the third target address exists in the second shared cluster.

[0237] S39: in the case where the third target address hits, write the data corresponding to the first data write request into the second cluster shared cache.

[0238] In this embodiment, in the case where the third target address hits, i.e. in the case where the third target address exists in the second cluster shared cache, the data corresponding to the first data write request is written into the second cluster shared cache.

[0239] In this embodiment, the method further comprises:

[0240] S310: in the case where the third target address does not hit, performing cache replacement, comprising:

[0241] storing the cache line data which has not been accessed for the longest time in the second cluster shared cache into shared memory.

[0242] In this embodiment, in the case where the third target address does not hit, i.e. in the case where the third target address does not exist in the second cluster shared cache, cache replacement is performed, and the cache line data which has not been accessed for the longest time in the second cluster shared cache is stored into shared memory.

[0243] S311: write the data corresponding to the first data write request into the second cluster shared cache.

[0244] In this embodiment, after performing cache replacement, the data corresponding to the first data write request is written into the second cluster shared cache.

[0245] In another embodiment of the present application, the method further comprises:

[0246] S41: In a case where a second data write request sent by any of the graphics processor cores in the graphics processor cluster is received, determine a fourth target address corresponding to the second data write request.

[0247] In this embodiment, the second data write request is a data write request sent by the graphics processor core, and the fourth target address is an address included in the data write request sent by the graphics processor core, at which data needs to be written into the storage.

[0248] S42: Determine whether the fourth target address hits in the private cache of the graphics processor core.

[0249] In this embodiment, it is determined whether the fourth target address hits in the private cache of the graphics processor core. Figure 9 , Figure 9 is a data writing process flowchart of a graphics processor according to an embodiment of the present application, as shown in FIG. 4, it is determined whether the fourth target address hits in the private cache of the graphics processor core, i.e., whether the fourth target address is in the private cache of the graphics processor core. Figure 9

[0250] S43: In a case where the fourth target address hits in the private cache, determine whether a cache line state of the private cache is an exclusive state.

[0251] In this embodiment, in a case where the fourth target address hits, it is determined whether the cache line state of the private cache is the exclusive state.

[0252] S44: In a case where the cache line state is not the exclusive state, change the cache line state of the private cache to the exclusive state.

[0253] In this embodiment, in a case where the cache line state is not the exclusive state, the cache line state of the private cache is changed to the exclusive state.

[0254] S45: In a case where the cache line state is the exclusive state, write data corresponding to the second data write request into the private cache.

[0255] In this embodiment, in a case where the cache line state is the exclusive state, data corresponding to the second data write request is written into the private cache.

[0256] In this embodiment, the method further includes:

[0257] S46: In a case where the fourth target address does not hit, perform cache replacement, including:

[0258] store cache line data in the private cache that has not been accessed for the longest time into the second cluster shared cache.

[0259] ​In the embodiment, in the case that the fourth target address is not hit, i.e., the fourth target address does not exist in the private cache, cache replacement is performed, and in the cache replacement, the cache line data with the longest time of not being accessed in the private cache is stored into the second cluster shared cache.

[0260] S47: writing the data corresponding to the second data write request into the private cache.

[0261] In the embodiment, after the cache replacement is completed, the data corresponding to the second data write request is written into the private cache.

[0262] In another embodiment of the present application, the architecture of the data processing system can be changed according to requirements, for example, the number of processor cores in the central processor cluster and the graphics processor cluster is expanded, and the multi-level cache in each central processor core and graphics processor core is expanded to ensure the data access speed of the processor core and further improve the running efficiency of the system.

[0263] In the above embodiment of the present application, a data processing system is designed, i.e., a heterogeneous multi-core processor architecture, which follows the cache consistency mechanism, and the central processor core can directly store data into the shared cache of the graphics processor cluster, greatly improving the data reading speed of the graphics processor core and further improving the running efficiency of the system.

[0264] Based on the same inventive concept, an embodiment of the present application provides a data processing device. Reference Figure 10 , Figure 10 is a schematic diagram of a data processing device 1000 according to an embodiment of the present application. As shown in Figure 10 , the device includes:

[0265] a first target address determination module 1001 configured to determine a first target address corresponding to a first data read request sent by any central processor core in the central processor cluster when the first data read request is received;

[0266] a first cache query module 1002 configured to query a corresponding cache in the central processor cluster according to the first target address in the case that the first target address is a central processor address;

[0267] a first data read module 1003 configured to read data corresponding to the first data read request from the cache in the case that the corresponding cache is queried.

[0268] Optionally, the device further includes:

[0269] The second data reading module is configured to read the data from the shared memory when the corresponding cache is not queried.

[0270] Optionally, the apparatus further comprises:

[0271] The first miss state determining module is configured to determine that the first target address is in a miss state in the central processor cluster when the first target address is a graphics processor address.

[0272] The third data reading module is configured to read the data corresponding to the first target address from the shared memory.

[0273] Optionally, the first cache querying module comprises:

[0274] The first hit state determining submodule is configured to determine whether the first target address hits in a first-level private cache in each central processor core in the central processor cluster.

[0275] The first cache determining submodule is configured to determine that the first-level private cache is the cache corresponding to the first target address when the first target address hits in the first-level private cache.

[0276] The second hit state determining submodule is configured to determine whether the first target address hits in a second-level private cache in the central processor core when the first target address misses in the first-level private cache.

[0277] The second cache determining submodule is configured to determine that the second-level private cache is the cache corresponding to the first target address when the first target address hits in the second-level private cache.

[0278] The third hit state determining submodule is configured to determine whether the first target address hits in a first cluster shared cache when the first target address misses in the second-level private cache.

[0279] The third cache determining submodule is configured to determine that the first cluster shared cache is the cache corresponding to the first target address when the first target address hits in the first cluster shared cache.

[0280] Optionally, the apparatus further comprises:

[0281] The second target address determining module is configured to determine a second target address corresponding to a second data reading request sent by any graphics processor core in a graphics processor cluster when the second data reading request is received.

[0282] a second cache query module, configured to query a corresponding cache in the graphics processor cluster according to the second target address;

[0283] a fourth data reading module, configured to read data corresponding to the second data reading request from the cache when the corresponding cache is queried.

[0284] Optionally, the apparatus further comprises:

[0285] a fifth data reading module, configured to read the data from shared memory when the corresponding cache is not queried.

[0286] Optionally, the second cache query module comprises:

[0287] a fourth hit status determination submodule, configured to determine whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster;

[0288] a fourth cache determination submodule, configured to determine that the private cache is the cache corresponding to the second target address when the second target address hits in the private cache;

[0289] a fifth hit status determination submodule, configured to determine whether the second target address hits in a second cluster shared cache when the second target address does not hit in the private cache;

[0290] a fifth cache determination submodule, configured to determine that the second cluster shared cache is the cache corresponding to the second target address when the second target address hits in the second cluster shared cache.

[0291] Optionally, the apparatus further comprises:

[0292] a third address determination module, configured to determine a third target address corresponding to a first data writing request sent by the central processor core when the first data writing request is received;

[0293] a first hit status determination module, configured to determine whether the third target address hits in a first-level private cache of a central processor core in the central processor cluster when the third target address is a central processor address;

[0294] a first cache line status determination module, configured to determine whether a cache line status of the first-level private cache is an exclusive state when the third target address hits in the first-level private cache;

[0295] The first state changing module is configured to change the cache line state to the exclusive state if the cache line state is not the exclusive state.

[0296] The first data writing module is configured to write the data corresponding to the first data writing request into the first-level private cache if the cache line state is the exclusive state.

[0297] Optionally, the apparatus further comprises:

[0298] The first cache replacement module is configured to perform cache replacement if the third target address is not hit, including:

[0299] storing cache line data in the first-level private cache which is not accessed for the longest time into a second-level private cache;

[0300] The second data writing module is configured to write the data corresponding to the first data writing request into the first-level private cache.

[0301] Optionally, the apparatus further comprises:

[0302] The second hit state determining module is configured to determine whether the third target address is hit in a second cluster shared cache if the third target address is a graphics processor address.

[0303] The third data writing module is configured to write the data corresponding to the first data writing request into the second cluster shared cache if the third target address is hit.

[0304] Optionally, the apparatus further comprises:

[0305] The second cache replacement module is configured to perform cache replacement if the third target address is not hit, including:

[0306] storing cache line data in the second cluster shared cache which is not accessed for the longest time into a shared memory;

[0307] The fourth data writing module is configured to write the data corresponding to the first data writing request into the second cluster shared cache.

[0308] Optionally, the apparatus further comprises:

[0309] The fourth target address determining module is configured to determine a fourth target address corresponding to a second data writing request if the second data writing request is received from any graphics processor core in a graphics processor cluster.

[0310] A third hit state determining module is configured to determine whether the fourth target address hits in a private cache of the graphics processor core;

[0311] A second cache line state determining module is configured to determine whether a cache line state of the private cache is an exclusive state in a case that the fourth target address hits in the private cache.

[0312] A second state changing module is configured to change the cache line state of the private cache to the exclusive state in a case that the cache line state is not the exclusive state.

[0313] A fifth data writing module is configured to write the data corresponding to the second data writing request into the private cache in a case that the cache line state is the exclusive state.

[0314] Optionally, the apparatus further comprises:

[0315] A second cache replacement module is configured to perform cache replacement in a case that the fourth target address does not hit, including:

[0316] storing cache line data in the private cache which has not been accessed for the longest time into a second cluster shared cache;

[0317] A sixth data writing module is configured to write the data corresponding to the second data writing request into the private cache.

[0318] Based on the same inventive concept, another embodiment of the present application provides a product comprising computer programs / instructions, which, when executed by a processor, implement the steps of the signal line design method according to any one of the above embodiments of the present application.

[0319] Based on the same inventive concept, another embodiment of the present application provides a readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the steps of the data processing method according to any one of the above embodiments of the present application.

[0320] Based on the same inventive concept, another embodiment of the present application provides an electronic device, Figure 11 is a schematic diagram of an electronic device 1100 according to an embodiment of the present application, which comprises a memory 1102, a processor 1101, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the data processing method according to any one of the above embodiments of the present application when executed.

[0321] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0322] The various embodiments in the specification are described in progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be mutually referred to.

[0323] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can adopt a computer program product in the form of being implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0324] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the method, terminal device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce an article of manufacture, including a device implemented in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0325] These computer program instructions can also be stored in a computer readable memory capable of directing the computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer readable memory produce a product including instruction apparatus, which implements the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0326] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are performed on the computer or other programmable terminal device to produce a computer implemented process, so that the instructions executed on the computer or other programmable terminal device provide a process for implementing the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0327] While preferred embodiments of the application have been described, those skilled in the art will appreciate that other modifications than those specifically described can be made within the scope of the application. Accordingly, the appended claims are intended to embrace all such alternatives as well as the embodiments specifically described.

[0328] Finally, it should be noted that, in the description above, relative terms such as first and second, etc. are used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0329] The data processing system, method, product, device and storage medium provided by the present application are described in detail above, the principles and implementation manners of the present application are described by applying specific examples in the present document, the above description of the embodiments is only for helping to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the above description of the present specification should not be understood as a limitation of the present application.

Claims

1. A data processing system, characterized by The data processing system comprises: a central processor cluster comprising a first central processor core, a second central processor core, a third central processor core, a fourth central processor core, and a first cluster shared cache; a graphics processor cluster comprising a first graphics processor core, a second graphics processor core, a third graphics processor core, a fourth graphics processor core, and a second cluster shared cache; a shared memory for storing data readable by both the central processor cluster and the graphics processor cluster; each central processor core in the central processor cluster is provided with a three-level cache comprising a first-level private cache, a second-level private cache, and the first cluster shared cache; each graphics processor core in the graphics processor cluster is provided with a two-level cache comprising a private cache and the second cluster shared cache; in a case where an address included in a received data write request is a graphics processor address, any central processor core in the central processor cluster writes corresponding data into the second cluster shared cache, the data being dirty data; any central processor core in the central processor cluster determines a corresponding cache according to a region segment at the address included in the received data write request, comprising: in a case where the address is a central processor address, the corresponding data is written into the corresponding cache of the central processor; in a case where the address is a graphics processor address, the corresponding data is written into the second cluster shared cache, the data being UD data, to ensure cache consistency of multi-core space; in a case where a data write request is received, any graphics processor core in the graphics processor cluster writes corresponding data of the data write request into the private cache; any central processor core directly stores the corresponding data of the graphics processor into the second cluster shared cache, and the graphics processor core acquires data from the second cluster shared cache.

2. The data processing system of claim 1, wherein, in a case where the storage space of the first-level private cache of each central processor core is insufficient, cache line data in the first-level private cache that has not been accessed for the longest time is sent to the second-level private cache for storage; in a case where the storage space of the second-level private cache is insufficient, cache line data in the second-level private cache that has not been accessed for the longest time is sent to the first cluster shared cache for storage; in a case where the storage space of the first cluster shared cache is insufficient, cache line data in the first cluster shared cache that has not been accessed for the longest time is sent to the shared memory for storage.

3. The data processing system of claim 1, wherein, in a case where the storage space of the private cache of each graphics processor core is insufficient, cache line data in the private cache that has not been accessed for the longest time is sent to the second cluster shared cache for storage; in a case where the storage space of the second cluster shared cache is insufficient, cache line data in the second cluster shared cache that has not been accessed for the longest time is sent to the shared memory for storage.

4. The data processing system of claim 1, wherein, In case each central processor core or graphics processor core writes data in the private cache, the cache state of the private cache is an exclusive state.

5. A data processing method, characterized by, The method is based on any one of the data processing systems as claimed in claims 1-4, comprising: In case a first data read request sent by any central processor core in the central processor cluster is received, determining a first target address corresponding to the first data read request, judging an address domain corresponding to the first target address, and determining whether the first target address is a central processor address or a graphics processor address; In case the first target address is a central processor address, querying a corresponding cache in the central processor cluster according to the first target address; In case the corresponding cache is queried, reading data corresponding to the first data read request from the cache; In case the first target address is a graphics processor address, determining that the first target address is in a miss state in the central processor cluster; Reading the data corresponding to the first target address in shared memory.

6. The data processing method according to claim 5, characterized in that, The querying a corresponding cache in the central processor cluster according to the first target address comprises: Determining whether the first target address hits in a first-level private cache in each central processor core in the central processor cluster; In case the first target address hits in the first-level private cache, determining that the first-level private cache is the cache corresponding to the first target address; In case the first target address misses in the first-level private cache, determining whether the first target address hits in a second-level private cache in the central processor core; In case the first target address hits in the second-level private cache, determining that the second-level private cache is the cache corresponding to the first target address; In case the first target address misses in the second-level private cache, determining whether the first target address hits in a first cluster shared cache; In case the first target address hits in the first cluster shared cache, determining that the first cluster shared cache is the cache corresponding to the first target address.

7. The data processing method according to claim 5, characterized in that, The method further comprises: In case a second data read request sent by any graphics processor core in the graphics processor cluster is received, determining a second target address corresponding to the second data read request; According to the second target address, querying a corresponding cache in the graphics processor cluster; In case the corresponding cache is queried, reading data corresponding to the second data read request from the cache.

8. The data processing method according to any one of claim 5 or claim 7, characterized in that, The method further comprises: In case the corresponding cache is not queried, reading the data from shared memory.

9. The data processing method according to claim 7, characterized in that, The querying a corresponding cache in the graphics processor cluster according to the second target address comprises: Determining whether the second target address hits in a private cache in each graphics processor core in the graphics processor cluster; determining that the private cache is the cache corresponding to the second target address in a case that the second target address hits in the private cache; determining whether the second target address hits in a second cluster shared cache in a case that the second target address misses in the private cache; determining that the second cluster shared cache is the cache corresponding to the second target address in a case that the second target address hits in the second cluster shared cache.

10. The data processing method according to claim 5, characterized in that, The method further comprises: determining a third target address corresponding to the first data write request in a case that the first data write request sent by the central processor core is received; determining whether the third target address hits in a first level private cache of a central processor core of the central processor cluster in a case that the third target address is a central processor address; determining whether a cache line state of the first level private cache is an exclusive state in a case that the third target address hits in the first level private cache; changing the cache line state to the exclusive state in a case that the cache line state is not the exclusive state; writing the data corresponding to the first data write request into the first level private cache in a case that the cache line state is the exclusive state.

11. The data processing method according to claim 10, characterized in that, The method further comprises: performing cache replacement in a case that the third target address misses, comprising: storing cache line data in the first level private cache which is not accessed for the longest time into a second level private cache; writing the data corresponding to the first data write request into the first level private cache.

12. The data processing method according to claim 10, characterized in that, The method further comprises: determining whether the third target address hits in a second cluster shared cache in a case that the third target address is a graphics processor address; writing the data corresponding to the first data write request into the second cluster shared cache in a case that the third target address hits.

13. The data processing method according to claim 12, characterized in that, The method further comprises: performing cache replacement in a case that the third target address misses, comprising: storing cache line data in the second cluster shared cache which is not accessed for the longest time into a shared memory; writing the data corresponding to the first data write request into the second cluster shared cache.

14. The data processing method according to claim 5, characterized by, The method further comprises: determining a fourth target address corresponding to the second data write request in a case that the second data write request sent by any graphics processor core in the graphics processor cluster is received; determining whether the fourth target address hits in a private cache of the graphics processor core; determining whether a cache line state of the private cache is an exclusive state in a case that the fourth target address hits in the private cache; changing the cache line state of the private cache to the exclusive state in a case that the cache line state is not the exclusive state; writing the data corresponding to the second data write request into the private cache in a case that the cache line state is the exclusive state.

15. The data processing method according to claim 14, characterized in that, The method further comprises: performing cache replacement in a case that the fourth target address misses, comprising: storing data of a cache line in the private cache that has not been accessed for the longest time into a second cluster shared cache; writing the data corresponding to the second data write request into the private cache.

16. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instructions, when executed by a processor, implement the steps of the method of any of claims 5 to 15.

17. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any of claims 5 to 15.

18. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor, when executing the computer program, implements the steps of the method of any of claims 5 to 15.

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