Interrupt control device and method, electronic equipment and computer readable storage medium

Abstract

The invention discloses an interrupt control device and method, electronic equipment and a non-volatile computer readable storage medium. The interrupt control device comprises an interrupt detection module, an interrupt arbitration module and an interrupt output module, the interrupt detection module is configured to detect a plurality of interrupt requests respectively sent by a plurality of target interrupt sources; the interrupt arbitration module is coupled with the interrupt detection module and is configured to perform an interrupt arbitration operation on the plurality of interrupt requests so as to select a target interrupt request from the plurality of interrupt requests; the interrupt output module is coupled with the interrupt arbitration module and is configured to output interrupt information according to the target interrupt request. The interrupt control device can reduce the area of a chip and effectively improve the performance, the power consumption and the area of the chip.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an interrupt control device and method, an electronic device, and a non-volatile computer-readable storage medium. Background Art

[0002] Ordinary interrupt handling architectures are usually used in processors, and there is a lack of advanced interrupt architecture design solutions that can better meet multi-core requirements. In addition, ordinary interrupt handling architectures may not be conducive to the physical layout and wiring of multi-core chips. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an interrupt control device, comprising: an interrupt detection module, configured to detect multiple interrupt requests respectively issued by multiple target interrupt sources; an interrupt arbitration module, coupled to the interrupt detection module and configured to perform interrupt arbitration operations on the multiple interrupt requests to select a target interrupt request from the multiple interrupt requests; and an interrupt output module, coupled to the interrupt arbitration module and configured to output interrupt information according to the target interrupt request.

[0004] For example, in the interrupt control device provided in an embodiment of the present disclosure, the interrupt arbitration module is further configured to perform the interrupt arbitration operation according to the interrupt identifiers and interrupt priorities of the multiple target interrupt sources.

[0005] For example, in an interrupt control device provided in an embodiment of the present disclosure, the interrupt output module is further configured to output the interrupt information to a target device corresponding to the interrupt request according to parameter information of an interrupt source corresponding to the target interrupt request.

[0006] For example, in an interrupt control device provided in an embodiment of the present disclosure, it also includes: a bus connection module, which is coupled to the bus and is configured to send the interrupt information through the bus coupled to the bus connection module.

[0007] For example, in the interrupt control device provided in an embodiment of the present disclosure, the bus connection module is configured to include: a bus write address channel, a bus write data channel and a bus write response channel.

[0008] For example, in the interrupt control device provided in one embodiment of the present disclosure, the interrupt detection module is further configured to determine whether corresponding to the multiple interrupt requests are received by detecting the detection bits corresponding to the multiple target interrupt sources respectively, and after outputting the interrupt information according to the target interrupt request, reset the detection bit corresponding to the interrupt source corresponding to the target interrupt request.

[0009] For example, in an interrupt control device provided in an embodiment of the present disclosure, the interrupt arbitration operation includes using a two-level interrupt arbitration tree to perform an interrupt arbitration operation.

[0010] For example, in an interrupt control device provided in an embodiment of the present disclosure, the interrupt output module is further configured to convert the parameter information of the interrupt source corresponding to the target interrupt request into the interrupt information according to the address conversion logic and the data conversion logic.

[0011] For example, in an interrupt control device provided in an embodiment of the present disclosure, the parameter information of the interrupt source corresponding to the target interrupt request includes: address coding information, interrupt priority information, interrupt source coding information, number of processors or number of processor cores.

[0012] For example, in an interrupt control device provided in an embodiment of the present disclosure, it also includes: a register control module, configured to store configuration information, wherein the configuration information is used to control the interrupt detection module, the interrupt arbitration module and / or the interrupt output module.

[0013] For example, in an interrupt control device provided in an embodiment of the present disclosure, the register control module includes multiple groups of registers, wherein each group of the multiple groups of registers includes multiple registers, and the multiple groups of registers are configured to correspond to multiple interrupt domains respectively.

[0014] For example, in an interrupt control device provided in an embodiment of the present disclosure, the register control module includes a plurality of registers, and the plurality of registers are configured to be used for a plurality of interrupt domains respectively in a time division multiplexing manner.

[0015] For example, in the interrupt control device provided in one embodiment of the present disclosure, the multiple registers are further configured to, when time division multiplexing is used for multiple interrupt domains, process interrupt requests belonging to an interrupt domain in an activated state and ignore interrupt requests belonging to an interrupt domain in an inactive state.

[0016] For example, in the interrupt control device provided in an embodiment of the present disclosure, the multiple interrupt domains include at least interrupt domains corresponding to a machine level and at least one management level.

[0017] For example, in an interrupt control device provided in an embodiment of the present disclosure, it also includes: a configuration message processing module configured to receive a configuration message and configure the register control module based on the configuration message.

[0018] For example, in the interrupt control device provided in one embodiment of the present disclosure, the configuration message complies with a first protocol, and the configuration message processing module is further configured to convert the configuration message that complies with the first protocol into a configuration command for configuring the register control module, and use the configuration command to configure the register control module.

[0019] For example, in an interrupt control device provided in an embodiment of the present disclosure, it also includes: multiple interrupt control modules, wherein each of the multiple interrupt control modules includes the interrupt detection module, the interrupt arbitration module and the interrupt output module corresponding to itself.

[0020] At least one embodiment of the present disclosure provides an interrupt control method, comprising: detecting multiple interrupt requests respectively issued by multiple target interrupt sources; performing interrupt arbitration operations on the multiple interrupt requests to select a target interrupt request from the multiple interrupt requests; and outputting interrupt information according to the target interrupt request.

[0021] At least one embodiment of the present disclosure provides an electronic device, including the interrupt control device provided by any embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure provides a non-volatile computer-readable storage medium for non-temporarily storing computer-readable instructions, and when the computer-readable instructions are executed by a computer, the interrupt control method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 A schematic block diagram of an interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 2 A schematic block diagram of another interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 3 An example diagram of an application of an interrupt control device provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 4 A diagram showing an application example of another interrupt control device provided by at least one embodiment of the present disclosure;

[0028] Figure 5 An example diagram of an application of an interrupt control device is shown;

[0029] Figure 6 A diagram showing an application example of yet another interrupt control device provided by at least one embodiment of the present disclosure;

[0030] Figure 7 A schematic flow chart of an interrupt control method provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0032] Fig. 9 A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0033] Fig.10 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] With the continuous development and improvement of the RISC-V (Reduced Instruction Set Computer-V) ecosystem, processor cores, SoC (System on Chip) and other chip products designed and produced using the RISC-V architecture have gradually been put into use in various fields, promoting the innovation and development of the entire industry. In particular, in recent years, with the rapid development of artificial intelligence technology, the computing power requirements for chips have become increasingly higher. Therefore, the demand for multi-core SoC chips based on RISC-V is also gradually increasing.

[0037] Multi-core SoC chips can better meet the computing needs of increasingly complex application scenarios, thereby achieving higher performance, lower power consumption, and better processor core collaboration. However, in multi-core SoC chips, different cores need to communicate and collaborate with each other, and there are many peripherals and devices that need to communicate with the processor core, which requires an effective interrupt control device to manage and distribute interrupt signals from various external devices or other cores, so that the interrupt signal can be correctly transmitted to the corresponding processor core, the processing system can respond to external events in a timely manner, and improve the stability and reliability of the processing system.

[0038] The inventors of the present disclosure have noticed that for a RISC-V processor, if the advanced interrupt architecture involved in the RISC-V Advanced Interrupt Architecture White Paper released by the RISC-V development community is adopted, and the message interrupt transmission method specified in the RISC-V Advanced Interrupt Architecture White Paper protocol is adopted, it may cause the interrupt control device to have problems such as increased chip area and power consumption relative to the ordinary interrupt architecture.

[0039] For example, in a multi-core chip, interrupt transmission modes may include linear interrupts (also called “direct interrupts”) and message interrupts.

[0040] Linear interrupt refers to an interrupt request that can be transmitted through an interrupt line. The interrupt request can be, for example, an internal event from an external device or the processor itself. For example, when data arrives from an external device, a timer is completed, or other events that need to be processed occur, the external device can send an interrupt signal to the processor to request the processor to suspend the current task and process the interrupt service program instead. After receiving the interrupt signal, the processor will save the current execution state, jump to the pre-defined interrupt service program to execute the corresponding processing logic, and return to the original task to continue execution after the processing is completed. In the interrupt transmission mode of linear interrupt, the transmission of interrupts is based on the interrupt line between the external device and the interrupt control device, and the interrupt control device and the processor. One interrupt line will only act on one processor core, and the number of interrupt lines is often positively correlated with the number of processor cores.

[0041] If the interrupt received by the processor core is information parsed from bus transactions, the interrupt transmission mode is called a message interrupt. Message interrupts can respond when data arrives from an external device, a timer is completed, or other events that need to be processed occur. In the interrupt transmission mode of message interrupts, the interrupt control device can collect and summarize interrupt sources from various devices and arbitrate the interrupt to be transmitted to the processor core based on the priority of the interrupt. Unlike linear interrupts, during the message interrupt transmission process, the connection between the interrupt control device and the processor is not a direct interrupt line, but a set of standardized buses.

[0042] The interrupt transmission method using message interrupts can better serve multi-core chips. For example, in multi-core SoC chips, the communication and collaboration between different cores are very close, and the communication between peripherals and multiple processor cores is more complicated than in the case of a single core. The transmission characteristics of bus transactions can enable interrupt information to accurately reach the target processor core, and there is no need for complex layout and routing. If interrupt information is transmitted in linear interrupts, there may be complex routing relationships between processor cores, which is a huge test for chip design. However, if interrupt information is transmitted in the form of message interrupts, the routing of interrupt information between processor cores can rely solely on bus transmission, without relying on complex interrupt lines to achieve communication between interrupt control devices and processor cores.

[0043] In chip design, the PPA (Performance, Power, Area) indicator is based on a comprehensive consideration of the three aspects of chip performance, power consumption and area. PPA is an important indicator for evaluating the quality of a chip design and a key factor in determining chip cost and performance. The performance of a chip can affect the performance of the chip in a specific application scenario, including operating speed, response time, etc. Good performance means that the chip can complete tasks faster and improve the overall efficiency of the system. The power consumption of a chip can affect the battery life, heat dissipation requirements and environmental impact of electronic devices. The area refers to the physical space occupied by the chip. For integrated circuits, the size of the area is related to the manufacturing cost, the size of the finished package, and the heat dissipation effect.

[0044] The inventors of the present disclosure also noticed that if the message interrupt transmission mode is adopted in a multi-core chip, although it is beneficial to the communication between the interrupt controller and the processor core and avoids the complex wiring problem of the linear interrupt transmission interrupt line, it may also increase the area and power consumption of the multi-core chip. In addition, in the actual operation of the chip, each time an interrupt is triggered, it is necessary to start the transmission of a transaction on the bus on the interrupt control device, which means that an additional bus transmission module needs to be introduced to support the communication mode of message interrupt. Therefore, compared with linear interrupt, the area of ​​the chip will increase to a certain extent. In addition, in order to realize message interrupt, the protocol of the RISC-V development community stipulates a large number of registers related to interrupt control, such as interrupt sources, interrupt domains and interrupt targets, but this will further increase the overall area of ​​the chip.

[0045] In view of the above problems, at least one embodiment of the present disclosure provides an interrupt control device and method, an electronic device and a non-volatile computer-readable storage medium. The interrupt control device includes: an interrupt detection module, an interrupt arbitration module and an interrupt output module; the interrupt detection module is configured to detect multiple interrupt requests respectively issued by multiple target interrupt sources; the interrupt arbitration module is coupled to the interrupt detection module and is configured to perform interrupt arbitration operations on multiple interrupt requests to select a target interrupt request from the multiple interrupt requests; the interrupt output module is coupled to the interrupt arbitration module and is configured to output interrupt information according to the target interrupt request. The interrupt control device can reduce the area of ​​the chip and effectively improve the performance, power consumption and area of ​​the chip.

[0046] For example, at least one example of the above-mentioned embodiments of the present disclosure proposes an architecture scheme for an interrupt control device based on, for example, RISC-V. This architecture scheme can effectively improve the performance of the interrupt control device. While meeting the multi-core interrupt requirements and complying with the RISC-V protocol, by reasonably dividing the different usage modes of interrupt-related registers, the number of registers can be reduced by nearly half, thereby greatly reducing the chip area and effectively improving the PPA of the chip.

[0047] Figure 1 A schematic block diagram of an interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0048] like Figure 1 As shown, the interrupt control device 100 includes an interrupt detection module 110 , an interrupt arbitration module 120 and an interrupt output module 130 . The interrupt arbitration module 120 is coupled to the interrupt detection module 110 , and the interrupt output module 130 is coupled to the interrupt arbitration module 120 .

[0049] The interrupt detection module 110, the interrupt arbitration module 120 and the interrupt output module 130 work together to realize the detection, arbitration and output processing of multiple interrupt requests, thereby achieving timely and accurate transmission of interrupt signals and effective processing of interrupt events.

[0050] The interrupt detection module 110 is configured to detect a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0051] The interrupt arbitration module 120 is configured to perform an interrupt arbitration operation on the plurality of interrupt requests to select a target interrupt request from the plurality of interrupt requests.

[0052] The interrupt output module 130 is configured to output interrupt information according to the target interrupt request.

[0053] For example, in at least one embodiment, in a multi-core SoC chip, the interrupt detection module 110 may be configured to monitor a plurality of interrupt requests respectively issued from a plurality of different target interrupt sources.

[0054] For example, these multiple target interrupt sources may include interrupts generated by external devices (such as sensors, communication interfaces, timers, etc.), and may also include interrupts triggered by internal events of the processor (such as software exceptions, internal timer overflows, etc.). For example, when a target interrupt source detects a specific event or meets a preset condition, the target interrupt source may send an interrupt request signal to the interrupt detection module 110.

[0055] For example, the interrupt detection module 110 can identify and capture these interrupt request signals, monitor each interrupt source, and when an interrupt request is detected, preliminarily process the relevant information of the interrupt request (such as the interrupt source identifier, interrupt type, etc.), and then provide it to the interrupt arbitration module 120 for further processing.

[0056] For example, the interrupt arbitration module 120 may be configured to arbitrate multiple interrupt requests arriving at the same time to determine which interrupt requests should be processed with priority.

[0057] For example, the interrupt arbitration module 120 can be configured to sort multiple interrupt requests according to a preset priority rule. For example, the priority rule can be determined based on factors such as the urgency of the interrupt, the importance of the interrupt source, the current load of the processor, etc., and the embodiments of the present disclosure are not limited to this. Through the arbitration process, the interrupt arbitration module 120 can select the interrupt request with the highest priority as the target interrupt request, and provide the target interrupt request to the interrupt output module 130 for further operation.

[0058] For example, the interrupt arbitration operation includes performing the interrupt arbitration operation in a manner such as using a one-level interrupt arbitration tree, a two-level interrupt arbitration tree, or a multi-level interrupt arbitration tree, and the embodiments of the present disclosure are not limited thereto.

[0059] For example, the interrupt output module 130 may be configured to convert the target interrupt request selected by the interrupt arbitration module 120 into specific interrupt information, and accurately route the interrupt information to the processor core responsible for processing the interrupt.

[0060] For example, in a multi-core SoC chip, different processor cores may be responsible for processing different tasks or applications. Therefore, the interrupt output module 130 may determine to which processor core the interrupt information is to be transmitted based on the nature and priority of the target interrupt request, or the current state and task load of the processor core.

[0061] In some embodiments of the present disclosure, the interrupt arbitration module 120 may be further configured to perform an interrupt arbitration operation according to the interrupt identifiers and interrupt priorities of multiple target interrupt sources.

[0062] For example, the interrupt arbitration module 120 receives multiple interrupt requests provided by the interrupt detection module 110. For example, for each interrupt request received, the interrupt arbitration module 120 can identify the target interrupt source that issued the interrupt request. For example, the interrupt arbitration module 120 can determine the target interrupt source by reading an interrupt identifier (ID) sent together with the interrupt request.

[0063] For example, after determining the target interrupt source, the interrupt arbitration module 120 may also determine the priority of each interrupt request. For example, the interrupt arbitration module 120 may be completed by consulting a predefined priority table or configuration, in which the priority of each interrupt source or interrupt type may be specified.

[0064] For example, after determining the target interrupt source and the priority information of each interrupt request, the interrupt arbitration module 120 may perform an interrupt arbitration operation according to the interrupt identifiers and interrupt priorities of the multiple target interrupt sources. For example, the interrupt arbitration module 120 may compare the priorities of all currently received interrupt requests and select the interrupt request with the highest priority as the target interrupt request.

[0065] For example, when there are multiple interrupt requests with the same highest priority at the same time, the interrupt arbitration module 120 can also resolve the priority conflict according to preset corresponding rules (such as polling, fixed order, etc.) and select one of them as the target interrupt request.

[0066] In at least one embodiment of the present disclosure, the interrupt arbitration module 120 performs its arbitration function by considering the interrupt identifier and interrupt priority of the interrupt source, so that the interrupt control device can respond to multiple simultaneous interrupt requests in an orderly and efficient manner.

[0067] In some embodiments of the present disclosure, the interrupt output module 130 is further configured to output interrupt information to a target device corresponding to the interrupt request according to parameter information of an interrupt source corresponding to the target interrupt request.

[0068] For example, the interrupt output module 130 receives the target interrupt request provided by the interrupt arbitration module 120 , and then the interrupt output module 130 may use the identifier of the target interrupt request as an index to retrieve parameter information of the interrupt source corresponding to the target interrupt request.

[0069] For example, after determining the parameter information of the interrupt source corresponding to the target interrupt request, the interrupt output module 130 may convert the parameter information into interrupt information.

[0070] Figure 2 A schematic block diagram of another interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0071] like Figure 2 As shown, the interrupt control device 100 may further include a bus connection module 140. The bus connection module 140 is coupled to the bus, thereby connecting the interrupt control device 100 to the bus and communicating with other parts of the system connected to the bus; the bus connection module 140 may be configured to send the interrupt information through the bus coupled to the bus connection module 140.

[0072] For example, the bus connection module 140 is a component of the interrupt control device 100, which is responsible for sending interrupt information to other parts of the system.

[0073] As described above, the interrupt control device 100 is connected to the bus via the bus connection module 140 . The bus may be, for example, a communication line for data transmission between the interrupt control device 100 and other devices outside the interrupt control device 100 (eg, multiple processor cores).

[0074] For example, when the interrupt detection module 110 detects an interrupt request and the interrupt arbitration module 120 has selected a target interrupt request, the interrupt output module 130 generates corresponding interrupt information. The interrupt information is then sent by the interrupt output module 130 to the bus connection module 140, which sends the interrupt information to the outside of the interrupt control device 100 (e.g., to the processor core corresponding to the interrupt information) through the bus, so as to respond to and process the interrupt request in a timely manner.

[0075] In some embodiments of the present disclosure, the bus connection module 140 is configured to include a bus write address channel, a bus write data channel, and a bus write response channel.

[0076] For example, the bus write address channel may be used to transmit target address information corresponding to a target interrupt request carried in the interrupt information.

[0077] For example, after the interrupt output module 130 generates interrupt information, the interrupt output module 130 may send the target address information to the bus through the bus write address channel.

[0078] For example, the target address information may include the address of the processor core to which the target interrupt request is directed.

[0079] For example, the bus write data channel may be used to transmit data information corresponding to the target interrupt request carried in the interrupt information.

[0080] For example, the bus write response channel may be used to receive a response to an interrupt message.

[0081] For example, when the processor core receives the interrupt information and completes the processing, it can send a corresponding response signal through the bus write response channel to indicate that the interrupt request has been received and processed. The response signal indicates that the interrupt information has been correctly transmitted and processed.

[0082] In at least one embodiment of the present disclosure, the bus connection module 140 includes a bus write address channel, a bus write data channel and a bus write response channel, which can enable effective transmission and processing of interrupt information between the interrupt control device 100 and multiple processor cores, so that the interrupt information can accurately reach the target processor core and respond to the target interrupt request in a timely manner.

[0083] In some embodiments of the present disclosure, the interrupt output module 130 may include address conversion logic and data conversion logic, and is further configured to convert parameter information of the interrupt source corresponding to the target interrupt request into interrupt information according to the address conversion logic and the data conversion logic.

[0084] For example, the address conversion logic may convert the parameter information into a physical address on a bus or an index address of an interrupt vector table, so that the interrupt information may be correctly sent to a designated location of a target device or processor.

[0085] For example, the address conversion logic may include a preset address conversion rule or a mapping table, etc. The embodiments of the present disclosure do not limit the specific form of the address conversion logic.

[0086] For example, the data conversion logic may convert parameter information of the interrupt source corresponding to the target interrupt request into a data format that can be transmitted on the bus.

[0087] For example, the data conversion logic can convert the data information of the interrupt source corresponding to the target interrupt request into a corresponding format (such as byte order, bit width, etc.) according to the data representation specification and communication protocol in the processor architecture (such as RISC-V architecture) protocol. The embodiments of the present disclosure do not limit the specific form of the data conversion logic.

[0088] In at least one embodiment of the present disclosure, the interrupt output module 130 converts the parameter information of the interrupt source corresponding to the target interrupt request into interrupt information that can be transmitted to the corresponding processor core through the bus through address conversion logic and data conversion logic, thereby improving the accuracy and effectiveness of the interrupt information and providing reliable guarantee for timely interrupt response and processing.

[0089] In some embodiments of the present disclosure, for example, the parameter information of the interrupt source corresponding to the target interrupt request may include: address coding information, interrupt priority information, interrupt source coding information, number of processors or number of processor cores, etc., and the embodiments of the present disclosure are not limited to this.

[0090] For example, the interrupt information may include bus write address channel information, bus write data channel information, bus write response channel information, etc., which is not limited in the embodiments of the present disclosure.

[0091] For example, the address encoding information may include a logical address or index of an interrupt service routine (ISR) in memory or an interrupt vector table.

[0092] For example, in the RISC-V architecture, the interrupt vector table can be used to store pointers to ISRs, and address encoding information can be used to locate these pointers.

[0093] For example, the interrupt priority information may include the interrupt priority of the interrupt source corresponding to the target interrupt request in a system where multiple interrupt sources coexist.

[0094] For example, the interrupt source encoding information may refer to identification information of an interrupt source corresponding to a target interrupt request, and may be used to identify the source of the interrupt.

[0095] For example, the address conversion logic can be further used to convert the address encoding information into a physical address or an index address of an interrupt vector table that can be recognized and transmitted by the bus. Exemplarily, the interrupt output module can parse the address encoding part in the interrupt source parameter to obtain the logical address or index of the interrupt service program; use a preset address mapping table or conversion rule to convert the logical address or index into a physical address or interrupt vector index; and encapsulate the converted physical address or interrupt vector index as part of the bus write address channel information and prepare to send it through the bus.

[0096] For example, the data conversion logic can be further used to convert the parameter information of the interrupt source (such as interrupt priority information, interrupt source encoding information, etc.) into a data format that can be transmitted on the bus. Exemplarily, the data conversion logic can format the parameter information such as interrupt priority information, interrupt source encoding information, etc. into a byte sequence or data packet according to the data representation specification and communication protocol of the processor architecture (such as RISC-V architecture). Afterwards, the formatted parameter information can be encapsulated into interrupt information together with the bus write address channel information.

[0097] In some embodiments of the present disclosure, the interrupt detection module 110 is further configured to determine whether multiple interrupt requests are received by detecting detection bits corresponding to multiple target interrupt sources respectively, and after outputting interrupt information according to the target interrupt request, reset the detection bit corresponding to the interrupt source corresponding to the target interrupt request.

[0098] For example, the interrupt detection module 110 is configured to detect detection bits corresponding to a plurality of target interrupt sources.

[0099] For example, each interrupt source may have a corresponding detection bit (e.g., a pending bit) for indicating whether the interrupt source has issued an interrupt request. When the pending bit of an interrupt source is pulled high (e.g., set to 1), it may indicate that the interrupt source has an interrupt request to be processed. The interrupt detection module 110 may determine whether interrupt requests corresponding to multiple interrupt sources have been received by checking the state of a corresponding pending bit for each interrupt source.

[0100] For example, when the interrupt arbitration module 120 selects a target interrupt request and the interrupt output module 130 outputs interrupt information according to the target interrupt request, the interrupt detection module 110 may perform a reset operation. For example, the reset operation may include resetting (e.g., clearing or setting to 0) the pending bit of the interrupt source corresponding to the target interrupt request.

[0101] In this way, the interrupt control device can perform a corresponding reset operation after the interrupt processing is completed, so that subsequent interrupt requests can be processed correctly and repeated responses to interrupts that have been processed can be avoided.

[0102] In some embodiments of the present disclosure, Figure 2 As shown, the interrupt control device 100 further includes a register control module 150. The register control module 150 may be configured to store configuration information; for example, the register control module 150 may be configured to store and manage configuration information related to the interrupt control device 100.

[0103] For example, the register control module 150 is coupled to the interrupt detection module 110 , the interrupt arbitration module 120 , and the interrupt output module 130 , respectively.

[0104] For example, the configuration information may be used to control the interrupt detection module 110 , the interrupt arbitration module 120 and / or the interrupt output module 130 .

[0105] For example, the configuration information may be used to define specific parameters or rules of an interrupt detection operation, an interrupt arbitration operation, and an interrupt output operation.

[0106] For example, the configuration information may be used to control the interrupt detection module 110 , the interrupt arbitration module 120 , and the interrupt output module 130 to perform corresponding operations.

[0107] In some embodiments of the present disclosure, the register control module 150 includes multiple groups of registers, each of which includes multiple registers, and the multiple groups of registers are configured to correspond to multiple interrupt domains respectively.

[0108] For example, the register control module 150 may include multiple groups of registers, and each group of registers may be configured to store and manage configuration information associated with a specific interrupt domain.

[0109] For example, each group of registers may include multiple registers, which may be used to store different types of configuration information, for example.

[0110] For example, each interrupt domain may be used to correspond to a specific set of interrupt sources, which may come from different hardware devices or software modules.

[0111] For example, each group of registers in the register control module 150 may be configured to form a one-to-one mapping relationship with a specific interrupt domain, and each interrupt domain may correspond to a group of registers for storing and managing interrupt-related configuration information in the interrupt domain.

[0112] In at least one embodiment of the present disclosure, the interrupt control device 100 can provide a modular and configurable interrupt management mechanism through the register control module 150. The mapping relationship between multiple groups of registers and multiple interrupt domains can more flexibly respond to and process interrupt requests from different interrupt sources, thereby improving the efficiency of interrupt processing.

[0113] In some embodiments of the present disclosure, the register control module 150 includes a plurality of registers, and the plurality of registers are configured to be used for a plurality of interrupt domains respectively in a time division multiplexing manner.

[0114] For example, the register control module 150 may include a plurality of registers, and the registers may be configured to store corresponding configuration information.

[0115] For example, in the register control module 150, multiple registers can use time division multiplexing to manage multiple interrupt domains. For example, each interrupt domain can be used to manage a group of specific interrupt sources. Through time division multiplexing technology, multiple registers in the register control module 150 can manage different interrupt domains in different time periods.

[0116] For example, time can be divided into multiple continuous time slices, each time slice corresponds to a specific interrupt domain, and in each time slice, multiple registers in the register control module 150 can be used to store and manage the configuration information of the interrupt domain corresponding to the time slice. For example, as time goes by, the register control module 150 can switch the interrupt domain it manages according to the switching of the time slice. For example, the switching of different interrupt domains by the register control module 150 can be triggered by the configuration information.

[0117] In at least one embodiment of the present disclosure, the interrupt control device 100 uses the register control module 150 to implement effective management and configuration of multiple interrupt domains in a time-division multiplexing manner, further improving the efficiency and flexibility of interrupt processing.

[0118] In some embodiments of the present disclosure, multiple registers are further configured to process interrupt requests belonging to an activated interrupt domain and ignore interrupt requests belonging to an inactive interrupt domain when time division multiplexing is used for multiple interrupt domains.

[0119] For example, when a certain interrupt domain is in an activated state, the interrupt request sent by the interrupt source in the activated interrupt domain needs to be processed and responded to. In this case, the multiple registers in the register control module 150 can normally store and manage the configuration information of the interrupt domain in the activated state, and ensure that the interrupt detection module 110, the interrupt arbitration module 120 and the interrupt output module 130 can correctly process the interrupt request from the interrupt domain in the activated state.

[0120] For example, when an interrupt domain is in an inactive state, an interrupt request from an interrupt source in the inactive interrupt domain will be ignored. In this case, the registers in the register control module 150 will not store or update configuration information for the inactive interrupt domain, and other modules of the interrupt control device 100 will not process interrupt requests from the inactive interrupt domain.

[0121] For example, the register control module 150 can dynamically adjust the use of registers according to the activation state of the interrupt domain. For example, when a certain interrupt domain is switched from an inactive state to an active state, the register control module 150 can allocate corresponding register resources to the interrupt domain switched to the active state, and store and manage the configuration information of the interrupt domain. On the contrary, when a certain interrupt domain is switched from an active state to an inactive state, the register control module 150 can release the register resources occupied by the interrupt domain switched to the inactive state.

[0122] In some embodiments of the present disclosure, the plurality of interrupt domains include at least an interrupt domain corresponding to a machine level and at least one management level.

[0123] For example, a machine-level interrupt domain may be used to manage or process interrupts related to the entire system of an electronic device. Machine-level interrupts may be processed, for example, in M-mode (i.e., machine mode (Machine Mode, M-mode)). Machine-level interrupts may include, for example, hardware fault interrupts, system-level abnormal interrupts, etc., which are critical to the stability and security of the entire system of the electronic device. Machine-level interrupts may be, for example, interrupts that need to be processed immediately.

[0124] For example, the management-level interrupt domain can be used to manage or process interrupts related to specific management functions or tasks. Management-level interrupts can be processed, for example, in S-mode (i.e., Supervisor Mode, S-mode) and responded to by the operating system or hypervisor of the electronic device. Management-level interrupts can include, for example, electronic device driver interrupts, task scheduling interrupts, etc.

[0125] In some embodiments of the present disclosure, Figure 2 As shown, the interrupt control device 100 further includes a configuration message processing module 160 .

[0126] The configuration message processing module 160 is configured to receive a configuration message and configure the register control module 150 based on the configuration message.

[0127] For example, the configuration message processing module 160 may be configured to receive configuration messages from external sources (eg, software, other hardware modules, etc.).

[0128] For example, the configuration message may include instructions or data on how to configure the interrupt control device 100 .

[0129] For example, the configuration message may include a target register address, a parameter value to be written, an operation type (eg, read, write, modify), and the like.

[0130] For example, upon receiving a configuration message, the configuration message processing module 160 may parse the configuration message to extract necessary information, such as a target register, an operation to be performed, and related parameters.

[0131] For example, after parsing the configuration message, the configuration message processing module 160 can perform corresponding configuration on the register control module 150 according to the extracted information, which may include writing a specific value to a specified register, modifying an existing register value, or reading a register status for subsequent processing, etc. The embodiments of the present disclosure are not limited to this.

[0132] In some embodiments of the present disclosure, the configuration message complies with a predetermined protocol (referred to herein as the "first protocol"); the configuration message processing module 160 is further configured to convert the configuration message that complies with the first protocol into a configuration command for configuring the register control module 150, and use the configuration command to configure the register control module 150.

[0133] For example, the configuration message may be encoded according to a specific format and a first protocol.

[0134] For example, in the case of using a RISC-V processor, the first protocol may include the RISC-V Advanced Interrupt Architecture protocol or other related protocols.

[0135] For example, the first protocol may be used to define the structure of a configuration message, the meaning of fields, and the transmission and processing rules of the message.

[0136] For example, the configuration message may include information such as controlling the interrupt detection module, the interrupt arbitration module, and the interrupt output module to perform corresponding interrupt detection operations, interrupt arbitration operations, and interrupt output operations.

[0137] For example, the configuration message may include information such as the address of a target register or an operation parameter (such as a value to be written or output).

[0138] For example, the configuration message processing module 160 may receive a configuration message conforming to the first protocol from an external source through a specific interface module or a communication bus.

[0139] For example, after receiving the configuration message, the configuration message processing module 160 may parse the message to extract necessary information, and convert the information into a configuration command for configuring the register control module 150 according to the provisions of the first protocol. For example, this conversion process may include decoding the message, verifying the integrity of the message, checking the validity of the fields, and generating a corresponding configuration command according to the message content.

[0140] For example, after the aforementioned conversion is completed, the configuration message processing module 160 may use the generated configuration command to configure the register control module 150 .

[0141] In some embodiments of the present disclosure, Figure 2 As shown, the interrupt control device 100 further includes a plurality of interrupt control modules 170. Each of the plurality of interrupt control modules 170 includes an interrupt detection module 110, an interrupt arbitration module 120 and an interrupt output module 130 corresponding to itself.

[0142] For example, each interrupt control module 170 includes an interrupt detection module 110 , an interrupt arbitration module 120 and an interrupt output module 130 corresponding to itself, so as to perform corresponding interrupt request detection operations, interrupt arbitration operations and interrupt information output operations respectively.

[0143] For example, each interrupt control module 170 can interact with the register control module 150, and control the interrupt detection module 110, the interrupt arbitration module 120 and the interrupt output module 130 to perform corresponding interrupt request detection operations, interrupt arbitration operations and interrupt information output operations through the configuration information stored in the register control module 150.

[0144] For example, the interrupt detection module 110, the interrupt arbitration module 120, the interrupt output module 130, the bus connection module 140, the register control module 150, the configuration message processing module 160 and the interrupt control module 170 involved in the above embodiments can be hardware, software, firmware and any feasible combination thereof. For example, the interrupt detection module 110, the interrupt arbitration module 120, the interrupt output module 130, the bus connection module 140, the register control module 150, the configuration message processing module 160 and the interrupt control module 170 can be dedicated or general circuits, chips or devices, etc., or can be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation form of the above-mentioned units.

[0145] It should be noted that, in the embodiment of the present disclosure, each module of the interrupt control device 100 may correspond to each step of the interrupt control method (described below). Figure 1 as well as Figure 2 The components and structures of the interrupt control device 100 shown are merely exemplary and not restrictive. The interrupt control device 100 may further include other components and structures as required.

[0146] Figure 3 A diagram showing an application example of an interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0147] In the following, the interrupt control device 200 is taken as an example to exemplarily describe the interrupt control device involved in the embodiment of the present disclosure.

[0148] In some embodiments of the present disclosure, Figure 3 As shown, the interrupt control device 200 may include a register control module 251 , an interrupt detection module 211 , an interrupt arbitration module 221 , an interrupt output module 230 , and a configuration message processing module 260 .

[0149] For example, in the interrupt control device 200, the register control module 251 is respectively coupled to the configuration message processing module 260, the interrupt detection module 211, the interrupt arbitration module 221 and the interrupt output module 230, the interrupt detection module 211 is coupled to the interrupt arbitration module 221, and the interrupt arbitration module 221 is coupled to the interrupt output module 230.

[0150] For example, the configuration message processing module 260 can receive a configuration message that complies with the first protocol through the software configuration bus, and convert the configuration message into a configuration command for configuring the register control module 251, and use the configuration command to configure the register control module 251 to obtain configuration information, which can be used to control the interrupt detection module 211, the interrupt arbitration module 221 and the interrupt output module 230 to perform corresponding interrupt detection operations, interrupt arbitration operations and interrupt output operations.

[0151] For example, the interrupt detection module 211 receives multiple interrupt requests respectively issued by multiple peripheral interrupt sources. The interrupt detection module 211 can be further configured to determine whether an interrupt source among the multiple peripheral interrupt sources has an interrupt pulled up (i.e., the pending bit is pulled high), that is, whether the interrupt detection module 211 has received an interrupt request issued by the corresponding interrupt source. The interrupt detection module 211 can determine whether the corresponding interrupt request is received by detecting the detection bits (i.e., pending bits) corresponding to the multiple interrupt sources.

[0152] For example, the interrupt arbitration module 211 may perform interrupt arbitration on the received multiple interrupt requests to determine the winning interrupt request (i.e., the target interrupt request) among the multiple interrupt requests. For example, the interrupt arbitration module 211 may perform interrupt arbitration using a secondary arbitration tree according to the interrupt identifiers and interrupt priorities of the interrupt sources corresponding to the multiple interrupt requests to determine the target interrupt request.

[0153] For example, the interrupt output module 230 can be configured to output interrupt information according to the target interrupt request. For example, the interrupt output module 230 can be configured to convert the parameter information of the interrupt source corresponding to the target interrupt request (for example, address encoding information, interrupt priority information, interrupt source encoding information, number information of processors, and number information of processor cores) into interrupt information (for example, bus write address channel information, bus write data channel information, and bus write response channel information) according to the address conversion logic and data conversion logic. For example, the interrupt output module 230 can be configured to adopt the transmission mode of message interruption, provide the interrupt information to the bus through the bus connection module 240, and transmit it to the processor core corresponding to the target interrupt request through the bus.

[0154] For example, after the interrupt output module 230 outputs the interrupt information, the interrupt detection module 221 may also be configured to reset the detection bit corresponding to the interrupt source corresponding to the target interrupt request (eg, clear the pending bit of the interrupt source).

[0155] For example, in some embodiments, the enabling (e.g., interrupt pull-up) and clearing of the interrupt pending bit may be related to a variety of factors, such as the interrupt source mode (e.g., the operating mode of the interrupt source), the sending mode of the interrupt domain, or the state of the correction input value of the interrupt source (e.g., it can be used to indicate that the high-valid and low-valid interrupt trigger types are corrected to a unified mode input. For example, if the trigger type of an interrupt is a low-valid interrupt trigger type, the interrupt will be triggered only when the input interrupt signal is a low-level signal. After correction processing, it can be corrected to a high-valid interrupt trigger type, that is, the interrupt is triggered when the input interrupt signal is a high-level signal).

[0156] In some embodiments of the present disclosure, the interrupt control device 200 may further include an interrupt arbitration module 222 , which is coupled to the register control module 251 and the interrupt detection module 211 .

[0157] For example, the interrupt arbitration module 222 may perform interrupt arbitration on the received multiple interrupt requests to determine the winning interrupt request (i.e., the target interrupt request) among the multiple interrupt requests. For example, the interrupt arbitration module 222 may perform interrupt arbitration using a secondary arbitration tree based on the interrupt identifiers and interrupt priorities of the interrupt sources corresponding to the multiple interrupt requests to determine the target interrupt request.

[0158] For example, the interrupt arbitration module 222 may also be configured to provide the target interrupt request to the corresponding processor core in a linear interrupt manner.

[0159] In some embodiments of the present disclosure, the interrupt control device 200 may further include a register control module 252 , an interrupt detection module 212 , and an interrupt arbitration module 223 / 224 .

[0160] For example, in the interrupt control device 200, the register control module 252 is coupled to the configuration message processing module 260, the interrupt detection module 212, the interrupt arbitration module 223 / 224 and the interrupt output module 230 respectively, the interrupt detection module 212 is coupled to the interrupt arbitration module 223 / 224, and the interrupt arbitration module 223 is coupled to the interrupt output module 230.

[0161] For example, the register control module 252 may be configured to store and manage configuration information, which may be used to control the interrupt detection module 212, the interrupt arbitration module 223 / 224 and / or the interrupt output module 230 to perform corresponding interrupt detection operations, interrupt arbitration operations and interrupt output operations.

[0162] For example, the relevant operations, functions or beneficial effects performed by the register control module 252, the interrupt detection module 212, and the interrupt arbitration module 223 / 224 can refer to the relevant descriptions about the register control module 251, the interrupt detection module 211, and the interrupt arbitration module 221 / 221 in the aforementioned embodiments, and will not be repeated here.

[0163] In some embodiments of the present disclosure, the register control module 251 / 252 in the interrupt control device 200 may include multiple registers, and the multiple registers may be configured to be used for multiple interrupt domains respectively in a time division multiplexing manner.

[0164] For example, the plurality of interrupt domains at least include an interrupt domain corresponding to a machine level and at least one management level.

[0165] For example, the machine-level interrupt domain may correspond to the register control module 251, and thus to the interrupt detection module 211, the interrupt arbitration modules 221 and 222, see Figure 3 The dotted box in the upper middle.

[0166] For example, the management-level interrupt domain may correspond to the register control module 252, and thus to the interrupt detection module 212, the interrupt arbitration modules 223 and 224, see Figure 3 The dotted box in the lower middle.

[0167] For example, the interrupt detection module 211 / 212, the interrupt arbitration module 221-224, the interrupt output module 130, the bus connection module 140, the register control module 251 / 252, and the configuration message processing module 260 involved in the above embodiments can be hardware, software, firmware, and any feasible combination thereof. For example, the interrupt detection module 211 / 212, the interrupt arbitration module 221-224, the interrupt output module 130, the bus connection module 140, the register control module 251 / 252, and the configuration message processing module 260 can be a dedicated or general circuit, chip or device, etc., or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation form of the above-mentioned units.

[0168] It should be noted that, in the embodiment of the present disclosure, the related operations, functions or beneficial effects performed by the various modules of the interrupt control device 200 may also refer to the related description about the interrupt control device 100 in the aforementioned embodiment. Figure 3 The components and structures of the interrupt control device 200 shown are merely exemplary and non-limiting. The interrupt control device 200 may further include other components and structures as required.

[0169] Figure 4 A diagram showing an application example of another interrupt control device provided by at least one embodiment of the present disclosure is shown.

[0170] The following takes message interruption as an example to exemplarily describe the method for generating interruption information in the interruption control device.

[0171] Figure 4 The method for generating interrupt information shown can be applied to an interrupt output module, for example.

[0172] For example, the interrupt output module may be configured to output interrupt information according to the target interrupt request determined by the interrupt arbitration module.

[0173] For example, the interrupt output module can be configured to convert the parameter information of the interrupt source corresponding to the target interrupt request (for example, address coding information, interrupt priority information, interrupt source coding information, number of processors, and number of processor cores) into interrupt information (for example, bus write address channel information, bus write data channel information, and bus write response channel information) according to the address conversion logic and data conversion logic.

[0174] For example, the interrupt output module may be configured to adopt a message interrupt transmission mode to transmit the interrupt information to the processor core corresponding to the target interrupt request through the bus.

[0175] Here, the interrupt output module converts the parameter information of the interrupt source corresponding to the target interrupt request into the interrupt information according to the address conversion logic and the data conversion logic. For example, the relevant contents may refer to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0176] Figure 5 A diagram showing an application example of an interrupt control device.

[0177] like Figure 5 As shown, some possible implementations of the register control module in the interrupt control device are exemplarily described.

[0178] For example, the register control module may include multiple groups of registers, and the multiple groups of registers may be configured to correspond to multiple interrupt domains respectively.

[0179] For example, the register control module may include at least one set of machine-level registers 310 and multiple sets of management-level registers 320 .

[0180] For example, each group of machine-level registers 310 and each group of management-level registers 320 correspond to an interrupt domain respectively.

[0181] For example, each group of machine-level registers 310 and each group of management-level registers 320 may be configured to form a one-to-one mapping relationship with a specific interrupt domain, and each interrupt domain may correspond to a group of registers for storing and managing interrupt-related configuration information within the interrupt domain.

[0182] For example, when the interrupt control device receives multiple interrupt requests respectively issued by multiple interrupt sources, the register control module can determine the interrupt domains corresponding to the multiple interrupt requests and the registers corresponding to these interrupt domains.

[0183] For example, each group of registers can control the interrupt arbitration module to determine the target interrupt request through the configuration information stored therein, and control the interrupt output module to output interrupt information according to the target interrupt request in a message interrupt manner.

[0184] For example, based on the delegation relationship in the RISC-V interrupt architecture, the interrupt processing can be transferred from one mode to another mode. For example, from M mode to S mode. Exemplarily, when the interrupt domain corresponding to the machine-level register 310 does not match or does not completely match the received multiple interrupt requests, the management-level register 320 can be delegated to handle these interrupt requests, and so on and so forth to the next management-level register 320.

[0185] Figure 6 A diagram showing an application example of yet another interrupt control device provided by at least one embodiment of the present disclosure.

[0186] like Figure 6As shown, some possible implementations of the register control module in the interrupt control device are exemplarily described.

[0187] For example, multiple interrupt domains may share a set of registers. For example, each set of registers may include configuration information required by multiple interrupt domains.

[0188] For example, the register control module may include at least one group of machine-level registers and multiple groups of management-level registers. Exemplarily, it may include one group of machine-level registers and two groups of management-level registers.

[0189] For example, the machine-level register may be actually present in the hardware module. For example, the machine-level register may be coupled to the configuration message processing module, the interrupt detection module, the interrupt arbitration module, and the interrupt output module respectively.

[0190] For example, the management-level register may be actually present in the hardware module. For example, the management-level register may be coupled to the configuration message processing module, the interrupt detection module, the interrupt arbitration module, and the interrupt output module respectively.

[0191] For example, multiple interrupt domains can share a set of management-level registers.

[0192] For example, a unique identifier may be assigned to each interrupt domain, and when accessing a shared register group, the interrupt domain identifier may be checked to determine which register groups are accessible to the current interrupt domain.

[0193] For example, the interrupt delegation mechanism of RISC-V (e.g., through machine-level registers or management-level registers, etc.) can be used to delegate interrupt processing to the corresponding processing mode (e.g., M mode or S mode). For example, each interrupt domain can be responsible for processing a specific set of interrupt requests, and when these interrupt requests are issued, the processing flow of the corresponding interrupt domain can be entered.

[0194] For example, in another possible implementation, a time division multiplexing method may be used to enable multiple interrupt domains to share a set of registers.

[0195] For example, in the case of time division multiplexing, management and control of a group of registers shared by multiple interrupt domains can be implemented through software.

[0196] Here, the specific implementation method of using time division multiplexing to realize that multiple interrupt domains share a set of registers can also refer to the relevant description of the aforementioned embodiment, and will not be repeated here.

[0197] Figure 7 A flowchart of an interrupt control method provided by at least one embodiment of the present disclosure is shown.

[0198] like Figure 7As shown, the interrupt control method may include steps S500 to S520. The interrupt control method may also be applied to the interrupt control device 100 or the interrupt control device 200 provided in the above embodiments, and the embodiments of the present disclosure are not limited thereto.

[0199] Step S500: Detecting a plurality of interrupt requests respectively issued by a plurality of target interrupt sources.

[0200] Step S510: performing an interrupt arbitration operation on the multiple interrupt requests to select a target interrupt request from the multiple interrupt requests.

[0201] Step S520: Outputting interrupt information according to the target interrupt request.

[0202] In some embodiments of the present disclosure, step S510 may further include: performing an interrupt arbitration operation according to interrupt identifiers and interrupt priorities of multiple target interrupt sources.

[0203] In some embodiments of the present disclosure, step S520 may further include: outputting interrupt information to a target device corresponding to the interrupt request according to parameter information of an interrupt source corresponding to the target interrupt request.

[0204] In some embodiments of the present disclosure, the interrupt control method may further include step S530.

[0205] Step S530: sending the interruption information via the bus coupled to the bus connection module.

[0206] In some embodiments of the present disclosure, the bus connection module is configured to include: a bus write address channel, a bus write data channel, and a bus write response channel.

[0207] In some embodiments of the present disclosure, step S500 may further include: determining whether multiple interrupt requests are received by detecting detection bits corresponding to multiple target interrupt sources respectively; and after outputting interrupt information according to the target interrupt request, resetting the detection bit corresponding to the interrupt source corresponding to the target interrupt request.

[0208] In some embodiments of the present disclosure, the interrupt arbitration operation includes using a two-level interrupt arbitration tree to perform the interrupt arbitration operation.

[0209] In some embodiments of the present disclosure, step S520 may further include: converting parameter information of the interrupt source corresponding to the target interrupt request into interrupt information according to the address conversion logic and the data conversion logic.

[0210] In some embodiments of the present disclosure, the parameter information of the interrupt source corresponding to the target interrupt request includes: address encoding information, interrupt priority information, interrupt source encoding information, and information on the number of processors or the number of processor cores.

[0211] In some embodiments of the present disclosure, the interrupt control method may further include step S540.

[0212] Step S540: the control register control module stores configuration information. Here, the configuration information is used to control the interrupt detection module, the interrupt arbitration module and / or the interrupt output module.

[0213] In some embodiments of the present disclosure, the register control module includes multiple groups of registers, each of the multiple groups of registers includes multiple registers, and the multiple groups of registers are configured to correspond to multiple interrupt domains respectively.

[0214] In some embodiments of the present disclosure, the register control module includes a plurality of registers. For example, the plurality of registers are configured to be used for a plurality of interrupt domains respectively in a time division multiplexing manner.

[0215] In some embodiments of the present disclosure, step S540 may further include: when time division multiplexing is used for multiple interrupt domains, processing interrupt requests belonging to an interrupt domain in an activated state, and ignoring interrupt requests belonging to an interrupt domain in an inactive state.

[0216] In some embodiments of the present disclosure, the plurality of interrupt domains include at least an interrupt domain corresponding to a machine level and at least one management level.

[0217] In some embodiments of the present disclosure, the interrupt control method may further include step S550.

[0218] Step S550: Control the configuration message processing module to receive the configuration message, and configure the register control module based on the configuration message.

[0219] In some embodiments of the present disclosure, the configuration message complies with the first protocol; step S550 may further include: converting the configuration message complying with the first protocol into a configuration command for configuring the register control module, and using the configuration command to configure the register control module.

[0220] In some embodiments of the present disclosure, each of the plurality of interrupt control modules includes an interrupt detection module, an interrupt arbitration module and an interrupt output module corresponding to itself.

[0221] The interrupt control method may further include step S560. Step S560: using the multiple interrupt control modules to respectively control the interrupt detection module, the interrupt arbitration module and the interrupt output module corresponding to each of the multiple interrupt control modules.

[0222] It should be noted that, for the functions or beneficial effects of each step in the above interrupt control method, for example, reference may be made to the description of the interrupt control device 100 in the above embodiment, which will not be repeated here.

[0223] Figure 8 1 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure also provides an electronic device, such as Figure 8 As shown, the electronic device 600 includes an interrupt control device 610. The interrupt control device 610 may include, for example, the interrupt control device 100 provided in any of the above embodiments. The electronic device can reduce the chip area and effectively improve the chip performance, power consumption and area.

[0224] For example, the electronic device 600 may further include a processor 620 and a memory 630. The memory 630 is used to store computer-readable instructions (e.g., one or more computer program modules) in a non-temporary manner. The processor 620 is used to execute the computer-readable instructions, and when the computer-readable instructions are executed by the processor 620, one or more steps in the interrupt control method described above may be executed. The memory 630 and the processor 620 may be interconnected via a bus system and / or other forms of connection mechanisms, which are not limited in the embodiments of the present disclosure.

[0225] For example, the processor 620 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be a RISC architecture (e.g., RISC-V), etc. The processor 620 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0226] For example, the memory 630 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 620 may run one or more computer program modules to implement various functions of the electronic device 600. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0227] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 600 can refer to the above description of the interrupt control method, which will not be repeated here.

[0228] Fig. 9 A schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure is shown.

[0229] At least some embodiments of the present disclosure also provide an electronic device, such as Fig. 9 As shown, the electronic device 700 includes an interrupt control device 708. For example, the interrupt control device 708 may include an interrupt control device provided by any embodiment of the present disclosure.

[0230] The electronic devices in the embodiments of the present disclosure may include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0231] For example, Fig. 9As shown, in some examples, the electronic device 700 includes a processor 701 (e.g., a central processing unit, a graphics processor, etc.), which may include a processor involved in any embodiment of the present disclosure, and the processor 701 can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device (not shown) to a random access memory (RAM) 703. In RAM 703, various programs and data required for the operation of the computer system are also stored. The processor 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0232] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed, so that the computer programs read therefrom can be installed into the storage device as needed. Although Fig. 9 The electronic device 700 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0233] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0234] For example, the electronic device 700 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0235] At least one embodiment of the present disclosure also provides a non-volatile computer-readable storage medium, which is used to non-temporarily store computer-readable instructions, and when the computer-readable instructions are executed by a computer, the above-mentioned interrupt control method can be implemented. Using this computer-readable storage medium, the area of ​​the chip can be reduced, and the performance, power consumption and area of ​​the chip can be effectively improved.

[0236] Fig.10 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Fig.10 As shown, the non-volatile computer-readable storage medium 800 is used to store computer-readable instructions 810. For example, when the computer-readable instructions 810 are executed by a computer, one or more steps in the interrupt control method described above can be executed.

[0237] For example, the non-volatile computer-readable storage medium 800 can be applied to the electronic device 600 or the electronic device 700. For example, the relevant description of the non-volatile computer-readable storage medium 800 can also refer to Fig. 9 The corresponding description of the storage device in the electronic device 700 is shown and will not be repeated here.

[0238] There are a few points to note:

[0239] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0240] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0241] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An interruption control device, comprising: An interrupt detection module is configured to detect a plurality of interrupt requests respectively issued by a plurality of target interrupt sources; an interrupt arbitration module, coupled to the interrupt detection module and configured to perform an interrupt arbitration operation on the multiple interrupt requests to select a target interrupt request from the multiple interrupt requests; as well as The interrupt output module is coupled to the interrupt arbitration module and is configured to output interrupt information according to the target interrupt request.

2. The interruption control device according to claim 1, wherein: The interrupt arbitration module is further configured to perform the interrupt arbitration operation according to the interrupt identifiers and interrupt priorities of the multiple target interrupt sources.

3. The interruption control device according to claim 1, wherein: The interrupt output module is further configured to output the interrupt information to a target device corresponding to the interrupt request according to parameter information of an interrupt source corresponding to the target interrupt request.

4. The interrupt control device according to claim 1, further comprising: The bus connection module is coupled to the bus and is configured to send the interrupt information through the bus coupled to the bus connection module.

5. The interruption control device according to claim 4, wherein: The bus connection module is configured to include: a bus write address channel, a bus write data channel and a bus write response channel.

6. The interruption control device according to any one of claims 1 to 5, wherein: The interrupt detection module is further configured to determine whether the plurality of interrupt requests are received by detecting detection bits respectively corresponding to the plurality of target interrupt sources, and After the interrupt information is output according to the target interrupt request, a detection bit corresponding to the interrupt source corresponding to the target interrupt request is reset.

7. The interruption control device according to any one of claims 1 to 5, wherein: The interrupt arbitration operation includes using a two-level interrupt arbitration tree to perform the interrupt arbitration operation.

8. The interruption control device according to any one of claims 1 to 5, wherein: The interrupt output module is further configured to convert the parameter information of the interrupt source corresponding to the target interrupt request into the interrupt information according to the address conversion logic and the data conversion logic.

9. The interruption control device according to claim 8, wherein: The parameter information of the interrupt source corresponding to the target interrupt request includes: address coding information, interrupt priority information, interrupt source coding information, and processor quantity information or processor core quantity information.

10. The interrupt control device according to claim 1, further comprising: A register control module configured to store configuration information, The configuration information is used to control the interrupt detection module, the interrupt arbitration module and / or the interrupt output module.

11. The interruption control device according to claim 10, wherein: The register control module includes multiple groups of registers. Each of the multiple groups of registers includes multiple registers, and the multiple groups of registers are configured to correspond to multiple interrupt domains respectively.

12. The interruption control device according to claim 10, wherein: The register control module includes a plurality of registers. The multiple registers are configured to be used for multiple interrupt domains respectively in a time division multiplexing manner.

13. The interruption control device according to claim 12, wherein: The multiple registers are further configured to process interrupt requests belonging to an active interrupt domain and ignore interrupt requests belonging to an inactive interrupt domain when time division multiplexing is used for multiple interrupt domains.

14. The interruption control device according to claim 12 or 13, wherein: The plurality of interrupt domains at least include interrupt domains corresponding to a machine level and at least one management level.

15. The interrupt control device according to claim 10, further comprising: The configuration message processing module is configured to receive a configuration message and configure the register control module based on the configuration message.

16. The interruption control device according to claim 15, wherein: The configuration message complies with a first protocol, The configuration message processing module is further configured to convert the configuration message conforming to the first protocol into a configuration command for configuring the register control module, and use the configuration command to configure the register control module.

17. The interruption control device according to any one of claims 1 to 5, further comprising: Multiple interrupt control modules, Each of the plurality of interrupt control modules includes the interrupt detection module, the interrupt arbitration module and the interrupt output module corresponding to itself.

18. An interrupt control method, comprising: Detecting multiple interrupt requests respectively issued by multiple target interrupt sources; performing an interrupt arbitration operation on the multiple interrupt requests to select a target interrupt request from the multiple interrupt requests; as well as Outputting interrupt information according to the target interrupt request.

19. An electronic device, comprising the interruption control device according to any one of claims 1 to 17.

20. A non-volatile computer-readable storage medium, used for non-temporarily storing computer-readable instructions, which implement the interrupt control method according to claim 18 when the computer-readable instructions are executed by a computer.

Images