A programmable aes encryption module hardware accelerator, instruction set and method of operation

Abstract

The application provides a programmable AES encryption module hardware accelerator, an instruction set and a running method, wherein the accelerator is connected with a bus to exchange data with the bus, and performs AES encryption and decryption on the data; the accelerator comprises a master device and a slave device connected with the bus, wherein the master device is used for transmitting and receiving data carrying instructions; the slave device communicates with other modules on the bus, and receives the data carrying instructions and data of the master device; the slave device is connected with a decoder through an instruction stack, and transmits instructions to the decoder; the decoder decodes the instructions transmitted from the slave device, and sends the decoded instructions to a calculation module or a carrying module connected with the decoder to perform corresponding calculation or data transmission; the instruction set is used for controlling the accelerator; and the running method is realized by using the accelerator.

Description

Technical Field

[0001] This invention relates to a hardware accelerator, instruction set, and operation method, and in particular to a programmable AES encryption module hardware accelerator, instruction set, and operation method. Background Technology

[0002] This section provides only background information relevant to this disclosure and is not necessarily prior art.

[0003] The existing AES (Advanced Encryption Standard) algorithm has an excessively large hardware implementation area, while using a purely software approach would result in prolonged CPU usage. Therefore, most existing AES implementations use a combination of hardware and software to address these issues. The AES hardware accelerator and the CPU typically work together using an interrupt method, whereby the AES hardware accelerator notifies the CPU to proceed with the next operation after completing its calculation.

[0004] However, in the existing technology, the above solutions require frequent interruptions to the CPU, resulting in low CPU efficiency.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] Purpose of the invention: The technical problem to be solved by the present invention is to provide a programmable AES encryption module hardware accelerator, instruction set and operation method to address the shortcomings of the prior art.

[0007] To address the aforementioned technical problems, this invention discloses a programmable AES encryption module hardware accelerator, instruction set, and operation method;

[0008] The accelerator is connected to a bus, interacts with the bus for data exchange, and performs AES encryption and decryption on the data. The accelerator includes:

[0009] A master device and a slave device are connected to the bus, wherein the master device is used to send and receive data transfer instructions; the slave device communicates with other modules on the bus and receives data transfer instructions and data from the master device.

[0010] Furthermore, the accelerator also includes an instruction stack and a decoder.

[0011] The slave device is connected to the decoder via an instruction stack and transmits its instructions to the decoder.

[0012] Furthermore, the accelerator also includes a computing module and a transport module.

[0013] The decoder decodes the instructions transmitted from the slave device and sends the decoded instructions to the computing module or transport module connected to it.

[0014] The calculation module is used to select different calculation sub-modules to perform corresponding operations according to instructions;

[0015] The data transfer module is used to transfer data in the computing module and registers according to the data transfer instructions issued by the master device.

[0016] Furthermore, the accelerator also includes: registers,

[0017] The register is used to store data in the accelerator.

[0018] Furthermore, the register includes:

[0019] Special purpose registers and general purpose registers, among which,

[0020] The dedicated register is used to store specific encrypted and decrypted data;

[0021] The general-purpose register is used to store regular data, including intermediate calculation results and auxiliary data;

[0022] The dedicated registers include: domain operation result register GF, verification information result register TAG, initialization vector register IV, key register H, encryption key register KEY, plaintext data register PTEXT, and ciphertext data register CTEXT.

[0023] Furthermore, the register also includes:

[0024] A status register connected to the slave device is used to store the current state of the accelerator.

[0025] Furthermore, the computing submodule includes:

[0026] The inverse operation submodule INV is used to perform the inverse transformation steps in the AES encryption and decryption process. The inverse operation submodule INV has four modes for inversion: byte-level inversion, word-level inversion, doubleword-level inversion, and full inversion.

[0027] The AES core submodule AES_CORE is used to perform the core operations of AES encryption and decryption, including byte substitution, row shifting, column obfuscation, and round key addition.

[0028] The Galois field operation submodule G2F is used for multiplication operations over finite fields, and the calculation results are placed in the field operation result register GF.

[0029] The XOR submodule is used to perform the XOR operation.

[0030] The addition submodule ADD is used to perform addition operations;

[0031] The dedicated DMA submodule is used only to move data from SRAM to dedicated registers and general-purpose registers;

[0032] The transport submodule MOV is used for moving data between special-purpose registers and general-purpose registers.

[0033] Furthermore, the bus, master device, and slave device are AHB bus, AHB master device, and AHB slave device.

[0034] This invention also proposes a programmable AES hardware accelerator instruction set for controlling the computing modules in the aforementioned accelerator to perform related calculations. The instruction set includes:

[0035] The XOR instruction performs an exclusive OR operation. Its input and output are either dedicated registers or general-purpose registers. The input is two registers, and the output is one register.

[0036] The AES_CORE instruction performs AES encryption or decryption. Before executing this instruction, ensure that the initialization vector register IV, encryption key register KEY, and plaintext data register PTEXT are configured. The output value is stored in the ciphertext data register CTEXT. The encryption or decryption mode must be specified before execution.

[0037] The G2F instruction performs Galois encryption. Before executing this instruction, it is confirmed that the domain operation result register GF and the encryption key register KEY are configured. The output value is stored in the domain operation result register GF.

[0038] The INV instruction performs a reverse operation and has four modes: byte-level inversion, word-level inversion, double-word-level inversion, and full inversion.

[0039] The ADD instruction performs addition operations, using a 32-bit adder to complete 128-bit addition operations. The input and output are either dedicated registers or general-purpose registers. The input also includes a selection bit constant value. There are two input registers and one output register.

[0040] The DMA instruction performs external data transfer, completing a bidirectional data transfer operation from SRAM to the general-purpose register;

[0041] The MOV instruction performs data transfer between registers, moving data into registers. The input can be a constant, a general-purpose register, or a special-purpose register, and the output can be a general-purpose register or a special-purpose register.

[0042] This invention also proposes a method for running a programmable AES hardware accelerator, implemented using the aforementioned accelerator, the method comprising:

[0043] Step 1: Determine whether the current round of AES encryption or decryption operation has been completed. If not, proceed to Step 2; otherwise, end the current round.

[0044] Step 2: Write the received new instruction into the instruction stack;

[0045] Step 3: Pop the last instruction from the instruction stack;

[0046] Step 4: Decode the popped instruction and assign it to the calculation module or the transport module for processing;

[0047] Step 5: Wait for the processing described in Step 4 to complete, check if the instruction stack is empty. If it is empty, end the execution; otherwise, return to Step 1.

[0048] Beneficial effects:

[0049] 1. This invention improves the speed of AES encryption and significantly speeds up data processing compared to pure software solutions.

[0050] 2. This invention reduces hardware costs by combining hardware acceleration with software control to achieve a balance between speed and cost.

[0051] 3. This invention reduces the CPU burden and uses DMA for efficient instruction transport.

[0052] 4. This invention improves system flexibility and supports both CPU and DMA instruction input methods.

[0053] 5. This invention optimizes energy utilization by reducing system power consumption through precise configuration and efficient data interaction. Attached Figure Description

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0055] Figure 1 This is a schematic diagram illustrating the overall working principle of the programmable AES module.

[0056] Figure 2 This is a schematic diagram of the overall architecture of the AES hardware accelerator proposed in this invention.

[0057] Figure 3 This is a schematic diagram of the overall operation flow of the AES hardware accelerator proposed in this invention.

[0058] Figure 4 This is a schematic diagram of the process of applying the AES hardware accelerator proposed in this invention to perform CBC encryption.

[0059] Figure 5 This is a schematic diagram of the process of applying the AES hardware accelerator proposed in this invention to perform GCM encryption. Detailed Implementation

[0060] The design concept of this invention is as follows: an AES hardware accelerator pre-fills AES instructions through the CPU. When the instructions are about to be completed, an interrupt is triggered to allow the CPU to continue filling the instructions. Therefore, as long as the instruction length is reasonable, the interruption of the CPU during the entire AES operation will not be too many, which greatly ensures the CPU's working efficiency.

[0061] This invention achieves AES encryption for large-scale data by working in conjunction with the CPU. This accelerator combines the high speed of hardware acceleration with the low cost of software encryption, supporting both CPU and DMA instruction input methods to improve system efficiency and flexibility. The AES module interacts with other system components via the AHB bus and reduces the CPU load through automated interrupts and DMA, optimizing the encryption process and making it suitable for efficient and secure data processing scenarios.

[0062] DMA is used for instruction transport, reducing the CPU's workload and allowing it to focus on other control tasks, thereby optimizing system performance and energy efficiency. It supports both CPU and DMA instruction input methods, providing flexibility and adaptability to meet the needs of different application scenarios.

[0063] This invention performs AES encryption on large-scale data in conjunction with the CPU. It combines the high encryption speed of a pure hardware AES accelerator with the low hardware cost of software encryption. While balancing speed and space constraints, it frees up the CPU to perform other control tasks, making the overall system more efficient.

[0064] The specific technical solution of the present invention is as follows:

[0065] The location and working principle of the programmable AES module in the overall system are as follows: Figure 1 As shown. In the entire system, the AES module interacts with modules such as DMA, CPU, FLASH, and SRAM via the AHB (Advanced High-performance Bus) to form a complete communication architecture.

[0066] When the AES module starts working, the CPU first configures the AES registers and starts the AES workflow.

[0067] Once configured, the system writes the processing instructions to the AES instruction stack. This operation can be performed by the CPU or DMA, while the instructions are typically stored in the system's SRAM or FLASH.

[0068] If the CPU is used to write instructions, the AES module sends an interrupt signal to the CPU when only one instruction remains on the instruction stack. Upon receiving the interrupt signal, the CPU quickly writes the new instruction onto the instruction stack, ensuring the stack remains fully loaded. This interrupt mechanism guarantees timely instruction transmission and processing, preventing the AES module's operating efficiency from being affected by an empty instruction stack.

[0069] Another approach is to use a general-purpose DMA as the instruction transfer medium. First, the general-purpose DMA is pre-configured, and then its operation is initiated. When the AES instruction stack is not full, the AES sends a request signal (req request) to the general-purpose DMA. Upon receiving the request signal, the general-purpose DMA moves instructions from FLASH or SRAM and writes them to the AES instruction stack. While the AES is processing existing instructions, the general-purpose DMA continues to load new instructions into the AES instruction stack. During this process, the AES module processes loaded instructions and received new instructions in parallel until the AES completes all work on its stack and the DMA has completed all instruction transfer work; only then is this stage truly complete.

[0070] This programmable AES encryption module offers several significant advantages. First, using DMA for instruction transfer greatly reduces the CPU's workload, improving overall system efficiency. DMA enables fast and efficient instruction transfer, preventing instruction loading from becoming a system bottleneck. Second, the automated interrupt mechanism ensures timely instruction updates when writing instructions using the CPU, keeping the AES instruction stack fully loaded and improving system responsiveness. Furthermore, this design supports both CPU and DMA instruction input methods, providing great flexibility and allowing for easy switching between different application scenarios, enhancing adaptability. By configuring registers, the AES module's operating status can be effectively managed, enabling on-demand resource use, improving energy efficiency, and reducing system power consumption. Finally, the AES module interacts with other system components (such as CPU, DMA, FLASH, and SRAM) via the AHB bus, forming an efficient collaborative working mechanism that ensures high performance in encryption and decryption tasks. Overall, this design not only improves the efficiency of the AES encryption module but also enhances the system's flexibility and adaptability, making it suitable for various scenarios requiring efficient and secure data processing.

[0071] Figure 2 The internal architecture of an Advanced Encryption Standard (AES) encryption and decryption hardware design proposed in this invention is described. The architecture shown in the diagram comprises several main parts, each with its unique function and role to ensure the efficient operation of the entire AES system.

[0072] First is the AHB SLV (AHB Slave), a slave device used to communicate with other modules on the Advanced High Performance Bus (AHB). The AHB SLV receives instructions and data from the AHB Master (AHB MST) and transmits instructions to the decoder via the instruction stack. Furthermore, the AHB SLV can also directly transmit data to computing modules or other data paths requiring processing.

[0073] The status register is another key component, used to store the current state of the AES cipher. The status register records the progress of the current operation and whether the system is functioning correctly. This is crucial for fault recovery and system stability.

[0074] The decoder is a crucial component, responsible for decoding the instructions received from the AHB SLV and distributing them to the appropriate modules. The decoder allows the AES system to flexibly handle various operational requests from the master device, such as encryption, decryption, and data transfer.

[0075] The calculation module contains multiple sub-modules, each of which implements a specific computational function:

[0076] • INV: The inverse operation module, used to perform the inverse transformation step in the AES algorithm. The INV module reverses the data input and output. There are four data reversal modes: bit-level inversion, word-level inversion, double-word-level inversion, and full inversion.

[0077] • AES_CORE: The AES core module, which performs the core operations for AES encryption and decryption, including byte substitution, row shifting, column obfuscation, and round key addition. Before encryption and decryption, the IV, KEY, PTEXT, and other data need to be configured.

[0078] • G2F: Galois field operation module, used for multiplication operations over finite fields, which is part of the AES algorithm. The calculation result is placed in the special register GF.

[0079] • XOR: The XOR operation module is used to perform the XOR operation, which is an indispensable step in the AES algorithm.

[0080] • ADD: Addition module. Although it is mainly used for arithmetic operations in the AES algorithm, it may also be extended for other purposes.

[0081] • DMA: Dedicated DMA modules are used only to move data in SRAM, mainly to move SRAM data to dedicated and general-purpose registers.

[0082] MOV: Transfers data between dedicated and general-purpose registers.

[0083] The data transfer module is responsible for data transfer between different computation modules and registers. It ensures that data flows smoothly and efficiently between different computation steps. This is a crucial part of ensuring the efficient operation of the system.

[0084] Dedicated registers and general-purpose registers together form the storage architecture of an AES system. Dedicated registers store specific encryption and decryption data, including the initialization vector (IV), encryption key (KEY), plaintext data (PTEXT), and ciphertext data (CTEXT). General-purpose registers are used to store regular data, such as REG_A (128-bit), REG_B (128-bit), and REG_C (128-bit). These registers are used to store temporary calculation results or other auxiliary data.

[0085] The master device is used for data transmission and reception of transfer instructions. By having a built-in master device within the AES system, data transmission and reception can be actively controlled, giving the AES system greater operational flexibility. Furthermore, the master device focuses on data transmission, while the slave devices focus on AES instruction transmission and reception; this separation of instructions and data makes transmission simpler and more efficient. The advantages of this design are mainly reflected in the following aspects:

[0086] 1. Modular Design: Each computing module and dedicated module is independent and responsible for different tasks, making the design easy to test and maintain. If a module fails, only that module needs to be debugged and repaired without affecting the entire system.

[0087] 2. Efficient Data Transfer: The use of transfer and DMA modules significantly improves data transfer speed and reduces processing time. This is especially important for applications requiring large amounts of data encryption and decryption.

[0088] 3. Flexible instruction processing: Through the decoder, tasks can be flexibly distributed according to different instructions, enabling the system to efficiently handle different types of operation requests. This flexibility allows the system to adapt to changing application needs.

[0089] 4. Parallel processing capability: Multiple computing modules can perform different steps simultaneously, improving the overall processing speed. Parallel processing capability is especially important when large amounts of data need to be processed quickly.

[0090] In addition, AES_CORE and G2F operations can also be performed using basic operations such as XOR and addition. However, using this method would cause the number of instructions to increase dramatically and significantly increase encryption time. Therefore, fully hardware-enabling AES_CORE and G2F operations is a trade-off between area and speed.

[0091] like Figure 3 As shown, an operating method is designed for the aforementioned programmable AES hardware accelerator. This method begins by checking if the current AES operation has been completed. If not, the system writes a new instruction to the instruction stack and pops the next instruction from the stack. The popped instruction is then decoded and allocated to the corresponding hardware resources for processing. After waiting for the current operation to complete, the system checks again if the instruction stack is empty. If the instruction stack is empty, the operation ends; if it is not empty, the above steps continue to be executed in a loop until all instructions have been executed. This process ensures that the AES encryption module can continuously and efficiently load, decode, and execute instructions, while also guaranteeing the order and integrity of instruction execution.

[0092] This invention also proposes an instruction set for the programmable AES hardware accelerator of the aforementioned design, as shown in Table 1:

[0093] Table 1 Instruction Set Table for Programmable AES Hardware Accelerator

[0094]

[0095] Example:

[0096] Because there are various derivative forms of AES, such as ECB, CBC, CTR, CCM, ECM and GMAC, each mode has its own fixed operation. Therefore, for a specific mode, it is necessary to write instructions separately.

[0097] like Figure 4 As shown, the following is an example of using the aforementioned AES hardware accelerator for CBC encryption:

[0098] 1. Configure external general-purpose DMA to transfer data to registers such as PTEXT, IV, and KEY;

[0099] 2. Use the XOR instruction to perform an XOR operation on PTEXT and IV and store the value in PTEXT; 3. Use the AES_CORE instruction to obtain the final data and put it into CTEXT;

[0100] 4. Use the DMA instruction CTEXT to move data to SRAM for storage;

[0101] 5. Use the MOV command to move the CTEXT data to the IV;

[0102] 6. Repeat steps 2-5 until all steps are completed;

[0103] like Figure 5 As shown, the following is an example of using the aforementioned AES hardware accelerator for GCM encryption:

[0104] 1. Configure external general-purpose DMA to transfer data to registers such as PTEXT, IV, and KEY;

[0105] 2. Use AES_CORE to calculate the final data and put it into CTEXT;

[0106] 3. Use the MOV instruction to move the CTEXT data into the H special register;

[0107] 4. Use the MOV instruction to move the value of the data register REG_A into the GF special register; 5. Use the G2F instruction to perform a Galois operation and store the result in the GF special register;

[0108] 6. Use the ADD instruction to add the data REG_A and the 1 data, and place the final result in REG_A; 7. Repeat steps 4-6 to complete the Header Phase operation;

[0109] 8. Use the MOV instruction to move 2 into REG_A;

[0110] 9. Use the ADD instruction to add the result of IV and REG_A into IV;

[0111] 10. Use the AES_CORE instruction to perform AES operations;

[0112] 11. Use DMA instructions to move plaintext into PTEXT;

[0113] 12. Use the XOR command to perform an XOR operation on the data CTEXT and PTEXT, and store the result in CTEXT; 13. Use the DMA command to move the plaintext CTEXT into SRAM;

[0114] 14. Use the XOR instruction to perform an XOR operation on GF and CTEXT and place the result into the GF register;

[0115] 15. Use the G2F instruction to begin the operation;

[0116] 16. Use the ADD instruction to add IV and 1 into IV;

[0117] 17. Repeat instructions 10-16 until the Payload Phase related operations are completed;

[0118] 18. Use the XOR instruction to perform an XOR operation on GF and CTEXT and place the result into the GF register;

[0119] 19. Use the G2F instruction to begin the operation;

[0120] 20. Use the DMA instruction to move the raw IV to the IV special register;

[0121] 21. Use the AES_CORE instruction to perform AES operations;

[0122] 22. Use the XOR instruction to perform an XOR operation on GF and CTEXT and put the result into the TAG register;

[0123] 23. Use DMA instructions to directly move the TAG to SRAM to complete the Final Phase operation;

[0124] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding a programmable AES encryption module hardware accelerator, instruction set, and running method, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0125] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MCU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0126] This invention provides a programmable AES encryption module hardware accelerator, instruction set, and operation method. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A programmable AES encryption module hardware accelerator, characterized in that, The accelerator is connected to the bus, interacts with the bus for data exchange, and performs AES encryption and decryption on the data. The accelerator includes: A master device and a slave device are connected to the bus, wherein the master device is used for sending and receiving data transfer instructions; the slave device communicates with other modules on the bus and receives data transfer instructions and data from the master device. The accelerator also includes an instruction stack and a decoder. The slave device is connected to the decoder via an instruction stack and transmits its instructions to the decoder. The accelerator further includes a computing module and a transport module. The decoder decodes the instructions transmitted from the slave device and sends the decoded instructions to the computing module or transport module connected to it. The calculation module is used to select different calculation sub-modules to perform corresponding operations according to instructions; The data transfer module is used to transfer data in the computing module and registers according to the data transfer instructions issued by the master device. The accelerator also includes: a register, The register is used to store data in the accelerator.

2. The programmable AES encryption module hardware accelerator according to claim 1, characterized in that, The register includes: Special purpose registers and general purpose registers, among which, The dedicated register is used to store specific encrypted and decrypted data; The general-purpose register is used to store regular data, including intermediate calculation results and auxiliary data; The dedicated registers include: domain operation result register GF, verification information result register TAG, initialization vector register IV, key register H, encryption key register KEY, plaintext data register PTEXT, and ciphertext data register CTEXT.

3. The programmable AES encryption module hardware accelerator according to claim 2, characterized in that, The register also includes: A status register connected to the slave device is used to store the current state of the accelerator.

4. The programmable AES encryption module hardware accelerator according to claim 3, characterized in that, The computing submodule includes: The inverse operation submodule INV is used to perform the inverse transformation steps in the AES encryption and decryption process. The inverse operation submodule INV has four modes for inversion: byte-level inversion, word-level inversion, doubleword-level inversion, and full inversion. The AES core submodule AES_CORE is used to perform the core operations of AES encryption and decryption, including byte substitution, row shifting, column obfuscation, and round key addition. The Galois field operation submodule G2F is used for multiplication operations over finite fields, and the calculation results are placed in the field operation result register GF. The XOR submodule is used to perform the XOR operation. The addition submodule ADD is used to perform addition operations; The dedicated DMA submodule is used only to move data from SRAM to dedicated registers and general-purpose registers; The transport submodule MOV is used for moving data between special-purpose registers and general-purpose registers.

5. A programmable AES encryption module hardware accelerator according to claim 4, characterized in that, The bus, master device, and slave device are AHB bus, AHB master device, and AHB slave device.

6. A programmable AES encryption module hardware accelerator instruction set, characterized in that, The instruction set is used to control the computing module in any one of the accelerators according to claims 1 to 5 to perform relevant calculations, and includes: The XOR instruction performs an exclusive OR operation. Its input and output are either dedicated registers or general-purpose registers. The input is two registers, and the output is one register. The AES_CORE instruction performs AES encryption or decryption. Before executing this instruction, ensure that the initialization vector register IV, encryption key register KEY, and plaintext data register PTEXT are configured. The output value is stored in the ciphertext data register CTEXT. The encryption or decryption mode must be specified before execution. The G2F instruction performs Galois encryption. Before executing this instruction, it is confirmed that the domain operation result register GF and the encryption key register KEY are configured. The output value is stored in the domain operation result register GF. The INV instruction performs a reverse operation and has four modes: byte-level inversion, word-level inversion, double-word-level inversion, and full inversion. The ADD instruction performs addition operations, using a 32-bit adder to complete 128-bit addition operations. The input and output are either dedicated registers or general-purpose registers. The input also includes a selection bit constant value. There are two input registers and one output register. The DMA instruction performs external data transfer, completing a bidirectional data transfer operation from SRAM to the general-purpose register; The MOV instruction performs data transfer between registers, moving data into registers. The input can be a constant, a general-purpose register, or a special-purpose register, and the output can be a general-purpose register or a special-purpose register.

7. A method for operating a programmable AES encryption module hardware accelerator, characterized in that, The method, implemented using any one of the accelerators described in claims 1 to 5, comprises: Step 1: Determine whether the current round of AES encryption or decryption operation has been completed. If not, proceed to Step 2; otherwise, end the current round. Step 2: Write the received new instruction into the instruction stack; Step 3: Pop the last instruction from the instruction stack; Step 4: Decode the popped instruction and assign it to the calculation module or the transport module for processing; Step 5: Wait for the processing described in Step 4 to complete, check if the instruction stack is empty. If it is empty, end the execution; otherwise, return to Step 1.

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