Customized IO IP core with power-on control, generation method and generation device of customized POC IP core, and chip

Abstract

The invention relates to the technical field of chip IP cores and EDA, in particular to a customized IO IP core with power-on control, a generation method and device of a customized POC IP core and a chip. According to the invention, the user demand is obtained through the customized EDA tool, the configurable POC IP core and the IO IP core are obtained through the customized EDA tool, the POC input threshold voltage adjustable module of the configurable POC IP core is configured, the configured POC input threshold voltage adjustable module is generated, and the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate the customized POC IP core. The customized POC IP core and the IO IP core are connected to generate the customized IO IP core with power-on control, and the customized IO IP core with power-on control can detect incomplete power-on conditions in time, so that the stability and the reliability under the incomplete power-on conditions such as sudden power failure of a power supply are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip IP core and EDA technology, and in particular to a method and device for generating a customized IO IP core with power-on control and a customized POC IP core, as well as a chip. Background Art

[0002] IO IP (Intellectual Property) cores usually refer to pre-designed functional modules for chip input and output functions. These modules contain reusable circuits and module designs in integrated circuit design and have specific input and output interface functions.

[0003] With the rapid development of chip technology, IO IP cores, as a key part of chip design, are facing increasing challenges in design. While the chip area is constantly decreasing, the reduction of leakage current has put forward higher requirements on the layout area and power consumption of IO IP cores. Especially in the context of thinning gate oxide layer thickness, gate oxide layer reliability and hot carrier degradation problems becoming increasingly prominent, reducing the internal chip supply voltage (VDD) has become a necessary measure to improve system performance and reduce circuit power consumption.

[0004] However, the reduction of power supply voltage also brings new problems, namely, the mismatch between the voltage inside and outside the chip. Generally, the internal circuit uses thin gate oxide devices and low power supply voltage (such as 1.8V), and the circuit system outside the chip usually operates at a higher voltage (the mainstream operating voltage is 5V). Therefore, the IO circuit is not only to receive and send signals, but also to convert the signal level and provide a large drive current. This requires the IO circuit to have at least two power supply systems, which increases the design difficulty from the perspective of circuit design. Although most process manufacturers provide IO IP cores as a solution, the IO IP cores provided by the existing IO IP library still face challenges in power management, especially when the power is suddenly cut off.

[0005] When one of the power supplies in the dual power supply circuit is suddenly powered off, the traditional IO IP design cannot provide accurate judgment for the subsequent circuit, causing some circuits to work normally while the other circuits fail, thus generating erroneous logic signals and seriously affecting the function of the entire chip. In addition, when the power supply is not powered on, if the IO circuit still outputs a large current, there is a potential safety risk.

[0006] How to design an IO IP core so that when an IO chip is generated using the IO IP core, the stability and reliability of its internal IO circuit under conditions such as reduced power supply voltage, mismatch between internal and external voltages, and sudden power failure is an urgent problem to be solved. Summary of the invention

[0007] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method and a device for generating a customized IO IP core with power-on control and a customized POC IP core, as well as a chip.

[0008] In a first aspect, an embodiment of the present disclosure provides a method for generating a customized IO IP core with power-on control, the method being implemented based on a customized EDA tool, the customized EDA tool providing a GUI interface, the GUI interface including a plurality of customized input boxes, the method comprising:

[0009] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0010] Get IO IP core;

[0011] Acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0012] The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module;

[0013] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core;

[0014] Connect the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0015] The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, the power supply includes: a first power supply and a second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded;

[0016] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group;

[0017] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

[0018] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal, including:

[0019] When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0020] When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0021] According to an embodiment of the present disclosure, the method further includes: generating a layout of the customized IO IP core with power-on control based on the customized IO IP core with power-on control.

[0022] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0023] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0024] According to an embodiment of the present disclosure, the method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0025] According to an embodiment of the present disclosure, the method further includes:

[0026] Acquire a bottom module, and use the bottom module to seal the bottom of the customized IO IP core with power-on control to generate a bottom-sealed customized IO IP core with power-on control;

[0027] Before obtaining the bottom module, if the custom IO IP core with power-on control contains a vacant position, then:

[0028] Obtain a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply, and the ground port of the filling module is grounded;

[0029] The filling module is used to fill the empty spaces in the customized IO IP core with power-on control.

[0030] According to an embodiment of the present disclosure, the method further includes:

[0031] Based on the bottom-enclosed custom IO IP core with power-on control, a layout of the bottom-enclosed custom IO IP core with power-on control is generated.

[0032] According to an embodiment of the present disclosure, the IO IP core is a customized IO IP core, and obtaining the IO IP core includes:

[0033] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module;

[0034] Acquire, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, and a low level output sink current input by a user for a specified pin module of the custom IO IP core;

[0035] According to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module is configured, the input threshold adjustable module includes a second MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0036] According to the high-level output source current and the low-level output sink current, the output current adjustable module is configured, the output current adjustable module includes a third MOS module group, and the configuring of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of the IO second control signal of the IO core circuit module;

[0037] The IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are connected to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: an IO first control signal input port and an IO second control signal output port, the configured input threshold adjustable module includes: an IO first control signal output port, and the configured output current adjustable module includes: an IO second control signal input port; the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module further include: a power supply voltage port and a ground port, the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply, and the ground ports are all grounded;

[0038] The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, so as to provide the IO first control signal to the IO core circuit module;

[0039] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal;

[0040] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the third MOS module group.

[0041] According to an embodiment of the present disclosure, the configuration of the input threshold adjustable module further includes:

[0042] Determine a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage;

[0043] A MOS module is selected from the second MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and the selected MOS module is connected to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0044] According to an embodiment of the present disclosure,

[0045] The MOS modules in the third MOS module group are divided into a plurality of unit output current adjustable modules;

[0046] The configuring the output current adjustable module comprises: selecting one or more unit output current adjustable modules from the plurality of unit output current adjustable modules according to the high level output source current and the low level output sink current, and when selecting a plurality of unit output current adjustable modules, the selected plurality of unit output current adjustable modules jointly provide the specified output current capability;

[0047] Wherein, the unit output current adjustable module comprises a power supply voltage port, a ground port and an IO second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply, and the ground port of the unit output current adjustable module is grounded;

[0048] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the selected unit output current adjustable module, and the IO second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the third MOS module group.

[0049] According to an embodiment of the present disclosure:

[0050] All MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected; and / or

[0051] A portion of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

[0052] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal, including:

[0053] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0054] Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current adjustable module;

[0055] The configured output current adjustable module controls the output of the IO IP core current according to the current control signal.

[0056] According to an embodiment of the present disclosure, the POC input threshold voltage includes a first power-on threshold voltage corresponding to the first power supply and a second power-on threshold voltage corresponding to the second power supply; the custom input box includes: an expected first power-on threshold voltage input box and an expected second power-on threshold voltage input box; the expected first power-on threshold voltage input box is used to obtain the first power-on threshold voltage corresponding to the first power supply input by the user, and the expected second power-on threshold voltage input box is used to obtain the second power-on threshold voltage corresponding to the second power supply input by the user;

[0057] When the IO IP core is a customized IO IP core, the customized input box also includes: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box, and an expected low level output sink current input box, so as to sequentially obtain the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user.

[0058] In a second aspect, an embodiment of the present disclosure provides a method for generating a customized POC IP core, the method is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, the method includes:

[0059] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0060] Acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0061] The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module;

[0062] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core;

[0063] Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0064] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, the power supply comprising: a first power supply and a second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded;

[0065] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0066] According to an embodiment of the present disclosure, the method further includes: generating a layout of the customized POC IP core based on the customized POC IP core.

[0067] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0068] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0069] According to an embodiment of the present disclosure, the method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0070] In a third aspect, an embodiment of the present disclosure provides a method for providing a configurable POC IP core, the method being implemented based on a customized EDA tool, comprising:

[0071] A POC core circuit module is provided for generating a POC control signal; the POC core circuit module comprises: a POC first control signal input port and a POC control signal output port;

[0072] A POC input threshold voltage adjustable module is provided, which is used to generate a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

[0073] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group, and the method further includes:

[0074] The custom EDA tool selects resistor modules with a number and resistance value corresponding to the POC input threshold voltage from the resistor module group and connects the selected MOS module and resistor module.

[0075] According to an embodiment of the present disclosure, the method further includes:

[0076] A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0077] According to an embodiment of the present disclosure, the method further includes:

[0078] A bottom module is provided, which is used to seal the bottom of the customized POC IP core or the customized IO IP core with power-on control when the customized POC IP core or the customized IO IP core with power-on control is generated based on the provided configurable POC IP core.

[0079] In a fourth aspect, an embodiment of the present disclosure provides a device for generating a customized IO IP core with power-on control, the device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes multiple customized input boxes, and the device includes:

[0080] A configurable POC IP core acquisition module is configured to acquire a configurable POC IP core, wherein the configurable POC IP core includes a POC core circuit module and a POC input threshold voltage adjustable module;

[0081] An IO IP core acquisition module, configured to acquire an IO IP core;

[0082] A POC input threshold voltage acquisition module, configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0083] a configuration module configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage comprising: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module;

[0084] A first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core;

[0085] The second connection module is configured to connect the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0086] The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, the power supply includes: a first power supply and a second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded;

[0087] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group;

[0088] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

[0089] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal, including:

[0090] When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0091] When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0092] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0093] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0094] According to an embodiment of the present disclosure, the customized IO IP core configuration module with power-on control further includes:

[0095] A bottom module acquisition module is configured to acquire a bottom module, and use the bottom module to seal the bottom of the custom IO IP core with power-on control, so as to generate a bottom-sealed custom IO IP core with power-on control;

[0096] The filling module acquisition module is configured to, before acquiring the bottom module, if the custom IO IP core with power-on control contains a vacant position, then: acquire a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to the power supply, and the ground port of the filling module being grounded; and use the filling module to fill the vacant position in the custom IO IP core with power-on control.

[0097] According to an embodiment of the present disclosure, when the IO IP core is a customized IO IP core, the IO IP core acquisition module includes:

[0098] A first acquisition submodule is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module;

[0099] A second acquisition submodule is configured to acquire, through the plurality of custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, and a low level output sink current input by a user for a designated pin module of the custom IOIP core;

[0100] A first configuration submodule is configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module includes a second MOS module group, and the configuring the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0101] A second configuration submodule is configured to configure the output current adjustable module according to the high-level output source current and the low-level output sink current, the output current adjustable module includes a third MOS module group, and the configuration of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of an IO second control signal of the IO core circuit module;

[0102] A third connection module is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: an IO first control signal input port and an IO second control signal output port, the configured input threshold adjustable module includes: an IO first control signal output port, and the configured output current adjustable module includes: an IO second control signal input port; the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module further include: a power supply voltage port and a ground port, the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply, and the ground ports are all grounded;

[0103] The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, so as to provide the IO first control signal to the IO core circuit module;

[0104] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal;

[0105] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the third MOS module group.

[0106] In a fifth aspect, an embodiment of the present disclosure provides a device for generating a customized POC IP core, the device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes multiple customized input boxes, and the device includes:

[0107] A configurable POC IP core acquisition module is configured to acquire a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0108] A POC input threshold voltage acquisition module, configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0109] a configuration module configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage comprising: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module;

[0110] A first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core;

[0111] Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0112] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, the power supply comprising: a first power supply and a second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded;

[0113] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0114] In a sixth aspect, an embodiment of the present disclosure provides a device for providing a configurable POC IP core, the device being implemented based on a customized EDA tool, and the device comprising:

[0115] A first providing module is configured to provide a POC core circuit module for generating a POC control signal; the POC core circuit module comprises: a POC first control signal input port and a POC control signal output port;

[0116] The second providing module is configured to provide a POC input threshold voltage adjustable module for generating a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

[0117] According to an embodiment of the present disclosure, the device further includes:

[0118] The third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which are used to fill the vacancies in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0119] According to an embodiment of the present disclosure, the device further includes:

[0120] The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0121] In the seventh aspect, a chip is provided in an embodiment of the present disclosure, which is manufactured using a customized IO IP core with power-on control generated by the method described in any one of the first aspects, or manufactured using a customized POC IP core generated by the method described in any one of the second aspects, or manufactured using a customized IO IP core with power-on control generated by a configurable POC IP core provided by the method described in any one of the third aspects.

[0122] In an eighth aspect, an electronic device is provided in an embodiment of the present disclosure, comprising the chip described in the seventh aspect.

[0123] In the ninth aspect, a computer-readable storage medium is provided in an embodiment of the present disclosure, on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in any one of the first aspect, the second aspect, and the third aspect is implemented.

[0124] In the tenth aspect, a computer program product is provided in an embodiment of the present disclosure, including a computer program, and when the computer program is executed by a processor, the method described in any one of the first aspect, the second aspect, and the third aspect is implemented.

[0125] According to the technical solution provided by the embodiment of the present disclosure, a customized EDA tool obtained by customizing the EDA tool is used to obtain user requirements (such as: a POC input threshold voltage for a customized POC IP core), and a configurable POC IP core and an IO IP core are obtained through the customized EDA tool, the POC input threshold voltage adjustable module of the configurable POC IP core is configured to generate a configured POC input threshold voltage adjustable module, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core, and then the customized POC IP core and the IO IP core are connected to generate a customized IO IP core with power-on control, wherein the customized IO IP core with power-on control can detect incomplete power-on in time, and control itself not to output current and enter a high-resistance state when incomplete power-on, so that when the customized IO IP core with power-on control is used to generate an IO chip, the stability and reliability of its internal IO circuit in incomplete power-on conditions such as reduced power supply voltage, mismatched internal and external voltages, and sudden power failure of the power supply are improved.

[0126] In addition, the present disclosure provides a customized EDA tool, and customizes the circuit module and layout of the POC IP core at the same time, and reconstructs a configurable POC IP core including a POC core circuit module and a POC input threshold adjustable module, so that user needs are obtained through the EDA tool and each module in the configurable POC IP core is configured, which can be adjusted according to the needs of the actual chip, thereby realizing the flexible configuration of the POC input threshold voltage, so that the customized POC IP core and customized IO IP core generated by the customized EDA tool and the configurable POC IP core can meet the design requirements of complex industrial chips such as different input threshold voltages.

[0127] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0128] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0129] Figure 1 A flow chart showing a method for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown;

[0130] Figure 2 A flow chart showing a method for generating a customized IO IP core with adjustable input threshold voltage and adjustable output current capability according to an embodiment of the present disclosure;

[0131] Figure 3 A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown;

[0132] Figure 4 A schematic diagram showing a designated pin module of a customized IO IP core according to an embodiment of the present disclosure is shown;

[0133] Figure 5 A schematic diagram showing a customized IO IP core according to an embodiment of the present disclosure;

[0134] Figure 6 A schematic diagram showing a configured POC input threshold voltage adjustable module according to an embodiment of the present disclosure;

[0135] Figure 7 A schematic diagram showing a customized POC IP core according to an embodiment of the present disclosure;

[0136] Figure 8 A schematic diagram showing a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown;

[0137] Fig. 9 A flowchart showing another method for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure;

[0138] Fig.10 A flow chart showing a method for generating a customized POC IP core according to an embodiment of the present disclosure;

[0139] Fig.11 A flowchart showing a method for providing a configurable POC IP core according to an embodiment of the present disclosure is shown;

[0140] Fig.12 A schematic structural diagram of a device for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown;

[0141] Fig.13 A schematic diagram showing the structure of a device for generating a customized POC IP core according to an embodiment of the present disclosure is shown;

[0142] Fig.14 A schematic structural diagram of a device for providing a configurable POC IP core according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0143] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0144] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0145] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0146] As mentioned above, when one of the power supplies in the dual power supply circuit is suddenly powered off, the traditional IO IP design cannot provide accurate judgment for the subsequent circuit, causing some circuits to work normally while the other circuits fail, thereby generating erroneous logic signals and seriously affecting the function of the entire chip. In addition, when the power supply is not powered on, if the IO IP still outputs a large current, there is a potential safety risk.

[0147] In order to improve the stability and reliability of the IO circuit under conditions such as reduced power supply voltage, mismatch between internal and external voltages, and sudden power failure, the inventors of the present disclosure have improved the existing IO IP design through in-depth research and repeated verification, combined the IO IP core with the POC IP, and considered proposing a method for generating a customized IO IP core with power-on control.

[0148] In the field of chip design, POC IP (Intellectual Property) core usually refers to a pre-designed functional module for the chip's power-on control function. Among them, POC contains reusable circuits and module designs in integrated circuit design for these modules, and has specific power-on control interface functions.

[0149] Generally, the POC IP core is used to design the POC (Power-On Control) chip. Designers will use integrated circuit design tools (such as EDA tools) to integrate the selected POC IP core that meets the design requirements with other circuit modules (such as logic circuits, storage circuits, etc.) to form a complete POC chip design. The POC chip thus produced is a chip that controls and monitors the system when powered on. It is mainly responsible for initializing system hardware, monitoring system status, and protecting power supply stability. Specifically, when the system is powered on, the POC chip ensures that each hardware component is correctly initialized according to the predetermined order and conditions, laying the foundation for the normal startup and operation of the system; after the system is powered on, the POC chip monitors the system's power supply voltage, current and other key parameters in real time to ensure that the system is always running in a safe and stable state.

[0150] The present disclosure utilizes the POC IP core to output different POC control signals when the power supply is not fully powered on and when the power supply is fully powered on in the dual power supply circuit. When generating a custom IO IP core with power-on control, the POC control signal output port of the POC IP is connected to the POC control signal input port of the IO IP, so that the IO IP obtains the POC control signal and monitors in real time whether the two power supplies in the dual power supply circuit are fully powered on through the POC control signal, thereby controlling the output of its own current. Designers can use the custom IO IP core with power-on control generated by the method to design an IO circuit with power-on control, thereby improving the stability and reliability of the IO circuit under conditions such as reduced power supply voltage, mismatched internal and external voltages, and sudden power failure.

[0151] However, the traditional POC IP design has great limitations in the input threshold voltage configuration. Specifically, the POC IP cores provided by most of the existing mainstream process plants usually have fixed power-on threshold voltages and power-off threshold voltages, but the actual situation is: even for the same process node and the same operating voltage, the power-on threshold voltage and power-off threshold voltage are not the same for different process plants and different POC IPs. For example: for a 5V power supply, some power-on threshold voltages need to reach 4.7V to indicate that the power supply is in the power-on state, while others only need to be 4.5V; for a 1.8V power supply, some power-off threshold voltages are 0.6V to indicate that the power supply is in the power-off state, while others must be 0.4V.

[0152] In order to configure the POC IP according to the different threshold voltages required by the actual chip, realize the flexible configuration of the POC input threshold voltage, and control the current output of the IO IP through the flexible and configurable POC IP, so that the generated customized IO IP core with power-on control can meet the design requirements of complex industrial chips, the present disclosure proposes a method for generating a customized IO IP core with power-on control based on a configurable POC IP core. Specifically, the method includes: using a customized EDA tool to obtain a configurable POC IP core and an IO IP core, configuring a POC input threshold voltage adjustable module of the configurable POC IP core according to a POC input threshold voltage input by a user, generating a configured POC input threshold voltage adjustable module, connecting a POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, and then connecting the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control, so that the IO IP core can control the output of its own current through a POC control signal output by the customized POC IP core, on the one hand, realizing the flexible configuration of the POC input threshold voltage, and on the other hand, controlling the current output of the IO IP through the flexible and configurable POC IP, so that the generated customized IOIP core with power-on control can meet the design requirements of complex industrial chips.

[0153] It should be noted that the customized POC IP core and the customized IO IP core with power-on control generated by the method provided in the embodiment of the present disclosure can form a customized IP library, and the designer can directly select the customized POC IP core and the customized IO IP core with power-on control to design the chip so that the designed chip meets the design requirements.

[0154] Figure 1A flow chart of a method for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown, wherein the method is implemented based on a customized EDA tool, wherein the customized EDA (Electronic Design Automation) tool provides a GUI interface, and the GUI interface includes a plurality of customized input boxes. Figure 1 As shown, the method includes the following steps S110 to S160:

[0155] In step S110, a configurable POC IP core is obtained, where the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module.

[0156] After research, the inventors of the present disclosure found that the reason why the existing POC IP core can only provide a fixed input threshold voltage (including a power-on threshold voltage and a power-down threshold voltage) is that the POC IP core is designed as an integral module, which makes it impossible to easily change it according to chip requirements, resulting in the existing IO IP core only being able to provide a fixed input threshold voltage, thereby failing to meet the actual requirements of different chips for different input threshold voltages.

[0157] The present disclosure splits the existing overall POC IP core into multiple functional modules, and separately configures the input threshold voltage module therein, thereby realizing a configurable POC IP core. In the configurable POC IP core, each function inside it can be easily and independently controlled, and then it can be automatically adjusted according to the actual needs of different chips, thereby realizing flexible configuration of the POC input threshold voltage.

[0158] In the present disclosure, the configurable POC IP core is no longer an integral module, but includes a POC core circuit module and a POC input threshold voltage adjustable module, wherein the POC input threshold voltage adjustable module can be configured according to the POC input threshold voltage input by the user, so that the customized POC IP core generated based on the configured POC input threshold voltage adjustable module meets the actual demand of supporting the specified POC input threshold voltage.

[0159] Wherein, the configurable POC IP core is provided by a customized EDA tool.

[0160] In step S120, the IO IP core is obtained.

[0161] Different from the IO IP core in the existing standard IO IP core library, the IO IP core involved in the present disclosure includes: a POC control signal input port, so as to receive the POC control signal through the port.

[0162] In addition to this difference, the IO IP cores involved in the present disclosure include two types: one is an IO IP core with a fixed input threshold voltage and a limited number of output current capabilities, and the other is an IO IP core with a flexibly configurable input threshold voltage and output current capabilities.

[0163] For the first type of IO IP core, when the customized EDA tool is acquired, it is necessary to add a POC control signal input port and a corresponding circuit module for processing the received POC control signal on the basis of the existing IO IP core.

[0164] For the second type of IO IP core, which is a customized IO IP core, when obtaining the customized IO IP core, the customized EDA tool needs to design it based on a configurable IO IP core with adjustable input threshold voltage and adjustable output current capability.

[0165] Figure 2 A flow chart of a method for generating a customized IO IP core with adjustable input threshold voltage and adjustable output current capability according to an embodiment of the present disclosure is shown. Figure 2 As shown, the method includes the following steps S121-S125:

[0166] In step S121, a configurable IO IP core is obtained, where the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module.

[0167] In the present disclosure, the configurable IO IP core is no longer an integral module, but includes an IO core circuit module, an input threshold adjustable module and an output current adjustable module, so that customized EDA tools can perform more customizable configurations on the input threshold voltage and output current capabilities inside the configurable IO IP core.

[0168] In step S122, the input threshold high level voltage, input threshold low level voltage, high level output source current and low level output sink current input by the user for the designated pin module of the customized IO IP core are obtained through the multiple customized input boxes.

[0169] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core; the input threshold high level voltage, input threshold low level voltage, high level output source current and low level output sink current input by the user are the input threshold voltage and output current capabilities that the designated pin module of the customized IO IP core is expected to be able to achieve.

[0170] According to an embodiment of the present disclosure, the customized input box also includes: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box and an expected low level output sink current input box, so as to sequentially obtain the input threshold high level voltage, input threshold low level voltage, high level output source current and low level output sink current input by the user.

[0171] Specifically, four input boxes are provided on the GUI (graphical user interface) interface of the custom EDA tool, namely: "Expected input threshold high level voltage VIH" input box, "Expected input threshold low level voltage VIL" input box, "Expected high level output source current IOH" input box, and "Expected low level output sink current IOL" input box. The user inputs the input threshold voltage and output current capabilities expected to be achieved for the specified pin module of the custom IO IP core from the four input boxes.

[0172] In the present disclosure, the voltage values ​​of the input threshold high level voltage and the input threshold low level voltage are relative. For example, when the input threshold high level voltage is 0.8*VDD, the input threshold low level voltage may be 0.35*VDD, 0.3*VDD, etc.; when the input threshold high level voltage is 4V, the input threshold low level voltage may be 0.8V, 1.2V, etc. Wherein, the input threshold high level voltage is less than the power supply voltage, and the input threshold low level voltage is greater than 0.

[0173] According to the embodiments of the present disclosure, since the configurable IO IP core is obtained by splitting and reconstructing the existing IO IP core, it cannot be directly configured using the existing EDA tools. Therefore, it is necessary to customize the EDA tools so as to configure the configurable IO IP core using the customized EDA tools.

[0174] Specifically, the existing EDA tool is customized, including: pre-setting multiple configurations for the input threshold adjustable module, each configuration corresponding to a different input threshold high level voltage VIH and input threshold low level voltage VIL. The customized EDA tool makes a mapping relationship table of different configurations in the input threshold adjustable module and corresponding VIH and VIL, so that when the user inputs the desired input threshold high level voltage VIH and input threshold low level voltage VIL through the GUI interface provided by the customized EDA tool, the customized EDA tool can directly call the corresponding configuration in the input threshold adjustable module through the mapping relationship table.

[0175] In step S123, the input threshold adjustable module is configured according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module includes a second MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, and the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module.

[0176] In the present disclosure, the IO first control signal of the IO core circuit module is a voltage level that provides a reference to the IO core circuit module, so that the IO core circuit module can compare and judge the voltage level of the IO input signal received from the outside with the IO first control signal, thereby obtaining a logical judgment result of the voltage level of the IO input signal.

[0177] The second MOS module group includes multiple MOS modules, each of which corresponds to a PMOS tube or NMOS tube when the custom IO IP core is implemented as an integrated circuit or chip, that is, the second MOS module group corresponds to a MOS tube group.

[0178] The configured input threshold adjustable module includes a power supply voltage port, a ground port and an IO first control signal output port.

[0179] According to an embodiment of the present disclosure, the power supply voltage port of the configured input threshold adjustable module is connected to the power supply to provide the operating voltage for the configured input threshold adjustable module, and the ground port of the configured input threshold adjustable module is grounded; the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module to provide the IO first control signal to the IO core circuit module;

[0180] According to an embodiment of the present disclosure, the IO first control signal output port of the configured input threshold adjustable module is connected to a MOS module selected from the second MOS module group, so that when the configured input threshold adjustable module is implemented as an integrated circuit or a chip, the IO first control signal is implemented through the selected MOS tube.

[0181] According to an embodiment of the present disclosure, the configuration of the input threshold adjustable module also includes: determining a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage; selecting a MOS module from the second MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0182] Figure 3 A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown.

[0183] like Figure 3 As shown, a hysteresis voltage Vhys is provided by a hysteresis circuit module, and the IO first control signal (VCH and VCL) is obtained by using the hysteresis voltage Vhys, an input threshold high voltage level VIH, and an input threshold low voltage level VIL, VCH=VIH-Vhys, VCL=VIL+Vhys.

[0184] In the present disclosure, after the input threshold high level voltage VIH and the input threshold low level voltage VIL are determined, the corresponding hysteresis voltage Vhys can be determined according to the values ​​of VIH and VIL. For example, the hysteresis voltage Vhys can be determined according to the difference between VIH and VIL and a preset ratio. Specifically, for example, when VIH = 0.8*VDD, VIL = 0.3*VDD, Vhys = (0.8*VDD-0.3*VDD) / 2 = 0.25*VDD. It should be understood by those skilled in the art that the above-mentioned method for solving the hysteresis voltage is only a specific example and is not a technical means for limiting the protection scope of the present disclosure. The hysteresis voltage can also be calculated using other solution methods, for example, Vhys = (0.8*VDD-0.3*VDD) / 3 = 0.2*VDD.

[0185] In a specific embodiment, assuming that VIH=0.8*VDD, VIL=0.3*VDD, Vhys=0.2*VDD, the IO first control signal can be determined: VCH=0.8*VDD-0.2*VDD=0.6*VDD, VCL=0.3*VDD+0.2*VDD=0.5*VDD, then when the voltage value of the IO input signal obtained from the IO core circuit module increases from 0 to VCH=0.6*VDD, the IO input signal is judged as a logic low level, in the interval where the voltage value of the IO input signal rises from VCH=0.6*VDD to VDD, and in the interval where the voltage value of the IO input signal drops from VDD to VCL=0.5*VDD, the IO input signal is judged as a logic high level, and in the interval where the voltage value of the IO input signal drops from VCL=0.5*VDD to 0, the IO input signal is judged as a logic low level.

[0186] When the customized IO IP core is implemented as an integrated circuit or chip, an analog voltage is generally obtained from an external device or sensor as an IO input signal. In order to prevent the voltage signal of the obtained analog voltage from jumping back and forth between the input threshold high level voltage VIH and the input threshold low level voltage VIL, it is necessary to use the hysteresis voltage Vhys to correct VIH and VIL to obtain the IO first control signal for judgment, so that the voltage signal of the analog voltage is judged as a high level when it does not reach but is close to the input threshold high level voltage VIH, and is judged as a low level when it is higher than but close to the input threshold low level voltage VIL, thereby avoiding the IO input signal from jumping back and forth when it is close to VIH or VIL.

[0187] Assume that the first MOS module group includes m PMOS modules and n NMOS modules; when configuring the input threshold adjustable module, p PMOS modules and q NMOS modules are selected from the first MOS module group for connection according to the input threshold high level voltage and the input threshold low level voltage, thereby generating a configured input threshold adjustable module to achieve the desired input threshold voltage and the corresponding hysteresis voltage, wherein p≤m, q≤n.

[0188] The inventors have found that in order to save the layout area of ​​the designed custom IO IP core when it is converted into a circuit layout, or in order to save the layout area of ​​the circuit layout of the designed custom IO IP core, while enabling the input threshold voltage to achieve the desired input accuracy, when the threshold voltage is input in proportion, the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to integer multiples of 0.05*VDD, for example: 0.45*VDD, 0.8*VDD, etc.; when the threshold voltage range is input in absolute value, the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to integer multiples of 0.1V, for example: 0.5V, 0.7V, etc., thereby making the layout area of ​​the designed custom IOIP core as small as possible while the settable values ​​of the input threshold voltage are as large as possible. Those skilled in the art should understand that when setting the input threshold high level voltage VIH and the input threshold low level voltage VIL, the specific values ​​of the minimum ratio and the minimum absolute value can be set according to the layout area of ​​the customized IO IP core required by the user and the desired accuracy of the input threshold voltage, and are not limited thereto.

[0189] For example, when the customized EDA tool configures the input threshold adjustable module to obtain the configured input threshold adjustable module, when the configured input threshold adjustable module is implemented as an integrated circuit or a chip, under a 0.18um design process (the minimum distance or feature size between circuits in chip manufacturing reaches 0.18 microns), when VIH=0.8*VDD, VIL=0.2*VDD, the customized EDA tool determines, based on the values ​​of VIH and VIL, that 18 PMOS tubes and 12 NMOS tubes need to be selected from the first MOS tube group for connection, wherein 16 PMOS tubes and 10 NMOS tubes are used to achieve the desired VIH and VIL, and 2 PMOS tubes and 2 NMOS are used to achieve the corresponding hysteresis voltage.

[0190] In a specific embodiment, the input threshold adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the second MOS module group, and according to the input threshold high level voltage VIH and the input threshold low level voltage VIL, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the second MOS module group, thereby selecting a MOS module from the second MOS module group and connecting the selected MOS module to achieve the desired input threshold voltage and hysteresis voltage.

[0191] In order to save the user's operation time, the embodiment of the present disclosure can pre-set multiple configurations for the input threshold adjustable module, and each configured input threshold adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different input threshold high level voltages VIH and input threshold low level voltages VIL. The customized EDA tool makes a mapping relationship table of input threshold adjustable modules with different configurations and corresponding VIH and VIL, so that when the user inputs the desired input threshold high level voltage VIH and input threshold low level voltage VIL through the GUI interface of the customized EDA tool, the input threshold adjustable module with the corresponding configuration can be directly selected through the mapping relationship table.

[0192] In another specific embodiment, a plurality of MOS module groups are pre-set in the second MOS module group of the input threshold adjustable module, and each MOS module group corresponds to a different input threshold high level voltage VIH and input threshold low level voltage VIL; thus, when the user inputs the required input threshold high level voltage VIH and input threshold low level voltage VIL, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0193] In step S124, the output current adjustable module is configured according to the high-level output source current and the low-level output sink current, and the output current adjustable module includes a third MOS module group. The configuring of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, and the configured output current adjustable module is used to provide an output signal with a specified output current capability under the control of the IO second control signal of the IO core circuit module.

[0194] According to an embodiment of the present disclosure, the configured output current adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port.

[0195] According to an embodiment of the present disclosure, the power supply voltage port of the configured output current adjustable module is connected to the power supply, and the ground port of the configured output current adjustable module is grounded. The IO second control signal input port of the configured output current adjustable module is connected to a MOS module selected from the third MOS module group, so that when the configured output current adjustable module is implemented as an integrated circuit or a chip, the selected MOS module can provide a specified output current capability according to the IO second control signal of the IO core circuit module, thereby achieving the output current capability expected by the user.

[0196] According to an embodiment of the present disclosure, the MOS modules in the third MOS module group are divided into multiple unit output current adjustable modules; the configuration of the output current adjustable module includes: selecting one or more unit output current adjustable modules from the multiple unit output current adjustable modules according to the high-level output pull current and the low-level output sink current, the selected one or more unit output current adjustable modules provide the specified output current capability, that is, when one unit output current adjustable module is selected, the selected one unit output current adjustable module provides the specified output current capability, and when multiple unit output current adjustable modules are selected, the selected multiple unit output current adjustable modules jointly provide the specified output current capability.

[0197] Specifically, when the desired high-level output source current IOH and the low-level output sink current IOL are input through the GUI interface of the customized EDA tool, one or more unit output current adjustable modules can be directly selected to provide the desired output current capability.

[0198] The unit output current adjustable module includes a power supply voltage port, a ground port and an IO second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply, and the ground port of the unit output current adjustable module is grounded. The IO second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the third MOS module group.

[0199] According to an embodiment of the present disclosure, all MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected.

[0200] According to an embodiment of the present disclosure, a part of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

[0201] In a specific embodiment, the unit output current adjustable module includes an output PMOS unit and an output NMOS unit, the output PMOS unit includes multiple PMOS modules, and the output NMOS unit includes multiple NMOS modules. Assuming IOH=3mA, IOL=5.1mA, and the unit output current capability provided by the unit output current adjustable module is 0.5mA, then IOH is 3mA / 0.5mA=6, which requires 6 complete output PMOS units, and IOL is 5.1mA / 0.5mA=10.2, which requires 10 complete output NMOS units and an output NMOS unit accounting for 20%, and the output NMOS unit accounting for 20% is: 20% of the number of NMOS modules are used in the multiple NMOS modules included in the output NMOS unit.

[0202] In the present disclosure, in the unit output current adjustable module, the IO second control signal of the IO core circuit module is received through the IO second control signal input port to control the PMOS module and the NMOS module connected to the IO second control signal input port in the output PMOS unit and the output NMOS unit respectively, so as to achieve the output current capability expected by the user.

[0203] The present disclosure divides the output current adjustable module into a plurality of unit output current adjustable modules, which not only improves the setting accuracy of the output current capability, but also further increases the flexibility of the output current capability configuration. Moreover, when the required high-level output source current IOH or low-level output sink current IOL is a relatively large value, a plurality of unit output current adjustable modules can be conveniently and directly selected for splicing, thereby simplifying the generation process of the customized IO IP core and improving the user experience.

[0204] In step S125, the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0205] Figure 4 A schematic diagram of a designated pin module of a customized IO IP core according to an embodiment of the present disclosure is shown.

[0206] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the power supply voltage port of the configured output current adjustable module is connected to the power supply, and the ground port of the configured output current adjustable module is grounded.

[0207] According to an embodiment of the present disclosure, the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module to provide the IO first control signal to the IO core circuit module.

[0208] According to an embodiment of the present disclosure, the IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal.

[0209] Specifically, in the obtained customized IO IP core, an IO first control signal is provided to an IO core circuit module through a configured input threshold adjustable module, and the IO core circuit module generates an IO second control signal by combining the IO first control signal and an IO input signal received from the outside, and transmits the IO second control signal to the configured output current adjustable module, thereby providing an output signal with a specified output current capability through the configured output current adjustable module.

[0210] According to an embodiment of the present disclosure, when one or more unit output current adjustable modules are selected from the multiple unit output current adjustable modules based on the high-level output pull current and the low-level output sink current, the IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the selected unit output current adjustable module.

[0211] After generating the designated pin module of the customized IO IP core, the input threshold voltage and output current capability of other pins of the customized IO IP core can be configured according to the actual configuration requirements, and other corresponding pin modules of the customized IO IP core are generated through the above steps S121 to 125, and then all the pin modules are spliced ​​to finally generate the customized IO IP core.

[0212] Figure 5 A schematic diagram of a customized IO IP core according to an embodiment of the present disclosure is shown. Figure 5 The following is an explanation using two pin modules for splicing.

[0213] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the generated custom IO IP core, thereby facilitating the subsequent manufacture of integrated circuits or chips.

[0214] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured input threshold adjustable module, and the configured output current adjustable module, the widths of the plurality of module layouts are consistent.

[0215] In order to save the design area of ​​the circuit layout, the widths of the modules in the designated pin modules are set to be consistent, thereby saving design costs and reducing resource waste.

[0216] The present disclosure can automatically select the MOS modules that need to be connected according to the requirements of different input threshold voltages and output current capabilities required by the actual chip, so as to form input threshold voltages and output current capabilities that meet the requirements, thereby achieving flexible configuration of input threshold voltages and output current capabilities.

[0217] In step S130 , the POC input threshold voltage input by the user is acquired through the plurality of customized input boxes.

[0218] Since the configurable POC IP core is obtained by splitting and reconstructing the existing POC IP core, it cannot be directly configured using the existing EDA tools. Therefore, it is necessary to customize the EDA tool to obtain a customized EDA tool, so as to configure the configurable POC IP core using the customized EDA tool.

[0219] Specifically, the EDA tool is customized, including: pre-setting multiple configurations for the POC input threshold voltage adjustable module, each configuration corresponding to a different POC input threshold voltage, the POC input threshold voltage including but not limited to a first power-on threshold voltage corresponding to a first power supply and a second power-on threshold voltage corresponding to a second power supply. The customized EDA tool makes a mapping relationship table of different configurations in the POC input threshold voltage adjustable module and the corresponding POC input threshold voltage, so that when the user inputs the desired POC input threshold voltage through the GUI interface provided by the customized EDA tool, the customized EDA tool can directly call the corresponding configuration in the POC input threshold voltage adjustable module through the mapping relationship table.

[0220] Through the GUI interface provided by the customized EDA tool, the POC input threshold voltage based on the chip design requirements input by the user can be obtained, and then a customized POC IP can be generated according to the configuration parameters input by the user.

[0221] In general, the POC IP core is connected to two power supplies, namely the first power supply and the second power supply. For each power supply, there can be two POC input threshold voltages, namely the power-on threshold voltage and the power-off threshold voltage, which represent the specific voltage levels of the power supply during the power-on and power-off processes. Among them, the power-on threshold voltage refers to the voltage point at which the chip starts to work normally or starts its internal circuit when the power supply voltage reaches or exceeds a certain value during the chip power-on process; the power-off threshold voltage refers to the voltage point at which the chip starts to shut down its internal circuit or enters low power mode when the power supply voltage drops below a certain value during the power-off process. The specific values ​​of the power-on threshold voltage and the power-off threshold voltage will vary depending on the design and application requirements of the chip. In some cases, both the power-on threshold voltage and the power-off threshold voltage are defined as a voltage range to adapt to the fluctuation of the power supply voltage.

[0222] In the present disclosure, after the POC IP is combined with the IO IP, since the IO IP mainly uses the POC control signal to reflect whether the dual power supplies are fully powered on, in a specific embodiment, the user can configure the POC input threshold voltage adjustable module only by inputting the first power-on threshold voltage and the second power-on threshold voltage.

[0223] In a specific implementation, two input boxes are provided through a customized EDA tool GUI interface, namely, an "expected first power-on threshold voltage" input box and an "expected second power-on threshold voltage" input box. After the user enters the power-on threshold voltages expected to be achieved by the first power supply and the second power supply of the POC IP core in the two input boxes, the customized EDA tool can obtain the first power-on threshold voltage corresponding to the first power supply and the second power-on threshold voltage corresponding to the second power supply input by the user.

[0224] Wherein, the POC input threshold voltage is a positive integer multiple of the product of the preset minimum proportional coefficient and the power supply voltage, or the POC input threshold voltage is a positive integer multiple of the preset minimum unit voltage. For example: when the power-on threshold voltage and the power-off threshold voltage are input in proportion, the input voltage value can be set to a positive integer multiple of 0.05*VDD, such as: 0.2*VDD. When the power-on threshold voltage and the power-off threshold voltage are input in absolute value, the input voltage value can be set to an integer multiple of 0.1V. For example, when the power supply voltage is 5V, the power-on threshold voltage value can be filled in 3.8V, 3.9V, 4.0V, ..., 4.5V; when the power supply standard voltage is 1.8V, the power-on threshold voltage value can be filled in 1.3V, 1.4V, ..., 1.8V. Those skilled in the art should understand that the specific values ​​of the preset minimum proportional coefficient and the preset minimum unit voltage can be set according to the layout area of ​​the customized POC IP core required by the user and the accuracy of the desired input threshold voltage, and are not limited thereto.

[0225] In step S140, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, and the POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0226] As mentioned above, the POC input threshold voltage includes: a first power-on threshold voltage and a second power-on threshold voltage, and in addition, may also include a first power-down threshold voltage and a second power-down threshold voltage. Among them, the first power-on threshold voltage and the first power-down threshold voltage are configuration parameters for the first power supply connected to the POC IP core, and the second power-on threshold voltage and the second power-down threshold voltage are configuration parameters for the second power supply connected to the POC IP core.

[0227] In the present disclosure, the POC first control signal of the POC core circuit module is a voltage level that provides a reference to the POC core circuit module, so that the POC core circuit module can compare and judge the power supply voltage signal received from the external power supply with the POC first control signal, thereby obtaining a judgment result of whether the power supply corresponding to the power supply voltage signal value is in a power-on or power-off state, and then generating a POC control signal.

[0228] The first MOS module group includes multiple MOS modules, each of which corresponds to a PMOS tube or NMOS tube when the custom IO IP core is implemented as an integrated circuit or chip, that is, the first MOS module group corresponds to a MOS tube group.

[0229] Figure 6 A schematic diagram of a configured POC input threshold voltage adjustable module according to an embodiment of the present disclosure is shown.

[0230] like Figure 6 As shown, the configured POC input threshold voltage adjustable module includes: a power supply voltage port, a ground port, and a POC first control signal output port; the power supply voltage port of the configured POC input threshold voltage adjustable module is connected to the first power supply and the second power supply, and the ground port of the configured POC input threshold voltage adjustable module is grounded; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group, so that when the configured POC input threshold voltage adjustable module is implemented as an integrated circuit or a chip, the POC first control signal is implemented through the selected MOS tube.

[0231] Assume that the first MOS module group includes m PMOS modules and n NMOS modules; when configuring the POC input threshold voltage adjustable module, p PMOS modules and q NMOS modules are selected from the first MOS module group according to the POC input threshold voltage for connection, thereby generating a configured POC input threshold voltage adjustable module to achieve the desired POC input threshold voltage, wherein p≤m, q≤n.

[0232] In a specific embodiment, the POC input threshold voltage adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the first MOS module group. According to the POC input threshold voltage, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the first MOS module group, thereby selecting a MOS module from the first MOS module group and connecting the selected MOS module to achieve a desired POC input threshold voltage.

[0233] In order to save the user's operation time, the embodiment of the present disclosure can pre-set multiple configurations for the POC input threshold voltage adjustable module, and each configured input threshold voltage adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different POC input threshold voltages. When the user inputs the desired POC input threshold voltage, the corresponding configured POC input threshold voltage adjustable module can be directly selected.

[0234] In another specific embodiment, a plurality of MOS module groups are pre-set in the first MOS module group of the POC input threshold voltage adjustable module, and each MOS module group corresponds to a different POC input threshold voltage; thus, when the user inputs the required POC input threshold voltage, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0235] In a specific embodiment, the POC input threshold voltage adjustable module includes not only a MOS module group but also a resistor module group.

[0236] Correspondingly, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage further includes: selecting a resistor module with a quantity and resistance value corresponding to the POC input threshold voltage from the resistor module group and connecting the selected MOS module and resistor module to generate the configured POC input threshold voltage adjustable module. That is, the configured POC input threshold voltage adjustable module is configured after jointly selecting a MOS module and a resistor module in the MOS module group and the resistor module group according to the POC input threshold voltage.

[0237] In order to configure the POC input threshold voltage adjustable module more accurately according to the POC input threshold voltage, it is possible to choose to perform resistor subdivision adjustment. The customized EDA tool will determine whether resistance subdivision is required based on the design requirements and circuit characteristics. Specifically, the customized EDA tool will first read the design specification document to understand the design requirements for the accuracy and stability of the POC input threshold voltage, and then the customized EDA tool will analyze the topology and component parameters of the POC input threshold voltage adjustable module, evaluate its impact on the threshold voltage, and then based on the design requirements and circuit characteristics, the customized EDA tool will configure the POC input threshold voltage adjustable module, including selecting the parameters of components such as resistors. After that, the customized EDA tool will use the circuit simulation function to simulate the working conditions of the configured POC input threshold voltage adjustable module under different conditions, calculate the actual value of the POC input threshold voltage, and then compare the simulated POC input threshold voltage with the target value in the design requirements to calculate the deviation. If the deviation is within the allowable error range, there is no need to perform resistance subdivision adjustment. If the deviation exceeds the allowable range, resistance subdivision adjustment is required.

[0238] When resistance subdivision is required, resistance subdivision adjustment is performed on the configured POC input threshold voltage adjustable module, specifically including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment of the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0239] In step S150, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core.

[0240] Figure 7 A schematic diagram of a customized POC IP core according to an embodiment of the present disclosure is shown.

[0241] Among them, the POC core circuit module includes: a power supply voltage port, a ground port, a POC first control signal input port, and a POC control signal output port; the power supply voltage port of the POC core circuit module is connected to a power supply, and the power supply includes: a first power supply and a second power supply, and the ground port of the POC core circuit module is grounded.

[0242] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal.

[0243] In step S160, the customized POC IP core and the IO IP core are connected to generate a customized IO IP core with power-on control.

[0244] Figure 8 A schematic diagram of a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown.

[0245] Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IOIP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0246] The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, the power supply includes: a first power supply and a second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded;

[0247] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group;

[0248] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

[0249] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal, including:

[0250] When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0251] When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0252] In a specific embodiment, if the IO IP core is a customized IO IP core, the IO IP core controls the output of its own current through the POC control signal, including:

[0253] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0254] Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current adjustable module;

[0255] The configured output current adjustable module controls the output of the IO IP core current according to the current control signal.

[0256] When the IO IP core specifically implements the output of its own current controlled by the POC control signal, it can be achieved by adding a corresponding circuit module for processing the received POC control signal on the basis of the existing IO IP core, such as: adding a signal analysis unit inside the IO core circuit module, the signal analysis unit can be a hardware logic circuit, it can identify and analyze the POC control signal, and generate a current control signal according to the POC control signal analysis unit, the current control signal can be an analog signal (such as a voltage signal) or a digital signal (such as a PWM signal), which is used to control the output current adjustable module. After generating the current control signal, the IO core circuit module will send this signal to the configured output current adjustable module through the internal signal transmission unit, the signal transmission unit can be a hardware interface (such as SPI, I2C, etc.) or a software communication protocol (such as UART, CAN, etc.), depending on the design and requirements of the system. After receiving the current control signal, the configured output current adjustable module adjusts its internal current regulation circuit according to the current control signal. The current regulation circuit may include some switching tubes, resistors, inductors and other components, and the output current is adjusted by changing the state or parameters of these components.

[0257] Specifically, when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state, that is, current can hardly pass through. In order to achieve the high-impedance state, a special circuit design can be used inside the IO IP core, such as an open-drain structure or a similar configuration. When entering the high-impedance state, the connection between the pin of the IO IP core and the internal circuit is disconnected, forming a high-impedance channel, making it almost impossible for current to pass through.

[0258] When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level. At this time, the IO IP core controls its own normal output current.

[0259] Fig. 9 FIG. 1 is a flow chart showing another method for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure. Fig. 9 As shown, in addition to the above steps S110 to S160, the method further includes the following step S170:

[0260] In step S170, a layout of the customized IO IP core with power-on control is generated based on the customized IO IP core with power-on control.

[0261] When manufacturing is subsequently carried out based on the above circuit layout, it is necessary to manufacture according to the layout border. The layout border defines the physical shape of the circuit board after processing. The chip process manufacturer or manufacturer will cut and process the circuit board according to the layout border to ensure that the size and shape of the circuit board meet the design requirements.

[0262] According to an embodiment of the present disclosure, before generating a layout of the customized IO IP core with power-on control based on the customized IO IP core with power-on control, the method further includes:

[0263] A bottom module is obtained, and the bottom of the customized IO IP core with power-on control is sealed by using the bottom module to generate a bottom-sealed customized IO IP core with power-on control.

[0264] In order to meet the design rule check (DRC) of the layout design, the present disclosure also provides a filling module so that the integrated circuit or chip can meet the design requirements during the manufacturing process.

[0265] Before obtaining the bottom module, if the custom IO IP core with power-on control contains a vacant position, then:

[0266] Obtain a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply, and the ground port of the filling module is grounded;

[0267] The filling module is used to fill the empty spaces in the customized IO IP core with power-on control.

[0268] Afterwards, a layout of the bottom-enclosed customized IO IP core with power-on control is generated based on the bottom-enclosed customized IO IP core with power-on control.

[0269] Fig.10 A flow chart of a method for generating a customized POC IP core according to an embodiment of the present disclosure is shown, wherein the method is implemented based on a customized EDA tool, wherein the customized EDA tool provides a GUI interface, and the GUI interface includes a plurality of customized input boxes. Fig.10 As shown, the method includes the following steps S110, S130, S140 and S150:

[0270] In step S110, a configurable POC IP core is obtained, where the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module.

[0271] In step S130 , the POC input threshold voltage input by the user is acquired through the plurality of customized input boxes.

[0272] In step S140, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, and the POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0273] In step S150, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core.

[0274] Among them, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0275] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, and the power supply includes: a first power supply and a second power supply. The grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded.

[0276] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0277] According to an embodiment of the present disclosure, the method further includes: generating a layout of the customized POC IP core based on the customized POC IP core.

[0278] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0279] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0280] According to an embodiment of the present disclosure, the method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0281] Fig.11 A flow chart of a method for providing a configurable POC IP core according to an embodiment of the present disclosure is shown, wherein the method is implemented based on a custom EDA tool. Fig.11 As shown, the method includes the following steps S1110 to S1120:

[0282] In step S1110, a POC core circuit module is provided to generate a POC control signal; the POC core circuit module includes: a POC first control signal input port and a POC control signal output port.

[0283] In step S1120, a POC input threshold voltage adjustable module is provided to generate a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

[0284] The present disclosure can provide a configurable POC IP core for a customized EDA tool, so that the configurable POC IP core can be configured through the customized EDA tool to achieve flexible adjustment of the POC input threshold voltage.

[0285] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group, and the method further includes:

[0286] The customized EDA tool selects resistor modules of a number and resistance value corresponding to the POC input threshold voltage from the resistor module group and connects the selected MOS module and resistor module.

[0287] According to an embodiment of the present disclosure, the method further includes:

[0288] A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0289] According to an embodiment of the present disclosure, the method further includes:

[0290] A bottom module is provided, and the bottom module is used to close the bottom of the custom IO IP core with power-on control when the custom IO IP core with power-on control is generated based on the provided configurable POC IP core.

[0291] Fig.12A schematic diagram of a device for generating a customized IO IP core with power-on control according to an embodiment of the present disclosure is shown. The device is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes. Fig.12 As shown, the device 1200 includes: a configurable POC IP core acquisition module, configured to acquire a configurable POC IP core, the configurable POC IP core includes a POC core circuit module and a POC input threshold voltage adjustable module; an IO IP core acquisition module, configured to acquire an IO IP core. The POC input threshold voltage acquisition module is configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes. A configuration module is configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module. The first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core. The second connection module is configured to connect the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control.

[0292] Among them, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IOIP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, and the power supply includes: a first power supply and a second power supply, and the ground ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded.

[0293] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0294] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

[0295] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal, including:

[0296] When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0297] When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0298] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0299] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0300] According to an embodiment of the present disclosure, the customized IO IP core configuration module with power-on control further includes:

[0301] The bottom module acquisition module is configured to acquire the bottom module, and use the bottom module to seal the bottom of the customized IO IP core with power-on control to generate a bottom-sealed customized IO IP core with power-on control.

[0302] The filling module acquisition module is configured to, before acquiring the bottom module, if the custom IO IP core with power-on control contains a vacant position, then: acquire a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to the power supply, and the ground port of the filling module being grounded; and use the filling module to fill the vacant position in the custom IO IP core with power-on control.

[0303] According to an embodiment of the present disclosure, when the IO IP core is a customized IO IP core, the IO IP core acquisition module includes:

[0304] The first acquisition submodule is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module; the second acquisition submodule is configured to acquire, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output pull current, and a low level output sink current input by a user for a specified pin module of the custom IO IP core; the first configuration submodule is configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, wherein the input threshold adjustable module includes a second MOS module group, wherein configuring the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; the second configuration submodule is configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage. The high-level output pull current and the low-level output sink current configure the output current adjustable module, the output current adjustable module includes a third MOS module group, and the configuration of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output pull current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, the configured output current adjustable module is used to provide an output signal with a specified output current capability under the control of the IO second control signal of the IO core circuit module; a third connection module is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate the custom IO The designated pin module of the IP core, wherein the IO core circuit module includes: an IO first control signal input port, an IO second control signal output port, the configured input threshold adjustable module includes: an IO first control signal output port, and the configured output current adjustable module includes: an IO second control signal input port; the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module also include: a power supply voltage port and a ground port, the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply, and the ground ports are all grounded; the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, and is used to provide the IO first control signal to the IO core circuit module;The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal; the IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the third MOS module group. ;

[0305] Fig.13 A schematic diagram of a structure of a device for generating a customized POC IP core according to an embodiment of the present disclosure is shown. The device is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes. Fig.13 As shown, the device 1300 includes:

[0306] The configurable POC IP core acquisition module is configured to acquire a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module.

[0307] The POC input threshold voltage acquisition module is configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes.

[0308] A configuration module is configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0309] The first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core.

[0310] Among them, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0311] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, and the power supply includes: a first power supply and a second power supply. The grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded.

[0312] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0313] Fig.14 FIG. 1 is a schematic diagram showing a structure of a device for providing a configurable POC IP core according to an embodiment of the present disclosure, wherein the device is implemented based on a customized EDA tool. Fig.14 As shown, the device 1400 includes:

[0314] The first providing module is configured to provide a POC core circuit module for generating a POC control signal; the POC core circuit module includes: a POC first control signal input port and a POC control signal output port.

[0315] The second providing module is configured to provide a POC input threshold voltage adjustable module for generating a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

[0316] According to an embodiment of the present disclosure, the device 1400 further includes:

[0317] The third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which are used to fill the vacancies in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0318] According to an embodiment of the present disclosure, the device 1400 further includes:

[0319] The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

[0320] The present disclosure provides a chip, including: a custom IO IP core with power-on control manufactured using the method described above, or a custom POC IP core generated using the method described above, or a custom IO IP core with power-on control manufactured using a configurable POC IP core provided by the method described above.

[0321] The present disclosure provides an electronic device, comprising: the chip as described above.

[0322] The present disclosure provides a computer-readable storage medium having computer instructions stored thereon. When the computer instructions are executed by a processor, the method described in any of the preceding items is implemented.

[0323] The present disclosure provides a computer program product, comprising computer instructions, which implement any of the above methods when executed by a processor.

[0324] According to the technical solution provided by the embodiment of the present disclosure, a customized EDA tool obtained by customizing the EDA tool is used to obtain user requirements (such as: a POC input threshold voltage for a customized POC IP core), and a configurable POC IP core and an IO IP core are obtained through the customized EDA tool, the POC input threshold voltage adjustable module of the configurable POC IP core is configured to generate a configured POC input threshold voltage adjustable module, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core, and then the customized POC IP core and the IO IP core are connected to generate a customized IO IP core with power-on control, wherein the customized IO IP core with power-on control can detect incomplete power-on in time, and control itself not to output current and enter a high-resistance state when incomplete power-on, so that when the customized IO IP core with power-on control is used to generate an IO chip, the stability and reliability of its internal IO circuit in incomplete power-on conditions such as reduced power supply voltage, mismatched internal and external voltages, and sudden power failure of the power supply are improved.

[0325] In addition, the present disclosure provides a customized EDA tool, and customizes the circuit module and layout of the POC IP core at the same time, and reconstructs a configurable POC IP core including a POC core circuit module and a POC input threshold adjustable module, so that user needs are obtained through the EDA tool and each module in the configurable POC IP core is configured, which can be adjusted according to the needs of the actual chip, thereby realizing the flexible configuration of the POC input threshold voltage, so that the customized POC IP core and customized IO IP core generated by the customized EDA tool and the configurable POC IP core can meet the design requirements of complex industrial chips such as different input threshold voltages.

[0326] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for generating a custom IO IP core with power-on control, characterized in that: The method is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, and the method includes: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Get IO IP core; Acquire the POC input threshold voltage input by the user through the multiple customized input boxes; The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core; Connect the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, the power supply includes: a first power supply and a second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group; The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

2. The method according to claim 1, characterized in that The IO IP core controls the output of its own current through the POC control signal, including: When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state; When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

3. The method according to claim 1, characterized in that The method further includes: generating a layout of the customized IO IP core with power-on control based on the customized IO IP core with power-on control.

4. The method according to claim 1, characterized in that: The POC input threshold voltage adjustable module further includes: a resistance module group; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

5. The method according to claim 4, characterized in that The method also includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

6. The method according to claim 1, characterized in that The method further comprises: Acquire a bottom module, and use the bottom module to seal the bottom of the customized IO IP core with power-on control to generate a bottom-sealed customized IO IP core with power-on control; Before obtaining the bottom module, if the custom IO IP core with power-on control contains a vacant position, then: Obtain a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply, and the ground port of the filling module is grounded; The filling module is used to fill the empty spaces in the customized IO IP core with power-on control.

7. The method according to claim 6, characterized in that The method further comprises: Based on the bottom-enclosed custom IO IP core with power-on control, a layout of the bottom-enclosed custom IO IP core with power-on control is generated.

8. The method according to claim 1, characterized in that The IO IP core is a customized IO IP core, and obtaining the IO IP core includes: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module; Acquire, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, and a low level output sink current input by a user for a specified pin module of the custom IO IP core; According to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module is configured, the input threshold adjustable module includes a second MOS module group, and the configuring of the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; According to the high-level output source current and the low-level output sink current, the output current adjustable module is configured, the output current adjustable module includes a third MOS module group, and the configuring of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of the IO second control signal of the IO core circuit module; The IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are connected to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: an IO first control signal input port and an IO second control signal output port, the configured input threshold adjustable module includes: an IO first control signal output port, and the configured output current adjustable module includes: an IO second control signal input port; the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module further include: a power supply voltage port and a ground port, the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply, and the ground ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, so as to provide the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the third MOS module group.

9. The method according to claim 8, characterized in that The configuration of the input threshold adjustable module also includes: Determine a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage; A MOS module is selected from the second MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and the selected MOS module is connected to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

10. The method according to claim 8, characterized in that in, The MOS modules in the third MOS module group are divided into a plurality of unit output current adjustable modules; The configuring the output current adjustable module comprises: selecting one or more unit output current adjustable modules from the plurality of unit output current adjustable modules according to the high level output source current and the low level output sink current, and when selecting a plurality of unit output current adjustable modules, the selected plurality of unit output current adjustable modules jointly provide the specified output current capability; Wherein, the unit output current adjustable module comprises a power supply voltage port, a ground port and an IO second control signal input port, the power supply voltage port of the unit output current adjustable module is connected to the power supply, and the ground port of the unit output current adjustable module is grounded; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the selected unit output current adjustable module, and the IO second control signal input port of the selected unit output current adjustable module is connected to the MOS module selected from the third MOS module group.

11. The method according to claim 10, characterized in that: All MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules are selected; and / or A portion of MOS modules of at least one unit output current adjustable module among the one or more unit output current adjustable modules is selected.

12. The method according to claim 8, characterized in that The IO IP core controls the output of its own current through the POC control signal, including: The IO core circuit module obtains the POC control signal through the POC control signal input port; Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current adjustable module; The configured output current adjustable module controls the output of the IO IP core current according to the current control signal.

13. The method according to claim 1, characterized in that The POC input threshold voltage includes a first power-on threshold voltage corresponding to the first power supply and a second power-on threshold voltage corresponding to the second power supply; the custom input box includes: an expected first power-on threshold voltage input box and an expected second power-on threshold voltage input box; the expected first power-on threshold voltage input box is used to obtain the first power-on threshold voltage corresponding to the first power supply input by the user, and the expected second power-on threshold voltage input box is used to obtain the second power-on threshold voltage corresponding to the second power supply input by the user; When the IO IP core is a customized IO IP core, the customized input box also includes: an expected input threshold high level voltage input box, an expected input threshold low level voltage input box, an expected high level output source current input box, and an expected low level output sink current input box, so as to sequentially obtain the input threshold high level voltage, input threshold low level voltage, high level output source current, and low level output sink current input by the user.

14. A method for generating a customized POC IP core, characterized in that: The method is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, and the method includes: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Acquire the POC input threshold voltage input by the user through the multiple customized input boxes; The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core; Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, the power supply comprising: a first power supply and a second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

15. The method according to claim 14, characterized in that The method further includes: generating a layout of the customized POC IP core based on the customized POC IP core.

16. The method according to claim 14, characterized in that The POC input threshold voltage adjustable module further includes: a resistance module group; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

17. The method according to claim 16, characterized in that The method also includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

18. A method for providing a configurable POC IP core, the method being implemented based on a custom EDA tool, characterized in that: include: Providing a POC core circuit module for generating a POC control signal; The POC core circuit module includes: a POC first control signal input port and a POC control signal output port; A POC input threshold voltage adjustable module is provided, which is used to generate a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

19. The method according to claim 18, characterized in that The POC input threshold voltage adjustable module further includes: a resistor module group, and the method further includes: The custom EDA tool selects resistor modules with a number and resistance value corresponding to the POC input threshold voltage from the resistor module group and connects the selected MOS module and resistor module.

20. The method according to claim 18, characterized in that The method further comprises: A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

21. The method according to claim 18, characterized in that The method further comprises: A bottom module is provided, which is used to seal the bottom of a customized POC IP core or a customized IO IP core with power-on control when a customized POC IP core or a customized IO IP core with power-on control is generated based on the provided configurable POC IP core.

22. A device for generating a customized IO IP core with power-on control, characterized in that: The device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, and the device includes: A configurable POC IP core acquisition module is configured to acquire a configurable POC IP core, wherein the configurable POC IP core includes a POC core circuit module and a POC input threshold voltage adjustable module; An IO IP core acquisition module, configured to acquire an IO IP core; A POC input threshold voltage acquisition module, configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes; a configuration module configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage comprising: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module; A first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core; The second connection module is configured to connect the customized POC IP core and the IO IP core to generate a customized IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IOIP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to a power supply, the power supply includes: a first power supply and a second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group; The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, and is used to input the POC control signal to the IO IP core through the POC control signal output port, so that the IO IP core controls the output of its own current through the POC control signal.

23. The device according to claim 22, characterized in that The IO IP core controls the output of its own current through the POC control signal, including: When any one of the first power supply and the second power supply is powered off, the POC control signal is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state; When the first power supply and the second power supply are fully powered on, the POC control signal is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

24. The device according to claim 22, characterized in that The POC input threshold voltage adjustable module further includes: a resistance module group; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

25. The device according to claim 22, characterized in that The custom IO IP core configuration module with power-on control also includes: A bottom module acquisition module is configured to acquire a bottom module, and use the bottom module to seal the bottom of the custom IO IP core with power-on control, so as to generate a bottom-sealed custom IO IP core with power-on control; The filling module acquisition module is configured to be before the bottom module. If the custom IO IP core with power-on control contains a vacant position, then: obtain a filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply, and the ground port of the filling module is grounded; use the filling module to fill the vacant position in the custom IO IP core with power-on control.

26. The device according to claim 22, characterized in that When the IO IP core is a customized IO IP core, the IO IP core acquisition module includes: A first acquisition submodule is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current adjustable module; A second acquisition submodule is configured to acquire, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, and a low level output sink current input by a user for a designated pin module of the custom IO IP core; A first configuration submodule is configured to configure the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, the input threshold adjustable module includes a second MOS module group, and the configuring the input threshold adjustable module includes: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; A second configuration submodule is configured to configure the output current adjustable module according to the high-level output source current and the low-level output sink current, the output current adjustable module includes a third MOS module group, and the configuration of the output current adjustable module includes: selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current adjustable module, wherein the configured output current adjustable module is used to provide a specified output current capability under the control of an IO second control signal of the IO core circuit module; A third connection module is configured to connect the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes: an IO first control signal input port and an IO second control signal output port, the configured input threshold adjustable module includes: an IO first control signal output port, and the configured output current adjustable module includes: an IO second control signal input port; the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module further include: a power supply voltage port and a ground port, the power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module and the configured output current adjustable module are all connected to the power supply, and the ground ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, so as to provide the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current adjustable module, and is used to output the IO second control signal to the configured output current adjustable module based on the IO first control signal and the IO input signal; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO second control signal input port of the configured output current adjustable module is connected to the MOS module selected from the third MOS module group.

27. A device for generating a customized POC IP core, characterized in that: The device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, and the device includes: A configurable POC IP core acquisition module is configured to acquire a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; A POC input threshold voltage acquisition module, configured to acquire the POC input threshold voltage input by the user through the multiple customized input boxes; a configuration module configured to configure the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, the configuration of the POC input threshold voltage adjustable module according to the POC input threshold voltage comprising: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module; A first connection module is configured to connect the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core; Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to a power supply, the power supply comprising: a first power supply and a second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module, so that the POC core circuit module generates a POC control signal based on the POC first control signal and the received power supply voltage signal; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

28. A device for providing a configurable POC IP core, characterized in that: The device is implemented based on a customized EDA tool, and the device includes: A first providing module is configured to provide a POC core circuit module for generating a POC control signal; the POC core circuit module comprises: a POC first control signal input port and a POC control signal output port; The second providing module is configured to provide a POC input threshold voltage adjustable module for generating a POC first control signal of the POC core circuit module; the POC input threshold voltage adjustable module includes a MOS module group and a POC first control signal output port; the POC core circuit module and the POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; the customized EDA tool selects a number of MOS modules corresponding to the POC input threshold voltage from the MOS module group according to the POC input threshold voltage input by the user and connects the selected MOS modules.

29. The device according to claim 28, characterized in that The device also includes: The third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which are used to fill the vacancies in the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POC IP core.

30. The device according to claim 28, characterized in that The device also includes: The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the customized POC IP core or the customized IO IP core with power-on control when generating the customized POC IP core or the customized IO IP core with power-on control based on the provided configurable POCIP core.

31. A chip, characterized in that: A customized IO IP core with power-on control generated by the method described in any one of claims 1 to 13, or a customized POC IP core generated by the method described in any one of claims 14 to 17, or a customized IO IP core with power-on control generated by a configurable POC IP core provided by the method described in any one of claims 18 to 21.

32. An electronic device, characterized in that: Comprising the chip as claimed in claim 31.

33. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 21 is implemented.

34. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 21 is implemented.

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