Method and device for generating integrated unit library, digitization method and device for integrated unit library, and chip

Abstract

The invention relates to the technical field of chip IP cores and EDA, in particular to a method and device for generating an integrated unit library, a digitization method and device of the integrated unit library and a chip. An IP core provided by an existing IP manufacturer is generally an integral module, can only provide fixed input configuration parameters, and cannot be conveniently changed according to chip requirements. According to the method, a customized EDA tool is researched and developed, the IP cores are subjected to customized design, the customized IP cores which support input configuration parameters and can be flexibly configured are reconstructed, and the customized IP cores are integrated into an integrated unit library different from a traditional standard unit library. Therefore, the problems existing in the aspects of comprehensiveness and integration level of a traditional standard unit library are solved, the problems existing in a current traditional POC IP core, an IO IP core and a standard unit are also solved, and the requirements of modern chip design are better met.

Description

Technical Field

[0001] The present disclosure relates to the field of chip IP core and EDA technology, and in particular to a method and device for generating an integrated cell library, and a digital method, device and chip for the integrated cell library. Background Art

[0002] In the field of integrated circuit and chip design, the Standard Cell Library (STD) is an indispensable basic part of the back-end design process. The Standard Cell Library usually includes layout library, symbol library, circuit logic library, etc., covering combinational logic, sequential logic, functional units and special type units, providing designers with pre-designed and optimized library units. These library units are widely used in the process of automatic logic synthesis and layout layout and routing, greatly improving design efficiency and shortening product time to market.

[0003] When forming semiconductor integrated circuits, standardized logic elements are usually designed in advance, and then the logic elements are combined to obtain multiple standard cells, which are pre-registered in the standard cell library. In the design process of digital ICs and mixed analog and digital ICs, designers can automatically perform logic synthesis and layout routing by using these pre-optimized library cells, which greatly simplifies the design process and significantly shortens the product development cycle.

[0004] However, traditional standard cell libraries mainly focus on basic logic circuits, such as INV, NAND, NOR, DFF triggers, etc., but often ignore key modules such as power-on control (POC) IP cores and input / output (IO) IP cores. Although the standard cell libraries provided by most processes contain a series of pre-designed basic standard cells, these libraries are not comprehensive enough and lack comprehensive consideration of analog characteristics in the actual physical world. In fact, every chip needs to have functions such as power-on control and input / output interfaces in real application scenarios to ensure its stable and reliable operation. Therefore, for modern chip design, a more comprehensive and more integrated standard cell library is particularly important.

[0005] How to solve the shortcomings of traditional standard cell libraries in terms of comprehensiveness and integration, so as to better meet the needs of modern chip design and provide more efficient and reliable design tools for modern chip design, is an urgent problem to be solved. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method and device for generating an integrated cell library, and a method, device and chip for digitizing the integrated cell library.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for generating an integrated unit library, the method is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, the customized input boxes are used to obtain configuration parameters input by a user, the method includes:

[0008] Generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control;

[0009] Generate an integrated cell library based on the layout of the customized IP core;

[0010] Wherein, generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameters include: POC input threshold voltage;

[0011] Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and a second configuration parameter input by the user; generating a layout of the customized IO IP core based on the customized IO IP core; the second configuration parameter comprising one or more of the following items: an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level;

[0012] Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameters include one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level;

[0013] Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POCIP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POCIP core and the standard cell module, including: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

[0014] According to an embodiment of the present disclosure, the generating of an integrated cell library based on the layout of the customized IP core includes:

[0015] Verifying the layout of the customized IP core, the verification including: design rule check DRC and layout and schematic comparison LVS;

[0016] Generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core;

[0017] Verify the post-simulation netlist data to ensure that it is consistent with the version of the custom IP core. Figure 1 To;

[0018] Input the post-simulation netlist data into a pre-provided Tcl script file, and add attribute parameters related to the customized IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption;

[0019] Generate a model file according to the Tcl script file, and verify the model file to ensure that the model file can correctly simulate the behavior of the customized IP core, the model file includes: a Verilog model file or a VHDL model file;

[0020] Perform post-simulation verification using the model file;

[0021] An integrated unit library is generated based on the model file using a library file generation tool.

[0022] According to an embodiment of the present disclosure, the method further includes: verifying the integrated cell library.

[0023] According to an embodiment of the present disclosure, generating post-simulation netlist data of the layout of the customized IP core includes:

[0024] Extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool; the parasitic parameters include: resistance, capacitance and inductance;

[0025] Obtaining pre-simulation netlist data of the layout of the customized IP core;

[0026] The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core containing the parasitic parameters.

[0027] According to an embodiment of the present disclosure, the step of using a library file generation tool and generating an integrated unit library based on the model file includes:

[0028] Select the model file;

[0029] Configuring properties of the integrated unit library, the properties of the integrated unit library including: library name, version and description;

[0030] Execute the command or operation used to generate the library file in the library file generation tool.

[0031] According to an embodiment of the present disclosure, the step of generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user includes:

[0032] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0033] Acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0034] The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module;

[0035] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal;

[0036] Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0037] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded;

[0038] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0039] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistor module group;

[0040] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

[0041] According to an embodiment of the present disclosure, the method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0042] According to an embodiment of the present disclosure, generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user includes:

[0043] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic release protection level adjustable module, wherein the input threshold adjustable module includes a second MOS module group, and the output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes a plurality of MOS modules;

[0044] Obtaining, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level input by a user for a specified pin module of a custom IO IP core;

[0045] Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0046] According to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, the output current and electrostatic release protection level adjustable module is configured, including: according to the electrostatic release protection level, one or more unit output current and electrostatic release protection level adjustable modules are selected from the output current and electrostatic release protection level adjustable modules and the selected one or more unit output current and electrostatic release protection level adjustable modules are connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module includes a third MOS module group; according to the high-level output pull current and the low-level output sink current, a MOS module is selected from the third MOS module group and the selected MOS module is connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module;

[0047] Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core;

[0048] Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port and an IO first control signal output port; the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port;

[0049] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0050] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0051] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic release protection level adjustable module based on the IO first control signal and the IO input signal;

[0052] The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability;

[0053] Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0054] According to an embodiment of the present disclosure, the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the second MOS module group, including: in any unit output current and electrostatic release protection level adjustable module of the configured output current and electrostatic release protection level adjustable module:

[0055] All MOS modules in any one unit electrostatic release protection module are connected to the IO second control signal input port of any one unit electrostatic release protection module, and all connected MOS modules provide unit electrostatic release protection capability and unit output current capability at the same time;

[0056] Alternatively, some MOS modules in any one of the unit electrostatic release protection modules are connected to the IO second control signal input port of any one of the unit electrostatic release protection modules, and some of the connected MOS modules provide corresponding electrostatic release protection capability and output current capability at the same time, and the remaining MOS modules provide corresponding electrostatic release protection capability;

[0057] Alternatively, all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

[0058] According to an embodiment of the present disclosure, when some MOS modules in any unit electrostatic release protection module are connected to the IO second control signal input port of any unit electrostatic release protection module, in the remaining MOS modules of any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port;

[0059] When all the MOS modules in any one of the unit electrostatic release protection modules are disconnected from the IO second control signal input port of any one of the unit electrostatic release protection modules, among all the MOS modules in any one of the unit electrostatic release protection modules: the gates of some of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0060] According to an embodiment of the present disclosure, the gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port, including:

[0061] The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the ground port.

[0062] According to an embodiment of the present disclosure, when some MOS modules in any unit electrostatic release protection module are connected to the IO second control signal input port of any unit electrostatic release protection module, in the remaining MOS modules of any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the grounding port;

[0063] When all the MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, among all the MOS modules in any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the grounding port.

[0064] According to an embodiment of the present disclosure, the gates of a part of the MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistor module and the ground port, including:

[0065] The gate and source of one part of the MOS modules are short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the resistor module and the grounding port.

[0066] According to an embodiment of the present disclosure, generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameter input by the user includes:

[0067] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0068] Get IO IP core;

[0069] Acquire the POC input threshold voltage input by the user through the multiple customized input boxes;

[0070] The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module;

[0071] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal;

[0072] Connect the customized POC IP core and the IO IP core to generate an IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0073] The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to the first power supply and the second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded;

[0074] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group;

[0075] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

[0076] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0077] When any one of the first power supply and the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0078] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0079] According to an embodiment of the present disclosure, the IO IP core is a customized IO IP core, and obtaining the IO IP core includes:

[0080] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic release protection level adjustable module, wherein the input threshold adjustable module includes a second MOS module group, and the output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes a plurality of MOS modules;

[0081] Obtaining, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level input by a user for a specified pin module of a custom IO IP core;

[0082] Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0083] According to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, the output current and electrostatic release protection level adjustable module is configured, including: according to the electrostatic release protection level, one or more unit output current and electrostatic release protection level adjustable modules are selected from the output current and electrostatic release protection level adjustable modules and the selected one or more unit output current and electrostatic release protection level adjustable modules are connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module includes a third MOS module group; according to the high-level output pull current and the low-level output sink current, a MOS module is selected from the third MOS module group and the selected MOS module is connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module;

[0084] Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core;

[0085] Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port and an IO first control signal output port; the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port;

[0086] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0087] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0088] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic release protection level adjustable module based on the IO first control signal and the IO input signal;

[0089] The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

[0090] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0091] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0092] Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current and electrostatic discharge protection level adjustable module;

[0093] The configured output current and electrostatic discharge protection level adjustable module controls the output of the IO IP core current according to the current control signal.

[0094] According to an embodiment of the present disclosure, generating the customized unit with power-on control according to the POC IP core and the standard unit module includes:

[0095] Obtain a POC IP core; the POC IP core comprises: a first power input terminal, a second power input terminal and a control signal output terminal;

[0096] Acquire a standard cell module; the standard cell module comprises: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal and a cell signal output terminal;

[0097] The POC IP core and the standard cell module are connected to generate a custom cell with power-on control; wherein the first logic control signal input terminal of the standard cell module is connected to a first power circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power circuit module; the second logic control signal input terminal of the standard cell module is connected to a second power circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power circuit module; the power input terminal of the standard cell module is connected to a power supply;

[0098] The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply;

[0099] The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal;

[0100] The obtaining of the voltage status of the first power supply and the second power supply includes:

[0101] Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0102] Comparing the current voltage value of the second power supply with a preset second power-on threshold voltage, when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state;

[0103] The generating a first control signal according to the voltage states of the first power supply and the second power supply comprises:

[0104] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0105] According to an embodiment of the present disclosure, the method further includes:

[0106] Acquire a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal;

[0107] The power input end of the standard cell module is connected to the power supply, and the control signal output end of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input end of the standard cell module through the first switch control circuit module, and the control signal output end of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input end of the first switch control circuit module, the control signal output end of the POC IP core is connected to the second input end of the first switch control circuit module, and the output end of the first switch control circuit module is connected to the power input end of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal, and uses the second control signal to control the connection or disconnection of the power supply, so that when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally;

[0108] The step of generating a second control signal according to the first control signal and using the second control signal to control the connection or disconnection of the power supply includes:

[0109] When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end of the first switch control circuit module;

[0110] When the first control signal is at a low level, the second control signal is a disconnection signal, and the disconnection signal disconnects the output end of the first switch control circuit module;

[0111] When the output end of the first switch control circuit module is closed, the power supply is turned on;

[0112] When the output end of the first switch control circuit module is disconnected, the power supply is cut off.

[0113] According to an embodiment of the present disclosure, the method further includes:

[0114] Acquire a second switch control circuit module; wherein the second switch control circuit module comprises: a signal input terminal and a signal output terminal;

[0115] The control signal output terminal of the POC IP core is connected to the standard cell module, including:

[0116] The control signal output end of the POC IP core is connected to the signal input end of the second switch control circuit module; the signal output end of the second switch control circuit module is connected to the cell signal output end of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally;

[0117] The step of generating a third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module includes:

[0118] When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the cell signal output terminal of the standard cell module;

[0119] When the first control signal is at a low level, the third control signal is a disconnection signal, and the disconnection signal cuts off the cell signal output end of the standard cell module;

[0120] When the cell signal output terminal of the standard cell module is turned on, the output of the standard cell module is turned on;

[0121] When the cell signal output terminal of the standard cell module is cut off, the output of the standard cell module is cut off.

[0122] According to an embodiment of the present disclosure, the standard cell module further includes: a control signal input terminal;

[0123] The control signal output end of the POC IP core is connected to the standard cell module, including: the control signal output end of the POC IP core is connected to the control signal input end of the standard cell module, so that the standard cell module controls whether it has output according to the first control signal;

[0124] The standard unit module controls whether it has output according to the first control signal, including:

[0125] When the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally;

[0126] When the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

[0127] According to an embodiment of the present disclosure, the POC IP core is a customized POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is a first power-on threshold voltage input by a user, the preset second power-on threshold voltage is a second power-on threshold voltage input by a user;

[0128] or,

[0129] The POC IP core is a default POC IP core; the default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values;

[0130] The default POC IP core includes: a connected POC IP core circuit module and a default threshold voltage module, wherein the default threshold voltage module includes MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

[0131] In a second aspect, an embodiment of the present disclosure provides a method for digitizing an integrated cell library, the method being implemented based on a customized EDA tool, the customized EDA tool integrating an integrated cell library generated using the method described in any one of the first aspects, the integrated cell library comprising a basic standard cell and a customized IP cell corresponding to a customized IP core, the customized IP core comprising one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control, the method comprising:

[0132] Acquire an RTL code for calling the basic standard cell and / or the custom IP cell corresponding to the custom IP core, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the custom IP cell;

[0133] Converting the RTL code into a gate-level netlist using a synthesizer;

[0134] Importing the synthesized gate-level netlist into a placement and routing tool;

[0135] Performing physical layout and routing based on the gate-level netlist to generate layout and routing data; performing physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0136] According to an embodiment of the present disclosure, the method further includes:

[0137] The layout and routing data is verified, and the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS, and electrical rule check ERC.

[0138] According to an embodiment of the present disclosure, the method further includes:

[0139] Manufacturing data is generated according to the layout and wiring data, and the manufacturing data includes: a GDSII file and a manufacturing mask.

[0140] In a third aspect, an embodiment of the present disclosure provides a device for generating an integrated unit library, the device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, the customized input boxes are used to obtain configuration parameters input by a user, and the device includes:

[0141] A customized IP layout generation module is configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the layout of the customized IP includes one or more of the following items: a layout of a customized POC IP core, a layout of a customized IO IP core, and a layout of an IO IP core with power-on control;

[0142] An integrated cell library generation module, configured to generate an integrated cell library based on the layout of the customized IP core;

[0143] Wherein, generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameters include: POC input threshold voltage;

[0144] Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and a second configuration parameter input by the user; generating a layout of the customized IO IP core based on the customized IO IP core; the second configuration parameter comprising one or more of the following items: an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level;

[0145] Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameters include one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level;

[0146] Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POCIP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POCIP core and the standard cell module, including: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

[0147] In a fourth aspect, an embodiment of the present disclosure provides a digitization device for an integrated cell library, wherein the digitization device is implemented based on a customized EDA tool, wherein the customized EDA tool integrates an integrated cell library generated using the method described in any one of the first aspects, wherein the integrated cell library includes a basic standard cell and a customized IP cell corresponding to a customized IP core, wherein the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control, wherein the digitization device includes:

[0148] An RTL code acquisition module is configured to acquire an RTL code for calling the basic standard unit and / or the customized IP unit, wherein the RTL code includes an instance of a hardware description language module describing the basic standard unit and / or an instance of a hardware description language module describing the customized IP unit;

[0149] A gate-level netlist generation module, configured to convert the RTL code into a gate-level netlist using a synthesizer;

[0150] A gate-level netlist import module, configured to import the synthesized gate-level netlist into a placement and routing tool;

[0151] A layout and routing data generation module is configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0152] According to an embodiment of the present disclosure, the digitizing device further includes:

[0153] The layout and routing data verification module is configured to verify the layout and routing data, wherein the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS, and electrical rule check ERC.

[0154] According to an embodiment of the present disclosure, the digitizing device further includes:

[0155] The manufacturing data generating module is configured to generate manufacturing data according to the layout and wiring data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

[0156] In a fifth aspect, a chip is provided in an embodiment of the present disclosure, wherein the chip is manufactured using library cells in an integrated cell library generated by the method described in any one of the first aspects, wherein the library cells include basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following items: customized POC IP core, customized IO IP core, IO IP core with power-on control, and customized cells with power-on control.

[0157] In a sixth aspect, an electronic device is provided in an embodiment of the present disclosure, comprising the chip described in the fifth aspect.

[0158] In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in any one of the first aspect and the second aspect is implemented.

[0159] In an eighth aspect, a computer program product is provided in an embodiment of the present disclosure, comprising a computer program, characterized in that when the computer program is executed by a processor, the method described in any one of the first aspect and the second aspect is implemented.

[0160] The IP core provided by the existing IP manufacturers is usually an integral module, which can only provide fixed input configuration parameters and cannot be easily changed according to the chip requirements. The present invention discloses the development of a customized EDA tool, and customizes the IP core, reconstructing it into a customized IP core including a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control, and integrating these customized IP cores into an integrated unit library different from the traditional standard unit library, wherein the customized POC IP core and the customized IO IP core support input configuration parameters that can be flexibly configured, and the IO IP core with power-on control and the customized unit with power-on control combine the POC IP core with the existing IO IP core and the standard unit. This solves the problems existing in the comprehensiveness and integration of the traditional standard unit library, and also solves the problems existing in the current traditional POC IP core, IO IP core and standard unit, thereby better meeting the needs of modern chip design.

[0161] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0162] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0163] Figure 1 A flowchart showing a method for generating an integrated cell library according to an embodiment of the present disclosure is shown;

[0164] Figure 2 A flow chart showing a method for generating a customized POC IP core based on a configurable POC IP core according to an embodiment of the present disclosure;

[0165] Figure 3 A schematic diagram showing the structure of a customized POC IP core according to an embodiment of the present disclosure is shown;

[0166] Figure 4 A flow chart showing a method for generating a customized IO IP core based on a configurable IO IP core with adjustable input threshold voltage, output current capability and electrostatic discharge protection level according to an embodiment of the present disclosure;

[0167] Figure 5A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown;

[0168] Figure 6 A schematic diagram showing the connection of an IO core circuit module, a configured input voltage adjustable module, and a configured output current and electrostatic discharge protection level adjustable module in a method for generating a customized IO IP core based on a configurable IO IP core according to an embodiment of the present disclosure;

[0169] Figure 7 A flow chart showing a method for generating an IOIP core with power-on control based on a configurable POC IP core according to an embodiment of the present disclosure;

[0170] Figure 8 A schematic diagram of the structure of an IO IP core with power-on control according to an embodiment of the present disclosure is shown;

[0171] Fig. 9 A flowchart showing a method for generating a customized unit with power-on control according to an embodiment of the present disclosure;

[0172] Fig.10 A structural connection diagram of a customization unit with power-on control according to an embodiment of the present disclosure is shown;

[0173] Fig.11 A structural connection diagram showing another customized unit with power-on control according to an embodiment of the present disclosure;

[0174] Fig.12 A structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure is shown;

[0175] Fig.13 A flow chart showing a method for digitizing an integrated cell library according to an embodiment of the present disclosure;

[0176] Fig.14 A schematic structural diagram of a device for generating an integrated cell library according to an embodiment of the present disclosure is shown;

[0177] Fig.15 A schematic structural diagram of a digitization device for an integrated cell library according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0178] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0179] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0180] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0181] As mentioned above, traditional standard cell libraries mainly focus on the design of basic logic circuits, such as INV, NAND, NOR, DFF triggers, etc., but are lacking in comprehensiveness, especially when dealing with key modules in modern chip design, such as POC IP cores and IO IP cores.

[0182] How to solve the deficiencies of traditional standard cell libraries in terms of comprehensiveness and integration? After repeated demonstrations and careful consideration, the inventors of the present disclosure proposed a method for designing a more comprehensive and more integrated integrated cell library based on a customized IP core using a customized EDA tool.

[0183] The integrated cell library involved in the present disclosure refers to a new library that integrates traditional standard cells, customized cells and customized IP cores, such as customized POC IP cores, customized IO IP cores, IO IP cores with power-on control and customized cells with power-on control, which can be imported into customized EDA tools for users to choose and use the required library cells when designing chips.

[0184] Among them, the custom cell is relative to the standard cell in the prior art standard cell library. The standard cell refers to a pre-designed, verified and optimized circuit module, which usually has fixed functions and interfaces, including basic logic unit modules such as logic units, storage units, and arithmetic units. The custom cell is a unit customized according to the logic design, performance requirements and specific design constraints of the specific circuit. In the present disclosure, the custom cell includes a custom cell with power-on control, which is obtained by combining the traditional standard cell with the POC IP, so that the traditional standard cell has the power-on control function.

[0185] Customized IP cores are relative to standard IP cores in existing technologies. Standard IP cores refer to pre-designed integrated circuit design modules with general functions. They are usually designed and verified, and follow certain industry standards to ensure their compatibility and interoperability in different chip designs. They are highly versatile, reusable, and standardized. In integrated circuit design tools (such as EDA tools), IP core libraries are usually integrated, and designers design chips by selecting the required IP cores from the IP core library. In general, standard IP cores in traditional processes have fixed configuration parameters.

[0186] For example, for the POC IP core, the input threshold voltage is usually fixed. For example, for a 5V power supply, the power-on threshold voltage is fixed at 4.7V, and the power-off threshold voltage is fixed at 2.5V. Users cannot change it after selecting it. But the actual situation is that even for the same process node and the same operating voltage, the power-on threshold voltage and power-off threshold voltage are different for different process factories and different POC IPs. For example, for a 5V power supply, some power-on threshold voltages need to reach 4.7V to indicate that the power supply is in the power-on state, while others only need to be 4.5V; for a 1.8V power supply, some power-off threshold voltages are 0.6V to indicate that the power supply is in the power-off state, while others must be 0.4V.

[0187] For another example: For IO IP cores, most of the IO IP cores provided by mainstream process plants only have fixed input threshold voltages (input threshold high level voltage VIH, input threshold low level voltage VIL). Even for the same process node and the same operating voltage, the input threshold high level voltage VIH and input threshold low level voltage VIL of IO IP cores produced by different process plants are not exactly the same. For example, the input threshold high level voltage VIH uses 0.65*VDD, 0.8*VDD or an absolute level value (such as 0.4V), and the input threshold low level voltage VIL uses 0.35*VDD, 0.3*VDD or an absolute level value (such as 0.8V, 1.2V). For different analog chips and digital-analog hybrid chips, the input threshold voltage will have different definition ranges depending on the application.

[0188] At the same time, the output current capability of the IO IP core is also fixed. For example, Huahong HHGRACE only provides three output current capabilities: 4mA, 8mA, and 16mA; TSMC mainly provides four output current capabilities: 2mA, 4mA, 8mA, and 12mA; SMIC mainly provides six output current capabilities: 2mA, 4mA, 8mA, 12mA, 16mA, and 24mA. However, in actual industrial chip design, the required output current capability of the IO IP core is also different. Some only require μA-level output current capability, such as 100μA, 500μA, etc., while others require an output current capability greater than 24mA.

[0189] In addition, most of the current mainstream process factories provide IO IPs that can only resist 2kV ESD (Electrostatic Discharge). However, in industrial chips, many power driver chips need to resist 4kV, 5kV ESD, and some interface chips even need to resist ESD above 10kV. Therefore, the ESD provided by the current process factory-specific IO IP cannot meet the design of chips for complex industrial application scenarios such as electromagnetic heat.

[0190] Another example: the IO IP cores provided by the existing IO IP library still face challenges in power management, especially when the power is suddenly cut off. Specifically, when one of the power supplies in the dual power circuit is suddenly cut off, the traditional IO IP design cannot provide accurate judgment for the subsequent circuit, resulting in some circuits working normally while the other circuits fail, thereby generating erroneous logic signals, which seriously affects the function of the entire chip. In addition, when the power supply is not powered on, if the IO circuit still outputs a large current, there is a potential safety risk.

[0191] Another example: for standard cells in the standard cell library that use a multi-power supply voltage solution, when one of the power supply voltages is suddenly powered off for some reason, the subsequent circuit cannot make a judgment on this situation, so that part of the circuit still works normally, while the other part of the circuit cannot work normally. The two signals have already generated errors before they are transmitted to the subsequent standard cell module. When the wrong logic signal is output or no signal is output, the standard cell cannot correctly perform its predetermined logic function. This logic error may be transmitted along the circuit chain, eventually causing the entire circuit system to produce wrong results or fail to perform the expected task, burying a major hidden danger in the industrial production process.

[0192] When designing an integrated cell library, the inventor of the present disclosure, in view of the problems existing in the POC IP core, IO IP core and standard cell in the prior art, in order to configure the POC IP core and IO IP core according to the different configuration parameters required by the actual chip, realize the flexible configuration of POC IP and IO IP, and in order to realize that the traditional standard cell and IO IP core can monitor and correctly deal with the situation where the dual power supply is not fully powered on, the customized POC IP core, customized IO IP core, IO IP core with power-on control and customized cell with power-on control that can solve the above problems are integrated into a library to form an integrated cell library. At the same time, combined with the corresponding modification of the EDA tool, the modified part is installed as a plug-in into the existing EDA tool, thereby obtaining a customized EDA tool. In this way, designers select the required custom cells or custom IP cores from the integrated cell library and use customized EDA tools to configure the parameters of the selected custom cells or custom IP cores according to the actual design requirements of the chip. In this way, while solving the problems of the traditional standard cell library in terms of comprehensiveness and integration, the designers also solve the above problems existing in the current traditional POC IP cores, IO IP cores and standard cells, thereby better meeting the needs of modern chip design.

[0193] Figure 1 A flow chart of a method for generating an integrated cell library according to an embodiment of the present disclosure is shown, wherein the method is implemented based on a customized EDA tool, wherein the customized EDA tool provides a GUI interface, wherein the GUI interface includes a plurality of customized input boxes, and wherein the customized input boxes are used to obtain configuration parameters input by a user. Figure 1 As shown, the method includes the following steps S110 to S120:

[0194] In step S110, a layout of a customized IP core is generated according to the configuration parameters input by the user; the customized IP includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control.

[0195] In step S120, an integrated cell library is generated based on the layout of the customized IP core.

[0196] According to an embodiment of the present disclosure, when generating an integrated cell library based on the layout of the customized IP core, the following steps are included:

[0197] First, the layout of the customized IP core is verified, and the verification includes: design rule checking DRC and layout and schematic comparison LVS; generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core; verifying the post-simulation netlist data to ensure that it is consistent with the layout of the customized IP core. Figure 1 The method comprises the steps of: inputting the post-simulation netlist data into a pre-provided Tcl (Tool Command Language) script file, and adding attribute parameters related to the custom IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption; generating a model file according to the Tcl script file, and verifying the model file to ensure that the model file can correctly simulate the behavior of the custom IP core, wherein the model file includes: a Verilog model file or a VHDL model file; performing post-simulation verification using the model file; and generating an integrated unit library based on the model file using a library file generation tool.

[0198] Then, the layout of the customized IP core is verified, and the verification includes: design rule check DRC and layout and schematic comparison LVS.

[0199] Among them, Design Rule Check (DRC) refers to using layout verification tools to perform DRC checks on the layout to ensure that the layout complies with design rules, such as minimum line width, minimum spacing, etc.

[0200] Layout Versus Schematics (LVS) refers to the use of LVS verification tools to compare the layout with the schematic to ensure the logical consistency between the layout and the schematic. Among them, LVS verification tools include but are not limited to: Dracula, which will check whether the layout and logic diagram match, and compare the logical equivalence between the transistor-level SPICE netlist extracted from the layout and the gate-level Verilog netlist generated in the design phase (which needs to be converted into a SPICE netlist). The LVS verification process helps to ensure the correctness and reliability of chip design.

[0201] After analyzing and processing the verification results of DRC and LVS, if there are errors or inconsistencies, it is necessary to return to step S110 for modification.

[0202] Afterwards, post-simulation netlist data of the layout of the customized IP core is generated; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core.

[0203] When generating post-simulation netlist data of the layout of the custom IP core, extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool (such as FastCap, Q3D, etc.); the parasitic parameters include: resistance, capacitance and inductance;

[0204] Obtaining pre-simulation netlist data of the layout of the customized IP core;

[0205] The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core containing the parasitic parameters.

[0206] Next, the post-simulation netlist data is verified to ensure that it is consistent with the version of the custom IP core. Figure 1 To.

[0207] The verification includes but is not limited to: netlist consistency check and functional verification. During the netlist consistency check, the post-simulation netlist data and the layout of the customized IP core are compared to ensure that the two are consistent in circuit structure and connection relationship; during functional verification, the post-simulation netlist data is simulated using a circuit simulation tool to verify whether its function meets the design requirements.

[0208] Afterwards, the post-simulation netlist data is input into a pre-provided Tcl script file, and attribute parameters related to the customized IP core are added to the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption.

[0209] Specifically, first prepare a predefined Tcl script file, then input the post-simulation netlist data into the Tcl script file, and finally add relevant attribute parameters in the Tcl script file according to the characteristics of the customized IP core, such as function description, area, pin information, delay, power consumption, etc.

[0210] Next, a model file is generated according to the Tcl script file, and the model file is verified to ensure that the model file can correctly simulate the behavior of the custom IP core, and the model file is used for post-simulation verification. The model file includes: a Verilog model file or a VHDL model file.

[0211] Specifically, the Tcl script file is first parsed to extract the post-simulation netlist data and attribute parameters, and then a model generation tool (such as ModelSim, VCS, etc.) is used to generate a Verilog model file or a VHDL model file based on the extracted data and parameters. If necessary, an IBIS model file can also be generated.

[0212] Finally, a library file generation tool is used to generate an integrated unit library based on the model file, wherein the integrated unit library includes a customized IP unit corresponding to the customized IP core.

[0213] The custom IP unit in the present disclosure refers to an intellectual property (IP) module with specific functions and performance generated in a customized manner according to the specific needs of the user in the integrated circuit (IC) design. These IP modules can be digital circuits, analog circuits or mixed signal circuits, which are designed as reusable components for integration in different IC designs.

[0214] In the present disclosure, for a customized POC IP core, a customized IO IP core, and an IO IP core with power-on control, the corresponding customized IP units are: a customized POC IP unit, a customized IO IP unit, and an IO IP unit with power-on control.

[0215] In general, custom IP units are IP modules with specific functions and performances generated in a customized manner. They can meet the special needs of users in different IC designs and improve the flexibility and efficiency of the design.

[0216] The library file generation tool may be a Library Generator.

[0217] According to an embodiment of the present disclosure, the step of using a library file generation tool and generating an integrated unit library based on the model file includes:

[0218] First, select the model file.

[0219] Then, the properties of the integrated unit library are configured, and the properties of the integrated unit library include: library name, version and description.

[0220] Afterwards, the command or operation for generating the library file in the library file generating tool is executed.

[0221] Finally, the generated integrated cell library is saved in a standard library file format for use by custom EDA tools.

[0222] After executing step S120, the method further includes: verifying the integrated cell library.

[0223] The specific implementation of step S110 is described in detail below.

[0224] The customized IP core involved in step S110 includes, but is not limited to: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control.

[0225] When the customized IP core is a customized POC IP core, a layout of the customized POC IP core is generated according to the configuration parameters input by the user, including: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; and generating the layout of the customized POC IP core based on the customized POC IP core.

[0226] Wherein, the first configuration parameter includes: POC input threshold voltage.

[0227] Figure 2 FIG. 1 is a flow chart showing a method for generating a customized POC IP core based on a configurable POC IP core according to an embodiment of the present disclosure. Figure 2 As shown, generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user specifically includes the following steps S210 to S240:

[0228] In step S210, a configurable POC IP core is obtained, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module.

[0229] After research, the inventors of the present disclosure found that the reason why the existing POC IP core can only provide a fixed input threshold voltage (including a power-on threshold voltage and a power-down threshold voltage) is that the POC IP core is designed as an integral module, which makes it impossible to easily change it according to chip requirements. As a result, the existing POC IP core can only provide a fixed input threshold voltage, thereby failing to meet the actual requirements of different chips for different input threshold voltages.

[0230] The present disclosure splits the existing overall POC IP core into multiple functional modules, and separately configures the input threshold voltage module therein, thereby realizing a configurable POC IP core. In the configurable POC IP core, each function inside it can be easily and independently controlled, and then it can be automatically adjusted according to the actual needs of different chips, thereby realizing flexible configuration of the POC input threshold voltage.

[0231] In the present disclosure, the configurable POC IP core is no longer an integral module, but includes a POC core circuit module and a POC input threshold voltage adjustable module, wherein the POC input threshold voltage adjustable module can be configured according to the POC input threshold voltage input by the user, so that the customized POC IP core generated based on the configured POC input threshold voltage adjustable module meets the actual demand of supporting the specified POC input threshold voltage.

[0232] Wherein, the configurable POC IP core is provided by a customized EDA tool.

[0233] In step S220, the POC input threshold voltage input by the user is obtained through the plurality of customized input boxes.

[0234] In general, the POC IP core is connected to two power supplies, namely the first power supply and the second power supply. For each power supply, there can be two POC input threshold voltages, namely the power-on threshold voltage and the power-off threshold voltage, which represent the specific voltage levels of the power supply during the power-on and power-off processes. Among them, the power-on threshold voltage refers to the voltage point at which the chip starts to work normally or starts its internal circuit when the power supply voltage reaches or exceeds a certain value during the chip power-on process; the power-off threshold voltage refers to the voltage point at which the chip starts to shut down its internal circuit or enters low power mode when the power supply voltage drops below a certain value during the power-off process. The specific values ​​of the power-on threshold voltage and the power-off threshold voltage will vary depending on the design and application requirements of the chip. In some cases, both the power-on threshold voltage and the power-off threshold voltage are defined as a voltage range to adapt to the fluctuation of the power supply voltage.

[0235] In a specific embodiment, four input boxes are provided through the graphical user interface of the customized EDA tool, namely: "Expected first power-on threshold voltage" input box, "Expected second power-on threshold voltage", "Expected first power-down threshold voltage" input box and "Expected second power-down threshold voltage" input box. After the user enters the power-on threshold voltage and power-down threshold voltage expected to be achieved by the first power supply and the second power supply of the POCIP core in the four input boxes, the customized EDA tool can obtain the first power-on threshold voltage, the second power-on threshold voltage, the first power-down threshold voltage and the second power-down threshold voltage input by the user.

[0236] Wherein, the POC input threshold voltage is a positive integer multiple of the product of the preset minimum proportional coefficient and the power supply voltage, or the POC input threshold voltage is a positive integer multiple of the preset minimum unit voltage. For example: when the power-on threshold voltage and the power-off threshold voltage are input in proportion, the input voltage value can be set to a positive integer multiple of 0.05*VDD, such as: 0.2*VDD. When the power-on threshold voltage and the power-off threshold voltage are input in absolute value, the input voltage value can be set to an integer multiple of 0.1V. For example, when the power supply voltage is 5V, the power-on threshold voltage value can be filled in 3.8V, 3.9V, 4.0V, ..., 4.5V; when the power supply standard voltage is 1.8V, the power-on threshold voltage value can be filled in 1.3V, 1.4V, ..., 1.8V. Those skilled in the art should understand that the specific values ​​of the preset minimum proportional coefficient and the preset minimum unit voltage can be set according to the layout area of ​​the customized POC IP core required by the user and the accuracy of the desired input threshold voltage, and are not limited thereto.

[0237] In step S230, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, and the POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0238] As mentioned above, the POC input threshold voltage includes: a first power-on threshold voltage, a second power-on threshold voltage, a first power-down threshold voltage, and a second power-down threshold voltage. The first power-on threshold voltage and the first power-down threshold voltage are configuration parameters for a first power supply connected to the POC IP core, and the second power-on threshold voltage and the second power-down threshold voltage are configuration parameters for a second power supply connected to the POC IP core.

[0239] In the present disclosure, the POC first control signal of the POC core circuit module is a voltage level that provides a reference to the POC core circuit module, so that the POC core circuit module can compare and judge the power supply voltage received from the external power supply with the POC first control signal, thereby obtaining a judgment result of whether the power supply corresponding to the power supply voltage value is in a power-on or power-off state.

[0240] The first MOS module group includes multiple MOS modules, each of which corresponds to a PMOS tube or NMOS tube when the custom IO IP core is implemented as an integrated circuit or chip, that is, the first MOS module group corresponds to a MOS tube group.

[0241] Assume that the first MOS module group includes m PMOS modules and n NMOS modules; when configuring the POC input threshold voltage adjustable module, p PMOS modules and q NMOS modules are selected from the first MOS module group according to the POC input threshold voltage for connection, thereby generating a configured POC input threshold voltage adjustable module to achieve the desired POC input threshold voltage, wherein p≤m, q≤n.

[0242] In a specific embodiment, the POC input threshold voltage adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the first MOS module group. According to the POC input threshold voltage, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the first MOS module group, thereby selecting a MOS module from the first MOS module group and connecting the selected MOS module to achieve a desired POC input threshold voltage.

[0243] In order to save the user's operation time, the embodiment of the present disclosure can pre-set multiple configurations for the POC input threshold voltage adjustable module, and each configured input threshold voltage adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different POC input threshold voltages. When the user inputs the desired POC input threshold voltage, the corresponding configured POC input threshold voltage adjustable module can be directly selected.

[0244] In another specific embodiment, a plurality of MOS module groups are pre-set in the first MOS module group of the POC input threshold voltage adjustable module, and each MOS module group corresponds to a different POC input threshold voltage; thus, when the user inputs the required POC input threshold voltage, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0245] In a specific embodiment, the POC input threshold voltage adjustable module includes not only a MOS module group but also a resistor module group.

[0246] Correspondingly, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage further includes: selecting a resistor module with a quantity and resistance value corresponding to the POC input threshold voltage from the resistor module group and connecting the selected MOS module and resistor module to generate the configured POC input threshold voltage adjustable module. That is, the configured POC input threshold voltage adjustable module is configured after jointly selecting a MOS module and a resistor module in the MOS module group and the resistor module group according to the POC input threshold voltage.

[0247] In order to configure the POC input threshold voltage adjustable module more accurately according to the POC input threshold voltage, it is possible to choose to perform resistor subdivision adjustment. The EDA tool will determine whether resistor subdivision is required based on the design requirements and circuit characteristics. Specifically, the EDA tool will first read the design specification document to understand the design requirements for the accuracy and stability of the POC input threshold voltage, and then the EDA tool will analyze the topology and component parameters of the POC input threshold voltage adjustable module, evaluate its impact on the threshold voltage, and then based on the design requirements and circuit characteristics, the EDA tool will configure the POC input threshold voltage adjustable module, including selecting the parameters of components such as resistors. After that, the EDA tool will use the circuit simulation function to simulate the working conditions of the configured POC input threshold voltage adjustable module under different conditions, calculate the actual value of the POC input threshold voltage, and then compare the simulated POC input threshold voltage with the target value in the design requirements to calculate the deviation. If the deviation is within the allowable error range, there is no need to perform resistor subdivision adjustment. If the deviation exceeds the allowable range, resistor subdivision adjustment is required.

[0248] When resistance subdivision is required, resistance subdivision adjustment is performed on the configured POC input threshold voltage adjustable module, specifically including: adjusting the resistance value or connection mode of the resistor in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment of the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

[0249] In step S240, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core.

[0250] The generated custom POC IP core also includes a bottom module and a filling module.

[0251] The present disclosure inserts a bottom module at the bottom of the customized POC IP core to achieve the requirement of overall circuit layout closure and meet the design rule check. In order to ensure the smoothness and integrity of the wiring in the customized POC IP core, the wiring requirements in the customized POC IP core layout are met by the bottom module. Figure 3 A schematic diagram of the structure of a customized POC IP core according to an embodiment of the present disclosure is shown.

[0252] Among them, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0253] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded.

[0254] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group, so that when the configured POC input threshold voltage adjustable module is implemented as an integrated circuit or a chip, the POC first control signal is implemented through the selected MOS tube.

[0255] Through the customized POC IP core provided in the present disclosure, users can configure the POC IP according to the different threshold voltages required by the actual chip, thereby achieving flexible configuration of the POC input threshold voltage and meeting the design requirements of complex industrial chips.

[0256] When the customized IP core is a customized IO IP core, generating a layout of the customized IO IP core according to the configuration parameters input by the user includes: generating the customized IO IP core according to the configurable IO IP core and the second configuration parameters input by the user; and generating a layout of the customized IO IP core based on the customized IO IP core.

[0257] The second configuration parameter includes one or more of the following items: input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level.

[0258] Figure 4 A flow chart showing a method for generating a customized IO IP core based on a configurable IO IP core with adjustable input threshold voltage, output current capability, and electrostatic discharge protection level according to an embodiment of the present disclosure. Figure 4 As shown, generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user specifically includes the following steps S410 to S450:

[0259] In step S410, a configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, an output current and electrostatic release protection level adjustable module, the input threshold adjustable module includes a second MOS module group, the output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes a plurality of MOS modules.

[0260] In the present disclosure, the configurable IO IP core is no longer an integral module, but includes multiple functional modules such as an IO core circuit module, an input threshold adjustable module, multiple unit output currents and an electrostatic discharge protection level adjustable module. Different functional modules implement corresponding functions, so that the customized EDA tool can perform more customizable and more sophisticated configurations on the input threshold voltage, output current capability and electrostatic discharge protection capability of the configurable IO IP core.

[0261] The second MOS module group included in the input threshold adjustable module includes a plurality of MOS modules, each of the plurality of MOS modules corresponds to a PMOS tube or an NMOS tube when the custom IO IP core is implemented as an integrated circuit or a chip, that is, at this time, the input threshold adjustable module includes a plurality of PMOS tubes and a plurality of NMOS tubes.

[0262] Similarly, in the multiple MOS modules included in each unit output current and electrostatic release protection level adjustable module, each MOS module corresponds to a PMOS tube or an NMOS tube when the customized IO IP core is implemented as an integrated circuit or a chip, that is, at this time, each unit output current and electrostatic release protection level adjustable module includes multiple PMOS tubes and multiple NMOS tubes.

[0263] In step S420, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core are obtained through the multiple customized input boxes.

[0264] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core; the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic release protection level input by the user are the input threshold voltage, output current capability and electrostatic release protection capability that the designated pin module of the customized IO IP core is expected to be able to achieve.

[0265] In a specific implementation, five input boxes are provided through the graphical user interface of the customized EDA tool, namely: "Expected input threshold high level voltage VIH" input box, "Expected input threshold low level voltage VIL" input box, "Expected high level output source current IOH" input box, "Expected low level output sink current IOL" input box, and "Expected electrostatic release protection level" input box. The user inputs the expected input threshold voltage, output current capability and electrostatic release protection capability corresponding to the expected electrostatic release protection level for the specified pin module of the customized IO IP core from the five input boxes, and the electrostatic release protection capability is divided into levels based on the unit electrostatic release protection capability. For example, assuming that the unit electrostatic release protection capability is 1 kV, the electrostatic release protection capability corresponding to the first-level electrostatic release protection level is 1 kV, the electrostatic release protection capability corresponding to the second-level electrostatic release protection level is 2 kV, the electrostatic release protection capability corresponding to the third-level electrostatic release protection level is 3 kV, and so on.

[0266] In the present disclosure, the voltage values ​​of the input threshold high level voltage and the input threshold low level voltage are relative. For example, when the input threshold high level voltage is 0.8*VDD, the input threshold low level voltage may be 0.35*VDD, 0.3*VDD, etc.; when the input threshold high level voltage is 4V, the input threshold low level voltage may be 0.8V, 1.2V, etc. Wherein, the input threshold high level voltage is less than the power supply voltage, and the input threshold low level voltage is greater than 0.

[0267] In step S430, the input threshold adjustable module is configured according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module.

[0268] In the present disclosure, the IO first control signal is a voltage level that provides a reference to the IO core circuit module, so that the IO core circuit module can compare and judge the voltage level of the IO input signal received from the outside with the IO first control signal, thereby obtaining a logical judgment result of the voltage level of the IO input signal.

[0269] According to an embodiment of the present disclosure, the configuration of the input threshold adjustable module also includes: determining a corresponding hysteresis voltage according to the input threshold high level voltage and the input threshold low level voltage; selecting a MOS module from the first MOS module group according to the input threshold high level voltage, the input threshold low level voltage and the hysteresis voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0270] Figure 5 A working principle diagram of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown.

[0271] like Figure 5 As shown, when the hysteresis voltage Vhys is provided by the hysteresis circuit module, the IO first control signal (VCH and VCL) is obtained by using the hysteresis voltage Vhys and the input threshold high voltage level VIH and the input threshold low voltage level VIL, VCH=VIH-Vhys, VCL=VIL+Vhys.

[0272] In the present disclosure, after the input threshold high level voltage VIH and the input threshold low level voltage VIL are determined, the corresponding hysteresis voltage Vhys can be determined according to the values ​​of VIH and VIL. For example, the hysteresis voltage Vhys can be determined according to the difference between VIH and VIL and a preset ratio. Specifically, for example, when VIH = 0.8*VDD, VIL = 0.3*VDD, Vhys = (0.8*VDD-0.3*VDD) / 2 = 0.25*VDD. It should be understood by those skilled in the art that the above-mentioned method for solving the hysteresis voltage is only a specific example and is not a technical means for limiting the protection scope of the present disclosure. The hysteresis voltage can also be calculated using other solution methods, for example, Vhys = (0.8*VDD-0.3*VDD) / 3 = 0.2*VDD.

[0273] In a specific embodiment, assuming that VIH=0.8*VDD, VIL=0.3*VDD, Vhys=0.2*VDD, the IO first control signal can be determined: VCH=0.8*VDD-0.2*VDD=0.6*VDD, VCL=0.3*VDD+0.2*VDD=0.5*VDD, then when the voltage value of the IO input signal obtained from the IO core circuit module increases from 0 to VCH=0.6*VDD, the voltage level of the IO input signal is judged as a logic low level, in the interval where the voltage value of the IO input signal rises from VCH=0.6*VDD to VDD, and in the interval where the voltage value of the IO input signal drops from VDD to VCL=0.5*VDD, the voltage level of the IO input signal is judged as a logic high level, and in the interval where the voltage value of the IO input signal drops from VCL=0.5*VDD to 0, the voltage level of the IO input signal is judged as a logic low level.

[0274] When the customized IO IP core is implemented as an integrated circuit or chip, an analog voltage is generally obtained from an external device or sensor as an IO input signal. In order to prevent the voltage signal of the obtained analog voltage from jumping back and forth between the input threshold high level voltage VIH and the input threshold low level voltage VIL, it is necessary to use the hysteresis voltage Vhys to correct VIH and VIL to obtain the IO first control signal for judgment, so that the voltage signal of the analog voltage is judged as a high level in the part that does not reach but is close to the input threshold high level voltage VIH, and is judged as a low level in the part that is higher than but close to the input threshold low level voltage VIL, thereby improving the stability and reliability of the integrated circuit or chip during operation.

[0275] Assume that the second MOS module group includes m PMOS modules and n NMOS modules; when configuring the input threshold adjustable module, p PMOS modules and q NMOS modules are selected from the second MOS module group for connection according to the input threshold high level voltage and the input threshold low level voltage, thereby generating a configured input threshold adjustable module to achieve the desired input threshold voltage and the corresponding hysteresis voltage, wherein p≤m, q≤n.

[0276] The inventors have found that in order to save the layout area of ​​the designed custom IO IP core when it is implemented as a circuit layout, and at the same time enable the input threshold voltage to achieve the desired input accuracy, the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to an integer multiple of 0.01*VDD, 0.02*VDD, ..., 0.2*VDD, or the voltage values ​​of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set to an integer multiple of 0.01V, 0.02V, ..., 0.2V, thereby making the layout area of ​​the designed custom IO IP core as small as possible while the input threshold voltage can be set as many as possible. Those skilled in the art should understand that the value settings of the input threshold high level voltage VIH and the input threshold low level voltage VIL can be set according to the layout area of ​​the custom IO IP core required by the user and the desired accuracy of the input threshold voltage, and are not limited thereto.

[0277] For example, when the customized EDA tool configures the input threshold adjustable module to obtain the configured input threshold adjustable module, when the configured input threshold adjustable module is implemented as an integrated circuit or a chip, under a 0.18 μm design process (the minimum distance or feature size between circuits in chip manufacturing reaches 0.18 microns), when VIH=0.8*VDD, VIL=0.2*VDD, the customized EDA tool determines, based on the values ​​of VIH and VIL, that 18 PMOS tubes and 12 NMOS tubes need to be selected from the second MOS tube group for connection, wherein 16 PMOS tubes and 10 NMOS tubes are used to achieve the desired VIH and VIL, and 2 PMOS tubes and 2 NMOS tubes are used to achieve the corresponding hysteresis voltage.

[0278] In a specific embodiment, the input threshold adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the second MOS module group, and according to the input threshold high level voltage VIH and the input threshold low level voltage VIL, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the second MOS module group, thereby selecting a MOS module from the second MOS module group and connecting the selected MOS module to achieve the desired input threshold voltage and hysteresis voltage.

[0279] In order to save the user's operation time, the embodiment of the present disclosure can pre-set multiple configurations of the input threshold adjustable module, and each configured input threshold adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different input threshold high level voltages VIH and input threshold low level voltages VIL. When the user inputs the desired input threshold high level voltage VIH and input threshold low level voltage VIL, the corresponding configured input threshold adjustable module can be directly selected.

[0280] In another specific embodiment, a plurality of MOS module groups are pre-set in the second MOS module group of the input threshold adjustable module, and each MOS module group corresponds to a different input threshold high level voltage VIH and input threshold low level voltage VIL; thus, when the user inputs the required input threshold high level voltage VIH and input threshold low level voltage VIL, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0281] In step S440, the output current and electrostatic release protection level adjustable module is configured according to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, including: according to the electrostatic release protection level, one or more unit output current and electrostatic release protection level adjustable modules are selected from the output current and electrostatic release protection level adjustable modules and the selected one or more unit output current and electrostatic release protection level adjustable modules are connected to generate a configured output current and electrostatic release protection level adjustable module, the configured output current and electrostatic release protection level adjustable module includes a third MOS module group; according to the high-level output pull current and the low-level output sink current, a MOS module is selected from the third MOS module group and the selected MOS module is connected to generate a configured output current and electrostatic release protection level adjustable module, the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of the IO second control signal of the IO core circuit module.

[0282] In step S450, the IO core circuit module, the configured input threshold adjustable module and the configured output current and electrostatic discharge protection level adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0283] Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port and an IO first control signal output port; the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port;

[0284] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded;

[0285] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0286] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic release protection level adjustable module based on the IO first control signal and the IO input signal;

[0287] The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

[0288] Specifically, the output current and electrostatic discharge protection level adjustable module configured once may include one or more unit output current and electrostatic discharge protection level adjustable modules, that is, the number of the selected unit output current and electrostatic discharge protection level adjustable modules may be one or more, wherein each selected output current and electrostatic discharge protection level adjustable module uses all the MOS modules it includes to provide unit electrostatic discharge protection capability. For example, the unit electrostatic discharge protection capability that can be provided by the selected unit output current and electrostatic discharge protection level adjustable module is 0.5kV. If the electrostatic discharge protection capability corresponding to the electrostatic discharge protection capability level input by the user is expected to be 4kV, it is necessary to select 4kV / 0.5kV=8 unit output current and electrostatic discharge protection level adjustable modules from the output current and electrostatic discharge protection level adjustable modules, and connect the selected 8 unit output current and electrostatic discharge protection level adjustable modules, so as to obtain the output current and electrostatic discharge protection level adjustable module configured once to provide 4kV electrostatic discharge protection capability.

[0289] After obtaining the output current and electrostatic release protection level adjustable module of the primary configuration, a MOS module is selected from the third MOS module group included in the output current and electrostatic release protection level adjustable module of the primary configuration and connected to the selected MOS module to generate a configured output current and electrostatic release protection level adjustable module, and the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to the MOS module selected from the third MOS module group, thereby providing a specified output current capability under the control of the IO second control signal of the IO core circuit module.

[0290] Among them, the selected unit output current and electrostatic release protection level adjustable module includes a power supply voltage port, a ground port and an IO second control signal input port, the power supply voltage port of the unit output current and electrostatic release protection level adjustable module is connected to the power supply voltage, the ground port of the unit output current and electrostatic release protection level adjustable module is grounded, the selected unit output current and electrostatic release protection level adjustable module is used to provide unit electrostatic release protection capability, and if all MOS modules in the selected unit output current and electrostatic release protection level adjustable module are controlled by the IO second control signal of the IO core circuit module, then the unit output current capability is provided.

[0291] In a specific embodiment, all MOS modules in any unit output current and electrostatic discharge protection level adjustable module are connected to the IO second control signal input port of any unit output current and electrostatic discharge protection level adjustable module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time, such as Figure 5 At this time, all MOS modules in any one of the modules with adjustable unit output current and electrostatic discharge protection level provide not only unit electrostatic discharge protection capability but also unit output current capability.

[0292] In specific embodiment 1, some MOS modules in any unit output current and electrostatic release protection level adjustable module are connected to the IO second control signal input port of any unit output current and electrostatic release protection level adjustable module, and the connected part of the MOS modules provide the corresponding electrostatic release protection capability and output current capability at the same time, and the remaining MOS modules provide the corresponding electrostatic release protection capability. At this time, some of the MOS modules in any unit output current and electrostatic release protection level adjustable module have the corresponding electrostatic release protection capability and output current capability at the same time, while the remaining MOS modules only have the corresponding electrostatic release protection capability, and the electrostatic release protection capability corresponding to the part of the MOS modules and the electrostatic release protection capability corresponding to the remaining MOS modules together constitute the unit electrostatic release protection capability.

[0293] In the specific embodiment 2, all MOS modules in any unit output current and electrostatic discharge protection level adjustable module are disconnected from the IO second control signal input port of any unit output current and electrostatic discharge protection level adjustable module, and all disconnected MOS modules provide unit electrostatic discharge protection capability, such as Figure 7 At this time, any unit output current and ESD protection level adjustable module can only provide unit ESD protection capability, but cannot provide any output current capability.

[0294] The unit output current and electrostatic release protection level adjustable module includes an output PMOS unit and an output NMOS unit, the output PMOS unit includes a plurality of PMOS modules, and the output NMOS unit includes a plurality of NMOS modules.

[0295] In the specific implementation mode 3, assuming that IOH=3mA, IOL=5.1mA, ESD=12kV, the unit output current capability provided by the unit output current and electrostatic discharge protection level adjustable module is 0.5mA, and the unit electrostatic discharge protection capability provided is 1kV. Then, IOH is 3mA / 0.5mA=6, and 6 complete output PMOS units are required to provide high-level output pull current, and IOL is 5.1mA / 0.5mA=10.2, and 10 complete output NMOS units and one output NMOS unit accounting for 20% are required to provide low-level output sink current, wherein the output NMOS unit accounting for 20% is: 20% of the number of NMOS modules are used in the multiple NMOS modules included in the output NMOS unit, and ESD=12kV / 1kV=12, and 12 complete output NMOS units and 12 complete output NMOS units are required.

[0296] Therefore, in order to realize the above-mentioned assumed conditions, it is necessary to connect 12 unit output current and electrostatic discharge protection level adjustable modules to the IO core circuit module to provide 12kV electrostatic discharge protection capability, and select 6 complete output PMOS units from the 12 unit output current and electrostatic discharge protection level adjustable modules to connect to the IO second control signal input port to provide high-level output pull current, select 10 complete output NMOS units and one output NMOS unit accounting for 20% to connect to the IO second control signal input port to provide low-level output sink current, and the output NMOS unit accounting for 20% is: 20% of the NMOS modules are used in the multiple NMOS modules included in the output NMOS unit.

[0297] In the present disclosure, in the unit output current and electrostatic release protection level adjustable module, the IO second control signal of the IO core circuit module is received through the IO second control signal input port to control the PMOS module and the NMOS module connected to the IO second control signal input port in the output PMOS unit and the output NMOS unit respectively, so as to achieve the output current capability expected by the user.

[0298] When the customized IO IP core is implemented as a circuit layout, the layout area of ​​the implemented circuit layout capable of providing electrostatic discharge protection capability needs to be implemented as the layout area of ​​the customized IO IP core.

[0299] After generating the designated pin module of the customized IO IP core, the input threshold voltage, output current capability, and anti-static protection capability of other pins of the customized IO IP core can be configured according to the actual configuration requirements, and the corresponding pin module of the customized IO IP core is generated through the above steps S410 to 450, and then all the pin modules are spliced ​​to finally generate the customized IO IP core.

[0300] The present disclosure divides the output current and electrostatic release protection level adjustable module into multiple unit output current and electrostatic release protection level adjustable modules, which not only improves the setting accuracy of the output current capability and the electrostatic release protection capability, but also further increases the flexibility of the output current capability and the electrostatic release protection capability configuration. Moreover, when the required high-level output pull current IOH or low-level output sink current IOL, and the electrostatic release protection capability ESD are large values, multiple unit output current and electrostatic release protection level adjustable modules can be conveniently and directly selected for splicing, which simplifies the design process of the customized IOIP core and improves the user experience.

[0301] Furthermore, in the above-mentioned specific embodiment 2, that is, when some MOS modules in the any unit output current and electrostatic release protection level adjustable module are connected to the IO second control signal input port of the any unit output current and electrostatic release protection level adjustable module, in the remaining MOS modules of the any unit output current and electrostatic release protection level adjustable module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0302] Specifically, in the remaining MOS modules of any unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the MOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the ground port. For example, when the configured output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining MOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS (Gate VDD PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining MOS modules and ground them through the ground port VSS to form a GGNMOS (Gate Ground NMOS) structure.

[0303] Alternatively, in the remaining MOS modules of any one of the unit output current and electrostatic release protection level adjustable modules: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the ground port.

[0304] Specifically, in the remaining MOS modules of any unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the MOS modules are short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the resistor module and the grounding port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining MOS modules and connect the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS (Resistor-Gate PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining MOS modules and ground them through the resistor module and the grounding port VSS to form an RGNMOS (Resistor-Gate NMOS) structure.

[0305] In the above-mentioned specific embodiment 2, that is, when all the MOS modules in the selected unit output current and electrostatic release protection level adjustable module are disconnected from the IO second control signal input port of the selected unit output current and electrostatic release protection level adjustable module, among all the MOS modules in the selected unit output current and electrostatic release protection level adjustable module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0306] Specifically, in all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: in all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: short-circuit the gate and source of a part of the MOS modules and connect them to the power supply voltage through the power supply voltage port, short-circuit the gate and source of another part of the MOS modules and connect them to the ground through the ground port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, all the MOS modules correspond to a plurality of PMOS tubes and a plurality of NMOS tubes, then it is necessary to short-circuit the gate and source of the plurality of PMOS tubes corresponding to the entire MOS modules and connect them to the power supply voltage through the power supply voltage port VDD to form a GDPMOS structure, and short-circuit the gate and source of the plurality of NMOS tubes corresponding to the entire MOS modules and connect them to the ground through the ground port VSS to form a GGNMOS structure.

[0307] Alternatively, among all MOS modules of the selected unit output current and electrostatic release protection level adjustable module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the ground port.

[0308] Specifically, in all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: the gate and source of a part of the MOS modules are short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the resistor module and the grounding port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the whole MOS modules correspond to a plurality of PMOS tubes and a plurality of NMOS tubes, then the gate and source of the plurality of PMOS tubes corresponding to the whole MOS modules need to be short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS structure, and the gate and source of the plurality of NMOS tubes corresponding to the whole MOS modules need to be short-circuited and connected to the power supply voltage through the resistor module and the grounding port VSS to form a GGNMOS structure.

[0309] Figure 6 A schematic diagram showing the connection of an IO core circuit module, a configured input voltage adjustable module, and a configured output current and electrostatic discharge protection level adjustable module in a method for generating a customized IO IP core based on a configurable IO IP core according to an embodiment of the present disclosure is shown. Figure 6In the example shown, the configured output current and electrostatic discharge protection level adjustable module includes 2 different unit output current and electrostatic discharge protection level adjustable modules. Those skilled in the art should understand that the number of the unit output current and electrostatic discharge protection level adjustable modules and the type of the unit output current and electrostatic discharge protection level adjustable modules are set according to user needs, and the number and type of the unit output current and electrostatic discharge protection level adjustable modules are not used as technical means to limit the scope of protection of the present disclosure.

[0310] like Figure 6 As shown, the customized IO IP core includes: an IO core circuit module, a configured input threshold adjustable module, and a configured unit output current and electrostatic release protection level adjustable module. The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, the IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of each unit output current and electrostatic release protection level adjustable module in the configured output current and electrostatic release protection level adjustable module, and the IO second control signal input port of the configured unit output current and electrostatic release protection level adjustable module is disconnected from all MOS modules of the configured unit output current and electrostatic release protection level adjustable module.

[0311] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the selected unit electrostatic release protection module includes: a power supply voltage port, a ground port and an IO second control signal input port.

[0312] The power supply voltage ports of the IO core circuit module and the selected unit output current and electrostatic release protection level adjustable module are both connected to the power supply voltage, and the ground ports are both grounded. The IO first control signal input port of the IO core circuit module receives an external IO input signal, obtains an IO second control signal after processing and outputs it through the IO second control signal output port, and the selected unit output current and electrostatic release protection level adjustable module obtains the IO second control signal through the IO second control signal input port to control the MOS module connected to the IO second control signal input port of the selected output current and electrostatic release protection level adjustable module to simultaneously provide corresponding electrostatic release protection capability and output current capability. Figure 6In the example shown, two modules with adjustable unit output current and electrostatic discharge protection level are included, one of which has a control input port disconnected from all the MOS modules it includes and can only provide unit electrostatic discharge protection capability, and the other has a control input port connected to all the MOS modules it includes, thereby being able to provide both unit electrostatic discharge protection capability and unit output current capability.

[0313] For example, when a pin module of a customized IO IP core needs to have a 5kV electrostatic discharge protection capability, when the configured output current and electrostatic discharge protection level adjustable module is implemented as an integrated circuit or a chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit output current and electrostatic discharge protection level adjustable module in the configured output current and electrostatic discharge protection level adjustable module is 0.5kV, then under the 0.18μm design process, 5kV / 0.5kV=10 unit electrostatic discharge protection modules need to be connected to the IO core circuit.

[0314] For another example, a pin module of a customized IO IP core needs to have both 4kV electrostatic discharge protection capability and 4mA output current capability. When the configured output current and electrostatic discharge protection level adjustable module is implemented as an integrated circuit or chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit output current and electrostatic discharge protection level adjustable module in the configured output current and electrostatic discharge protection level adjustable module is 0.5kV, then under a 0.18μm design process, when all MOS tubes in a unit output current and electrostatic discharge protection level adjustable module are used, the unit output current capability that can be provided is 1mA, then 4kV / 0.5kV=8 unit output current and electrostatic discharge protection level adjustable modules need to be connected to the IO core circuit, of which 4 unit output current and electrostatic discharge protection level adjustable modules need to provide both unit electrostatic discharge protection capability and unit output current capability, and the remaining 4 unit output current and electrostatic discharge protection level adjustable modules only need to provide unit electrostatic discharge protection capability.

[0315] The present invention can automatically select the unit output current and electrostatic release level adjustable protection module that needs to be connected and automatically select the MOS module that needs to be connected in the selected unit output current and electrostatic release level adjustable protection module according to the requirements of different input threshold voltages, output current capabilities and electrostatic release protection capabilities required by the actual chip, so as to form a chip design with input threshold voltage, output current capability and electrostatic release protection capability that meets the requirements, thereby realizing flexible configuration of input threshold voltage, output current capability and electrostatic release protection capability.

[0316] When the customized IP core is an IO IP core with power-on control, a layout of the IO IP core with power-on control is generated according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; and generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control.

[0317] The third configuration parameter includes one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level.

[0318] Figure 7 FIG. 1 is a flow chart showing a method for generating an IOIP core with power-on control based on a configurable POC IP core according to an embodiment of the present disclosure. Figure 7 As shown, generating the IO IP core with power-on control according to the IO IP core, the configurable POC IP core and the third configuration parameter input by the user specifically includes the following steps S710 to S760:

[0319] In step S710, a configurable POC IP core is obtained, where the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module.

[0320] After research, the inventors of the present disclosure found that the reason why the existing POC IP core can only provide a fixed input threshold voltage (including a power-on threshold voltage and a power-down threshold voltage) is that the POC IP core is designed as an integral module, which makes it impossible to easily configure the various functional modules inside it (such as: POC input threshold voltage module) independently, resulting in the IO IP core only being able to provide a fixed input threshold voltage, thereby failing to meet the actual requirements of different chips for different input threshold voltages.

[0321] The present disclosure splits the existing overall POC IP core into multiple functional modules, and separately configures the input threshold voltage module therein, thereby realizing a configurable POC IP core. In the configurable POC IP core, each function inside it can be easily and independently controlled, and then it can be automatically adjusted according to the actual needs of different chips, thereby realizing flexible configuration of the POC input threshold voltage.

[0322] In the present disclosure, the configurable POC IP core is no longer an integral module, but includes a POC core circuit module and a POC input threshold voltage adjustable module, wherein the POC input threshold voltage adjustable module can be configured according to the POC input threshold voltage input by the user, so that the customized POC IP core generated based on the configured POC input threshold voltage adjustable module meets the actual demand of supporting the specified POC input threshold voltage.

[0323] Wherein, the configurable POC IP core is provided by a customized EDA tool.

[0324] In step S720, the IO IP core is obtained.

[0325] Different from the IO IP core in the existing standard IO IP core library, the IO IP core involved in step S720 includes: a POC control signal input port, so as to receive the POC control signal through the port.

[0326] In addition to this difference, the IO IP cores involved in the present disclosure involve two types: one is an IO IP core with a fixed input threshold voltage and anti-static protection capability and a limited number of output current capabilities, and the other is an IO IP core with a flexibly configurable input threshold voltage and anti-static protection capability and output current capability.

[0327] For the first type of IO IP core, when the customized EDA tool is acquired, it is necessary to add a POC control signal input port and a corresponding circuit module for processing the received POC control signal on the basis of the existing IO IP core.

[0328] For the second type of IO IP core, which is a customized IO IP core, the customized EDA tool needs to design it based on a configurable IO IP core with adjustable input threshold voltage, adjustable output current capability, and adjustable anti-static protection capability when obtaining the customized IO IP core. The specific method can be found according to Figure 4 The custom IO IP core is designed based on a configurable IO IP core with adjustable input threshold voltage, output current capability, and electrostatic discharge protection level.

[0329] In step S730, the POC input threshold voltage input by the user is obtained through the plurality of customized input boxes.

[0330] In the present disclosure, after the POC IP is combined with the IO IP, since the IO IP mainly uses the POC control signal to reflect whether the dual power supplies are fully powered on, in a specific embodiment, the user can configure the POC input threshold voltage adjustable module only by inputting the first power-on threshold voltage and the second power-on threshold voltage.

[0331] In step S740, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, and the POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, and the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0332] In step S750, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core, and the customized POC IP core is used to generate a POC control signal.

[0333] In step S760, the customized POC IP core and the IO IP core are connected to generate an IO IP core with power-on control.

[0334] Figure 8 A schematic structural diagram of an IO IP core with power-on control according to an embodiment of the present disclosure is shown, wherein the IO IP core is a customized IO IP core.

[0335] Among them, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IOIP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0336] The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to the first power supply and the second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded.

[0337] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0338] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

[0339] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0340] When any one of the first power supply and the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0341] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0342] In a specific embodiment, if the IO IP core is a customized IO IP core, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0343] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0344] Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current adjustable module;

[0345] The configured output current adjustable module controls the output of the IO IP core current according to the current control signal.

[0346] When the IO IP core specifically implements the output of the POC control signal output by the customized POC IP core to control the output of its own current, a corresponding circuit module for processing the received POC control signal can be added on the basis of the existing IO IP core, for example: a signal parsing unit is added inside the IO core circuit module, and the signal parsing unit can be a hardware logic circuit, which can identify and parse the POC control signal, and generate a current control signal according to the POC control signal parsing unit, and the current control signal can be an analog signal (such as a voltage signal) or a digital signal (such as a PWM signal) for controlling the output current adjustable module. After generating the current control signal, the IO core circuit module will send this signal to the configured output current adjustable module through the internal signal transmission unit, and the signal transmission unit can be a hardware interface (such as SPI, I2C, etc.) or a software communication protocol (such as UART, CAN, etc.), depending on the design and requirements of the system. After receiving the current control signal, the configured output current adjustable module adjusts its internal current regulation circuit according to the current control signal. The current regulating circuit may include some switching tubes, resistors, inductors and other components, and the output current can be adjusted by changing the states or parameters of these components.

[0347] Specifically, when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state, that is, current can hardly pass through. In order to achieve the high-impedance state, a special circuit design can be used inside the IO IP core, such as an open-drain structure or a similar configuration. When entering the high-impedance state, the connection between the pin of the IO IP core and the internal circuit is disconnected, forming a high-impedance channel, making it almost impossible for current to pass through.

[0348] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level. At this time, the IO IP core controls its own normal output current.

[0349] The IO IP core with power-on control provided in the embodiment of the present disclosure controls the current output of the IOIP through a flexible and configurable POC IP, so that the generated customized IO IP core with power-on control can meet the design requirements of complex industrial chips.

[0350] When the customized IP core is a customized unit with power-on control, a layout of the customized unit with power-on control is generated according to the configuration parameters input by the user, including: generating the customized unit with power-on control according to the POC IP core and the standard unit module; generating the layout of the customized unit with power-on control based on the customized unit with power-on control; when the POCIP core is a customized POC IP core, generating the customized unit with power-on control according to the POC IP core and the standard unit module includes: generating the customized unit with power-on control according to the customized POC IP core and the standard unit module and the first configuration parameters.

[0351] Fig. 9 A flow chart of a method for generating a customized unit with power-on control according to an embodiment of the present disclosure is shown. Fig. 9 As shown, generating the customized unit with power-on control according to the POC IP core and the standard unit module specifically includes the following steps S910 to S930:

[0352] In step S910, a POC IP core is obtained; the POC IP core includes: a first power input terminal, a second power input terminal and a control signal output terminal.

[0353] In step S920, a standard cell module is obtained; the standard cell module includes: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal and a cell signal output terminal.

[0354] Specifically, the custom EDA tool provides a POC IP core and a standard cell module for the user to design the custom cell with power-on control.

[0355] The standard cell module may be a library cell in a standard cell library provided by a custom EDA tool, or a library cell designed as required and stored in a cell library; the POC IP core may be a POC IP core provided by the custom EDA tool.

[0356] In step S930 , the POC IP core and the standard cell module are connected to generate a custom cell with power-on control.

[0357] Wherein, the first logic control signal input end of the standard cell module is connected to a first power circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power circuit module; the second logic control signal input end of the standard cell module is connected to a second power circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power circuit module; the power input end of the standard cell module is connected to a power supply;

[0358] The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply;

[0359] The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal;

[0360] The obtaining of the voltage status of the first power supply and the second power supply includes:

[0361] Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0362] Comparing the current voltage value of the second power supply with a preset second power-on threshold voltage, when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state;

[0363] The generating a first control signal according to the voltage states of the first power supply and the second power supply comprises:

[0364] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0365] When step S930 is specifically executed, it can be performed in the following three ways:

[0366] The first method: using the first control signal to control the connection and disconnection of the power supply of the standard cell module. When the first control signal is at a high level, that is, when the dual power supplies are fully powered on, the power supply of the standard cell module is controlled to be connected; when the first control signal is at a low level, that is, when the dual power supplies are not fully powered on, the power supply of the standard cell module is controlled to be disconnected.

[0367] The first method cuts off the power supply of the subsequent standard unit module when the dual power supply is not fully powered on, thereby avoiding erroneous logic output and preventing the standard unit module from continuing to generate power consumption, thereby reducing the power consumption output of the overall circuit.

[0368] The second method: using the first control signal to control the connection or disconnection of the output of the standard cell module. When the first control signal is at a high level, that is, when the dual power supplies are fully powered on, the connection of the output of the standard cell module is controlled; when the first control signal is at a low level, that is, when the dual power supplies are not fully powered on, the disconnection of the output of the standard cell module is controlled.

[0369] The third method: directly input the first control signal to the standard cell module, and the standard cell module controls whether it has output according to the first control signal. When the first control signal is at a high level, that is, when the dual power supplies are fully powered on, the standard cell module controls its output to be turned on; when the first control signal is at a low level, that is, when the dual power supplies are not fully powered on, the standard cell module controls its output to be turned off.

[0370] The first and second methods mentioned above do not require any modification to the standard cell module. In this way, it is easier to customize the standard cells in the standard cell library with power-on control functions, which simplifies the design process and makes it easier to upgrade and maintain the standard cell module.

[0371] The specific implementation plans of the above three methods are described in detail below.

[0372] For the first method:

[0373] According to an embodiment of the present disclosure, the method further includes: acquiring a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal.

[0374] The power input end of the standard cell module is connected to the power supply, and the control signal output end of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input end of the standard cell module through the first switch control circuit module, and the control signal output end of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input end of the first switch control circuit module, the POC The control signal output end of the IP core is connected to the second input end of the first switch control circuit module, and the output end of the first switch control circuit module is connected to the power input end of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal, and uses the second control signal to control the connection or disconnection of the power supply, so that when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally; wherein, generating the second control signal according to the first control signal, and using the second control signal to control the connection or disconnection of the power supply, includes:

[0375] When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end of the first switch control circuit module; when the first control signal is at a low level, the second control signal is a disconnecting signal, and the disconnecting signal disconnects the output end of the first switch control circuit module; when the output end of the first switch control circuit module is closed, the power supply is turned on; when the output end of the first switch control circuit module is disconnected, the power supply is cut off.

[0376] For example: Assuming that the first power supply is a 5V power supply, the second power supply and the power supply of the standard cell module are 1.8V power supplies, and the preset first power-on threshold voltage is 4.5V, when the current voltage value of the first power supply is 4.3V, the POC IP core detects that the current voltage value is lower than the preset first power-on threshold voltage, and determines that the voltage state of the first power supply is a non-power-on state, then the first control signal output to the first switch control circuit module is a low level. The second control signal generated by the first switch control circuit module according to the first control signal is a disconnection signal, and the disconnection signal controls the output end of the first switch control circuit module to disconnect, so that the power supply is cut off, the standard cell module stops processing the first logic control signal and the second logic control signal, and the standard cell module has no output.

[0377] When the current voltage value of the first power supply is 4.9V, the POC IP core detects that the current voltage value is higher than the preset first power-on threshold voltage, and determines that the voltage state of the first power supply is the power-on state, and the first control signal output to the first switch control circuit module is a high level. The second control signal generated by the first switch control circuit module according to the first control signal is a closed signal, and the closed signal controls the output end of the first switch control circuit module to close, so that the power supply is turned on, the standard cell module resumes the processing of the first logic control signal and the second logic control signal, and the standard cell module outputs normally.

[0378] For the second method:

[0379] According to an embodiment of the present disclosure, the method further includes: acquiring a second switch control circuit module; wherein the second switch control circuit module includes: a signal input terminal and a signal output terminal.

[0380] According to an embodiment of the present disclosure, the control signal output terminal of the POC IP core is connected to the standard cell module, including:

[0381] The control signal output end of the POC IP core is connected to the signal input end of the second switch control circuit module; the signal output end of the second switch control circuit module is connected to the cell signal output end of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally; wherein, the generating of the third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module include:

[0382] When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the unit signal output end of the standard unit module; when the first control signal is at a low level, the third control signal is a disconnecting signal, and the disconnecting signal cuts off the unit signal output end of the standard unit module; when the unit signal output end of the standard unit module is connected, the output of the standard unit module is connected; when the unit signal output end of the standard unit module is cut off, the output of the standard unit module is cut off.

[0383] For the third method:

[0384] According to an embodiment of the present disclosure, the standard cell module further includes: a control signal input terminal;

[0385] The connecting the control signal output end of the POC IP core to the standard cell module includes: connecting the control signal output end of the POC IP core to the control signal input end of the standard cell module, so that the standard cell module controls whether it has output according to the first control signal.

[0386] According to an embodiment of the present disclosure, the standard cell module controls whether it has output according to the first control signal, including: when the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally; when the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

[0387] The POC IP cores involved in the embodiments of the present disclosure include but are not limited to two types. One is a default POC IP core provided by a customized EDA tool. The default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values, that is, the user can only select an existing POC IP core with a fixed first power-on threshold voltage value and a fixed second power-on threshold voltage value provided by the customized EDA tool, and cannot flexibly set the power-on threshold voltage of the selected POC IP core according to actual application needs.

[0388] According to an embodiment of the present disclosure, the default POC IP core includes: a POC IP core circuit module and a default threshold voltage module connected to each other, wherein the default threshold voltage module includes a number of MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

[0389] That is, in the default POC IP core, the number of MOS modules in the default threshold voltage module corresponds to the preset first power-on threshold voltage and the preset second power-on threshold voltage, and cannot be flexibly adjusted.

[0390] In order to achieve flexible and adjustable power-on threshold voltage, the generated customized unit with power-on control can meet the design requirements of complex industrial chips such as different power-on threshold voltages. Figure 2 The customized POC IP core shown is designed based on the configurable POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is the first power-on threshold voltage input by the user, and the preset second power-on threshold voltage is the second power-on threshold voltage input by the user.

[0391] Directly using the default POC IP core and customized POC IP core provided by the custom EDA tool can greatly simplify the complexity of system design and reduce the cost of design and maintenance. In addition, the default POC IP core and customized POC IP core provided by the custom EDA tool are usually designed based on widely accepted and verified standards, which means that they have higher reliability and predictability; in contrast, the power-on control circuit designed by yourself may have unknown problems or design defects, and more testing and verification are required to ensure its reliability. Therefore, directly using the default POC IP core and customized POC IP core provided by the custom EDA tool has higher reliability, lower complexity and better compatibility.

[0392] Fig.10 FIG. 1 shows a structural connection diagram of a customized unit with power-on control according to an embodiment of the present disclosure. Fig.10 As shown, the customized unit includes: a POC IP core, a first switch control circuit module and a standard unit module.

[0393] Among them, the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard unit module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, and a unit signal output terminal 240; the first switch control circuit module includes: a first input terminal 310, a second input terminal 320, and an output terminal 330.

[0394] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0395] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0396] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0397] Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0398] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0399] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0400] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0401] The control signal output terminal 130 of the POC IP core is connected to the standard cell module, and the POC IP core is also configured to output the first control signal to the standard cell module through the control signal output terminal 130 to control whether the standard cell module outputs normally through the first control signal.

[0402] Specifically, the power input terminal 230 of the standard cell module is connected to the power supply through the first switch control circuit module, and the control signal output terminal 130 of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input terminal 310 of the first switch control circuit module, the control signal output terminal 130 of the POC IP core is connected to the second input terminal 320 of the first switch control circuit module, and the output terminal 330 of the first switch control circuit module is connected to the power input terminal 230 of the standard cell module; the first switch control circuit module is configured to generate a second control signal according to the first control signal, and use the second control signal to control the connection or disconnection of the power supply; when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally.

[0403] According to an embodiment of the present disclosure, generating a second control signal according to the first control signal, and using the second control signal to control the connection or disconnection of the power supply includes:

[0404] When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end 330 of the first switch control circuit module; when the first control signal is at a low level, the second control signal is a disconnecting signal, and the disconnecting signal disconnects the output end 330 of the first switch control circuit module; when the output end 330 of the first switch control circuit module is closed, the power supply is turned on; when the output end 330 of the first switch control circuit module is disconnected, the power supply is cut off.

[0405] Fig.11 FIG. 2 shows a structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure. Fig.11 As shown, the customized unit includes: a POC IP core, a second switch control circuit module and a standard unit module.

[0406] Among them, the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard unit module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, and a unit signal output terminal 240; the second switch control circuit module includes: a signal input terminal 410 and a signal output terminal 420.

[0407] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0408] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0409] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0410] Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0411] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0412] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0413] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0414] The control signal output terminal 130 of the POC IP core is connected to the standard cell module, and the POC IP core is also configured to output the first control signal to the standard cell module through the control signal output terminal 130 to control whether the standard cell module outputs normally through the first control signal.

[0415] Specifically, the control signal output terminal 130 of the POC IP core is connected to the signal input terminal 410 of the second switch control circuit module; the signal output terminal 420 of the second switch control circuit module is connected to the unit signal output terminal 240 of the standard unit module; the second switch control circuit module is configured to generate a third control signal according to the first control signal, and use the third control signal to control the connection or disconnection of the output of the standard unit module; when the output of the standard unit module is disconnected, the standard unit module has no output; when the output of the standard unit module is connected, the standard unit module outputs normally.

[0416] According to an embodiment of the present disclosure, generating a third control signal according to the first control signal, and using the third control signal to control the on or off of the output of the standard cell module includes:

[0417] When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the unit signal output terminal 240 of the standard unit module; when the first control signal is at a low level, the third control signal is a disconnection signal, and the disconnection signal disconnects the unit signal output terminal 240 of the standard unit module; when the unit signal output terminal 240 of the standard unit module is connected, the output of the standard unit module is connected; when the unit signal output terminal 240 of the standard unit module is disconnected, the output of the standard unit module is disconnected.

[0418] Fig.12 FIG. 2 shows a structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure. Fig.12 As shown, the customized unit includes: a POC IP core, a standard cell module, a threshold voltage adjustable power supply monitoring circuit module and a third switch control circuit module.

[0419] In the embodiment of the present disclosure, the POC IP core is a default POC IP core.

[0420] Among them, the POC IP core includes: the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard unit module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, a unit signal output terminal 240, and a control signal input terminal 250; the threshold voltage adjustable power supply monitoring circuit module includes: a first power input terminal 510, a second power input terminal 520 and a control signal output terminal 530; the third switch control circuit module includes: a control signal input terminal 610, a power enable signal output terminal 620.

[0421] Specifically, the first power input terminal 510 of the threshold voltage adjustable power supply monitoring circuit module is connected to the first power supply; the second power input terminal 520 of the threshold voltage adjustable power supply monitoring circuit module is connected to the second power supply; the control signal output terminal 530 of the threshold voltage adjustable power supply monitoring circuit module is connected to the control signal input terminal 610 of the third switch control circuit module; the power enable signal output terminal 620 of the third switch control circuit module is respectively connected to the first power input terminal 110 and the second power input terminal 120 of the POC IP core;

[0422] Wherein, the threshold voltage adjustable power supply monitoring circuit module includes a first threshold voltage adjustable power supply monitoring circuit module, a second threshold voltage adjustable power supply monitoring circuit module and a fourth control signal generating module; the first threshold voltage adjustable power supply monitoring circuit module is connected to the first power supply, the second threshold voltage adjustable power supply monitoring circuit module is connected to the second power supply, the first threshold voltage adjustable power supply monitoring circuit module and the second threshold voltage adjustable power supply monitoring circuit module are respectively connected to the fourth control signal generating module, and the fourth control signal generating module is connected to the control signal input terminal 610 of the third switch control circuit module;

[0423] The first threshold voltage adjustable power supply monitoring circuit module is configured to receive a first external control signal and determine a dynamically adjustable first power-on threshold voltage according to the first external control signal;

[0424] The second threshold voltage adjustable power supply monitoring circuit module is configured to receive a second external control signal and determine a dynamically adjustable second power-on threshold voltage according to the second external control signal;

[0425] The first threshold voltage adjustable power supply monitoring circuit module is further configured to compare the current voltage value of the first power supply with the dynamically adjustable first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the dynamically adjustable first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0426] The second threshold voltage adjustable power supply monitoring circuit module is further configured to compare the current voltage value of the second power supply with the dynamically adjustable second power-on threshold voltage, and when the current voltage value of the second power supply is not lower than the dynamically adjustable second power-on threshold voltage, the voltage state of the second power supply is a power-on state;

[0427] The fourth control signal generating module is configured to generate a fourth control signal according to the voltage state of the first power supply and the voltage state of the second power supply, including: when the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the fourth control signal is a high level, otherwise, the fourth control signal is a low level;

[0428] The fourth control signal generating module is further configured to output the fourth control signal to the control signal input terminal 610 of the third switch control circuit module;

[0429] The third switch control circuit module is configured to control the connection or disconnection of the first power supply and the second power supply for supplying power to the POC IP core according to the fourth control signal, including: when the fourth control signal is at a high level, the first power supply and the second power supply for supplying power to the POC IP core are disconnected; when the fourth control signal is at a low level, the first power supply and the second power supply for supplying power to the POC IP core are connected;

[0430] When the first power supply and the second power supply for supplying power to the POC IP core are cut off, the first control signal is at a low level; when the first power supply and the second power supply for supplying power to the POC IP core are connected, the first control signal is at a high level.

[0431] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0432] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0433] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0434] Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0435] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0436] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0437] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0438] The control signal output terminal 130 of the POC IP core is connected to the control signal input terminal 250 of the standard cell module; the standard cell module is also configured to control whether it has output according to the first control signal.

[0439] According to an embodiment of the present disclosure, controlling whether or not to output according to the first control signal includes:

[0440] When the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally; when the first control signal is at a low level, the output of the standard cell module is turned off, and the standard cell module has no output.

[0441] By combining the POC IP core with the standard cell module, and utilizing the different control signals output by the POC IP core when the power supply is not fully powered on and when the power supply is fully powered on in the dual power supply circuit, it is possible to monitor in real time whether both power supplies in the dual power supply circuit are in place, and to control the subsequent standard cell modules so that they do not output when the dual power supplies are not fully powered on. When both power supplies are fully powered on, the subsequent standard cell modules can resume normal output, thereby avoiding logic output errors. This solves the problem of output logic errors caused by a sudden power failure of one of the power supplies in the dual power supply circuit, and ensures the stability and reliability of the circuit system under abnormal power supply voltage conditions.

[0442] Fig.13 A flowchart of a method for digitizing an integrated cell library according to an embodiment of the present disclosure is shown. The digitization method is implemented based on a customized EDA tool. The customized EDA tool integrates an integrated cell library generated by the above method described in the embodiment of the present disclosure. The integrated cell library includes standard cells and customized IP cells corresponding to customized IP cores. The customized IP cores include one or more of the following items: customized POC IP cores, customized IO IP cores, IOIP cores with power-on control, and customized cells with power-on control. Fig.13 As shown, the digital method includes the following steps S1310 to S1360:

[0443] In step S1310, the RTL code for calling the basic standard unit and / or the custom IP unit is obtained, wherein the RTL (Register-Transfer Level Code) code includes an instance of a hardware description language module describing the basic standard unit and / or an instance of a hardware description language module describing the custom IP unit.

[0444] In step S1320, a synthesizer is used to convert the RTL code into a gate-level netlist.

[0445] In step S1330, the synthesized gate-level netlist is imported into a placement and routing tool.

[0446] In step S1340, physical layout and routing are performed based on the gate-level netlist to generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP unit and the basic standard unit, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0447] In addition to the above steps S1310 to S1340, the digitization method further includes the following steps S1350 to S1360:

[0448] In step S1350, the layout and routing data is verified, and the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS, and electrical rule check ERC.

[0449] In step S1360, manufacturing data is generated according to the layout and routing data, and the manufacturing data includes but is not limited to: a GDSII file and a manufacturing mask.

[0450] Fig.14 A schematic diagram of a structure of a device for generating an integrated cell library according to an embodiment of the present disclosure is shown, wherein the device is implemented based on a customized EDA tool, wherein the customized EDA tool provides a GUI interface, wherein the GUI interface includes a plurality of customized input boxes, wherein the customized input boxes are used to obtain configuration parameters input by a user. Fig.14As shown, the device 1400 includes: a customized IP layout generation module, configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control; an integrated unit library generation module, configured to generate an integrated unit library based on the layout of the customized IP core; wherein, generating the layout of the customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; generating the layout of the customized POC IP core based on the customized POC IP core; the first configuration parameters include: POC input threshold voltage; generating the layout of the customized IO IP core according to the configuration parameters input by the user includes: generating the customized IO IP core according to the configurable IO IP core and the second configuration parameters input by the user; generating the customized IO based on the customized IO IP core the layout of the IP core; the second configuration parameter includes one or more of the following items: input threshold high level voltage, input threshold low level voltage, high level output pull current, low level output sink current and electrostatic discharge protection level; generating a layout of the IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating the layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameter includes one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output pull current, low level output sink current and electrostatic discharge protection level; generating a layout of the custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POC IP core and the standard unit module; generating the layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, the configuration parameters according to the POC The IP core and the standard cell module generate the customized cell with power-on control, including: generating the customized cell with power-on control according to the customized POC IP core, the standard cell module and the first configuration parameters.

[0451] Fig.15A schematic diagram of the structure of a digitization device of an integrated cell library according to an embodiment of the present disclosure is shown. The digitization device is implemented based on a customized EDA tool, and the customized EDA tool integrates an integrated cell library generated using the method described in any one of the embodiments of the present disclosure, and the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, and the customized IP cores include one or more of the following items: customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control.

[0452] like Fig.15 As shown, the device 1500 includes: an RTL code acquisition module, configured to acquire RTL code that calls the basic standard unit and / or the customized IP unit corresponding to the customized IP core, wherein the RTL code contains an instance of a hardware description language module that describes the basic standard unit and / or an instance of a hardware description language module that describes the customized IP unit; a gate-level netlist generation module, configured to use a synthesizer to convert the RTL code into a gate-level netlist; a gate-level netlist import module, configured to import the synthesized gate-level netlist into a layout and routing tool; a layout and routing data generation module, configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the customized IP unit and the basic standard unit, and generating connections between the customized IP units and / or between the basic standard units and / or between the customized IP units and the basic standard units.

[0453] According to an embodiment of the present disclosure, the digitization device also includes: a layout and routing data verification module, configured to verify the layout and routing data, and the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS and electrical rule check ERC.

[0454] According to an embodiment of the present disclosure, the digitizing device further includes: a manufacturing data generating module configured to generate manufacturing data according to the layout and wiring data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

[0455] According to the technical solution provided by the embodiment of the present disclosure, the customized POC IP core, customized IO IP core, IO IP core with power-on control and customized unit with power-on control generated according to the configuration parameters input by the user are integrated into an integrated unit library different from the traditional standard unit library, wherein the customized POC IP core and the customized IO IP core support the input configuration parameters to be flexibly configured, and the IO IP core with power-on control and the customized unit with power-on control combine the POC IP core with the existing IO IP core and standard unit. This solves the problems existing in the comprehensiveness and integration of the traditional standard unit library, and also solves the problems existing in the current traditional POC IP core, IO IP core and standard unit, thereby better meeting the needs of modern chip design.

[0456] The present disclosure provides a chip, comprising: manufacturing according to library cells in an integrated cell library generated by the method as described above, the library cells including basic standard cells and customized IP cells corresponding to customized IP cores, the customized IP cores including one or more of the following items: customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control.

[0457] The present disclosure provides an electronic device, comprising: the chip as described above.

[0458] The present disclosure provides a computer-readable storage medium having computer instructions stored thereon. When the computer instructions are executed by a processor, the method described in any of the preceding items is implemented.

[0459] The present disclosure provides a computer program product, comprising computer instructions, which implement any of the above methods when executed by a processor.

[0460] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for generating an integrated cell library, characterized in that: The method is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, the customized input boxes are used to obtain configuration parameters input by a user, and the method includes: Generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control; Generate an integrated cell library based on the layout of the customized IP core; Wherein, generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameters include: POC input threshold voltage; Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and a second configuration parameter input by the user; generating a layout of the customized IO IP core based on the customized IO IP core; the second configuration parameter comprising one or more of the following items: an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level; Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameters include one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level; Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POCIP core and the standard cell module, including: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

2. The method according to claim 1, characterized in that The generating an integrated cell library based on the layout of the customized IP core comprises: Verifying the layout of the customized IP core, the verification including: design rule check DRC and layout and schematic comparison LVS; Generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core; Verifying the post-simulation netlist data to ensure that it is consistent with the layout of the customized IP core; Input the post-simulation netlist data into a pre-provided Tcl script file, and add attribute parameters related to the customized IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption; Generate a model file according to the Tcl script file, and verify the model file to ensure that the model file can correctly simulate the behavior of the customized IP core, the model file includes: a Verilog model file or a VHDL model file; Perform post-simulation verification using the model file; An integrated unit library is generated based on the model file using a library file generation tool.

3. The method according to claim 2, characterized in that The method further includes: verifying the integrated cell library.

4. The method according to claim 2, characterized in that: The post-simulation netlist data of the layout of the customized IP core is generated, including: Extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool; the parasitic parameters include: resistance, capacitance and inductance; Obtaining pre-simulation netlist data of the layout of the customized IP core; The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core containing the parasitic parameters.

5. The method according to claim 2, characterized in that: The method of using a library file generation tool to generate an integrated unit library based on the model file includes: Select the model file; Configuring properties of the integrated unit library, the properties of the integrated unit library including: library name, version and description; Execute the command or operation used to generate the library file in the library file generation tool.

6. The method according to claim 1, characterized in that The step of generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user comprises: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Acquire the POC input threshold voltage input by the user through the multiple customized input boxes; The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal; Wherein, the POC core circuit module includes: a POC first control signal input port, a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the grounding ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide a reference voltage to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

7. The method according to claim 6, characterized in that The POC input threshold voltage adjustable module further includes: a resistance module group; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage also includes: selecting resistance modules with a quantity and resistance value corresponding to the POC input threshold voltage from the resistance module group and connecting the selected MOS module and resistance module to generate the configured POC input threshold voltage adjustable module.

8. The method according to claim 7, characterized in that The method also includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection or a series-parallel mixed mode.

9. The method according to claim 1, characterized in that: The step of generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user includes: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic release protection level adjustable module, wherein the input threshold adjustable module includes a second MOS module group, and the output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes a plurality of MOS modules; Obtaining, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level input by a user for a specified pin module of a custom IO IP core; Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; According to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, the output current and electrostatic release protection level adjustable module is configured, including: according to the electrostatic release protection level, one or more unit output current and electrostatic release protection level adjustable modules are selected from the output current and electrostatic release protection level adjustable modules and the selected one or more unit output current and electrostatic release protection level adjustable modules are connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module includes a third MOS module group; according to the high-level output pull current and the low-level output sink current, a MOS module is selected from the third MOS module group and the selected MOS module is connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module; Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core; Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port and an IO first control signal output port; the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port; The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic release protection level adjustable module based on the IO first control signal and the IO input signal; The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability; Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

10. The method according to claim 9, characterized in that The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the second MOS module group, including: in any unit output current and electrostatic release protection level adjustable module of the configured output current and electrostatic release protection level adjustable module: All MOS modules in any one unit electrostatic release protection module are connected to the IO second control signal input port of any one unit electrostatic release protection module, and all connected MOS modules provide unit electrostatic release protection capability and unit output current capability at the same time; Alternatively, some MOS modules in any one of the unit electrostatic release protection modules are connected to the IO second control signal input port of any one of the unit electrostatic release protection modules, and some of the connected MOS modules provide corresponding electrostatic release protection capability and output current capability at the same time, and the remaining MOS modules provide corresponding electrostatic release protection capability; Alternatively, all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

11. The method according to claim 10, characterized in that When some MOS modules in any unit electrostatic release protection module are connected to the IO second control signal input port of any unit electrostatic release protection module, in the remaining MOS modules of any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port; When all the MOS modules in any one of the unit electrostatic release protection modules are disconnected from the IO second control signal input port of any one of the unit electrostatic release protection modules, among all the MOS modules in any one of the unit electrostatic release protection modules: the gates of some of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

12. The method according to claim 11, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port, including: The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the ground port.

13. The method according to claim 10, characterized in that When some MOS modules in any unit electrostatic release protection module are connected to the IO second control signal input port of any unit electrostatic release protection module, in the remaining MOS modules of any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the grounding port; When all the MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, among all the MOS modules in any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the grounding port.

14. The method according to claim 13, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistor module and the ground port, including: The gate and source of one part of the MOS modules are short-circuited and connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the resistor module and the grounding port.

15. The method according to claim 1, characterized in that The step of generating the IO IP core with power-on control according to the IO IP core, the configurable POC IP core and the third configuration parameter input by the user comprises: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Get IO IP core; Acquire the POC input threshold voltage input by the user through the multiple customized input boxes; The POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, the POC input threshold voltage adjustable module includes a first MOS module group, and the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage, including: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, wherein the configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal; Connect the customized POC IP core and the IO IP core to generate an IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all connected to the first power supply and the second power supply, and the grounding ports of the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module are all grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, and is used to provide the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group; The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

16. The method according to claim 15, characterized in that The IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including: When any one of the first power supply and the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state; When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

17. The method according to claim 15, characterized in that The IO IP core is a customized IO IP core, and obtaining the IO IP core includes: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic release protection level adjustable module, wherein the input threshold adjustable module includes a second MOS module group, and the output current and electrostatic release protection level adjustable module includes a plurality of unit output current and electrostatic release protection level adjustable modules, and the unit output current and electrostatic release protection level adjustable module includes a plurality of MOS modules; Obtaining, through the multiple custom input boxes, an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level input by a user for a specified pin module of a custom IO IP core; Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; According to the high-level output pull current, the low-level output sink current and the electrostatic release protection level, the output current and electrostatic release protection level adjustable module is configured, including: according to the electrostatic release protection level, one or more unit output current and electrostatic release protection level adjustable modules are selected from the output current and electrostatic release protection level adjustable modules and the selected one or more unit output current and electrostatic release protection level adjustable modules are connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module includes a third MOS module group; according to the high-level output pull current and the low-level output sink current, a MOS module is selected from the third MOS module group and the selected MOS module is connected to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module; Connecting the IO core circuit module, the configured input threshold adjustable module and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core; Wherein, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port and an IO first control signal output port; the configured output current and electrostatic release protection level adjustable module includes: a power supply voltage port, a ground port and an IO second control signal input port; The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the grounding ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic release protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic release protection level adjustable module based on the IO first control signal and the IO input signal; The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

18. The method according to claim 17, characterized in that The IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including: The IO core circuit module obtains the POC control signal through the POCIO second control signal input port; Generate a current control signal according to the POC control signal, and send the current control signal to the configured output current and electrostatic discharge protection level adjustable module; The configured output current and electrostatic discharge protection level adjustable module controls the output of the IO IP core current according to the current control signal.

19. The method according to claim 1, characterized in that The step of generating the customized unit with power-on control according to the POC IP core and the standard unit module includes: Obtain a POC IP core; the POC IP core comprises: a first power input terminal, a second power input terminal and a control signal output terminal; Acquire a standard cell module; the standard cell module comprises: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal and a cell signal output terminal; The POC IP core and the standard cell module are connected to generate a custom cell with power-on control; wherein the first logic control signal input terminal of the standard cell module is connected to a first power circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power circuit module; the second logic control signal input terminal of the standard cell module is connected to a second power circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power circuit module; the power input terminal of the standard cell module is connected to a power supply; The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply; The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal; The obtaining of the voltage status of the first power supply and the second power supply includes: Comparing the current voltage value of the first power supply with a preset first power-on threshold voltage, when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state; Comparing the current voltage value of the second power supply with a preset second power-on threshold voltage, when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state; The generating a first control signal according to the voltage states of the first power supply and the second power supply comprises: When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

20. The method according to claim 19, characterized in that The method further comprises: Acquire a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal; The power input end of the standard cell module is connected to the power supply, and the control signal output end of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input end of the standard cell module through the first switch control circuit module, and the control signal output end of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input end of the first switch control circuit module, the control signal output end of the POC IP core is connected to the second input end of the first switch control circuit module, and the output end of the first switch control circuit module is connected to the power input end of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal, and uses the second control signal to control the connection or disconnection of the power supply, so that when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally; The step of generating a second control signal according to the first control signal and using the second control signal to control the power supply to be turned on or off includes: When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end of the first switch control circuit module; When the first control signal is at a low level, the second control signal is a disconnection signal, and the disconnection signal disconnects the output end of the first switch control circuit module; When the output end of the first switch control circuit module is closed, the power supply is turned on; When the output end of the first switch control circuit module is disconnected, the power supply is cut off.

21. The method according to claim 19, characterized in that The method further comprises: Acquire a second switch control circuit module; wherein the second switch control circuit module comprises: a signal input terminal and a signal output terminal; The control signal output terminal of the POC IP core is connected to the standard cell module, including: The control signal output end of the POC IP core is connected to the signal input end of the second switch control circuit module; the signal output end of the second switch control circuit module is connected to the cell signal output end of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally; The step of generating a third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module includes: When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the cell signal output terminal of the standard cell module; When the first control signal is at a low level, the third control signal is a disconnection signal, and the disconnection signal cuts off the cell signal output end of the standard cell module; When the cell signal output terminal of the standard cell module is turned on, the output of the standard cell module is turned on; When the cell signal output terminal of the standard cell module is cut off, the output of the standard cell module is cut off.

22. The method according to claim 19, characterized in that The standard cell module further includes: a control signal input terminal; The control signal output end of the POC IP core is connected to the standard cell module, including: the control signal output end of the POC IP core is connected to the control signal input end of the standard cell module, so that the standard cell module controls whether it has output according to the first control signal; The standard unit module controls whether it has output according to the first control signal, including: When the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally; When the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

23. The method according to claim 19, characterized in that The POC IP core is a customized POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is a first power-on threshold voltage input by a user, and the preset second power-on threshold voltage is a second power-on threshold voltage input by a user; or, The POC IP core is a default POC IP core; the default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values; The default POC IP core includes: a connected POC IP core circuit module and a default threshold voltage module, wherein the default threshold voltage module includes MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

24. A method for digitizing an integrated cell library, characterized in that: The method is implemented based on a customized EDA tool, wherein the customized EDA tool integrates an integrated cell library generated by the method according to any one of claims 1 to 23, wherein the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control, wherein the method includes: Acquire an RTL code for calling the basic standard cell and / or the custom IP cell corresponding to the custom IP core, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the custom IP cell; Converting the RTL code into a gate-level netlist using a synthesizer; Importing the synthesized gate-level netlist into a placement and routing tool; Performing physical layout and routing based on the gate-level netlist to generate layout and routing data; performing physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

25. The method according to claim 24, characterized in that The method further comprises: The layout and routing data is verified, and the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS, and electrical rule check ERC.

26. The method according to claim 24, characterized in that The method further comprises: Manufacturing data is generated according to the layout and wiring data, and the manufacturing data includes: a GDSII file and a manufacturing mask.

27. A device for generating an integrated cell library, characterized in that: The device is implemented based on a customized EDA tool, the customized EDA tool provides a GUI interface, the GUI interface includes a plurality of customized input boxes, the customized input boxes are used to obtain configuration parameters input by a user, and the device includes: A customized IP layout generation module is configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the layout of the customized IP includes one or more of the following items: a layout of a customized POC IP core, a layout of a customized IO IP core, and a layout of an IO IP core with power-on control; An integrated cell library generation module, configured to generate an integrated cell library based on the layout of the customized IP core; Wherein, generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameters include: POC input threshold voltage; Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and a second configuration parameter input by the user; generating a layout of the customized IO IP core based on the customized IO IP core; the second configuration parameter comprising one or more of the following items: an input threshold high level voltage, an input threshold low level voltage, a high level output source current, a low level output sink current, and an electrostatic discharge protection level; Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameters include one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level; Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POCIP core and the standard cell module, including: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

28. A digital device for an integrated cell library, characterized in that: The digitization device is implemented based on a customized EDA tool, the customized EDA tool integrates an integrated cell library generated by the method according to any one of claims 1 to 23, the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, the customized IP cores include one or more of the following items: customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control, the digitization device includes: An RTL code acquisition module is configured to acquire an RTL code for calling the basic standard unit and / or the customized IP unit, wherein the RTL code includes an instance of a hardware description language module describing the basic standard unit and / or an instance of a hardware description language module describing the customized IP unit; A gate-level netlist generation module, configured to convert the RTL code into a gate-level netlist using a synthesizer; A gate-level netlist import module, configured to import the synthesized gate-level netlist into a placement and routing tool; A layout and routing data generation module is configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

29. The digitizing device according to claim 28, characterized in that The digitizing device also includes: The layout and routing data verification module is configured to verify the layout and routing data, wherein the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS, and electrical rule check ERC.

30. The digitizing device according to claim 28, characterized in that The digitizing device also includes: The manufacturing data generating module is configured to generate manufacturing data according to the layout and wiring data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

31. A chip, characterized in that: The chip is manufactured using library cells in an integrated cell library generated by the method described in any one of claims 1 to 23, the library cells include basic standard cells and customized IP cells corresponding to customized IP cores, and the customized IP cores include one or more of the following items: customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control.

32. An electronic device, characterized in that: Comprising a chip according to claim 31.

33. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 23 is implemented.

34. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 23 is implemented.

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