Display device
By designing the active area circuit and the test control circuit in the liquid crystal display device, abnormal diagnosis of the vertical direction data line is realized, problems that cannot be diagnosed in the prior art are solved, and driving safety is ensured.
Patent Information
- Application Number
- CN202411923786.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-28
- Filing Date
- 2024-12-25
- Publication Date
- 2025-02-18
AI Technical Summary
The existing LCD display device cannot diagnose abnormalities of data lines in the vertical direction, resulting in the inability to ensure driving safety.
A display device is designed, including an active area circuit and a test control circuit. The active area circuit includes a plurality of display units coupled to a plurality of gate lines and data lines. The test control circuit includes a detection transistor and an array test switch transistor, which can selectively transmit a data signal to the detection transistor, forming a diagnostic signal to detect an abnormal state of the data line.
The abnormal diagnosis function of vertical direction data lines is realized, which can ensure the normal operation of the display device and driving safety.
Smart Images
Figure CN119479514A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a display device, and more particularly to a display device with a data line diagnosis function. Background Art
[0002] With the development of flat panel display technology, various display devices have been widely used in various aspects of daily life. For example, liquid crystal display devices (LCD) have been widely used in driving (including assisted driving, etc.).
[0003] Since driving applications have high safety requirements, safety regulations related to liquid crystal display devices have been developed accordingly. It is necessary to diagnose the panel of the liquid crystal display device to confirm whether it is abnormal or not, so as to ensure driving safety. The existing liquid crystal display device provides an abnormality diagnosis function for the horizontal gate line; when the abnormal state of the gate line is diagnosed, the liquid crystal display device can be immediately turned off.
[0004] However, the existing liquid crystal display device cannot perform abnormal diagnosis on the data lines in the vertical direction. Therefore, an improved circuit structure of the display device is needed to diagnose the abnormal state of the data lines in the vertical direction. Summary of the invention
[0005] An object of the present invention is to provide a display device to solve at least one of the above problems.
[0006] According to one embodiment of the present disclosure, a display device is provided, including an active area circuit and a test control circuit. The active area circuit includes a plurality of display units, and the display units are correspondingly coupled to a plurality of gate lines and a plurality of data lines, the gate lines extend in a first direction, and the data lines extend in a second direction, and the second direction is substantially orthogonal to the first direction. The test control circuit includes a plurality of detection transistors and a plurality of array test switch transistors. The detection transistors are commonly coupled to the detection signal line to receive the detection signal, and are commonly coupled to the diagnostic signal line to provide the diagnostic signal. The array test switch transistors are correspondingly coupled to the data line to receive a plurality of data signals, and the data signals are selectively transmitted to the detection transistor. The detection transistor is turned on or off according to the data signal. When the detection transistor is turned on, the detection signal is transmitted to the diagnostic signal line to form a diagnostic signal.
[0007] Other aspects and advantages of the present disclosure will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 FIG. 4 is a circuit diagram of a display device according to an embodiment of the present disclosure.
[0009] Figure 2AThe waveform diagram is a voltage change diagram of related signals of some data lines of the display device in the display mode.
[0010] Figure 2B The figure is a waveform diagram showing voltage changes of related signals of some data lines of the display device in the diagnosis mode.
[0011] Figure 2C The waveform diagram is a voltage variation diagram of related signals of some data lines of the display device in the array test mode.
[0012] Figure 3 FIG. 4 is a circuit diagram of a display device according to another embodiment of the present disclosure.
[0013] Figure 4A for Figure 3 A waveform diagram showing voltage changes of related signals of some data lines of a display device in a display mode.
[0014] Figure 4B for Figure 3 A waveform diagram showing voltage changes of related signals of some data lines of a display device in a diagnosis mode.
[0015] Figure 4C for Figure 3 A waveform diagram showing voltage changes of related signals of some data lines of a display device in an array test mode.
[0016] The reference numerals are as follows:
[0017] 1000: Display device
[0018] 1002: Display device
[0019] 100: Test control circuit
[0020] 200: Active area circuit
[0021] 310,320,320b: External control circuit
[0022] T(ac)1,T(ac)2,T(dd)0,T(dd)1,T(dd)2: transistor
[0023] T(as)1,T(as)2: Transistor
[0024] 11: Array test control line
[0025] 12: Display control line
[0026] 13: Diagnostic signal line
[0027] 14: Detection signal line
[0028] 15: Array test switch line
[0029] pd1, pd2: array test pads
[0030] AT_PAD: array test signal
[0031] AT_CTRL: array test control signal
[0032] DP_CTRL: display control signal
[0033] ASIL_V: Diagnostic Signals
[0034] DET: Detection signal
[0035] AT_SW: array test switch signal
[0036] P(0,1),P(0,2),P(0,M): Display unit
[0037] P(1,1),P(1,2),P(1,M): Display unit
[0038] T01, T02, T11, T12: Transistors
[0039] C01, C02, C11, C12: Capacitors
[0040] DATA: data signal
[0041] G[0]~G[N]: gate lines
[0042] DL[1]~DL[M]: data line
[0043] S[1],S[2],S[5],S[M-1],S[M],SR',SR”: output ports
[0044] ASIL1~ASIL3: Input port
[0045] SR,SR1,SR2: shift register unit
[0046] T1~T9: Time interval DETAILED DESCRIPTION
[0047] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, technicians in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0048] Figure 1FIG. 1 is a circuit diagram of a display device 1000 according to an embodiment of the present disclosure. Figure 1 As shown, the display device 1000 includes a test control circuit 100 and an active area circuit 200. In addition, the display device 1000 is electrically coupled to an external control circuit 310 and an external control circuit 320. The external control circuit 310 and the external control circuit 320 are, for example, integrated circuit chips outside the display device 1000 (the external control circuits 310 and 320 can be integrated into the same integrated circuit chip, or can be two separate integrated circuit chips).
[0049] The active area circuit 200 includes a plurality of display units. These display units are arranged into an array having (N+1) horizontal columns and (M+1) vertical rows. Among the (N+1) horizontal columns, the first horizontal column includes display unit P(0,1), display unit P(0,2), ..., display unit P(0,M), the second horizontal column includes display unit P(1,1), display unit P(1,2), ..., display unit P(1,M), and so on. The display units P(0,1) to P(0,M) arranged in the first horizontal column are commonly coupled to the gate line G[0], which is also called the "dummy gate line". The display units P(1,1) to P(1,M) arranged in the second horizontal column are commonly coupled to the gate line G[1]. Similarly, the display units P(1,1) to P(1,M) arranged in the third horizontal column are commonly coupled to the gate line G[1]. Figure 1 Not shown) are coupled to the gate line G[2]. Furthermore, the display units ( Figure 1 The gate lines G[0] to G[N] are connected to the last two gate lines G[N-1] and the gate line G[N] respectively. Therefore, the gate lines G[0] to G[N] extend in the horizontal direction (ie, the direction of the horizontal row). The horizontal direction may be referred to as the "first direction".
[0050] The display unit P(0,1) arranged in the first vertical row, etc. ( Figure 1 The other display units in the 1st vertical row not shown) are coupled together to the data line DL[1], and the display unit P(1,1) arranged in the 2nd vertical row is also coupled to the data line DL[1]. On the other hand, the display unit P(0,2) arranged in the 2nd vertical row is coupled to another data line DL[2]. Similarly, the display unit P(0,M) arranged in the Mth vertical row is coupled to the data line DL[M], and the display unit P(1,M) arranged in the (M+1)th vertical row is also coupled to the data line DL[M]. Accordingly, the data lines DL[1]~DL[M] extend in the vertical direction (i.e., the direction of the vertical row). The vertical direction can be referred to as the "second direction". The second direction is substantially orthogonal to the first direction.
[0051] The above-mentioned display units P(0,1) to P(1,M) (and those not shown in Figure 1 Each of the other display units) includes a transistor and a capacitor. For example, display unit P(0,1) includes transistor T01 and capacitor C01, display unit P(0,2) includes transistor T02 and capacitor C02, display unit P(1,1) includes transistor T11 and capacitor C11, display unit P(1,2) includes transistor T12 and capacitor C12, and so on. The control end (e.g., gate) of transistor T01 is coupled to gate line G[0], and the first end (e.g., drain) of transistor T01 is coupled to data line DL[1]. The control end of transistor T02 is coupled to gate line G[0], and the first end of transistor T02 is coupled to data line DL[2]. Similarly, in the display unit P(1,1) and the display unit P(1,2) arranged in the second horizontal row, the control end of the transistor T11 and the first end are correspondingly coupled to the gate line G[1] and the data line DL[1], and the control end of the transistor T12 and the first end are correspondingly coupled to the gate line G[1] and the data line DL[2]. According to the above configuration, the gate lines G[0] to G[N] are used to control the conduction or disconnection of the corresponding transistors in the display units P(0,1) to P(1,M). When the corresponding transistor is turned on, the data signal DATA transmitted by the corresponding data line DL[1] to DL[M] is transmitted to the corresponding capacitor via the turned-on transistor. For example, when the gate line G[0] controls the transistor T01 of the display unit P(0,1) to be turned on, the data signal DATA transmitted by the data line DL[1] is transmitted to the capacitor C01 via the turned-on transistor T01. The display unit P(0,1) presents a corresponding brightness according to the data voltage of the data signal DATA.
[0052] The active area circuit 200 is coupled to the test control circuit 100 via data lines DL[1]-DL[M]. The test control circuit 100 includes M array test control transistors, (M+1) detection transistors, and M array test switch transistors. The array test control transistors include, for example, transistor T(ac)1, transistor T(ac)2, etc. ( Figure 1 Other array test control transistors are not shown). The detection transistors include, for example, transistor T(dd)0, transistor T(dd)1, transistor T(dd)2, and so on. Figure 1 Other detection transistors are not shown). The array test switch transistors include, for example, transistor T(as)1, transistor T(as)2, and so on ( Figure 1 Other array test switch transistors not shown).
[0053] Among the array test control transistors, the control terminals (e.g., gates) of transistors T(ac)1 and T(ac)2 are commonly coupled to an array test control line 11, and the array test control line 11 receives an array test control signal AT_CTRL. The first terminals (e.g., drains) of transistors T(ac)1 and T(ac)2 are respectively coupled to array test pads pd1 and pd2, for correspondingly receiving array test signals AT_PAD. In addition, the second terminal (e.g., source) of transistor T(ac)1 is correspondingly coupled to transistors T(dd)1 and T(as)1 in a vertical direction. The second terminal (e.g., source) of transistor T(ac)2 is correspondingly coupled to transistors T(dd)2 and T(as)2 in a vertical direction.
[0054] Among the detection transistors, transistor T(dd)0 can be called a "first detection transistor". The control end of transistor T(dd)0 is coupled to the display control line 12 for receiving the display control signal DP_CTRL. On the other hand, the control ends of transistor T(dd)1 and transistor T(dd)2 are respectively coupled to the second ends of transistor T(ac)1 and transistor T(ac)2. The first ends of transistor T(dd)0, transistor T(dd)1 and transistor T(dd)2 are respectively coupled to the diagnostic signal line 13 for providing the diagnostic signal ASIL_V. The second ends of transistor T(dd)0, transistor T(dd)1 and transistor T(dd)2 are respectively coupled to the detection signal line 14 for receiving the detection signal DET.
[0055] Among the array test switch transistors, the control terminals of transistors T(as)1 and T(as)2 are respectively coupled to the array test switch line 15 for receiving the array test switch signal AT_SW. The first terminal of transistor T(as)1 is coupled to the control terminal of transistor T(dd)1 and the second terminal of transistor T(ac)1. The first terminal of transistor T(as)2 is coupled to the control terminal of transistor T(dd)2 and the second terminal of transistor T(ac)2. The second terminals of transistors T(as)1 and T(as)2 are respectively coupled to data lines DL[1] and DL[2].
[0056] The active area circuit 200 is coupled to the external control circuit 310 via the gate lines G[0]-G[N]. The external control circuit 310 includes a plurality of shift register units SR, which are coupled to the gate lines G[0]-G[N] accordingly. These shift register units SR generate timing shifted detection signals to diagnose whether the gate lines G[0]-G[N] are in an abnormal state. The timing shifted detection signals are sequentially transmitted to the gate lines G[0]-G[N] at corresponding time intervals.
[0057] On the other hand, the active area circuit 200 is coupled to the external control circuit 320 via the data lines DL[1] to DL[M]. The external control circuit 320 includes a plurality of output ports, for example, an output port S[1], an output port S[2], and an output port SR'. The output ports S[1] and S[2] may be referred to as "data output ports", which are used to generate a data signal DATA to be transmitted to the data lines DL[1] and DL[2] accordingly. The data signal DATA is transmitted to the corresponding display unit via the data lines DL[1] and DL[2]. Similarly, the external control circuit also includes a device not shown in FIG. Figure 1 The other output ports are correspondingly coupled to other data lines to transmit the data signal DATA. In addition, the output port SR' can be called a "control output port" for generating a control signal to control the shift register unit SR of the external control circuit 310 so that the shift register unit SR generates a timing shift detection signal.
[0058] The external control circuit 320 also includes a plurality of input ports, for example, input port ASIL1, input port ASIL2 and input port ASIL3. Among them, input port ASIL3 can be referred to as the "first diagnostic input port", which is correspondingly coupled to the diagnostic signal line 13 to receive the diagnostic signal ASIL_V, and the abnormal state of the data lines DL[1] to DL[M] is determined according to the diagnostic signal ASIL_V. On the other hand, input port ASIL1 and input port ASIL2 can be referred to as the "second diagnostic input port", which are correspondingly coupled to the diagnostic signal line 21 and the diagnostic signal line 22. The diagnostic signal lines 21 and 22 are correspondingly coupled to the last two gate lines G[N] and G[N-1], and the diagnostic signals transmitted by the gate lines G[N] and G[N-1] are received to determine the abnormal state of the gate lines.
[0059] The display device 1000 may have at least three operation modes, including: a display mode, a diagnostic mode, and an array test mode. Table 1 shows the voltage values of various signals and the input / output types of the display device 1000 in the display mode, the diagnostic mode, and the array test mode.
[0060] Table 1
[0061]
[0062] First, see also Figure 1 Table 1 and Table 1 illustrate the operation of the display device 1000 in the display mode. In the display mode, the output port S[1] and the output port S[2] (and other ports not shown in FIG. 1 ) of the external control circuit 320 are connected to the external control circuit 320. Figure 1 The display units P(0,1)-P(1,M) (and other output ports not shown in FIG. 1 ) of the active area circuit 200 generate a data signal DATA, whose voltage is the “data voltage”. Figure 1Other display units) present corresponding brightness according to the data voltage of the data signal DATA.
[0063] In the display mode, the voltage of the array test switch signal AT_SW is a negative voltage of -9V. The array test switch signal AT_SW is transmitted to the control terminals of the transistors T(as)1 and T(as)2 via the array test switch line 15. The transistors T(as)1 and T(as)2 are NMOS transistors, and the array test switch signal AT_SW is a negative voltage, so the transistors T(as)1 and T(as)2 are disconnected. The data signal DATA transmitted via the data lines DL[1] and DL[2] is transmitted upward to the transistors T(dd)1, T(dd)2, T(ac)1 and T(ac)2 without passing through the disconnected transistors T(as)1 and T(as)2.
[0064] The array test control signal AT_CTRL is transmitted to the control terminals of the transistors T(ac)1 and T(ac)2 via the array test control line 11. The array test signal AT_PAD is a floating voltage, and the voltage of the array test control signal AT_CTRL is a negative voltage -9V, so the transistors T(ac)1 and T(ac)2 are disconnected; the array test signal AT_PAD is not transmitted downward to the transistors T(dd)1, T(dd)2, T(as)1, T(as)2 and the data lines DL[1], DL[2] via the disconnected transistors T(ac)1 and T(ac)2.
[0065] The display control signal DP_CTRL is transmitted to the control end of the transistor T(dd)0 via the display control line 12. The voltage of the display control signal DP_CTRL is a positive voltage of 10V, so the transistor T(dd)0 is turned on. The voltage of the detection signal DET transmitted by the detection signal line 14 is -5V. The detection signal DET is transmitted to the diagnostic signal line 13 via the turned-on transistor T(dd)0 to become the diagnostic signal ASIL_V. That is, the voltage of the diagnostic signal ASIL_V is equal to the voltage of the detection signal DET, and both are -5V. Accordingly, in the display mode, the diagnostic signal line 13 will not be in a floating state, but will be maintained at a negative voltage of -5V (that is, the voltage of the detection signal DET and the diagnostic signal ASIL_V is -5V).
[0066] Figure 2A 1 is a waveform diagram showing voltage changes of related signals of some data lines of the display device 1000 in the display mode. Figure 2A The waveform diagram is described by taking 7 data lines DL[1], DL[2], DL[3], DL[4], DL[5], DL[M-1] and DL[M] as examples ( Figure 1The display device 1000 does not show the data lines DL[3], DL[4], DL[5] and DL[M-1]).
[0067] In the display mode, the data signals DATA transmitted by the data lines DL[1]-DL[5], DL[M-1] and DL[M] are generated by the corresponding output ports S[1]-S[5], S[M-1] and S[M] of the external control circuit 320 ( Figure 1 The display device 1000 does not show output ports S[3] to S[5], S[M-1], and S[M]).
[0068] First, the voltage change of the signal of the relevant path of the data line DL[1] is explained. The time lengths of the time intervals T1 and T3 are both 1μs, for example, and the time length of the time interval T2 is 13μs, for example. In the display mode, the data signal DATA generated by the output port S[1] is a data voltage that may change over time. In the time interval T1, the voltage of the data signal DATA is 0V; in the subsequent time interval T2, the voltage of the data signal DATA is increased to 5V; in the subsequent time interval T3, the voltage of the data signal DATA drops back to 0V. That is, in the time intervals T1 to T3, the data voltage of the data signal DATA is increased from 0V to 5V and then dropped back to 0V.
[0069] In the display mode, the voltage of the array test switch signal AT_SW is maintained at a negative voltage of -9V during the time interval T1 to T3. Similarly, the voltage of the array test control signal AT_CTRL is also maintained at a negative voltage of -9V during the time interval T1 to T3. On the other hand, the voltage of the display control signal DP_CTRL is maintained at a positive voltage of 10V during the time interval T1 to T3. Furthermore, the detection signal DET and the diagnostic signal ASIL_V are maintained at a negative voltage of -5V during the time interval T1 to T3.
[0070] In this embodiment, the voltage changes of the signals related to the odd-numbered data lines DL[1], DL[3], DL[5] and DL[M-1] are the same. For example, the data signal DATA related to the data line DL[3] is 0V in the time interval T7, increases to 5V in the time interval T8, and drops back to 0V in the time interval T9.
[0071] On the other hand, the voltage changes of the signals related to the even-numbered data lines DL[2], DL[4], and DL[M] are the same, but the voltage changes of the even-numbered data lines are different from those of the odd-numbered data lines. For example, the data signal DATA related to the data line DL[2] is 0V in the time interval T4, drops to -5V in the time interval T5, and rises back to 0V in the time interval T6. That is, the change polarity of the data signal DATA of the even-numbered data line DL[2] is opposite to the change polarity of the data signal DATA of the odd-numbered data line DL[1].
[0072] Next, please continue with Table 1 to explain the operation of the display device 1000 in the diagnostic mode. The diagnostic mode is used to diagnose whether the data lines DL[1] to DL[M] in the vertical direction are in an abnormal state. In the diagnostic mode, the data signal DATA is provided by the output ports S[1], S[2], etc. of the external control circuit 320, and the voltage of the data signal DATA is a fixed positive voltage of 10V. The data signal DATA is transmitted to the data lines DL[1], DL[2], etc. to diagnose the abnormal state of these data lines (the abnormal state is, for example, a broken line). For example, when the data lines DL[1] and DL[2] are both in a normal state, the data signal DATA can be transmitted to the transistors T(as)1 and T(as)2 via the data lines DL[1] and DL[2] respectively. In addition, the array test switch signal AT_SW is a positive voltage of 10V, so the transistors T(as)1 and T(as)2 are turned on. The data signal DATA is transmitted to the control terminals of the transistors T(dd)1 and T(dd)2 via the turned-on transistors T(as)1 and T(as)2. The data signal DATA with a positive voltage turns on the transistors T(dd)1 and T(dd)2.
[0073] The voltage of the display control signal DP_CTRL is a negative voltage of -9V, so the transistor T(dd)0 is disconnected. The detection signal DET transmitted by the detection signal line 14 is not transmitted to the diagnostic signal line 13 via the disconnected transistor T(dd)0. In contrast, the detection signal DET of a positive voltage (for example, 5V) can be transmitted to the diagnostic signal line 13 via the turned-on transistors T(dd)1 and T(dd)2 to form the diagnostic signal ASIL_V. That is, the voltage of the diagnostic signal ASIL_V is also 5V; the diagnostic signal ASIL_V is transmitted to the input port ASIL3 of the external control circuit 320. When the input port ASIL3 receives the diagnostic signal ASIL_V with a voltage of 5V, the external control circuit 320 can confirm that the data line DL[1] and the data line DL[2] are in a normal state.
[0074] On the other hand, when either of the data lines DL[1] and DL[2] is in an abnormal state (for example, the data line DL[1] is disconnected), the data signal DATA cannot be transmitted to the transistor T(as)1 via the disconnected data line DL[1], and cannot be further transmitted to the control end of the transistor T(dd)1, so the transistor T(dd)1 is disconnected. The detection signal DET cannot be transmitted to the diagnostic signal line 13 via the disconnected transistor T(dd)1. The voltage of the diagnostic signal ASIL_V of the diagnostic signal line 13 is not equal to the positive voltage 5V of the detection signal DET. The diagnostic signal ASIL_V received by the input port ASIL3 is not equal to the positive voltage 5V, and the external control circuit 320 confirms that the data line DL[1] is in an abnormal state.
[0075] Figure 2B 1 is a waveform diagram showing voltage changes of related signals of some data lines of the display device 1000 in the diagnosis mode. Figure 2B The waveform diagram is also described by taking the seven data lines DL[1] to DL[5], DL[M-1] and DL[M] as examples. In the diagnostic mode, the data signal DATA is also generated by the output ports S[1] to S[5], S[M-1] and S[M] of the external control circuit 320. First, the voltage change of the signal of the relevant path of the data line DL[1] is described. The time lengths of the time intervals T1 and T3 are both 1μs, for example, and the time length of the time interval T2 is 13μs, for example. In the time interval T1, the voltage of the data signal DATA of the data line DL[1] is -9V; in the subsequent time interval T2, the voltage of the data signal DATA is increased to 10V; in the subsequent time interval T3, the voltage of the data signal DATA drops back to -9V. The voltage of the array test switch signal AT_SW is maintained at a positive voltage of 10V in the time interval T1 to T3. The voltage of the array test control signal AT_CTRL is maintained at a negative voltage of -9V in the time interval T1 to T3. The voltage of the display control signal DP_CTRL is maintained at a negative voltage of -9V during the time interval T1 to T3. The voltage of the detection signal DET is maintained at a positive voltage of 5V during the time interval T1 to T3. When the data line DL[1] is in a normal state, the voltage of the data signal DATA is increased to 10V during the time interval T2, so the transistor T(dd)1 is turned on. The detection signal DET can be transmitted to the diagnostic signal line 13 via the turned-on transistor T(dd)1 to form a diagnostic signal ASIL_V. Therefore, the voltage of the diagnostic signal ASIL_V is increased to 5V during the time interval T2. The diagnostic signal ASIL_V is transmitted to the input port ASIL3 of the external control circuit 320, and the external control circuit 320 confirms that the data line DL[1] is in a normal state based on the positive voltage 5V of the diagnostic signal ASIL_V.
[0076] On the other hand, the voltage changes of the signals related to the other data lines DL[2] to DL[5], DL[M-1] and DL[M] are the same as those of the data line DL[1]. For example, the voltage of the data signal DATA of the data line DL[2] is -9V in the time interval T4, increases to 10V in the subsequent time interval T5, and decreases back to -9V in the subsequent time interval T6. The voltage of the diagnostic signal ASIL_V related to the data line DL[2] increases to 5V in the time interval T5.
[0077] Similarly, the voltage of the data signal DATA on the data line DL[3] is -9V in time interval T7, increases to 10V in the following time interval T8, and decreases back to -9V in the following time interval T9. The voltage of the diagnostic signal ASIL_V related to the data line DL[3] increases to 5V in time interval T8.
[0078] Next, referring to Table 1, the operation of the display device 1000 in the array test mode is described. In the array test mode, the output ports S[1] and S[2] of the external control circuit 320 do not generate the data signal DATA. When the data line DL[1] is in an abnormal state, or one of the transistors T(ac)1 and T(as)1 is disconnected, the voltage of the data signal DATA on the data line DL[1] is temporarily a floating voltage. When the data line DL[1] is in a normal state and the transistors T(ac)1 and T(as)1 are turned on, the array test signal AT_PAD of the array test pad pd1 can be transmitted to the data line DL[1], so the voltage of the data signal DATA of the data line DL[1] is equal to the data voltage of the array test signal AT_PAD. Similarly, the voltage of the data signal DATA on the other data line DL[2] is a floating voltage, or equal to the data voltage of the array test signal AT_PAD of the array test pad pd2.
[0079] The voltage of the array test control signal AT_CTRL is 10V, so the transistors T(ac)1 and T(ac)2 are turned on. Also, the voltage of the array test switch signal AT_SW is 10V, so the transistors T(as)1 and T(as)2 are turned on. The array test signal AT_PAD received by the array test pad pd1 is a data voltage, and the array test signal AT_PAD is transmitted to the data line DL[1] via the turned-on transistors T(ac)1 and T(as)1. Similarly, the array test signal AT_PAD of the array test pad pd2 is a data voltage, which is transmitted to the data line DL[2] via the turned-on transistors T(ac)2 and T(as)2.
[0080] Furthermore, the voltage of the display control signal DP_CTRL is a negative voltage of -9V, so the transistor T(dd)0 is turned off. The detection signal DET transmitted by the detection signal line 14 is not transmitted to the diagnosis signal line 13 via the turned-off transistor T(dd)0. Therefore, the diagnosis signal ASIL_V of the diagnosis signal line 13 is a floating voltage.
[0081] Figure 2C 1 is a waveform diagram showing voltage changes of related signals of some data lines of the display device 1000 in the array test mode. Figure 2C The waveform diagram is also explained using the seven data lines DL[1] to DL[5], DL[M-1] and DL[M] as examples. First, the voltage change of the signal of the relevant path of the data line DL[1] is explained. The time lengths of the time intervals T1 and T3 are both 1μs, for example, and the time length of the time interval T2 is 13μs, for example. The array test signal AT_PAD received by the array test pad pd1 corresponding to the data line DL[1] is a data voltage that may change over time. In the time interval T1, the voltage of the array test signal AT_PAD is 0V; in the subsequent time interval T2, the voltage of the array test signal AT_PAD is increased to 5V; in the subsequent time interval T3, the voltage of the array test signal AT_PAD drops back to 0V. That is, the data voltage of the array test signal AT_PAD increases from 0V to 5V and then drops back to 0V.
[0082] As described above, when the data line DL[1] is in a normal state and the transistors T(ac)1 and T(as)1 are turned on, the voltage of the data signal DATA is equal to the voltage of the array test signal AT_PAD. Therefore, the voltage of the data signal DATA is 0V in the time interval T1, increases to 5V in the time interval T2, and decreases back to 0V in the time interval T3.
[0083] The voltage of the array test switch signal AT_SW is maintained at a positive voltage of 10V during the time interval T1 to T3. Similarly, the voltage of the array test control signal AT_CTRL is also maintained at a positive voltage of 10V during the time interval T1 to T3. On the other hand, the voltage of the display control signal DP_CTRL is maintained at a negative voltage of -9V during the time interval T1 to T3. Furthermore, the detection signal DET and the diagnostic signal ASIL_V are floating voltages during the time interval T1 to T3.
[0084] In this embodiment, the voltage changes of the signals related to the odd-numbered data lines DL[1], DL[3], DL[5] and DL[M-1] are the same. For example, the data signal DATA related to the data line DL[3] is 0V in the time interval T7, increases to 5V in the time interval T8, and drops back to 0V in the time interval T9.
[0085] On the other hand, the voltage changes of the related signals of the even-numbered data lines DL[2], DL[4] and DL[M] are the same, but the voltage changes of the even-numbered data lines are different from those of the odd-numbered data lines. For example, the voltage of the array test signal AT_PAD of the even-numbered data line DL[2] is 0V in the time interval T4, decreases to -5V in the subsequent time interval T5, and rises back to 0V in the subsequent time interval T6.
[0086] When the data line DL[2] is in a normal state and the transistors T(ac)2 and T(as)2 are turned on, the voltage of the data signal DATA is equal to the voltage of the array test signal AT_PAD. Therefore, the voltage of the data signal DATA is 0V in the time interval T4, drops to -5V in the time interval T5, and rises back to 0V in the time interval T6. The voltage changes of the signals related to the other even-numbered data lines DL[4] and DL[M] are similar.
[0087] Figure 3 FIG. 1 is a circuit diagram of a display device 1002 according to another embodiment of the present disclosure. The display device 1002 of this embodiment is similar to Figure 1 The display device 1000 of the embodiment of the present invention is different in that the external control circuit 320 b of the display device 1002 of the present embodiment further includes a plurality of shift register units SR2 . These shift register units SR2 are similar to the shift register units SR1 of another external control circuit 310 .
[0088] The shift register unit SR1 of the external control circuit 310 is used to perform a timing shift process to generate a timing shift detection signal. The timing shift detection signal is sequentially transmitted to the gate lines G[0]-G[N] at corresponding time intervals, and is used to diagnose the abnormal state of the gate lines G[1]-G[N].
[0089] On the other hand, the multiple output ports S[1], S[2], ..., S[M] of the external control circuit 320b generate original data signals. These multiple output ports S[1], S[2], ..., S[M] are coupled to the corresponding shift register unit SR2. The shift register unit SR2 performs a timing shift process on the original data signal to generate a timing shifted data signal DATA. The timing shifted data signal DATA is transmitted to the data lines DL[1]~DL[M] in sequence in the corresponding time interval, which is used to diagnose the abnormal state of the data lines DL[1]~DL[M]. The shift register unit SR2 is turned on according to the timing; the shift register unit SR2 turned on in a certain time interval can allow the original data signal generated by the corresponding output port to be transmitted upward. For example, the i-th shift register unit SR2 activated in the i-th time interval may allow the original data signal generated by the corresponding i-th output port S[i] to be transmitted upward to the corresponding i-th data line DL[i] for diagnosing abnormal status of the data line DL[i].
[0090] In addition, the external control circuit 320b further includes another output port SR". The output port SR" is used to control the timing shift processing of the shift register unit SR2. Figure 1 The external control circuit 320 of the embodiment directly generates a timing-shifted data signal DATA through output ports S[1], S[2], etc. and provides it to the corresponding data line. The external control circuit 320b of this embodiment performs timing shift processing through the shift register unit SR2 to generate a timing-shifted data signal DATA.
[0091] Please refer to Table 2 below, which shows the voltage values of various signals and the input / output types of the display device 1002 in the display mode, the diagnosis mode and the array test mode of this embodiment.
[0092] Table 2
[0093]
[0094] As shown in Table 2, in the display mode, all the shift register units SR2 of the external control circuit 320b are in the open state in each time interval to allow all the output ports S[1]~S[M] to transmit the data signal DATA to the data lines DL[1]~DL[M] and provide it to the corresponding display units P(0,1)~P(1,M). On the other hand, in the diagnostic mode, the shift register unit SR2 is turned on in sequence (i.e., turned on in sequence in different time intervals). Furthermore, in the array test mode, the shift register unit SR2 is in a floating state. More detailed behaviors of the shift register unit SR2 in the display mode, diagnostic mode, and array test mode (for example, detailed voltage changes related to the shift register unit SR2) can be seen in Figure 4A , Figure 4B and Figure 4C Waveform diagram of .
[0095] Please see first Figure 4A , which is Figure 3 A waveform diagram showing voltage changes of related signals of some data lines of the display device 1002 in the display mode. Figure 4A is similar to Figure 2A ,and Figure 4A The voltage associated with the shift register unit SR2 is also shown. In the display mode, all the shift register units SR2 of the external control circuit 320b are in an on state in each time interval; for example, the voltage associated with all the shift register units SR2 is a positive voltage of 10V in each time interval.
[0096] Next, see Figure 4B , which is Figure 3 FIG. 1 is a waveform diagram showing voltage changes of related signals of some data lines of the display device 1002 in the diagnosis mode. Figure 4B is similar to Figure 2B , and further shows the voltage associated with the shift register unit SR2. In the diagnostic mode, the shift register unit SR2 corresponding to the seven data lines DL[1] to DL[5], DL[M-1] and DL[M] is turned on in different time intervals according to the timing sequence. For example, the shift register unit SR2 corresponding to DL[1] is turned on in time interval T2, the shift register unit SR2 corresponding to DL[2] is turned on in time interval T5, the shift register unit SR2 corresponding to DL[3] is turned on in time interval T8, and so on.
[0097] More specifically, the voltage associated with the shift register unit SR2 corresponding to DL[1] is a negative voltage of -9V in time interval T1, increases to a positive voltage of 10V in time interval T2, and decreases back to a negative voltage of -9V in time interval T3. Similarly, the voltage associated with the shift register unit SR2 corresponding to DL[2] increases from a negative voltage of -9V to a positive voltage of 10V in time intervals T4 to T6, and then decreases back to a negative voltage of -9V. The voltage associated with the shift register unit SR2 corresponding to DL[3] increases from a negative voltage of -9V to a positive voltage of 10V in time intervals T7 to T9, and then decreases back to a negative voltage of -9V.
[0098] Next, see Figure 4C , which is Figure 3 FIG. 1 is a waveform diagram of voltage changes of related signals of some data lines of the display device 1002 in the array test mode. Figure 4C is similar to Figure 2C , and further shows the voltage associated with the shift register unit SR2. In the array test mode, the shift register units SR2 corresponding to all the data lines DL[1]-DL[M] are in a floating state in each time interval. Figure 4C Only the floating states of the shift register units SR2 corresponding to seven data lines DL[1]-DL[5], DL[M-1] and DL[M] are shown. The voltages of these shift register units SR2 are in the floating state in each time interval.
[0099] In summary, the diagnostic mode is to diagnose whether the data lines DL[1] to DL[M] arranged in the vertical direction are in an abnormal state. Taking the diagnosis of the data line DL[1] as an example, in order to perform the diagnostic function, the display device 1000 (or the display device 1002 of another embodiment) is provided with a transistor T(dd)1 for controlling the diagnostic function at the tail end of the data line DL[1] (the tail end refers to: the end where the data line DL[1] is coupled to the test control circuit 100). The data line DL[1], the transistors T(as)1, T(dd)1 and the diagnostic signal line 13 form a "diagnostic path". In addition, a data signal DATA is provided at the front end of the data line DL[1] (the front end refers to: the end where the data line DL[1] is coupled to the external control circuit 320). When the data line DL[1] is in a normal state, the data signal DATA is transmitted from the front end of the data line DL[1] to the control end of the transistor T(dd)1 at the tail end, so that the transistor T(dd)1 is turned on. Furthermore, the detection signal DET can be introduced into the diagnostic signal line 13 via the turned-on transistor T(dd)1 to form a diagnostic signal ASIL_V which is transmitted to the input port ASIL3 of the external control circuit 320. The external control circuit 320 confirms whether the data line DL[1] is in an abnormal state according to the diagnostic signal ASIL_V received by the input port ASIL3. The above operation of the display device 1000 in the diagnostic mode does not affect the operation of other modes (i.e., the display mode and the array test mode). After the user uses the display device 1000, the user can switch from the display mode to the diagnostic mode at any time to diagnose whether the data lines DL[1] to DL[M] are in an abnormal state.
[0100] Although the present disclosure has been disclosed in detail with preferred embodiments and examples as above, it is to be understood that these examples are intended to be illustrative rather than restrictive. It is contemplated that a person skilled in the art may conceive of various modifications and combinations, which fall within the spirit of the present disclosure and the scope of the appended claims.
Claims
1. A display device, comprising: An active area circuit includes a plurality of display units, wherein the plurality of display units are correspondingly coupled to a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines extend in a first direction, and the plurality of data lines extend in a second direction, and the second direction is substantially orthogonal to the first direction; as well as A test control circuit, comprising: A plurality of detection transistors are commonly coupled to a detection signal line to receive a detection signal, and are commonly coupled to a diagnosis signal line to provide a diagnosis signal; and A plurality of array test switch transistors are respectively coupled to the plurality of data lines to receive a plurality of data signals and selectively transmit the plurality of data signals to the plurality of detection transistors. The plurality of detection transistors are turned on or off according to the plurality of data signals. When the plurality of detection transistors are turned on, the detection signal is transmitted to the diagnosis signal line to form the diagnosis signal.
2. The display device as claimed in claim 1, wherein the plurality of array test switch transistors are commonly coupled to an array test switch line to receive an array test switch signal, and when the display device operates in a diagnostic mode, the array test switch signal has a positive voltage and the plurality of array test switch transistors are turned on.
3. The display device as described in claim 2, wherein when the display device operates in the diagnostic mode and at least one of the plurality of data lines is in a normal state, a corresponding one of the plurality of data signals is transmitted to the corresponding detection transistor via the at least one data line and the corresponding array test switch transistor to turn on the detection transistor, and the detection signal is transmitted to the diagnostic signal line via the turned-on detection transistor. 4 . The display device as claimed in claim 2 , wherein when the display device operates in a display mode, the array test switch signal has a negative voltage and the plurality of array test switch transistors are turned off.
5. The display device as claimed in claim 4, wherein the plurality of detection transistors comprises: a first detection transistor coupled to a display control line to receive a display control signal, When the display device operates in the display mode, the display control signal has the positive voltage to turn on the first detection transistor. 6 . The display device as claimed in claim 5 , wherein when the display device operates in the display mode, the detection signal has the negative voltage, and the detection signal is transmitted to the diagnosis signal line via the turned-on first detection transistor so that the potential of the diagnosis signal is the negative voltage.
7. The display device as claimed in claim 5, wherein when the display device operates in the diagnosis mode, the display control signal has the negative voltage to turn off the first detection transistor, and the detection signal is selectively transmitted to the diagnosis signal line via the other plurality of detection transistors except the first detection transistor.
8. The display device as claimed in claim 5, wherein the test control circuit further comprises: A plurality of array test control transistors are commonly coupled to an array test control line to receive an array test control signal. When the display device operates in the display mode and the diagnosis mode, the array test control signal has the negative voltage to turn off the plurality of array test control transistors. 9 . The display device as claimed in claim 8 , wherein a plurality of the array test control transistors are correspondingly coupled to a plurality of array test pads to receive a plurality of array test signals.
10. The display device as claimed in claim 9, wherein when the display device operates in an array test mode, the array test control signal has the positive voltage to turn on the plurality of array test control transistors, and the plurality of array test signals are transmitted to the plurality of data lines via the plurality of array test control transistors and the plurality of array test switch transistors.
11. The display device according to claim 1, further comprising: A first external control circuit, comprising: a plurality of data output ports, correspondingly coupled to the plurality of data lines and used to generate a plurality of the data signals; and a first diagnostic input port coupled to the diagnostic signal line to receive the diagnostic signal, The first external control circuit confirms the normal status of the plurality of data lines according to the diagnostic signal received by the first diagnostic input port.
12. The display device as claimed in claim 11, wherein the detection signal has a positive voltage when the display device operates in a diagnostic mode, and when the voltage of the diagnostic signal is equal to the positive voltage of the detection signal, the first external control circuit confirms that the plurality of data lines are in a normal state.
13. The display device as claimed in claim 12, wherein the first external control circuit further comprises: A plurality of first shift register units are correspondingly coupled between the plurality of data output ports and the plurality of data lines. Wherein, the plurality of first shift register units perform timing shift processing on the plurality of data signals.
14. The display device according to claim 11, further comprising: A second external control circuit, comprising: A plurality of second shift register units are correspondingly coupled to at least two of the plurality of gate lines and are used to generate a plurality of timing shifted signals.
15. The display device as claimed in claim 14, wherein the first external control circuit further comprises: at least two second diagnostic input ports, correspondingly coupled to at least two of the plurality of gate lines, and used for receiving the plurality of signals generated by the plurality of the second shift register units, The first external control circuit confirms the normal status of the plurality of gate lines according to the plurality of signals received by the plurality of the second diagnostic input ports.
16. The display device as claimed in claim 1, wherein each of the display units comprises: a transistor having a control terminal coupled to a corresponding one of the plurality of gate lines and a first terminal coupled to a corresponding one of the plurality of data lines; as well as a capacitor coupled to a second terminal of the transistor, When the transistor is turned on, the data signal transmitted by the corresponding data line is provided to the capacitor.