Display panel, driving method and display device

Abstract

Embodiments of the present application disclose a display panel, a driving method and a display device. The display panel comprises a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a node voltage adjusting module, and further comprises a first node connected with the driving transistor or the light emitting element; the node voltage adjusting module is configured to write a first voltage adjusting signal to the first node in a node voltage adjusting stage of a refresh frame, and write a second voltage adjusting signal to the first node in a node voltage adjusting stage of a holding frame; wherein the first voltage adjusting signal and the second voltage adjusting signal are both used for adjusting the voltage state of the first node, and the voltage of the first voltage adjusting signal is different from the voltage of the second voltage adjusting signal. Embodiments of the present application solve the problem of the difference in the light emitting brightness of the light emitting element caused by the different biasing time of the driving transistor between the refresh frame and the holding frame, the flicker problem in the low frequency refresh area, ensure the display uniformity, and improve the display quality.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display panel, a driving method and a display device. BACKGROUND

[0002] With the development of display technology, new display panels such as organic light emitting diode (OLED) display panels and micro light emitting diode (Micro LED) display panels are emerging in endlessly and are widely favored by consumers.

[0003] Electronic products will adopt different refresh rates for display in different application scenarios, such as using a driving mode with a higher refresh rate to drive display of dynamic pictures (such as game scenes) to ensure the smoothness of the display pictures, and using a driving mode with a lower refresh rate to drive display of slow-motion images or static pictures to reduce power consumption.

[0004] In some application scenarios, the display screen can also be set to perform dynamic partition refresh, that is, the display screen is divided into a plurality of partitions, and different partitions have independent refresh frequencies, thereby achieving the effect of reducing the driving power consumption of the display screen. However, this dynamic partition refresh mode can cause partition flickering, resulting in uneven display and poor display quality. SUMMARY

[0005] The present application provides a display panel, a driving method and a display device to improve the flickering problem during dynamic partition refresh, improve display uniformity and improve display quality.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0007] a pixel circuit and a light emitting element;

[0008] The pixel circuit comprises a driving module and a node voltage adjustment module;

[0009] The driving module is configured to provide a driving current for the light emitting element, and the driving module comprises a driving transistor;

[0010] The pixel circuit further comprises a first node connected with the driving transistor or the light emitting element, and the node voltage adjustment module is connected with the first node;

[0011] The picture display process of the display panel comprises a plurality of display frames, the display panel comprises a first partition, the plurality of display frames of the first partition comprise refresh frames and holding frames, and the refresh frames and the holding frames each comprise a node voltage adjustment phase;

[0012] The node voltage adjustment module is configured to:

[0013] In the node voltage adjustment phase of the refresh frame, a first voltage adjustment signal is written to the first node;

[0014] In the node voltage adjustment phase of the holding frame, a second voltage adjustment signal is written to the first node;

[0015] The first voltage adjustment signal and the second voltage adjustment signal are both used to adjust the voltage state of the first node, and the voltage of the first voltage adjustment signal is different from the voltage of the second voltage adjustment signal.

[0016] In a second aspect, an embodiment of the present application also provides a driving method of a display panel,

[0017] The display panel includes a pixel circuit and a light emitting element;

[0018] The pixel circuit includes a driving module and a node voltage adjustment module;

[0019] The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0020] The pixel circuit further includes a first node connected with the driving transistor or the light emitting element, and the node voltage adjustment module is connected with the first node;

[0021] The display panel has a picture display process including a plurality of display frames, and the display panel includes a first sub-region, the plurality of display frames of the first sub-region include a refresh frame and a holding frame, and the refresh frame and the holding frame both include a node voltage adjustment phase;

[0022] The driving method includes:

[0023] In the node voltage adjustment phase of the refresh frame, the node voltage adjustment module is controlled to write a first voltage adjustment signal to the first node;

[0024] In the node voltage adjustment phase of the holding frame, the node voltage adjustment module is controlled to write a second voltage adjustment signal to the first node;

[0025] The first voltage adjustment signal and the second voltage adjustment signal are both used to adjust the voltage state of the first node, and the voltage of the first voltage adjustment signal is different from the voltage of the second voltage adjustment signal.

[0026] In a third aspect, the embodiments of the present application further provide a display device comprising any one of the display panels provided by the embodiments of the present application.

[0027] In the technical solution of the embodiments of the present application, the node voltage adjustment module writes two different voltage adjustment signals, i.e., the first voltage adjustment signal and the second voltage adjustment signal, in the node voltage adjustment stage of the refresh frame and the sustain frame, respectively, so as to meet the differentiated bias adjustment requirements of the driving transistor in the refresh frame and the sustain frame, respectively, compensate for the drift of the characteristic curve of the driving transistor caused by the forward bias in the sustain frame and the refresh frame, or weaken or eliminate the difference between the voltage states of the first node in the refresh frame and the sustain frame, thereby ensuring that the pixel circuit has the same driving process on the light emitting element in the light emitting stage, providing the same driving current, realizing the same light emitting brightness, solving the problem of the difference in the light emitting brightness of the light emitting element between the refresh frame and the sustain frame caused by the different biasing times of the driving transistor, ensuring the display uniformity, and improving the display quality. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application;

[0029] Figure 2 and Figure 3 is Figure 1 are two circuit structure schematic diagrams of the pixel circuit and the light emitting element in the display panel shown in FIG. 1;

[0030] Figure 4 is a driving timing diagram of a first partitioned pixel circuit provided by the embodiments of the present application;

[0031] Figure 5 is a flowchart of a driving method of a pixel circuit provided by the embodiments of the present application;

[0032] Figure 6 is another circuit structure schematic diagram of a pixel circuit and a light emitting element provided by the embodiments of the present application;

[0033] Figure 7 and Figure 8 are still two circuit structure schematic diagrams of a pixel circuit and a light emitting element provided by the embodiments of the present application;

[0034] Figure 9 is a driving timing diagram of another first partitioned pixel circuit provided by the embodiments of the present application;

[0035] Figure 10 and Figure 11 are still two circuit structure schematic diagrams of a pixel circuit and a light emitting element provided by the embodiments of the present application;

[0036] Figure 12is a driving timing diagram of a second sub-pixel circuit provided by the embodiment of the present application;

[0037] Figure 13 is a structural schematic diagram of a display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended for the purpose of interpretation of the present application, but not for the limitation of the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0039] The terms used in the embodiments of the present application are merely for the purpose of describing specific embodiments, and are not intended to limit the present application. It should be noted that the terms “upper”, “lower”, “left”, “right” and the like described in the embodiments of the present application are described in the angle shown in the drawings, and should not be understood as the limitation of the embodiments of the present application. In addition, it should be understood in the context that when referring to one element being formed “on” or “under” another element, it can be directly formed “on” or “under” another element, or indirectly formed “on” or “under” another element through an intermediate element. The terms “first”, “second” and the like are merely for the purpose of description, and do not represent any order, quantity or importance, but are only used to distinguish different components. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0040] The term “including” and its variants used in the present application are open inclusion, i.e. “including but not limited to”. The term “based on” is “at least partially based on”. The term “one embodiment” means “at least one embodiment”.

[0041] It should be noted that the concepts of “first”, “second” and the like mentioned in the present application are only used to distinguish the corresponding content, and are not used to limit the order or mutual dependency.

[0042] It should be noted that the modification of “one”, “multiple” mentioned in the present application is illustrative but not limiting, and those skilled in the art should understand that, unless otherwise explicitly indicated in the context, it should be understood as “one or more”.

[0043] As described in the background section, the existing display panel drives the light emitting element to emit light through the pixel circuit to realize the display function, and the driving transistor in the pixel circuit is in a forward bias state during display. Long-term forward bias can cause the characteristic curve of the driving transistor to shift, the threshold voltage to change, and the display brightness of the light emitting element to fail to reach the target brightness. Therefore, it is usually necessary to bias the driving transistor during the light emitting gap of the light emitting element, that is, to reverse bias the driving transistor, so as to compensate for the influence of long-term forward bias on the characteristics of the driving transistor, avoid changes in the threshold voltage, and ensure the accuracy of the light emitting brightness of the light emitting element.

[0044] However, when reverse biasing, a reverse bias signal is usually uniformly provided to each pixel circuit to realize reverse bias adjustment. For the low-frequency refresh area, data signals are written in the refresh frame, and no data signals are written in the holding frame, but the display brightness of the refresh frame is maintained. When writing data signals, the bias state of the driving transistor changes, thereby causing the time of the driving transistor in the refresh frame and the holding frame to be in a forward bias state to be different. Therefore, when a uniform reverse bias signal is provided in the refresh frame and the holding frame to realize bias adjustment, the different bias adjustment requirements of the low-frequency refresh area in each display frame cannot be met, the characteristic curve of the driving transistor in the low-frequency refresh area in different display frames is different, the display brightness between different display frames is different, the display of the low-frequency refresh area changes in brightness, and flickering phenomenon occurs, affecting the display quality.

[0045] To solve the above technical problems, an embodiment of the present application provides a display panel, which comprises a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a node voltage adjustment module; the driving module is configured to provide a driving current for the light emitting element, and the driving module comprises a driving transistor; the pixel circuit further comprises a first node connected with the driving transistor or the light emitting element; the node voltage adjustment module is connected with the first node; the picture display process of the display panel comprises a plurality of display frames, and the display panel comprises a first sub-area; the plurality of display frames of the first sub-area comprise a refresh frame and a holding frame, and the refresh frame and the holding frame both comprise a node voltage adjustment stage.

[0046] The node voltage adjustment module is configured to: in the node voltage adjustment stage of the refresh frame, write a first voltage adjustment signal to the first node; and in the node voltage adjustment stage of the holding frame, write a second voltage adjustment signal to the first node; wherein the first voltage adjustment signal and the second voltage adjustment signal are both used to adjust the voltage state of the first node, and the voltage of the first voltage adjustment signal is different from the voltage of the second voltage adjustment signal.

[0047] In the technical solution, the display panel has a first sub-area, and in the picture display process of the display panel, the multiple display frames of the first sub-area include refresh frames and holding frames. That is, not all display frames of the first sub-area are refresh frames, but part of the display frames are holding frames, so that the number of refresh frames is limited, the refresh frequency of the first sub-area is controlled, and the power consumption of the panel is reduced. Considering the influence of the bias time difference of the driving transistor in the refresh frame and the holding frame on the display brightness of the light emitting element, the embodiment of the application determines a node that can adjust the bias state of the driving transistor in the pixel circuit or a node that is affected by the bias state of the driving transistor and then affects the light emitting brightness of the light emitting element, defines the node as a first node, sets a node voltage adjustment module for the first node, and sets a node voltage adjustment stage in the refresh frame and the holding frame. The node voltage adjustment module writes two different voltage adjustment signals, i.e., a first voltage adjustment signal and a second voltage adjustment signal, in the node voltage adjustment stage of the refresh frame and the holding frame, respectively, so as to meet the differentiated bias adjustment requirements of the driving transistor in the refresh frame and the holding frame, respectively compensate for the drift of the characteristic curve of the driving transistor caused by the forward bias in the holding frame and the refresh frame, or weaken or eliminate the difference in the voltage state of the first node between the refresh frame and the holding frame, so as to ensure that the pixel circuit has the same driving process on the light emitting element in the light emitting stage, provides the same driving current, realizes the same light emitting brightness, solves the problem of the difference in the light emitting brightness of the light emitting element between the refresh frame and the holding frame caused by the different bias times of the driving transistor, the flicker problem of the low-frequency refresh area, ensures the display uniformity, and improves the display quality.

[0048] The above is the core idea of the application. The technical solutions in the embodiments of the application will be described clearly and completely with reference to the drawings in the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0049] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the application, Figure 2 and Figure 3 is Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the application, Figure 4 is a driving timing diagram of a first sub-area pixel circuit provided by an embodiment of the application, and Figures 1-4The display panel in the embodiment of the present application comprises a pixel circuit 10 and a light emitting element 20; the pixel circuit 10 comprises a driving module 11 and a node voltage adjusting module 12; the driving module 11 is configured to provide a driving current for the light emitting element 20, and the driving module 11 comprises a driving transistor M1. The pixel circuit 10 further comprises a first node N1 connected with the driving transistor M1 or the light emitting element 20; and the node voltage adjusting module 12 is connected with the first node N1.

[0050] The picture display process of the display panel comprises a plurality of display frames T, the display panel comprises a first sub-area AA1, the plurality of display frames T of the first sub-area AA1 comprise a refresh frame Trefersh and a holding frame Thold, and the refresh frame Trefersh and the holding frame Thold both comprise a node voltage adjusting stage td; the node voltage adjusting module 12 is configured to: write a first voltage adjusting signal V1 to the first node N1 in the node voltage adjusting stage td of the refresh frame Trefersh; and write a second voltage adjusting signal V2 to the first node N1 in the node voltage adjusting stage td of the holding frame Thold; wherein the first voltage adjusting signal V1 and the second voltage adjusting signal V2 are both used for adjusting the voltage state of the first node N1, and the voltage of the first voltage adjusting signal V1 is different from the voltage of the second voltage adjusting signal V2.

[0051] Firstly, those skilled in the art can understand that the pixel circuit 10 and the light emitting element 20 are electrically connected to provide a driving current for the light emitting element 20 to drive the light emitting element 20 to emit light. A plurality of light emitting elements 20 of different colors can constitute a pixel unit, and the pixel unit can present different colors through color matching of the plurality of light emitting elements 20, and a display picture can be formed on a macroscopic scale through cooperation of a certain number of pixel units. The time for the display panel to display a display picture by driving the corresponding light emitting element 20 to emit light by using each pixel circuit 10 in turn is called a display frame T, and a plurality of display frames T are continuously displayed to form an animation. It should be noted that the light emitting elements 20 in the display panel do not emit light at the same time, but are driven to emit light in turn through scanning, and a display picture is displayed through the human visual persistence effect. Meanwhile, different data signals Vdata are written to the pixel circuit 10 in different display frames, and the pixel circuit 10 provides different driving currents for the light emitting element 20, so that the pixel unit emits light in different colors, thereby displaying different pictures in each display frame, and realizing continuous dynamic pictures through the human visual persistence effect.

[0052] Reference Figure 4On the basis of ensuring that continuous pictures are realized through the visual persistence effect of a person, the pixel circuits 10 in different regions of the display panel can be designed to have independent data signal writing frequencies. In other words, the pixel circuits 10 in a partial region, for example, the first sub-region AA1, can be designed to write data signals Vdata only in partial display frames, refresh the luminance of the light emitting element 20, and for the pixel circuits 10 in this region, the display frame is a refresh frame Trefresh. In a partial number of display frames T after the refresh frame Trefresh, the data signals Vdata written in the refresh frame Trefresh are maintained, the luminance of the light emitting element 20 in the refresh frame Trefresh continues to emit light, and the region continues to display the same picture, and for the pixel circuits 10 in this region, the display frame at this time is a holding frame Thold. Therefore, by controlling the frequency of writing data signals Vdata to the pixel circuits 10, that is, changing the number and proportion of refresh frames Trefresh and holding frames Thold, the frequency of the refresh frame Trefresh in the region can be adjusted, and the control of the picture refresh frequency can be realized.

[0053] For the driving process of the light emitting element 20 realized by writing data signals Vdata to the pixel circuit, reference is made to Figures 2-4 First, to ensure the normal driving of the pixel circuit 10, for example, in addition to the driving module 11 and the node voltage adjustment module 12, the pixel circuit 10 in the display panel can further include a data writing module 13, a compensation module 14, a gate reset module 15, and a light emitting control module 16.

[0054] The refresh frame further includes a gate reset stage ta, a data writing stage tb, and a light emitting stage tc, and the data writing stage tb is located between the gate reset stage ta and the light emitting stage tc. The holding frame Thold further includes the light emitting stage tc.

[0055] The data writing module 13 is connected between the data signal end Vdata and the first electrode of the driving transistor M1, and is configured to be controlled by a data writing control signal SP to write data signals Vdata to the gate of the driving transistor M1 in the data writing stage tb of the refresh frame Trefresh.

[0056] The compensation module 14 is connected between the gate and the second electrode of the driving transistor M1, and is configured to be controlled by a threshold compensation control signal S2N to compensate the threshold voltage of the driving transistor M1 in the data writing stage tb of the refresh frame Trefresh.

[0057] The gate reset module 15 is connected between the gate reset signal end Vref1 and the gate of the driving transistor M1, and is configured to be controlled by a gate reset control signal S1N to reset the potential of the gate of the driving transistor M1 in the gate reset stage ta of the refresh frame Trefresh.

[0058] The light emitting control module 16 is connected with the driving module 11 and the light emitting element 20 at the first power signal end PVDD and the second power signal end PVEE, and is configured to be controlled by the light emitting control signal Emit to control the light emitting element 20 to emit light in the light emitting stage tc of the refresh frame Trefresh and the light emitting stage tc of the holding frame Thold.

[0059] Further, the light emitting control module 16 includes a first light emitting control unit 161 and a second light emitting control unit 162. The first light emitting control unit 161, the driving module 11, the second light emitting control unit 162, and the light emitting element 20 are connected in series between the first power signal end PVDD and the second power signal end PVEE. The pixel circuit 10 can further include a storage capacitor Cst connected between the first power signal end PVDD and the gate of the driving transistor M1.

[0060] The above circuit modules can be specifically composed of transistors, and the channel type of the transistors can be N type or P type. For example, referring to Figure 2 and Figure 3 The remaining circuit modules can be P type channel transistors except for the compensation module 14 and the gate reset module 15 which are N type channel transistors. The storage capacitor Cst is used to store the data signal Vdata written to the gate of the driving transistor M1.

[0061] The driving process and principle of the pixel circuit will be introduced below taking the pixel circuit shown in Figure 2 and Figure 3 as an example. For example, referring to Figures 2-4 In the refresh frame Trefresh, the pixel circuit 10 includes a gate reset stage ta, a data writing stage tb, and a light emitting stage tc.

[0062] In the gate reset stage ta, the gate reset control signal S1N received by the gate of the gate reset transistor M5 in the gate reset module 15 is high at this time, which is an effective pulse signal, the gate reset module 15 is turned on, and the gate reset signal Vref1 is input to the gate of the driving transistor M1 to reset the gate of the driving transistor M1.

[0063] During the data write phase tb, the data write control signal SP received by the gate of the data write transistor M3 in the data write module 13 is at a low level, a valid pulse signal, and the data write module 13 is turned on. Simultaneously, the threshold compensation control signal S2N received by the gate of the compensation transistor M4 in the compensation module 14 is at a high level, a valid pulse signal, and the compensation module 14 is turned on. The data signal Vdata is input to the gate of the drive transistor M1 through the data write module 13, the drive module 11, and the compensation module 14, and is stored by the storage capacitor Cst.

[0064] In the light-emitting stage tc, the gates of the first light-emitting control transistor M61 in the first light-emitting control unit 161 and the second light-emitting control transistor M62 in the second light-emitting control unit 162 both receive the light-emitting control signal Emit, which is at a low level and a valid pulse. The first light-emitting control unit 161 and the second light-emitting control unit 162 are turned on, and the driving transistor M1 provides a corresponding driving current to the light-emitting element 20 according to the data signal Vdata stored in the gate, so that the light-emitting element 20 emits light at the target brightness.

[0065] As can be seen from the above, the light emitting element 20 can be controlled by the data signal Vdata to display the target brightness corresponding to the data signal Vdata in the current display frame, namely the refresh frame Trefresh. Figure 4 From the refresh frame Trefersh and hold frame Thold, it can be seen that in the hold frame Thold of the first subarea AA1, the gate reset control signal S1N received by the gate of the gate reset transistor M5, the threshold compensation control signal S2N received by the gate of the compensation transistor M4, and the data write control signal SP received by the gate of the data write transistor M3 all have no valid pulses, that is, there is no gate reset phase ta and data write phase tb. However, the light emission control signal Emit received by the gates of the first light emission control transistor M61 and the second light emission control transistor M62 has a valid pulse, that is, there is a light emission phase tc. Therefore, it can be seen that in the hold frame Thold, the pixel circuit 10 includes a light emission phase tc, but does not set the gate reset phase ta and the data write phase tb, and only maintains the target brightness in the refresh frame Trefresh for display.

[0066] Furthermore, as mentioned above, for the first partition AA1, there is a light-emitting phase tc in both the refresh frame Trefresh and the hold frame Thold, which causes the driving transistor M1 to be in a forward biased state for a long time, causing the electrical characteristic curve to drift. And because the refresh frame Trefresh and the hold frame Thold differ in whether there is a data writing phase tb, the degree of drift of the electrical characteristic curve of the driving transistor M1 will be different. In view of this, in the embodiment of the present invention, reference is made toFigure 2 and Figure 3 In the pixel circuit, a node voltage adjustment module 12 is arranged to adjust the node affected by the difference of the electrical characteristic curve drift of the driving transistor M1 in the pixel circuit, so as to weaken or avoid the difference of the light emitting brightness of the light emitting element 20. Specifically, the embodiment of the present application further provides a driving method of the pixel circuit. Figure 5 is a flow chart of the driving method of the pixel circuit provided by the embodiment of the present application, referring to Figures 2-5 Specifically, the driving method comprises:

[0067] S110, in the node voltage adjustment stage of the refresh frame, the node voltage adjustment module is controlled to write the first voltage adjustment signal to the first node.

[0068] S120, in the node voltage adjustment stage of the holding frame, the node voltage adjustment module is controlled to write the second voltage adjustment signal to the first node.

[0069] Referring to Figures 2-4 The refresh frame Trefresh and the holding frame Thold are also provided with a node voltage adjustment stage td which does not overlap with the light emitting stage ta, that is, is arranged in the non-light emitting stage of the pixel circuit, so that when the voltage state of the node in the pixel circuit 10 is adjusted, the light emitting process of the light emitting element 20 is not disturbed. Moreover, the node voltage adjustment stage td is substantially arranged before the light emitting stage ta, so that in the node voltage adjustment stage td, by controlling the node voltage adjustment module 12 to write the voltage adjustment signal to the first node N1, the node affected by the difference of the electrical characteristic curve drift of the driving transistor M1 in the pixel circuit can be adjusted in advance, and the pixel circuit 10 in the current display frame T is adjusted, so as to unify the light emitting brightness of the light emitting element 20 in the light emitting stage ta. Wherein, the first voltage adjustment signal V1 is written in the node voltage adjustment stage td of the refresh frame Trefresh, and the second voltage adjustment signal V2 is written in the node voltage adjustment stage td of the holding frame Thold, which aims to adjust the voltage of the node in the refresh frame Trefresh and the holding frame Thold respectively, so as to meet the requirement of unifying the light emitting brightness.

[0070] Specifically, the present application illustrates the node which needs to be adjusted in the pixel circuit, and the two specific embodiments are introduced respectively referring to Figure 2 and Figure 3 First of all, it should be pointed out that, for the convenience of understanding, the same symbols are used to represent the signal terminals and signals connected to the pixel circuit, and no longer be distinguished.

[0071] As Figure 2As shown, in a specific embodiment, the first end of the node voltage adjustment module 12 is connected with the first voltage adjustment signal end V1 and the second voltage adjustment signal end V2, and the first pole of the driving transistor M1 is connected with the second end of the node voltage adjustment module 12 as the first node N1; the first voltage adjustment signal end V1 receives the first voltage adjustment signal V1, and the second voltage adjustment signal end V2 receives the second voltage adjustment signal V2; in the node voltage adjustment stage td of the refresh frame Trefresh, the node voltage adjustment module 12 turns on the first voltage adjustment signal end V1 and the first pole of the driving transistor M1 to write the first voltage adjustment signal V1 to the first pole of the driving transistor M1; in the node voltage adjustment stage td of the holding frame Thold, the node voltage adjustment module 12 turns on the second voltage adjustment signal end V2 and the first pole of the driving transistor M1 to write the second voltage adjustment signal V2 to the first pole of the driving transistor M1; wherein the first voltage adjustment signal V1 and the second voltage adjustment signal V2 are both used to adjust the voltage state of the driving transistor M1.

[0072] In this embodiment, the first node N1 is essentially the first pole of the driving transistor M1, and the node voltage adjustment module 12 adjusts the voltage state of the first pole of the driving transistor M1, which is essentially adjusting the bias state of the driving transistor M1, and the node voltage adjustment stage td is essentially a bias adjustment stage. It can be understood that, in the light emitting stage ta of the refresh frame Trefresh and the holding frame Thold, the first pole voltage of the driving transistor M1 is greater than the second pole voltage, and the driving transistor M1 is in a positive bias state for a long time, which causes the electrical characteristic curve to drift. In this embodiment, the node voltage adjustment stage td, i.e. the bias adjustment stage, is set in both the refresh frame Trefresh and the holding frame Thold, so that the bias state of the driving transistor M1 can be adjusted before the light emitting stage ta, i.e. the first pole voltage of the driving transistor M1 can be written with a voltage adjustment signal, i.e. a bias adjustment signal, in this bias adjustment stage, so that the first pole voltage is less than the second pole voltage, and the driving transistor M1 is in a reverse bias state, thereby compensating for the electrical characteristic curve drift caused by the positive bias, and ensuring the electrical stability of the driving transistor M1. At the same time, different voltage adjustment signals, i.e. the first voltage adjustment signal V1 and the second voltage adjustment signal V2, are written in the bias adjustment stages of the refresh frame Trefresh and the holding frame Thold respectively, and the two bias adjustment signals are different, which can compensate for the difference in the positive bias state caused by the data writing stage tb in the refresh frame Trefresh and the holding frame Thold, so as to meet the respective needs of bias state adjustment, so that the driving transistor M1 has the same and stable electrical state, and the light emitting element 20 has the same light emitting brightness in the light emitting stage ta.

[0073] It should be noted that, in the above embodiment, the node voltage adjustment module 12 is used to adjust the voltage state of the first pole of the driving transistor M1, and the node voltage adjustment stage td is used to adjust the bias state of the driving transistor M1, but the present application is not limited to this. For example, the node voltage adjustment module 12 can be used to adjust the voltage state of the second pole of the driving transistor M1, and the node voltage adjustment stage td can be used to adjust the bias state of the driving transistor M1. Figure 2In the pixel circuit shown, the node voltage adjusting module 12 is essentially a bias adjusting module for adjusting the bias state of the driving transistor M1. In addition, the pixel circuit also comprises an anode reset module 17 connected between the anode of the light emitting element 20 and an anode reset signal terminal Vref2.

[0074] It is also to be added that, as to the magnitude relationship between the two voltage adjusting signals, it can be understood that, as the data writing stage tb is added in the refresh frame Trefresh, the driving transistor M1 will be in a reverse bias state, which will compensate the forward bias of the driving transistor M1 in the light emitting stage to some extent, so that the driving transistor M1 is affected by the forward bias state in the refresh frame Trefresh to a relatively weak degree compared with the degree of the driving transistor M1 affected by the forward bias state in the holding frame Thold, and therefore the bias adjustment in the node voltage adjusting stage td in the refresh frame Trefresh and the node voltage adjusting stage td in the holding frame Thold should be different, and the first node voltage adjusting signal V1 and the second node voltage adjusting signal V2 input in the two voltage adjusting stages, i.e. the two bias adjusting signals, should be different. In actual use, through the verification of display panel flicker adjustment, generally, the second node voltage adjusting signal V2 provided to the holding frame Thold will be greater than the first node voltage adjusting signal V1 provided to the refresh frame Trefresh. Of course, due to the complexity of the circuit structure, when the first node voltage adjusting signal V1 and the second node voltage adjusting signal V2 are provided, the degree of the driving transistor M1 affected by the forward bias state in the holding frame Thold and the refresh frame Trefresh can be determined according to simulation or actual measurement, so as to determine the specific values and magnitudes of the first node voltage adjusting signal V1 and the second node voltage adjusting signal V2, and the present embodiment does not make too many limitations on this.

[0075] As Figure 3As shown, in another specific embodiment, the first end of the node voltage adjustment module 12 is connected with the first voltage adjustment signal end V1 and the second voltage adjustment signal end V2, and the anode of the light emitting element 20 is connected with the second end of the node voltage adjustment module 12 as the first node N1; the first voltage adjustment signal end V1 receives the first voltage adjustment signal V1, and the second voltage adjustment signal end V2 receives the second voltage adjustment signal V2; in the node voltage adjustment stage td of the refresh frame Trefresh, the node voltage adjustment module 12 turns on the first voltage adjustment signal end V1 and the anode of the light emitting element 20 to write the first voltage adjustment signal V1 to the anode of the light emitting element 20; in the node voltage adjustment stage td of the holding frame Thold, the node voltage adjustment module 12 turns on the second voltage adjustment signal end V2 and the anode of the light emitting element 20 to write the second voltage adjustment signal V2 to the anode of the light emitting element 20; wherein the first voltage adjustment signal V1 and the second voltage adjustment signal V2 are both used to reset the potential of the anode of the light emitting element 20.

[0076] In this embodiment, the first node N1 is substantially the anode of the light emitting element 20, and the node voltage adjustment module 12 adjusts the voltage state of the anode of the light emitting element 20, which is substantially resetting the anode of the light emitting element 20, and the node voltage adjustment stage td is substantially the anode reset stage. It can be understood that in the light emitting stage ta of the refresh frame Trefresh and the hold frame Thold, the path between the first power signal end PVDD and the second power signal end PVEE is turned on, and the voltage of the anode of the light emitting element 20 directly determines the current passing through the light emitting element 20, that is, determines the brightness of the light emitting element 20. In each display frame T, in order to avoid the influence of the charge stored in the anode of the light emitting element 20 in the previous display frame T on the light emitting brightness of the current display frame T, the anode voltage of the light emitting element 20 needs to be reset before the light emitting stage ta. The embodiment sets the node voltage adjustment stage td, that is, the anode reset stage, in both the refresh frame Trefresh and the hold frame Thold, so that the anode voltage of the light emitting element 20 can be reset before the light emitting stage ta, that is, the first electrode of the driving transistor M1 can be written with a voltage adjustment signal, that is, an anode reset signal, in the anode reset stage, so as to avoid the influence of the charge stored in the anode of the light emitting element 20 on the light emitting. At the same time, because there is a difference in the bias state of the driving transistor M1 in the refresh frame Trefresh and the hold frame Thold, which will affect the anode voltage of the light emitting element 20, therefore, the embodiment writes different voltage adjustment signals, that is, the first voltage adjustment signal V1 and the second voltage adjustment signal V2, in the anode reset stage of the refresh frame Trefresh and the hold frame Thold, respectively. The two bias adjustment signals are different, which can compensate for the difference in the anode voltage of the light emitting element 20 in the refresh frame Trefresh and the hold frame Thold, so as to meet the respective requirements of the anode reset, so that the anode of the light emitting element 20 has the same initial state, and the light emitting element 20 has the same light emitting brightness in the light emitting stage ta.

[0077] It should be noted that in the pixel circuit shown in FIG. 1, the node voltage adjustment module 12 is substantially an anode reset module for resetting the anode potential of the light emitting element 20. Figure 3 In the pixel circuit shown in FIG. 1, the node voltage adjustment module 12 is substantially an anode reset module for resetting the anode potential of the light emitting element 20.

[0078] It is also necessary to supplement that, due to the complexity of the circuit structure, in providing the first node voltage regulation signal V1 and the second node voltage regulation signal V2, the difference of the anode of the light emitting element 20 driven transistor M1 bias state difference can be determined according to simulation or actual measurement, etc. To determine the specific value and size of the first node voltage regulation signal V1 and the second node voltage regulation signal V2, the embodiments of the present application do not make too many limitations.

[0079] Figure 6 is another schematic circuit structure diagram of the pixel circuit and the light emitting element provided by the embodiments of the present application, referring to Figure 6 In the embodiments of the present application, two node voltage regulation modules 12, i.e. the bias adjustment module 18 and the anode reset module 17, can be provided at the same time.

[0080] Specifically, the first end of the bias adjustment module 18 is connected with the first bias adjustment signal end DVHA and the second bias adjustment signal end DVHB, and the first pole of the driving transistor M1 is connected with the second end of the node voltage regulation module 12 as the first node N1'; the first bias adjustment signal end DVHA receives the first bias adjustment signal DVHA, and the second bias adjustment signal end DVHB receives the second bias adjustment signal DVHB; in the node voltage regulation stage td of the refresh frame Trefresh, the bias adjustment module 18 turns on the first bias adjustment signal end DVHA and the first pole of the driving transistor M1, so as to write the first bias adjustment signal DVHA to the first pole of the driving transistor M1; in the node voltage regulation stage td of the holding frame Thold, the bias adjustment module 18 turns on the second bias adjustment signal end DVHB and the first pole of the driving transistor M1, so as to write the second bias adjustment signal DVHB to the first pole of the driving transistor M1; wherein, the first bias adjustment signal DVHA and the second bias adjustment signal DVHB are both used to adjust the voltage state of the driving transistor M1.

[0081] The first end of the anode reset module 17 is connected with a first anode reset signal end Vref1 and a second anode reset signal end Vref2, and the anode of the light emitting element 20 is connected with the second end of the anode reset module 17 as a first node N1". The first anode reset signal end Vref1 receives a first anode reset signal Vref1, and the second anode reset signal end Vref2 receives a second anode reset signal Vref2. In the node voltage adjustment stage td of the refresh frame Trefresh, the anode reset module 17 turns on the first anode reset signal end Vref1 and the anode of the light emitting element 20 to write the first anode reset signal Vref1 to the anode of the light emitting element 20. In the node voltage adjustment stage td of the holding frame Thold, the anode reset module 17 turns on the second anode reset signal end Vref2 and the anode of the light emitting element 20 to write the second anode reset signal Vref2 to the anode of the light emitting element 20. The first anode reset signal Vref1 and the second anode reset signal Vref2 are both used to reset the potential of the anode of the light emitting element 20.

[0082] Reference will be made to the embodiments of the present application below Figure 2 and Figure 3 The specific structure and driving principle of the node voltage adjustment module in the embodiments of the present application will be introduced. Specifically, the node voltage adjustment module 12 can include a first transistor M21 and a second transistor M22. The first end of the first transistor M21 and the first end of the second transistor M22 are both connected with the first node N1. The second end of the first transistor M21 is connected with a first voltage adjustment signal end V1, and the second end of the second transistor M22 is connected with a second voltage adjustment signal end V2. The first transistor M21 is configured to be turned on in the node voltage adjustment stage td of the refresh frame Trefresh. The second transistor M22 is configured to be turned on in the node voltage adjustment stage td of the holding frame Thold.

[0083] In optional embodiments, the gate of the first transistor M21 and the gate of the second transistor M22 can be connected with corresponding control signals for on-off control. For the first transistor M21, a corresponding control signal is used to provide an effective pulse at least in the node voltage adjustment stage td of the refresh frame Trefresh to control the first transistor M21 to be turned on. For the second transistor M22, a corresponding control signal is used to provide an effective pulse at least in the node voltage adjustment stage td of the holding frame Thold to control the second transistor M22 to be turned on.

[0084] Based on this, in the driving method provided by the present application, the step S110 can be specifically refined as:

[0085] The first transistor M21 is controlled to be turned on in the node voltage adjustment stage td of the refresh frame Trefresh.

[0086] The step S120 can be specifically refined as:

[0087] The second transistor M22 is controlled to be turned on in the node voltage adjustment stage td of the holding frame Thold.

[0088] Reference Figure 4 In the specific embodiments of the present application, the channel types of the first transistor M21 and the second transistor M22 are opposite, and the gates of the first transistor M21 and the second transistor M22 receive the same first voltage adjustment control signal SW.

[0089] More specifically, with continued reference to Figure 4 Optionally, the first transistor M21 is a P-type channel transistor, and the second transistor M22 is an N-type channel transistor; the first voltage adjustment control signal SW is configured as a first voltage V1_SW at least in the node voltage adjustment stage td of the refresh frame Trefresh; the first voltage adjustment control signal SW is configured as a second voltage V2_SW at least in the node voltage adjustment stage td of the holding frame Thold; wherein V1_SW < V2_SW.

[0090] In the node voltage adjustment stage td of the refresh frame Trefresh, for the P-type first transistor M21, the first voltage adjustment control signal SW at the first voltage V1_SW is an effective level, so as to control the first transistor M21 to be turned on; for the N-type second transistor M22, the first voltage adjustment control signal SW at the first voltage V1_SW is an ineffective level, so as to control the second transistor M22 to be turned off, thereby controlling the first transistor M21 to be turned on, so that the node voltage adjustment module 12 writes the first node voltage adjustment signal V1 to the first node N1.

[0091] In the node voltage adjustment stage td of the holding frame Thold, for the P-type first transistor M21, the first voltage adjustment control signal SW at the second voltage V2_SW is an ineffective level, so as to control the first transistor M21 to be turned off; for the N-type second transistor M22, the first voltage adjustment control signal SW at the second voltage V2_SW is an ineffective level, so as to control the second transistor M22 to be turned on, thereby controlling the second transistor M22 to be turned on, so that the node voltage adjustment module 12 writes the second node voltage adjustment signal V2 to the first node N1.

[0092] Of course, in another embodiment of the present application, the first transistor M21 can also be an N-type channel transistor, and the second transistor M22 can be a P-type channel transistor; the first voltage adjustment control signal SW is configured as a first voltage V1_SW at least in the node voltage adjustment stage td of the refresh frame Trefresh; the first voltage adjustment control signal SW is configured as a second voltage V2_SW at least in the node voltage adjustment stage td of the holding frame Thold; wherein V1_SW>V2_SW.

[0093] As known by those skilled in the art, since the channels of the first transistor M21 and the second transistor M22 are opposite to the previous embodiment, and at the same time, the voltage of the first voltage adjustment control signal SW is also opposite to the previous embodiment, therefore, its on and off states remain consistent with the previous embodiment, and the same node voltage adjustment signal input control can be achieved, which will not be described here.

[0094] Further, continuing to refer to Figure 2 and Figure 3 , the node voltage adjustment module 12 further comprises a third transistor M23, the first end of the third transistor M23 is connected to the first end of the first transistor M21 and the second transistor M22, and the second end of the third transistor M23 is connected to the first node N1; the third transistor M23 is configured to be turned on in the node voltage adjustment stage td of the refresh frame Trefresh and the node voltage adjustment stage td of the holding frame Thold.

[0095] First, as shown in the pixel circuit Figure 2 , the anode reset module 17 can specifically include an anode reset transistor M7, the gate of the anode reset transistor M7 receives a scan signal SPX, which serves as an anode reset control signal. As shown in the pixel circuit Figure 3 , the bias adjustment module 18 can specifically include a bias adjustment transistor M8, the gate of the bias adjustment transistor M8 receives a scan signal SPX, which serves as a bias adjustment control signal. Based on this, in the pixel circuit as shown in Figure 2 and Figure 3 , the third transistor M23 is also configured to be controlled by the scan signal SPX, thereby avoiding setting a control signal line for anode reset and bias adjustment in the pixel circuit respectively, reducing the number of signal lines in the pixel circuit, which helps to reduce the area of the pixel circuit and improve the resolution of the panel. Based on the fact that the anode reset and the bias adjustment share the same scan signal SPX for control, it can be understood that the node voltage adjustment in the embodiment of the present application is not only controlled by the first voltage adjustment control signal SW, but also controlled by the scan signal SPX. Referring to Figure 2 and Figure 4, the node voltage adjustment stage td in the embodiment substantially synchronously completes the anode reset, that is, the node voltage adjustment stage td is also the anode reset stage. Similarly, referring to Figure 3 and Figure 4 , the node voltage adjustment stage td in the embodiment substantially synchronously completes the bias adjustment, that is, the node voltage adjustment stage td is also the bias adjustment stage.

[0096] Figure 7 and Figure 8 are still two pixel circuit and circuit structure schematic diagram of light emitting element provided by the embodiment of the application, referring to Figure 7 and Figure 8 , in other optional embodiments, the node voltage adjustment module 12 can include a first transistor M21, a second transistor M22 and a third transistor M23, the first end of the first transistor M21 and the second transistor M22 are both connected to the second node N2, the second end of the first transistor M21 is connected to the first voltage adjustment signal end V1, the second end of the second transistor M22 is connected to the second voltage adjustment signal end V2, the first end of the third transistor M23 is connected to the second node N2, and the second end of the third transistor M23 is connected to the first node N1; the first transistor M21 is configured to be turned on before the node voltage adjustment stage td of the refresh frame Trefresh to write the first voltage adjustment signal V1 to the second node N2; the second transistor M22 is configured to be turned on before the node voltage adjustment stage td of the holding frame Thold to write the second voltage adjustment signal V2 to the second node N2; the third transistor M23 is configured to be turned on in the node voltage adjustment stage td of the refresh frame Trefresh and the node voltage adjustment stage td of the holding frame Thold, to write the first voltage adjustment signal V1 stored by the second node N2 to the first node N1 in the node voltage adjustment stage td of the refresh frame Trefresh, and write the second voltage adjustment signal V2 stored by the second node N2 to the first node N1 in the node voltage adjustment stage td of the holding frame Thold.

[0097] In the embodiment, the node voltage adjustment module 12 is also provided with a first transistor M21, a second transistor M22 and a third transistor M23, and the difference lies in that the switching time of the three transistors, especially the first transistor M21 and the second transistor M22, is different. Specifically, as Figures 2-4In the shown embodiment, the first transistor M21 and the second transistor M22 are turned on at the node voltage adjustment stage td corresponding to the display frame T, and at the same time, the third transistor M23 is turned on, so as to directly write the first node voltage adjustment signal V1 or the second node voltage adjustment signal V2 to the first node N1 through the turned-on first transistor M21 or the turned-on second transistor M22. However, in this embodiment, the first transistor M21 and the second transistor M22 are turned on before the node voltage adjustment stage td corresponding to the display frame T, that is, before the third transistor M23 is turned on, and the first node voltage adjustment signal V1 or the second node voltage adjustment signal V2 is written to the second node N2 connected with the third transistor M23 in advance and saved in the node. When the third transistor M23 is turned on, the saved first node voltage adjustment signal V1 or second node voltage adjustment signal V2 is written to the first node N1, so as to realize the node voltage adjustment of the first node N1.

[0098] Based on this, in the driving method provided by the present application, the step S110 can be specifically refined as:

[0099] The first transistor M21 is controlled to be turned on before the node voltage adjustment stage td of the refresh frame Trefresh, so as to write the first voltage adjustment signal V1 to the second node N2;

[0100] The third transistor M23 is controlled to be turned on at the node voltage adjustment stage td of the refresh frame Trefresh, so as to write the first voltage adjustment signal V1 stored in the second node N2 to the first node N1 at the node voltage adjustment stage td of the refresh frame Trefresh.

[0101] The step S120 can be specifically refined as:

[0102] The second transistor M22 is controlled to be turned on before the node voltage adjustment stage td of the holding frame Thold, so as to write the second voltage adjustment signal V2 to the second node N2;

[0103] The third transistor M23 is controlled to be turned on at the node voltage adjustment stage td of the holding frame Thold, so as to write the second voltage adjustment signal V2 stored in the second node N2 to the first node N1 at the node voltage adjustment stage td of the holding frame Thold.

[0104] Figure 9 is another driving timing diagram of the first sub-pixel circuit provided by the embodiment of the present application, and reference is made to Figures 7-9 Specifically, the gate of the first transistor M21 receives the second voltage adjustment control signal SW2, the gate of the second transistor M22 receives the third voltage adjustment control signal SW3, and the second voltage adjustment control signal SW2 and the third voltage adjustment control signal SW3 are different.

[0105] Continue to refer Figures 8-10 Optionally, any one of the gate reset control signal S1N, the threshold compensation control signal S2N and the data write control signal SP is multiplexed into the second voltage adjustment control signal SW2. The figure takes the multiplexing with the threshold compensation control signal S2N as an example; the light-emitting control signal Emit is multiplexed into the third voltage adjustment control signal SW3.

[0106] In an optional embodiment, the channel types of the first transistor M21 and the second transistor M22 are opposite, and the gate reset control signal S1N or the threshold compensation control signal S2N is multiplexed into the second voltage adjustment control signal SW2 .

[0107] Reference below Figures 7-9 , the node voltage regulation process of this embodiment is described in detail. First, Figure 7 and Figure 8 As shown, the first transistor M21 is an N-type channel transistor, and the gate of the first transistor M21 receives the threshold compensation control signal S2N as the second voltage adjustment control signal SW2. The second transistor M22 is a P-type channel transistor, and the gate of the second transistor M22 receives the light emission control signal Emit as the third voltage adjustment control signal SW3.

[0108] For refresh frame Trefresh: During the light-emitting phase tc of the previous display frame T, the light-emitting control signal Emit is at a low level, which is an active level for the second transistor M22. At this time, the second transistor M22 is turned on, and the second node voltage adjustment signal V2 is written to the second node N2 through the second transistor M22. Before the node voltage adjustment phase td, a high-level pulse is present in the threshold compensation control transistor S2N, which is an active pulse for the first transistor M21. At this time, the first transistor M21 is turned on, and the first node voltage adjustment signal V1 is written to the second node N2 through the first transistor M21. Therefore, before the node voltage adjustment phase td, the second node N2 is sequentially written with the second node voltage adjustment signal V2 and the first node voltage adjustment signal V1, and remains at the first node voltage adjustment signal V1. During the node voltage adjustment phase td, which is also the low level phase of the scan signal SPX, the third transistor M23 is turned on, and the first node voltage adjustment signal V1 from the second node N2 is written to the first node N1.

[0109] For the holding frame Thold: likewise, in the light emitting stage tc of the last display frame T, the light emitting control signal Emit is low, which is effective for the second transistor M22, and the second transistor M22 is turned on, and the second node voltage adjusting signal V2 can be written to the second node N2 through the second transistor M22; and before the node voltage adjusting stage td, the threshold compensation control transistor S2N does not have a high level pulse, and the first transistor M21 is continuously in the off state, so that before the node voltage adjusting stage td, the second node N2 only writes the second node voltage adjusting signal V2 and holds. In the node voltage adjusting stage td, i.e. the low level stage of the scanning signal SPX, the third transistor M23 is turned on, and the second node voltage adjusting signal V2 of the second node N2 is written into the first node N1.

[0110] Figure 10 and Figure 11 are another two pixel circuit and circuit structure schematic diagram of the light emitting element provided by the embodiment of the present application, referring to Figures 10-12 , in another optional embodiment of the present application, the channel type of the first transistor M21 and the second transistor M22 is the same, and the data writing control signal SP is multiplexed as the second voltage adjusting control signal SW2.

[0111] It should be noted that the pixel circuit driving timing shown in Figure 9 is also applicable to the pixel circuit shown in Figure 10 and Figure 11 . The following refers to Figures 9-11 , and the node voltage adjusting process of this embodiment is also described in detail. First, as shown in Figure 10 and Figure 11 , the first transistor M21 and the second transistor M22 are both P-type transistors, the gate of the first transistor M21 receives the data writing control signal SP as the second voltage adjusting control signal SW2, and the gate of the second transistor M22 receives the light emitting control signal Emit as the third voltage adjusting control signal SW3.

[0112] For the refresh frame Trefresh: in the light emitting stage tc of the last display frame T, the light emitting control signal Emit is at low level, which is effective level for the second transistor M22, so the second transistor M22 is turned on, and the second node voltage adjusting signal V2 can be written into the second node N2 through the second transistor M22; before the node voltage adjusting stage td, the data writing control signal SP has a low level pulse, which is effective pulse for the first transistor M21, so the first transistor M21 is turned on, and the first node voltage adjusting signal V1 is written into the second node N2 through the first transistor M21. Thus, before the node voltage adjusting stage td, the second node N2 is written with the second node voltage adjusting signal V2 and the first node voltage adjusting signal V1 in turn, and keeps the first node voltage adjusting signal V1. In the node voltage adjusting stage td, i.e. the low level stage of the scanning signal SPX, the third transistor M23 is turned on, and the first node voltage adjusting signal V1 of the second node N2 is written into the first node N1.

[0113] For the hold frame Thold: similarly, in the light emitting stage tc of the last display frame T, the light emitting control signal Emit is at low level, which is effective level for the second transistor M22, so the second transistor M22 is turned on, and the second node voltage adjusting signal V2 can be written into the second node N2 through the second transistor M22; before the node voltage adjusting stage td, the data writing control signal SP has no low level pulse, and the first transistor M21 keeps off, so before the node voltage adjusting stage td, the second node N2 is written with only the second node voltage adjusting signal V2 and keeps it. In the node voltage adjusting stage td, i.e. the low level stage of the scanning signal SPX, the third transistor M23 is turned on, and the second node voltage adjusting signal V2 of the second node N2 is written into the first node N1.

[0114] Further, to ensure that the second node N2 can continuously keep the voltage state of the written node voltage adjusting signal, continuing to refer to Figure 7 、 Figure 8 、 Figure 10 and Figure 11 , the node voltage adjusting module 12 can further include a storage unit 120 connected between the fixed potential signal end and the second node N2; the storage unit 120 is used to store the first voltage adjusting signal V1 written by the first transistor M21 or the second voltage adjusting signal V2 written by the second transistor M22.

[0115] Specifically, the storage unit 120 includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected with the power supply signal end PVDD or PVEE, and a second plate of the first capacitor C1 is electrically connected with the second node N2.

[0116] Thus, when the first transistor M21 or the second transistor M22 is turned on, the node voltage adjustment signal written into the second node N2 can be stored through the first capacitor C2, so that the node voltage adjustment signal V of the second node N2 is written into the first node N1 when the third transistor M23 is turned on.

[0117] Figure 12 is a driving timing diagram of a second sub-region pixel circuit provided by the embodiment of the present application, referring to Figures 1-3 and Figure 12 The display panel of the embodiment of the present application can further include a second sub-region AA2, the first sub-region AA1 and the second sub-region AA2 do not overlap; the plurality of display frames T of the second sub-region AA2 are all refresh frames Trefresh; the node voltage adjustment module in the pixel circuit of the second sub-region is configured to: write the first voltage adjustment signal V1 into the first node N1 in the node voltage adjustment stage td of the refresh frame Trefresh.

[0118] The display panel is set as the first sub-region AA1 and the second sub-region AA2, and the driving process of the first sub-region AA1 includes the refresh frame Trefresh and the holding frame Thold, while the second sub-region AA2 only has the refresh frame Trefresh, which means that the display panel adopts the driving mode of dynamic sub-region refresh, that is, the first sub-region AA1 adopts low-frequency refresh driving display, and the second sub-region AA2 adopts high-frequency refresh driving display. As described above, since there is a difference between whether the refresh frame Trefresh and the holding frame Thold are provided with the data writing stage tb, the degree of the electrical characteristic curve drift of the driving transistor M1 will be different, and therefore, for the first sub-region AA1 provided with the holding frame Thold and the second sub-region AA2 not provided with the holding frame Thold, the degree of the electrical characteristic curve drift of the driving transistor M1 in the pixel circuit will also be different, and the display brightness of the two regions will be different, resulting in the brightness split-screen phenomenon. In the embodiment of the present application, the refresh frame Trefresh and the holding frame Thold of the first sub-region AA1 are respectively adjusted by the first voltage adjustment signal V1 and the second voltage adjustment signal V2, and the refresh frame Trefresh of the second sub-region AA2 is also adjusted by the first voltage adjustment signal V1, so that the drift of the characteristic curve of the driving transistor caused by the forward bias in the holding frame and the refresh frame can be compensated, or the difference between the voltage states of the first node in the refresh frame and the holding frame can be weakened or eliminated, thereby ensuring that the pixel circuits in all regions of the display panel have the same driving process, provide the same driving current, and achieve the same luminous brightness in the light-emitting stage, solving the problem that the luminous brightness of the light-emitting element is different between different sub-regions due to the different biasing time of the driving transistor, and the brightness split-screen phenomenon exists in the sub-regions, ensuring the display uniformity and improving the display quality.

[0119] Based on the same inventive concept, the embodiment of the present application also provides a display device. Figure 13 A structural schematic diagram of a display device provided by the embodiment of the present application is shown in FIG. 1. Figure 13 The display device comprises the display panel 1 provided by any of the embodiments of the present application, and thus the display device provided by the embodiment of the present application has the corresponding beneficial effects of the display panel provided by the embodiment of the present application, which will not be described herein. For example, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and the like, and the embodiment of the present application is not limited thereto.

[0120] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, Comprise: A pixel circuit and a light emitting element; The pixel circuit comprises a driving module and a node voltage adjusting module; The driving module is configured to provide a driving current for the light emitting element, and the driving module comprises a driving transistor; The pixel circuit further comprises a first node connected with the driving transistor or the light emitting element; and the node voltage adjusting module is connected with the first node; The picture display process of the display panel comprises a plurality of display frames, the display panel comprises a first sub-region, the plurality of display frames of the first sub-region comprise refresh frames and holding frames, and the refresh frames and the holding frames each comprise a node voltage adjusting stage; The node voltage adjusting module is configured to: write a first voltage adjusting signal to the first node in the node voltage adjusting stage of the refresh frame; write a second voltage adjusting signal to the first node in the node voltage adjusting stage of the holding frame; The first voltage adjusting signal and the second voltage adjusting signal are both used for adjusting the voltage state of the first node, and the voltage of the first voltage adjusting signal is different from the voltage of the second voltage adjusting signal.

2. The display panel of claim 1, wherein, The first end of the node voltage adjusting module is connected with a first voltage adjusting signal end and a second voltage adjusting signal end, and the first electrode of the driving transistor is connected with the second end of the node voltage adjusting module as the first node; The first voltage adjusting signal end receives the first voltage adjusting signal, and the second voltage adjusting signal end receives the second voltage adjusting signal; In the node voltage adjusting stage of the refresh frame, the node voltage adjusting module turns on the first voltage adjusting signal end and the first electrode of the driving transistor to write the first voltage adjusting signal to the first electrode of the driving transistor; In the node voltage adjusting stage of the holding frame, the node voltage adjusting module turns on the second voltage adjusting signal end and the first electrode of the driving transistor to write the second voltage adjusting signal to the first electrode of the driving transistor; The first voltage adjusting signal and the second voltage adjusting signal are both used for adjusting the voltage state of the driving transistor.

3. The display panel of claim 1, wherein, The first end of the node voltage adjusting module is connected with a first voltage adjusting signal end and a second voltage adjusting signal end, and the anode of the light emitting element is connected with the second end of the node voltage adjusting module as the first node; The first voltage adjusting signal end receives the first voltage adjusting signal, and the second voltage adjusting signal end receives the second voltage adjusting signal; In the node voltage adjusting stage of the refresh frame, the node voltage adjusting module turns on the first voltage adjusting signal end and the anode of the light emitting element to write the first voltage adjusting signal to the anode of the light emitting element; In the node voltage adjusting stage of the holding frame, the node voltage adjusting module turns on the second voltage adjusting signal end and the anode of the light emitting element to write the second voltage adjusting signal to the anode of the light emitting element; The first voltage adjustment signal and the second voltage adjustment signal are both used for resetting the potential of the anode of the light emitting element.

4. The display panel of claim 1, wherein, The node voltage adjustment module comprises a first transistor and a second transistor, the first ends of the first transistor and the second transistor are both connected to the first node, the second end of the first transistor is connected to the first voltage adjustment signal end, and the second end of the second transistor is connected to the second voltage adjustment signal end; The first transistor is configured to be turned on in the node voltage adjustment phase of the refresh frame; The second transistor is configured to be turned on in the node voltage adjustment phase of the holding frame.

5. The display panel of claim 4, wherein, The channel types of the first transistor and the second transistor are opposite, and the gates of the first transistor and the second transistor receive the same first voltage adjustment control signal.

6. The display panel of claim 5, wherein, The first transistor is a P-type channel transistor, and the second transistor is an N-type channel transistor; the first voltage adjustment control signal is configured as a first voltage V1_SW at least in the node voltage adjustment phase of the refresh frame; the first voltage adjustment control signal is configured as a second voltage V2_SW at least in the node voltage adjustment phase of the holding frame; wherein V1_SW The first transistor is an N-type channel transistor, and the second transistor is a P-type channel transistor; the first voltage adjustment control signal is configured as a first voltage V1_SW at least in the node voltage adjustment phase of the refresh frame; the first voltage adjustment control signal is configured as a second voltage V2_SW at least in the node voltage adjustment phase of the holding frame; wherein V1_SW 7. The display panel of claim 4, wherein, The node voltage adjustment module further comprises a third transistor, the first end of the third transistor is connected to the first ends of the first transistor and the second transistor, and the second end of the third transistor is connected to the first node; The third transistor is configured to be turned on in the node voltage adjustment phase of the refresh frame and the node voltage adjustment phase of the holding frame.

8. The display panel of claim 1, wherein, The node voltage adjustment module comprises a first transistor, a second transistor and a third transistor, the first ends of the first transistor and the second transistor are both connected to a second node, the second end of the first transistor is connected to the first voltage adjustment signal end, the second end of the second transistor is connected to the second voltage adjustment signal end, the first end of the third transistor is connected to the second node, and the second end of the third transistor is connected to the first node; The first transistor is configured to be turned on before the node voltage adjustment phase of the refresh frame to write the first voltage adjustment signal to the second node; The second transistor is configured to be turned on before the node voltage adjustment phase of the holding frame to write the second voltage adjustment signal to the second node; The third transistor is configured to be turned on in both the node voltage adjusting stage of the refresh frame and the node voltage adjusting stage of the holding frame, to write the first voltage adjusting signal stored by the second node into the first node in the node voltage adjusting stage of the refresh frame, and to write the second voltage adjusting signal stored by the second node into the first node in the node voltage adjusting stage of the holding frame.

9. The display panel of claim 8, wherein, The gate of the first transistor receives a second voltage adjusting control signal, and the gate of the second transistor receives a third voltage adjusting control signal, the second voltage adjusting control signal and the third voltage adjusting control signal being different.

10. The display panel of claim 9, wherein, The pixel circuit further comprises a data writing module, a compensation module, a gate reset module and a light emitting control module. The refresh frame further comprises a gate reset stage, a data writing stage and a light emitting stage, the data writing stage being located between the gate reset stage and the light emitting stage; the holding frame further comprises a light emitting stage. The data writing module is connected between a data signal terminal and the first electrode of the driving transistor, and is configured to write a data signal into the gate of the driving transistor in the data writing stage of the refresh frame under the control of a data writing control signal. The compensation module is connected between the gate and the second electrode of the driving transistor, and is configured to compensate the threshold voltage of the driving transistor in the data writing stage of the refresh frame under the control of a threshold compensation control signal. The gate reset module is connected between a gate reset signal terminal and the gate of the driving transistor, and is configured to reset the potential of the gate of the driving transistor in the gate reset stage of the refresh frame under the control of a gate reset control signal. The light emitting control module is connected to a first power signal terminal and a second power signal terminal with the driving module and the light emitting element, respectively, and is configured to control the light emitting element to emit light in the light emitting stage of the refresh frame and the light emitting stage of the holding frame under the control of a light emitting control signal. Any one of the gate reset control signal, the threshold compensation control signal and the data writing control signal is multiplexed as the second voltage adjusting control signal. The light emitting control signal is multiplexed as the third voltage adjusting control signal.

11. The display panel of claim 10, wherein, The channel types of the first transistor and the second transistor are opposite, and the gate reset control signal or the threshold compensation control signal is multiplexed as the second voltage adjusting control signal. Alternatively, the channel types of the first transistor and the second transistor are the same, and the data writing control signal is multiplexed as the second voltage adjusting control signal.

12. The display panel of claim 8, wherein, The node voltage adjusting module further comprises a storage unit connected between a fixed potential signal terminal and the second node. The storage unit is used to store the first voltage adjusting signal written by the first transistor or the second voltage adjusting signal written by the second transistor.

13. The display panel of claim 12, wherein, The storage unit comprises a first capacitor, a first electrode plate of the first capacitor being electrically connected to a power signal terminal, and a second electrode plate of the first capacitor being electrically connected to the second node.

14. The display panel of claim 1, wherein, The display panel further comprises a second sub-region, the first sub-region and the second sub-region do not overlap; The plurality of display frames of the second sub-region are all refresh frames; The node voltage adjustment module in the pixel circuit of the second sub-region is configured to: In the node voltage adjustment stage of the refresh frame, write the first voltage adjustment signal to the first node.

15. A driving method of a display panel, comprising: The display panel comprises a pixel circuit and a light emitting element; The pixel circuit comprises a driving module and a node voltage adjustment module; The driving module is configured to provide a driving current for the light emitting element, and the driving module comprises a driving transistor; The pixel circuit further comprises a first node connected with the driving transistor or the light emitting element, and the node voltage adjustment module is connected with the first node; The picture display process of the display panel comprises a plurality of display frames, and the display panel comprises a first sub-region, the plurality of display frames of the first sub-region comprise refresh frames and holding frames, and the refresh frames and the holding frames both comprise a node voltage adjustment stage; The driving method comprises: In the node voltage adjustment stage of the refresh frame, control the node voltage adjustment module to write a first voltage adjustment signal to the first node; In the node voltage adjustment stage of the holding frame, control the node voltage adjustment module to write a second voltage adjustment signal to the first node; The first voltage adjustment signal and the second voltage adjustment signal are both used for adjusting the voltage state of the first node, and the voltage of the first voltage adjustment signal is different from the voltage of the second voltage adjustment signal.

16. The driving method of claim 15, wherein: The node voltage adjustment module comprises a first transistor and a second transistor, the first ends of the first transistor and the second transistor are both connected with the first node, the second end of the first transistor is connected with the first voltage adjustment signal end, and the second end of the second transistor is connected with the second voltage adjustment signal end; In the node voltage adjustment stage of the refresh frame, controlling the node voltage adjustment module to write a first voltage adjustment signal to the first node comprises: Controlling the first transistor to be turned on in the node voltage adjustment stage of the refresh frame; In the node voltage adjustment stage of the holding frame, controlling the node voltage adjustment module to write a second voltage adjustment signal to the first node comprises: Controlling the second transistor to be turned on in the node voltage adjustment stage of the holding frame.

17. The driving method according to claim 15, wherein The node voltage adjustment module comprises a first transistor, a second transistor and a third transistor, the first ends of the first transistor and the second transistor are both connected with the second node, the second end of the first transistor is connected with the first voltage adjustment signal end, the second end of the second transistor is connected with the second voltage adjustment signal end, the first end of the third transistor is connected with the second node, and the second end of the third transistor is connected with the first node; In the node voltage adjusting stage of the refresh frame, the node voltage adjusting module is controlled to write a first voltage adjusting signal to the first node, comprising: the first transistor is controlled to be configured to be turned on before the node voltage adjusting stage of the refresh frame to write the first voltage adjusting signal to the second node; the third transistor is controlled to be turned on in the node voltage adjusting stage of the refresh frame to write the first voltage adjusting signal stored in the second node to the first node in the node voltage adjusting stage of the refresh frame; In the node voltage adjusting stage of the refresh frame, the node voltage adjusting module is controlled to write a first voltage adjusting signal to the first node, comprising: the second transistor is controlled to be turned on before the node voltage adjusting stage of the holding frame to write the second voltage adjusting signal to the second node; the third transistor is controlled to be turned on in the node voltage adjusting stage of the holding frame to write the second voltage adjusting signal stored in the second node to the first node in the node voltage adjusting stage of the holding frame.

18. A display device comprising: The display panel comprises any one of claims 1-14.

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