Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a level amplification circuit, and the level amplification circuit comprises: a first inverter configured to output a target voltage signal to a shift register circuit through an output end under the action of a first level signal to drive the shift register circuit, the first level signal being a level signal output by an output end of a driving circuit, the target voltage signal being a signal of a first reference voltage end or a signal of a second reference voltage end, and the first level signal being used for selecting a first input end to be turned on or a second input end to be turned on; a control end of the first inverter is electrically connected with the output end of the driving circuit, a first input end of the first inverter is electrically connected with the first reference voltage end, and a second input end of the first inverter is electrically connected with the second reference voltage end. The display panel can ensure high-voltage output of the shift register circuit while reducing the area of the driving circuit by adding a level amplification circuit in the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The OLED industry can be divided into three categories according to the panel demand voltage, namely low voltage, medium voltage and high voltage. The low voltage is below 1.8V, the medium voltage is below 7V, and the high voltage is below 32V. The low voltage is mainly used for digital operation in the driving circuit. The medium voltage is used to provide the related voltage for driving the pixels. The high voltage is used to provide the driving voltage for the shift register circuit.

[0003] Due to the characteristics of the panel device, only the shift register related circuit needs to be driven by the high voltage such as VGH / VGL, and other areas do not need to be driven. However, providing high voltage needs to make the line width and line spacing to be above 0.27um, that is, the high voltage process will relatively occupy a larger area, and has a certain influence on other processes, which increases the process difficulty and makes it difficult to implement the high voltage process. It is difficult to achieve a small overall area of the driving circuit. The larger panel device and circuit have a greater tolerance to the high voltage process, which greatly increases the difficulty of manufacturing the driving circuit. SUMMARY

[0004] The main purpose of the present application is to provide a display panel and a display device to at least solve the problem that the driving circuit needs to provide high voltage input to the shift register circuit, resulting in a large line area and high manufacturing difficulty.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a display panel is provided, which comprises a level amplification circuit, a shift register circuit and a driving circuit. The level amplification circuit comprises a first inverter for outputting a target voltage signal to the shift register circuit through an output end under the action of a first level signal to drive the shift register circuit. The first level signal is a level signal output by the output end of the driving circuit. The target voltage signal is a signal of a first reference voltage end or a signal of a second reference voltage end. The first level signal is used to select the conduction of the first input end or the second input end. The signal of the first reference voltage end is greater than the first level signal. The first inverter has a control end, a first input end, a second input end and an output end. The control end of the first inverter is electrically connected with the output end of the driving circuit. The first input end of the first inverter is electrically connected with the first reference voltage end. The second input end of the first inverter is electrically connected with the second reference voltage end. The output end of the first inverter is electrically connected with the input end of the shift register circuit.

[0006] According to another aspect of the present application, a display device is provided, which comprises any one of the display panels.

[0007] With the technical scheme of the present application, the display panel comprises a level amplification circuit, a shift register circuit and a driving circuit. The level amplification circuit comprises a first inverter. The first inverter is configured to output a target voltage signal to the shift register circuit through an output end under the action of a first level signal to drive the shift register circuit. The first level signal is a level signal output by an output end of the driving circuit. The target voltage signal is a signal of a first reference voltage end or a signal of a second reference voltage end. The first level signal is used to select the conduction of a first input end or the conduction of a second input end. The signal of the first reference voltage end is greater than the first level signal. A control end of the first inverter is electrically connected with the output end of the driving circuit. A first input end of the first inverter is electrically connected with the first reference voltage end. A second input end of the first inverter is electrically connected with the second reference voltage end. The output end of the first inverter is electrically connected with an input end of the shift register circuit. The display panel amplifies the first level signal to obtain the target voltage signal by adding the level amplification circuit in the display panel. The target voltage signal is used as the driving signal of the shift register circuit. The high-voltage output of the shift register circuit can be ensured while the area of the driving circuit is reduced. The problem that the line area is large and the manufacturing difficulty is high due to the need to provide high-voltage input for the shift register circuit in the existing driving circuit is solved. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which form a part of the present application, are used to provide further understanding of the present application, and serve as an explanation of the present application, and do not constitute improper limitations to the present application. In the drawings:

[0009] Figure 1 A structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0010] Figure 2 A structural schematic diagram of another display panel provided in an embodiment of the present application is shown;

[0011] Figure 3 A structural schematic diagram of another display panel provided in an embodiment of the present application is shown;

[0012] Figure 4 A structural schematic diagram of another display panel provided in an embodiment of the present application is shown;

[0013] Figure 5 A structural schematic diagram of another display panel provided in an embodiment of the present application is shown;

[0014] Figure 6 A structural schematic diagram of another display panel provided in an embodiment of the present application is shown;

[0015] Figure 7 Fig. 2 shows a structural schematic diagram of another display panel according to an embodiment of the present application;

[0016] Figure 8 Fig. 3 shows a structural schematic diagram of another display device according to an embodiment of the present application.

[0017] In the drawings, the following reference signs are used:

[0018] 100, level amplification circuit; 110, first inverter; 120, level conversion module; 121, second inverter; 122, first switch unit; 123, second switch unit; 124, first switch module; 125, second switch module; 126, third switch module; 127, fourth switch module; 200, shift register circuit; 300, drive circuit; 400, display panel; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor. DETAILED DESCRIPTION

[0019] It should be noted that the embodiments and features of the present application can be combined if there is no conflict. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work should be within the scope of protection of the present application.

[0020] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work should be within the scope of protection of the present application.

[0021] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, not necessarily to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and their any variations, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0022] For the convenience of description, the following describes some nouns or terms related to the embodiments of the present application:

[0023] Drive Integrated Circuit, abbreviated as Drive IC;

[0024] Video Shift Register, abbreviated as VER.

[0025] As introduced in the background, the OLED industry can be divided into two categories, low voltage, medium voltage and high voltage, according to the demand voltage of the panel. The low voltage is below 1.8V, which mainly performs digital operation in the IC. The medium voltage is about 7V below, which is used to provide pixel-related power. The high voltage is about 32V below, which is used to provide VSR circuit driving voltage.

[0026] Due to the characteristics of the panel device, only the VSR related circuit needs VGH / VGL high voltage power for driving, and other areas do not need it. The high voltage process of the IC requires higher requirements, and the process considering high voltage will greatly increase the difficulty of IC manufacturing. And the precision of wafer industry is getting higher and higher, high voltage process will relatively occupy larger area, and has certain influence on other processes, process difficulty increases, high voltage process is not easy to realize.

[0027] To solve the problem that the existing driving circuit needs to provide high voltage input to the shift register circuit, resulting in a large line area and high manufacturing difficulty, the embodiments of the present application provide a display panel and a display device.

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. It should be noted that the embodiments in the present application are for better explanation of the present application, but do not limit the present application.

[0029] It should be noted that in the specific implementation, the first end of the transistor can be used as the source of the transistor and the second end as the drain of the transistor according to the type of the transistor and the signal of the gate of the transistor; or vice versa, the first end of the transistor is used as the drain of the transistor and the second end is used as the source of the transistor, which is not specifically distinguished here.

[0030] It should be noted that generally, transistors are divided into N-type transistors and P-type transistors. Among them, the N-type transistor is turned on under the control of the high level signal and is turned off under the control of the low level signal; the P-type transistor is turned on under the control of the low level signal and is turned off under the control of the high level signal.

[0031] The display panel provided by the embodiments of the present application is like Figure 1As shown in the above display panel, the display panel comprises a level amplification circuit 100, a shift register circuit 200 and a driving circuit 300, the level amplification circuit 100 comprises:

[0032] a first inverter 110, configured to output a target voltage signal to the shift register circuit 200 through an output end under the action of a first level signal to drive the shift register circuit 200, the first level signal being a level signal output by an output end of the driving circuit 300, the target voltage signal being a signal of a first reference voltage end VGH or a signal of a second reference voltage end VGL, the first level signal being used to select the first input end to be turned on or the second input end to be turned on, and the signal of the first reference voltage end VGH being greater than the first level signal;

[0033] The first inverter 110 has a control end, a first input end, a second input end and an output end, the control end of the first inverter 110 is electrically connected with the output end of the driving circuit 300, the first input end of the first inverter 110 is electrically connected with the first reference voltage end VGH, the second input end of the first inverter 110 is electrically connected with the second reference voltage end VGL, and the output end of the first inverter 110 is electrically connected with an input end of the shift register circuit 200.

[0034] The display panel comprises a level amplification circuit, a shift register circuit and a driving circuit, the level amplification circuit comprises a first inverter, configured to output a target voltage signal to the shift register circuit through an output end under the action of a first level signal to drive the shift register circuit, the first level signal being a level signal output by an output end of the driving circuit, the target voltage signal being a signal of a first reference voltage end or a signal of a second reference voltage end, the first level signal being used to select the first input end to be turned on or the second input end to be turned on, and the signal of the first reference voltage end being greater than the first level signal; the control end of the first inverter is electrically connected with the output end of the driving circuit, the first input end of the first inverter is electrically connected with the first reference voltage end, the second input end of the first inverter is electrically connected with the second reference voltage end, and the output end of the first inverter is electrically connected with an input end of the shift register circuit. The display panel increases a level amplification circuit in the display panel, amplifies the first level signal to obtain the target voltage signal, and takes the target voltage signal as a driving signal of the shift register circuit, so that the high-voltage output of the shift register circuit can be ensured while the area of the driving circuit is reduced, and the problem that a high-voltage input needs to be provided for the shift register circuit in the existing driving circuit, resulting in a large line area and high manufacturing difficulty, is solved.

[0035] The above embodiment can convert a lower level driving signal into a higher voltage output, and reduce the process difficulty of the driving circuit.

[0036] In the embodiment, when the first level signal is at low level, the first input end of the first inverter is turned on, the target voltage signal is the signal of the first reference voltage end, and the absolute value of the voltage of the signal of the first reference voltage end is greater than the absolute value of the voltage of the first level signal. For example, when the first level signal is -1V and the signal of the first reference voltage end is 2V, the first input end of the first inverter is turned on, the target voltage signal is 2V, and the target voltage signal is amplified to 2V through the reverse amplification of the first inverter, that is, the high voltage control of the driving signal of the shift register circuit can be ensured through one level amplification circuit.

[0037] Optionally, as shown in Figure 2 The first inverter 110 further includes:

[0038] The first transistor T1 has its control end electrically connected to the output end of the driving circuit 300, its first end electrically connected to the first reference voltage end VGH, and its second end electrically connected to the voltage output end.

[0039] The second transistor T2 has its control end electrically connected to the output end of the driving circuit 300, its first end electrically connected to the second reference voltage end VGL, and its second end electrically connected to the voltage output end.

[0040] In the embodiment, the first level signal output by the output end of the driving circuit is used to control the turn-on or turn-off of the first transistor T1 and the second transistor T2. When the first level signal controls the first transistor T1 to be turned on and the second transistor T2 to be turned off, the signal of the first reference voltage end VGH can be transmitted to the output end of the first inverter 110, that is, the target voltage signal output by the output end of the first inverter 110 is the signal of the first reference voltage end VGH. When the first level signal controls the first transistor T1 to be turned off and the second transistor T2 to be turned on, the signal of the second reference voltage end VGL can be transmitted to the output end of the first inverter 110, that is, the target voltage signal output by the output end of the first inverter 110 is the signal of the second reference voltage end VGL.

[0041] Optionally, as shown in Figure 2 The first transistor T1 and the second transistor T2 are one of NMOS and the other is PMOS.

[0042] In the present example, one of the first transistor T1 and the second transistor T2 is NMOS, and the other is PMOS, so that the first level signal can only control one transistor to be turned on, and the other transistor to be turned off, that is, the signal of one of the first reference voltage terminal VGH and the second reference voltage terminal VGL is transmitted to the shift register circuit through the output terminal of the first inverter.

[0043] In the present example, as shown in Figure 2 , the first transistor T1 is PMOS, and the second transistor T2 is NMOS. When the first level signal is low, the first transistor T1 is turned on, and the second transistor T2 is turned off. The target voltage signal is the signal of the first reference voltage terminal VGH, and the absolute value of the signal of the first reference voltage terminal VGH is greater than the absolute value of the first level signal, so as to realize the effect of reverse amplification of the signal. When the first level signal is high, the first transistor T1 is turned off, and the second transistor T2 is turned on. The target voltage signal is the signal of the second reference voltage terminal VGL, and the absolute value of the signal of the second reference voltage terminal VGL is greater than the absolute value of the first level signal, so as to realize the effect of reverse amplification of the signal.

[0044] Optionally, as shown in Figure 3 , the level amplification circuit 100 further comprises:

[0045] a level conversion module 120, the input terminal of the level conversion module 120 is electrically connected with the output terminal of the driving circuit 300, the output terminal of the level conversion module 120 is electrically connected with the input terminal of the first inverter 110, and the level conversion module 120 is used to convert the first level signal into an intermediate level signal, so that the first inverter 110 outputs the target voltage signal to the shift register circuit 200 through the voltage output terminal under the action of the intermediate level signal.

[0046] In the present example, the level conversion module is used to provide the intermediate level signal to the first inverter under the control of the first level signal. The first level signal is first amplified once by the level conversion module, and then amplified twice by the first inverter, so that the amplification multiple is higher, and the high voltage demand of the shift register circuit can be better met.

[0047] For example, when the first level signal is 1V, the first level signal will be converted into an intermediate level signal of -2V under the action of the level conversion module, and the intermediate level signal will be converted into a target voltage signal of 4V under the action of the first inverter, that is, the target voltage signal is positively amplified by 4 times compared with the first level signal, the amplification multiple is higher, and the high voltage demand of the shift register circuit can be better met.

[0048] Optionally, as shown in Figure 4As shown, the level conversion module 120 also includes:

[0049] The second inverter 121 has a control terminal, a first input terminal, a second input terminal, and an output terminal. The control terminal of the second inverter 121 is electrically connected to the output terminal of the drive circuit 300. The first input terminal of the second inverter 121 is connected to the power signal terminal AVDD. The second input terminal of the second inverter 121 is grounded.

[0050] The first switching unit 122 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the first switching unit 122 is electrically connected to the output terminal of the driving circuit 300. The second terminal of the first switching unit 122 is electrically connected to the second reference voltage terminal VGL. The third terminal of the first switching unit 122 is electrically connected to the output terminal of the second inverter 121. The fourth terminal of the first switching unit 122 is connected to the input terminal of the first inverter 110 at the first node N. The fifth terminal of the first switching unit 122 is connected to the second node M.

[0051] The second switching unit 123 has a first terminal, a second terminal and a third terminal. The first terminal of the second switching unit 123 is connected to the first reference voltage terminal VGH, the second terminal of the second switching unit 123 is connected to the first node N, and the third terminal of the second switching unit 123 is connected to the second node M.

[0052] In this example, the second inverter, under the control of the first level signal, provides either the power supply signal terminal AVDD or the ground signal from the second input terminal to the first switching unit. The first switching unit, under the control of the signal provided by the second inverter, provides the signal from the second reference voltage terminal VGL to the first node N and the second node M. The second switching unit, under the control of the second node M, provides the signal from the first reference voltage terminal VGH to the first node N. The first inverter, under the control of the first node N, provides either the signal from the first reference voltage terminal VGH or the signal from the second reference voltage terminal VGL to the shift register circuit to meet the high-voltage requirements of the shift register circuit.

[0053] Optional, such as Figure 5 As shown, the second inverter 121 includes:

[0054] The third transistor T3 has its control terminal electrically connected to the output terminal of the drive circuit 300, its first terminal connected to the power signal terminal AVDD, and its second terminal electrically connected to the third terminal of the first switching unit 122.

[0055] The fourth transistor T4 has a control terminal electrically connected to the output terminal of the driving circuit 300, a first terminal grounded, and a second terminal electrically connected to the third terminal of the first switch unit 122.

[0056] In the present example, the first level signal is used to control the on or off of the third transistor T3 and the fourth transistor T4. When the first level signal controls the third transistor T3 to be on and the fourth transistor T4 to be off, the signal of the power signal terminal AVDD can be transmitted to the first switch unit; when the first level signal controls the third transistor T3 to be off and the fourth transistor T4 to be on, the signal of the ground terminal can be transmitted to the first switch unit.

[0057] Optionally, as shown in Figure 6 The first switch unit 122 includes:

[0058] The first switch module 124 is used to be off when the first level signal is low, and transmit the signal of the second reference voltage terminal VGL to the first node N when the first level signal is high.

[0059] The second switch module 125 is used to be off when the signal output by the output terminal of the second inverter 121 is low, and transmit the signal of the second reference voltage terminal VGL to the second node M when the signal output by the output terminal of the second inverter 121 is high.

[0060] In the present example, the first switch module is used to transmit the signal of the second reference voltage terminal VGL to the first node N under the control of the first level signal; and the second switch module is used to transmit the signal of the second reference voltage terminal VGL to the second node M under the control of the signal output by the output terminal of the second inverter 121.

[0061] Optionally, as shown in Figure 6 The second switch unit 123 includes:

[0062] The third switch module 126 is used to be off when the signal of the second node M is high, and transmit the signal of the first reference voltage terminal VGH to the first node N when the signal of the second node M is low.

[0063] The fourth switch module 127 is used to be off when the signal of the first node N is high, and transmit the signal of the first reference voltage terminal VGH to the second node M when the signal of the first node N is low.

[0064] In the present example, the third switch module is configured to transmit the signal of the first reference voltage terminal VGH to the first node N under the control of the signal of the second node M; and the fourth switch module is configured to transmit the signal of the first reference voltage terminal VGH to the second node M under the control of the signal of the first node N.

[0065] Optionally, as shown in Figure 7 The first switch module 124 includes a fifth transistor T5, a control terminal of the fifth transistor T5 is electrically connected with an output terminal of the driving circuit 300, a first terminal of the fifth transistor T5 is connected with the first node N, and a second terminal of the fifth transistor T5 is connected with the second reference voltage terminal VGL.

[0066] The second switch module 125 includes a sixth transistor T6, a control terminal of the sixth transistor T6 is electrically connected with an output terminal of the second inverter 121, a first terminal of the sixth transistor T6 is connected with the second node M, and a second terminal of the sixth transistor T6 is connected with the second reference voltage terminal VGL.

[0067] In the present example, the first level signal is configured to control the conduction or the cutoff of the fifth transistor T5, and the signal output by the output terminal of the second inverter is configured to control the conduction or the cutoff of the sixth transistor T6. In the case that the fifth transistor T5 is conducted, the signal of the second reference voltage terminal VGL can be transmitted to the first node N, and in the case that the sixth transistor T6 is conducted, the signal of the second reference voltage terminal VGL can be transmitted to the second node M.

[0068] Optionally, as shown in Figure 7 The third switch module 126 includes a seventh transistor T7, a control terminal of the seventh transistor T7 is electrically connected with the second node M, a first terminal of the seventh transistor T7 is connected with the first reference voltage terminal VGH, and a second terminal of the seventh transistor T7 is electrically connected with the first node N.

[0069] The fourth switch module 127 includes an eighth transistor T8, a control terminal of the eighth transistor T8 is electrically connected with the first node N, a first terminal of the eighth transistor T8 is connected with the first reference voltage terminal VGH, and a second terminal of the eighth transistor T8 is electrically connected with the second node M.

[0070] In the present example, the signal of the second node M is configured to control the conduction or the cutoff of the seventh transistor T7, and the signal of the first node N is configured to control the conduction or the cutoff of the eighth transistor T8. In the case that the seventh transistor T7 is conducted, the signal of the first reference voltage terminal VGH can be transmitted to the first node N, and in the case that the eighth transistor T8 is conducted, the signal of the first reference voltage terminal VGH can be transmitted to the second node M.

[0071] That is, the first node N and the second node M are in the interlocking state.

[0072] Optionally, as shown in Figure 7 The fifth transistor T5 and the sixth transistor T6 are both NMOS.

[0073] In this example, when the first level signal is low, the fifth transistor T5 is off, the signal output by the first level signal after being reversed by the second inverter is high, the sixth transistor T6 is on, and the signal of the second reference voltage terminal VGL can be transmitted to the second node M through the sixth transistor T6; when the first level signal is high, the fifth transistor T5 is on, the signal of the second reference voltage terminal VGL can be transmitted to the first node N through the fifth transistor T5, the signal output by the first level signal after being reversed by the second inverter is low, and the sixth transistor T6 is off.

[0074] Optionally, the first switch module 124 includes a first double-gate transistor, and the second switch module 125 includes a second double-gate transistor.

[0075] In this example, the structure of the double-gate transistor can provide higher gain, so that the signal amplification effect is better, and the double-gate transistor can reduce the generation of noise and improve the clarity and stability of the signal.

[0076] Optionally, as shown in Figure 7 The seventh transistor T7 and the eighth transistor T8 are PMOS.

[0077] In this example, when the second node M is low, the seventh transistor T7 is on, and the signal of the first reference voltage terminal VGH can be transmitted to the first node N through the seventh transistor T7; when the second node M is high, the seventh transistor T7 is off; when the first node N is low, the eighth transistor T8 is on, and the signal of the first reference voltage terminal VGH can be transmitted to the second node M through the eighth transistor T8; when the first node N is high, the eighth transistor T8 is off.

[0078] Optionally, the third switch module 126 includes a third double-gate transistor, and the fourth switch module 127 includes a fourth double-gate transistor.

[0079] In this example, the structure of the double-gate transistor can provide higher gain, so that the signal amplification effect is better, and the double-gate transistor can reduce the generation of noise and improve the clarity and stability of the signal.

[0080] Embodiment 1

[0081] As shown in Figure 7As shown, the first level signal output by the driving circuit 300 is high. The fifth transistor T5 is turned on under the control of the first level signal. The signal of the second reference voltage terminal VGL can be transmitted to the first node N through the fifth transistor T5. That is, the signal of the first node N is low at this time. The second inverter outputs the ground signal to the sixth transistor T6 under the control of the first level signal. The sixth transistor T6 is turned off under the control of the ground signal. The eighth transistor T8 is turned on under the control of the signal of the first node N. The signal of the first reference voltage terminal VGH can be transmitted to the second node M through the eighth transistor T8. That is, the signal of the second node M is high at this time. The seventh transistor T7 is turned off under the control of the signal of the second node M. The first inverter outputs the signal of the first reference voltage terminal VGH to the shift register circuit under the control of the signal of the first node N. That is, the target voltage signal is the signal of the first reference voltage terminal VGH. The signal of the first reference voltage terminal VGH is a signal higher than the first level signal.

[0082] Example 2

[0083] like Figure 7 As shown, the first level signal output by the driving circuit 300 is low. The fifth transistor T5 is cut off under the control of the first level signal. The second inverter outputs the power supply signal AVDD to the sixth transistor T6 under the control of the first level signal. The sixth transistor T6 is turned on under the control of the power supply signal AVDD. The signal of the second reference voltage terminal VGL can be transmitted to the second node M through the sixth transistor T6. That is, the signal of the second node M is low at this time. The seventh transistor T7 is turned on under the control of the signal of the second node M. The signal of the first reference voltage terminal VGH can be transmitted to the first node N through the seventh transistor T7. That is, the signal of the first node N is high at this time. The eighth transistor T8 is cut off under the control of the signal of the first node N. The first inverter outputs the signal of the second reference voltage terminal VGL to the shift register circuit under the control of the signal of the first node N. That is, the target voltage signal is the signal of the second reference voltage terminal VGL. The signal of the second reference voltage terminal VGL is a signal lower than the first level signal.

[0084] In the above embodiments, only the medium-voltage and low-voltage circuits are retained inside the IC, and the high-voltage process is eliminated. The gate signal output terminal of the driving circuit uses medium voltage for output, and the high and low levels are provided by the power supply signal terminals AVDD and -AVDD. In addition to the original power input, the display panel adds two voltage inputs, the first reference voltage terminal VGH and the second reference voltage terminal VGL, to provide driving voltage for the shift register circuit VSR. At the IC Gout output terminal of the display panel, level amplification circuits are added to achieve high-level output.

[0085] In the above embodiment, the IC cancels the high-voltage process related circuit design, and the level conversion action is realized by the level amplification circuit to increase the additional value of the panel, the panel increases the level conversion circuit (level amplification circuit), and the medium voltage to high level switching action is realized on the panel; in addition, two voltage inputs of the first reference voltage end VGH and the second reference voltage end VGL are added, the driving IC can get rid of the high-voltage process limitation, reduce the process difficulty, reduce the size of the driving circuit, improve the battery efficiency, and realize low-cost manufacturing.

[0086] In some embodiments, the battery efficiency can be improved from 80% to more than 90%, the driving circuit adopts the chargepump architecture, and the PMIC adopts the buck and boost circuit architecture.

[0087] Based on the same inventive concept, the application further provides a display device, as shown in Figure 8 The display panel 400.

[0088] The display panel provided by the embodiment of the application can amplify the first level signal to obtain a target voltage signal by adding a level amplification circuit in the display panel, and the target voltage signal is used as a driving signal of the shift register circuit, so that the high-voltage output of the shift register circuit can be ensured while the area of the driving circuit is reduced, and the problem that the shift register circuit needs to be provided with a high-voltage input in the existing driving circuit, resulting in a large line area and high manufacturing difficulty, is solved.

[0089] The above only describes the preferred embodiments of the application and is not used to limit the application, and the application can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A display panel, characterized by, The display panel comprises a level amplification circuit, a shift register circuit and a driving circuit, and the level amplification circuit comprises: a first inverter for outputting a target voltage signal to the shift register circuit through an output end under the action of a first level signal to drive the shift register circuit, the first level signal being a level signal output by an output end of the driving circuit, the target voltage signal being a signal of a first reference voltage end or a signal of a second reference voltage end, the first level signal being used to select a first input end to be turned on or a second input end to be turned on, the signal of the first reference voltage end being greater than the first level signal; wherein the first inverter has a control end, a first input end, a second input end and an output end, the control end of the first inverter being electrically connected with the output end of the driving circuit, the first input end of the first inverter being electrically connected with the first reference voltage end, the second input end of the first inverter being electrically connected with the second reference voltage end, and the output end of the first inverter being electrically connected with an input end of the shift register circuit; The level amplification circuit further comprises: a level conversion module, an input end of the level conversion module being electrically connected with an output end of the driving circuit, an output end of the level conversion module being electrically connected with an input end of the first inverter, and the level conversion module being used to convert the first level signal into an intermediate level signal, so that the first inverter outputs the target voltage signal to the shift register circuit through a voltage output end under the action of the intermediate level signal; The level conversion module further comprises: a second inverter having a control end, a first input end, a second input end and an output end, the control end of the second inverter being electrically connected with the output end of the driving circuit, the first input end of the second inverter being connected with a power supply signal end, and the second input end of the second inverter being grounded; a first switch unit having a first end, a second end, a third end, a fourth end and a fifth end, the first end of the first switch unit being electrically connected with the output end of the driving circuit, the second end of the first switch unit being electrically connected with the second reference voltage end, the third end of the first switch unit being electrically connected with the output end of the second inverter, the fourth end of the first switch unit being connected with the input end of the first inverter at a first node, and the fifth end of the first switch unit being connected with a second node; a second switch unit having a first end, a second end and a third end, the first end of the second switch unit being connected with the first reference voltage end, the second end of the second switch unit being connected with the first node, and the third end of the second switch unit being connected with the second node.

2. The display panel of claim 1, wherein, The first inverter further comprises: a first transistor, a control end of the first transistor being electrically connected with the output end of the driving circuit, a first end of the first transistor being electrically connected with the first reference voltage end, and a second end of the first transistor being electrically connected with the voltage output end; A second transistor, a control terminal of the second transistor being electrically connected with an output terminal of the driving circuit, a first terminal of the second transistor being electrically connected with the second reference voltage terminal, and a second terminal of the second transistor being electrically connected with the voltage output terminal.

3. The display panel of claim 2, wherein, One of the first transistor and the second transistor is an NMOS, and the other is a PMOS.

4. The display panel of claim 1, wherein, The second inverter comprises: A third transistor, a control terminal of the third transistor being electrically connected with the output terminal of the driving circuit, a first terminal of the third transistor being electrically connected with the power signal terminal, and a second terminal of the third transistor being electrically connected with the third terminal of the first switch unit; A fourth transistor, a control terminal of the fourth transistor being electrically connected with the output terminal of the driving circuit, a first terminal of the fourth transistor being grounded, and a second terminal of the fourth transistor being electrically connected with the third terminal of the first switch unit.

5. The display panel of claim 1, wherein, The first switch unit comprises: A first switch module, configured to be turned off when the first level signal is at a low level, and configured to transmit a signal of the second reference voltage terminal to the first node when the first level signal is at a high level; A second switch module, configured to be turned off when a signal output by the output terminal of the second inverter is at a low level, and configured to transmit the signal of the second reference voltage terminal to the second node when the signal output by the output terminal of the second inverter is at a high level.

6. The display panel of claim 5, wherein The first switch module comprises a fifth transistor, a control terminal of the fifth transistor being electrically connected with the output terminal of the driving circuit, a first terminal of the fifth transistor being electrically connected with the first node, and a second terminal of the fifth transistor being electrically connected with the second reference voltage terminal; The second switch module comprises a sixth transistor, a control terminal of the sixth transistor being electrically connected with the output terminal of the second inverter, a first terminal of the sixth transistor being electrically connected with the second node, and a second terminal of the sixth transistor being electrically connected with the second reference voltage terminal.

7. The display panel of claim 6, wherein, The fifth transistor and the sixth transistor are both NMOS.

8. The display panel of claim 5, wherein, The first switch module comprises a first double-gate transistor, and the second switch module comprises a second double-gate transistor.

9. The display panel of claim 1, wherein, The second switch unit comprises: A third switch module, configured to be turned off when a signal of the second node is at a high level, and configured to transmit a signal of the first reference voltage terminal to the first node when the signal of the second node is at a low level; A fourth switch module, configured to be turned off when a signal of the first node is at a high level, and configured to transmit the signal of the first reference voltage terminal to the second node when the signal of the first node is at a low level.

10. The display panel of claim 9, wherein The third switch module comprises a seventh transistor, a control terminal of the seventh transistor being electrically connected with the second node, a first terminal of the seventh transistor being electrically connected with the first reference voltage terminal, and a second terminal of the seventh transistor being electrically connected with the first node. The fourth switch module includes an eighth transistor, a control end of the eighth transistor is electrically connected with the first node, a first end of the eighth transistor is connected with the first reference voltage end, and a second end of the eighth transistor is electrically connected with the second node.

11. The display panel of claim 10, wherein, The seventh transistor and the eighth transistor are PMOS.

12. The display panel of claim 9, wherein, The third switch module includes a third double-gate transistor, and the fourth switch module includes a fourth double-gate transistor.

13. A display device comprising: The display panel includes any one of claims 1 to 12.

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