Memory and its operation methods

Abstract

This disclosure provides a memory and its operation method. The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and word lines. The peripheral circuitry is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, so that target memory cells coupled to the selected word lines and selected bit lines are in a conducting state, and non-target memory cells coupled to unselected word lines and / or unselected bit lines are in a non-conducting state.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and for example to a memory and a method of operating the same. Background Technology

[0002] Semiconductor memories can be roughly divided into two categories, depending on whether they retain stored data when power is off: volatile memory and non-volatile memory. Volatile memory loses stored data when power is off, while non-volatile memory retains stored data when power is off.

[0003] Phase-change memory (PCM), as a new type of non-volatile memory, has significant advantages over flash memory in many aspects, such as read / write speed, read / write cycles, data retention time, cell area, and multi-value implementation. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuitry is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, such that a target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state.

[0005] In some alternative embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution, and the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0006] In some alternative embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than the absolute value of the second voltage.

[0007] In some alternative embodiments, the difference between the first voltage and the power supply voltage is a first value, and the difference between the ground voltage and the second voltage is a second value, wherein both the first value and the second value are less than the minimum value of the first threshold voltage distribution.

[0008] In some alternative embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

[0009] In some alternative embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

[0010] In some alternative embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0011] In some alternative embodiments, the peripheral circuit is configured to perform a set operation or a reset operation on the target memory cell based on the target memory cell being in a conducting state.

[0012] In some alternative embodiments, the storage unit includes a phase-change storage unit; the phase-change storage unit includes a phase-change element and a gating element connected in series with the phase-change element.

[0013] According to a second aspect of the present disclosure, a method for operating a memory is provided, the method comprising: in response to a write command, applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a ground voltage to an unselected word line, and applying a power supply voltage to the unselected bit line, such that a target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state.

[0014] In this embodiment, by applying a first voltage to the selected word line and a second voltage to the selected bit line, the target memory cell is put into a conducting state. A ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line, further putting the non-target memory cell coupled to the unselected word line and / or unselected bit line into a non-conducting state. The solution of this embodiment, firstly, employs a dual-rail power supply, applying voltage to both the selected word line and the selected bit line simultaneously. This improves upon the single-rail power supply solution, which requires high-voltage technology, consumes a large amount of power, and causes high voltage to accelerate threshold voltage drift of stored data in non-target memory cells. Secondly, by applying the first voltage and the second voltage to the selected word line and the selected bit line coupled to the target memory cell respectively, the problem of requiring high-voltage technology and consuming a large amount of power, which is caused by applying only a high voltage to the selected word line or the selected bit line, is avoided. Thirdly, a ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line. The power supply voltage is applied to the midline to compensate for the voltage of the unselected word line and the unselected bit line, thereby keeping the non-target memory cell in a non-conductive state and preventing the data in the non-target memory cell from being accidentally opened and overwritten. Fourthly, the ground voltage applied to the unselected word line and the power supply voltage applied to the unselected bit line can be provided by the existing logic circuit power supply in the memory, without adding any additional voltage. This avoids the problem of adding too many voltage sources in the memory and the complex power supply wiring in the memory cell array caused by adding additional voltage, which can save memory area and cost. Attached Figure Description

[0015] Figure 1 A schematic diagram of the structure of an exemplary system provided in this disclosure embodiment;

[0016] Figure 2 A schematic diagram of a memory structure including a memory cell array and peripheral circuitry is provided for an embodiment of this disclosure;

[0017] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of this disclosure. Figure 1 ;

[0018] Figure 4 A schematic diagram of the structure of a storage unit provided in an embodiment of this disclosure. Figure 2 ;

[0019] Figure 5 The diagram shows the pulses used to perform set and reset operations on the phase-change memory cell.

[0020] Figure 6 A schematic diagram of the threshold voltage distribution of a memory cell in a memory provided in an embodiment of this disclosure;

[0021] Figure 7 A schematic diagram illustrating the relationship between the threshold voltage distribution and the applied voltage provided in embodiments of this disclosure. Figure 1 ;

[0022] Figure 8 A schematic diagram illustrating the voltage application conditions of each memory cell provided in an embodiment of this disclosure;

[0023] Figure 9 A schematic diagram illustrating the relationship between the threshold voltage distribution and the applied voltage provided in embodiments of this disclosure. Figure 2 . Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0027] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] like Figure 1 As shown in the illustration, this disclosure presents an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory 34 therein. The host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The memory system 30 includes a memory controller 32 and memory 34 coupled to the memory controller 32.

[0030] For example, the memory controller 32 can communicate with an external host through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, ONFI, DDR, LPDDR, etc.

[0031] The memory includes an array of memory cells and peripheral circuitry coupled to the array, wherein the array of memory cells may include a plurality of memory cells. The array of memory cells may be integrated on the same die as the peripheral circuitry, allowing for wider buses and higher operating speeds. In some embodiments, the array of memory cells and the peripheral circuitry may be formed in different regions on the same plane; or the array of memory cells and the peripheral circuitry may be formed in a stacked structure, i.e., they are formed on different planes.

[0032] Figure 2 A schematic diagram of a memory structure including a memory cell array and peripheral circuitry is shown. Figure 2 As shown, the memory 304 includes a memory cell array 401 and peripheral circuitry 402 coupled to the memory cell array 401. The memory cell array 401 may include a plurality of memory cells 4013 arranged in rows and columns. The plurality of memory cells 4013 arranged in rows are coupled to the same word line (WL) 4011, and the plurality of memory cells arranged in columns are coupled to the same bit line (BL) 4012.

[0033] In this disclosure, the memory includes, but is not limited to, various memory types such as phase-change memory (PCM) and selector-only memory (SOM). It should be understood that this disclosure is not limited thereto. In some embodiments, the memory cell is a phase-change memory cell, such as... Figure 3As shown, the phase-change memory cell 130 includes a gating element 110 and a phase-change element 120 connected in series. In some embodiments, the memory cell is a selectable memory cell, such as... Figure 4 As shown, only the storage cell 140 is selected, including the gating element 110.

[0034] The following explanation uses phase-change memory (PCM) as an example. The basic storage principle of PCM involves applying voltage or current pulse signals of varying widths and heights to the PCM cells. This causes a change in the physical phase state of the phase-change material within the PCM cell's phase-change element. For example, it enables reversible interconversion between a crystalline (low-resistance) and amorphous (high-resistance) state, thereby storing data. The memory cells in crystalline and amorphous states have different threshold voltages, with the crystalline state (defined as 1) having a lower threshold voltage and the amorphous state (defined as 0) having a higher threshold voltage. Operations that complete the crystalline transition of a memory cell are defined as set operations, and operations that complete the amorphous transition are defined as reset operations.

[0035] In some embodiments, in order to realize the phase change material in the phase change memory switching between crystalline and amorphous states, different pulses (e.g., optical pulses, electrical pulses) can be used to control the heating of the phase change material. Figure 5 The diagram illustrates the pulses used to perform set and reset operations on the phase-change memory cell. (Example:) Figure 5 As shown, the set operation includes: applying a long and moderately strong set pulse to raise the temperature of the phase change material in the phase change memory cell to below the melting temperature Tm and above the crystallization temperature Tx, maintaining this temperature for a period of time and promoting crystal nucleus growth, thereby achieving the conversion of the phase change material in the phase change memory cell from an amorphous state (corresponding to a high-resistivity state) to a crystalline state (corresponding to a low-resistivity state). The reset operation includes: applying a short and strong reset pulse to raise the temperature of the phase change material in the phase change memory cell to above the melting temperature Tm, followed by rapid cooling, thereby achieving the conversion of the phase change material in the phase change memory cell from a crystalline state to an amorphous state. The set and reset processes are reversible, thus the phase change memory cell can use the crystalline state to represent the unit binary data "1" and the amorphous state to represent the binary data "0".

[0036] Figure 6 This is a schematic diagram of the threshold voltage distribution of a memory cell in an embodiment of the present disclosure. Figure 6 As shown, multiple memory cells in the memory have a set state (crystalline state) and a reset state (amorphous state). Memory cells with a set state correspond to a first threshold voltage distribution, and memory cells with a reset state correspond to a second threshold voltage distribution. The minimum voltage of the second threshold voltage distribution is greater than the maximum voltage of the first threshold voltage distribution.

[0037] To perform a write operation, that is, to complete the above set or reset operation, such as Figure 7 As shown, a voltage higher than the maximum voltage of the threshold voltage distribution (second threshold voltage distribution) corresponding to the memory cell in the reset state needs to be applied across the target memory cell to ensure that the target memory cell is in the conducting state. This voltage, Vwrite, which is higher than the maximum voltage of the threshold voltage distribution corresponding to the memory cell in the reset state, is generally quite high.

[0038] In some embodiments, a higher Vwrite is applied to the selected word line or selected bit line coupled to the target memory cell via a single-rail power supply. Non-target memory cells on the common selected word line or common selected bit line in the memory cell array will also be subjected to a higher voltage. This higher voltage will accelerate the threshold voltage drift of the stored data in the non-target memory cells, potentially causing errors when reading data from these non-target memory cells. Furthermore, the single-rail power supply solution requires high-voltage processing and has relatively high power consumption.

[0039] This disclosure provides a memory including a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines. The peripheral circuitry is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a power supply voltage to an unselected bit line, such that a target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state.

[0040] Figure 8 This is a schematic diagram illustrating the voltage application conditions of each memory cell provided in an embodiment of this disclosure. For example... Figure 8 As shown, a first voltage (VH) is applied to the selected word line, a second voltage (VN) is applied to the selected bit line, a ground voltage (VSS) is applied to the unselected word line, and a power supply voltage (VDD) is applied to the unselected bit line. The target memory cell is cell0.

[0041] In this embodiment, by applying a first voltage to the selected word line and a second voltage to the selected bit line, the target memory cell is put into a conducting state. A ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line, further putting the non-target memory cell coupled to the unselected word line and / or unselected bit line into a non-conducting state. The solution of this embodiment, firstly, employs a dual-rail power supply, applying voltage to both the selected word line and the selected bit line simultaneously. This improves upon the single-rail power supply solution, which requires high-voltage technology, consumes a large amount of power, and causes high voltage to accelerate threshold voltage drift of stored data in non-target memory cells. Secondly, by applying the first voltage and the second voltage to the selected word line and the selected bit line coupled to the target memory cell respectively, the problem of requiring high-voltage technology and consuming a large amount of power, which is caused by applying only a high voltage to the selected word line or the selected bit line, is avoided. Thirdly, a ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line. The power supply voltage is applied to the midline to compensate for the voltage of the unselected word line and the unselected bit line, thereby keeping the non-target memory cell in a non-conductive state and preventing the data in the non-target memory cell from being accidentally opened and overwritten. Fourthly, the ground voltage applied to the unselected word line and the power supply voltage applied to the unselected bit line can be provided by the existing logic circuit power supply in the memory, without adding any additional voltage. This avoids the problem of adding too many voltage sources in the memory and the complex power supply wiring in the memory cell array caused by adding additional voltage, which can save memory area and cost.

[0042] In some embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution, and the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0043] In this embodiment, a first voltage is applied to the selected word line and a second voltage is applied to the selected bit line. The first voltage is greater than 0, and the second voltage is less than 0. That is, a positive voltage is applied to the selected word line, and a negative voltage is applied to the selected bit line. The voltage across the target memory cell is the difference between the first voltage and the second voltage. This difference is greater than the maximum value of the second threshold voltage distribution. In other words, the voltage across the target memory cell is greater than the maximum threshold voltage of the memory cell. This ensures that the target memory cell is in a conducting state regardless of whether it is in a set or reset state, or regardless of whether the threshold voltage of the target memory cell is high or low.

[0044] Figure 9This diagram illustrates the relationship between the threshold voltage distribution and the applied voltage, as provided in embodiments of this disclosure. Figure 8 as well as Figure 9 As shown, non-target memory cells can be divided into three types based on the voltage across them: First, non-target memory cell cell1, which is coupled to the selected word line and the unselected bit line, with a voltage of (VH-VDD); second, non-target memory cell cell2, which is coupled to the unselected word line and the selected bit line, with a voltage of (VSS-VN); and third, non-target memory cell cell3, which is coupled to the unselected word line and the unselected bit line, with a voltage of (VSS-VDD). Additionally, the voltage across the target memory cell cell0 is (VH-VN), where (VH-VN) equals Vwrite.

[0045] In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than the absolute value of the second voltage.

[0046] In this embodiment, the first voltage is greater than the absolute value of the second voltage, and an asymmetrical voltage application method is used for the selected word line and the selected bit line. This allows the voltage (VSS-VN) across the non-target memory cell cell2 to be less than Vwrite / 2. Figure 7 As shown, Vwrite / 2 here is greater than the minimum voltage of the first threshold voltage distribution and less than the maximum voltage of the first threshold voltage distribution.

[0047] In some embodiments, the difference between the first voltage and the power supply voltage is a first value, and the difference between the ground voltage and the second voltage is a second value, wherein both the first value and the second value are less than the minimum value of the first threshold voltage distribution.

[0048] Here, the first value is (VH-VDD) and the second value is (VSS-VN). Both the first and second values ​​are less than the minimum value of the first threshold voltage distribution, so that when the target memory cell cell0 is in the conducting state, the non-target memory cell cell1 and the non-target memory cell cell2 will not be accidentally turned on.

[0049] In this embodiment, the voltage across the non-target memory cell 3 is (VSS-VDD), which is less than the minimum value of the first threshold voltage distribution. While the target memory cell 0 is in the conducting state, the non-target memory cell 3 will not be accidentally turned on.

[0050] In some embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

[0051] In this embodiment, the absolute value of the difference between the first value and the second value is small, meaning the first value and the second value are close. This makes the voltage across different non-target memory cells more balanced, significantly improving the bias drift phenomenon. Here, bias drift can be understood as the phenomenon where applying voltage to the selected word line and selected bit line causes a shift in the threshold voltage of the non-target memory cell coupled to the selected word line or selected bit line.

[0052] In some embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

[0053] It is understandable that when the absolute value of the difference between the first and second values ​​is equal to 0, the first and second values ​​are equal. In this case, the voltage across different non-target memory cells can be more balanced, thus maximizing the improvement of bias drift. Furthermore, when the absolute value of the difference between the first and second values ​​is equal to 0, compared to the binary search method (applying Vwrite / 2 to the selected word line and -Vwrite / 2 to the selected bit line), the above embodiment can reduce the voltage across non-target memory cell cell1 and non-target memory cell cell2 by VDD / 2.

[0054] In some embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0055] It should be noted that the ranges of the first voltage, the second voltage, and the power supply voltage given in the above embodiments are merely examples and are not intended to limit the ranges of the first voltage, the second voltage, and the power supply voltage in the embodiments of this disclosure. In some specific examples, corresponding adjustments can be made according to actual needs.

[0056] In some embodiments, the peripheral circuit is configured as follows:

[0057] Based on the fact that the target storage cell is in the on state, a set operation or a reset operation is performed on the target storage cell.

[0058] In this embodiment of the disclosure, after the target storage cell is put into a conducting state in response to the write command, a set operation or a reset operation is performed on the target storage cell to realize writing "0" or writing "1".

[0059] In some embodiments, the storage unit includes a phase-change storage unit; the phase-change storage unit includes a phase-change element and a gating element connected in series with the phase-change element.

[0060] In some specific examples, the phase change element may include chalcogenide components, such as binary compounds like GaSb, InSb, InSe, SbTe, and GeTe; ternary compounds like GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe; and quaternary compounds like AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS. The gating element may include a material with bidirectional threshold switch (OTS) properties. Materials with OTS properties may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as ZnxTey, GexTey, NbxOy, and SixAsyTez.

[0061] In this embodiment, the power supply voltage and ground voltage applied to the unselected word lines and unselected bit lines are commonly used voltages in memory. The VDD and VSS provided by existing general-purpose logic circuit power supplies are used to reduce the voltage across non-target memory cells coupled to the selected word lines and / or selected bit lines. This eliminates the risk of falsely opening non-target memory cells coupled to the selected word lines and / or selected bit lines due to excessively low threshold voltage, and also reduces bias drift. Furthermore, since charging and discharging all unselected bit lines requires significant power consumption, if an internal additional voltage source is used to charge the unselected bit lines, the required voltage source... It has a large load capacity, so it requires a large chip area, and the interconnects that power the memory cell array also require a large current capacity, thus requiring a wide power path, which may further increase the area of ​​the memory cell array. However, directly using the existing logic power supply VDD and VSS effectively avoids these problems. The logic power supply VDD and VSS are the most frequently used voltages in the chip, so the power paths of VDD and VSS in the memory cell array are already sufficient to support the charging and discharging of the unselected bit lines. Therefore, no additional traces or additional chip area are needed.

[0062] Based on the above-described memory, this disclosure also provides a memory system, the memory system including the memory described in any of the above embodiments and a memory controller coupled to the memory, the memory controller being configured to control the memory.

[0063] Based on the above-described memory, this disclosure also provides a memory operation method, the operation method comprising: in response to a write command, applying a first voltage to a selected word line, applying a second voltage to a selected bit line, applying a ground voltage to an unselected word line, and applying a power supply voltage to the unselected bit line, so that a target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and a non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state.

[0064] In some embodiments, a plurality of memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution, and the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

[0065] In some embodiments, the first voltage is greater than 0, the second voltage is less than 0, and the first voltage is greater than the absolute value of the second voltage.

[0066] In some embodiments, the difference between the first voltage and the power supply voltage is a first value, and the difference between the ground voltage and the second voltage is a second value, wherein both the first value and the second value are less than the minimum value of the first threshold voltage distribution.

[0067] In some embodiments, the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

[0068] In some embodiments, the absolute value of the difference between the first value and the second value is equal to 0.

[0069] In some embodiments, the first voltage ranges from 4V to 5V, the second voltage ranges from -4V to -3V, and the power supply voltage ranges from 1.1V to 1.2V.

[0070] In some embodiments, the operation method further includes: performing a set operation or a reset operation on the target storage cell based on the target storage cell being in a conducting state.

[0071] In some embodiments, the storage unit includes a phase-change storage unit; the phase-change storage unit includes a phase-change element and a gating element connected in series with the phase-change element.

[0072] The specific details of the memory operation method have been described in detail in the aforementioned memory section, and will not be repeated here for the sake of brevity.

[0073] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0074] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0075] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple bit lines, multiple word lines, and multiple memory cells located between the multiple bit lines and the multiple word lines; the peripheral circuitry is configured as follows: In response to a write command, a dual-rail power supply is used to simultaneously apply voltage to the selected word line and the selected bit line. A first voltage is applied to the selected word line, a second voltage is applied to the selected bit line, a ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line. This ensures that the target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and that the non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state. The second voltage ranges from -4V to -3V. The difference between the first voltage and the power supply voltage is a first value, and the difference between the ground voltage and the second voltage is a second value; the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

2. The memory according to claim 1, characterized in that, The multiple memory cells in the memory cell array are configured to have a set state and a reset state; the set state corresponds to a first threshold voltage distribution, the reset state corresponds to a second threshold voltage distribution, the minimum value of the second threshold voltage distribution is greater than the maximum value of the first threshold voltage distribution; the difference between the first voltage and the second voltage is greater than the maximum value of the second threshold voltage distribution.

3. The memory according to claim 2, characterized in that, The first voltage is greater than 0, the second voltage is less than 0, and the absolute value of the first voltage is greater than that of the second voltage.

4. The memory according to claim 2, characterized in that, Both the first value and the second value are less than the minimum value of the first threshold voltage distribution.

5. The memory according to claim 1, characterized in that, The absolute value of the difference between the first value and the second value is equal to 0.

6. The memory according to claim 1, characterized in that, The first voltage ranges from 4V to 5V, and the power supply voltage ranges from 1.1V to 1.2V.

7. The memory according to claim 1, characterized in that, The peripheral circuit is configured as follows: Based on the fact that the target storage cell is in the on state, a set operation or a reset operation is performed on the target storage cell.

8. The memory according to claim 1, characterized in that, The storage unit includes a phase-change storage unit; the phase-change storage unit includes a phase-change element and a gating element connected in series with the phase-change element.

9. A method for operating a memory, characterized in that, The operation method includes: In response to a write command, a dual-rail power supply is used to simultaneously apply voltage to the selected word line and the selected bit line. A first voltage is applied to the selected word line, a second voltage is applied to the selected bit line, a ground voltage is applied to the unselected word line, and a power supply voltage is applied to the unselected bit line. This ensures that the target memory cell coupled to the selected word line and the selected bit line is in a conducting state, and that the non-target memory cell coupled to the unselected word line and / or the unselected bit line is in a non-conducting state. The second voltage ranges from -4V to -3V. The difference between the first voltage and the power supply voltage is a first value, and the difference between the ground voltage and the second voltage is a second value; the absolute value of the difference between the first value and the second value is less than or equal to 0.2V.

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