Test structure, system and method

Abstract

The present disclosure relates to a test structure, system and method, the test structure comprising a wafer and a plurality of test pads; wherein the wafer comprises a plurality of chips to be tested arranged in an array along a first direction and a second direction, a cutting lane being arranged between any two chips to be tested adjacent along the first direction and between any two chips to be tested adjacent along the second direction, the two chips to be tested adjacent along the second direction being mutually centrosymmetric; wherein each chip to be tested comprises a plurality of chip pads arranged along the first direction, the chip pads being arranged on a side of the chip to be tested close to the cutting lane along the second direction; the plurality of test pads are arranged corresponding to the chip pads, in the cutting lane between any two chip pads adjacent along the second direction; wherein the same test pad and the chip pad adjacent to the same test pad along the second direction are electrically connected and have equal channel length, the first direction and the second direction intersecting. The above structure can improve test efficiency, improve chip capacity, ensure test stability and reduce test cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a test structure, system and method. Background Technology

[0002] In semiconductor manufacturing, wafers undergo probe testing after production to verify their quality. This involves using probe cards to connect to the test pads of each chip on the wafer, forming test paths for testing. The number and placement of the test pads are a crucial part of chip design, affecting the maximum number of simultaneous tests and consequently the cost and efficiency of the entire testing process.

[0003] With the development of semiconductor technology and the shrinking of process nodes, the test pads in general wafer probe testing occupy a large space and result in a smaller number of chips being tested simultaneously, which reduces the yield and efficiency of wafer testing. Summary of the Invention

[0004] Based on this, the present disclosure provides a test structure, system and method that can save the space occupied by test pads, increase the maximum number of simultaneous tests in the wafer testing process, and ensure the stability and accuracy of the testing process, thereby improving the product yield.

[0005] According to various embodiments of this disclosure, one aspect provides a test structure including a wafer and a plurality of test pads; wherein the wafer includes chips under test (DUTs) arranged in an array along a first direction and a second direction, and dicing channels are provided between two adjacent DUTs along the first direction and between two adjacent DUTs along the second direction, and the two adjacent DUTs along the second direction are centrally symmetrical to each other; wherein the DUTs include a plurality of chip pads arranged along the first direction, and the chip pads are disposed on the side of the DUTs along the second direction near the dicing channels; the plurality of test pads are correspondingly disposed with the chip pads and located in the dicing channels between adjacent chip pads along the second direction; wherein the same test pad and the chip pads adjacent to it along the second direction are electrically connected and have equal channel lengths, and the first direction and the second direction intersect.

[0006] In the test structure described above, by placing multiple test pads within the dicing channels between adjacent chip pads along the second direction and corresponding to the chip pads, at least two chips under test (DUTs) can be tested simultaneously based on a single test pad. This increases the number of simultaneous tests, thereby improving test efficiency. It also saves space within the DUTs reserved for testing, increasing their capacity. Furthermore, the reduced number of test pads lowers testing costs, reducing both the cost of the testing equipment and the testing process. Since the two adjacent DUTs along the second direction are centrally symmetrical, the channel length is equal when testing multiple DUTs with a single test pad, ensuring equal signal transmission paths and guaranteeing consistent and stable test results, thus improving test accuracy. This test structure addresses the problems of low simultaneous test count, high testing costs, and low testing efficiency associated with directly testing chip pads in related technologies. Additionally, the large number of pads used in related technologies reduces the success rate of probe card design and lowers test accuracy. This disclosure improves wafer probe testing yield and efficiency by placing test pads within the dicing channel, enabling one test pad to electrically connect at least two chips under test simultaneously. Furthermore, it sets two adjacent chips under test along the second direction to be mutually centrally symmetrical, reducing the wiring differences from the test pads to different chips and ensuring the consistency of signals and power supply.

[0007] In some embodiments, the same test pad and the adjacent chip pad along the second direction are connected by wires of equal length along the second direction.

[0008] In some embodiments, there are two chips under test adjacent to the same test pad along the second direction, namely a first chip and a second chip. The first chip and the second chip share a set of test pads. The chip pads of the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad, and a first ground pad arranged in sequence along the first direction. The chip pads of the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad, and a second ground pad arranged in sequence along the first direction.

[0009] In some embodiments, each set of test pads includes a first test pad, a second test pad, a third test pad, a fourth test pad, a fifth test pad, a sixth test pad, and a seventh test pad; wherein, the first test pad is electrically connected to the first ground pad and the second ground pad of the second chip; the second test pad is electrically connected to the first voltage pad and the second voltage pad of the second chip; the third test pad is electrically connected to the power pad of the second chip; the fourth test pad is electrically connected to the address pad of the second chip and the address pad of the first chip; the fifth test pad is electrically connected to the power pad of the first chip; the sixth test pad is electrically connected to the second voltage pad of the second chip and the first voltage pad of the first chip; and the seventh test pad is electrically connected to the second ground pad of the second chip and the first ground pad of the first chip.

[0010] In some embodiments, the address pads include a plurality of address sub-pads arranged along a first direction, each address sub-pad having an address number.

[0011] In some embodiments, the address numbers of the address sub-pads of the first chip and the address numbers of the address sub-pads of the second chip are centrally symmetrical to each other.

[0012] In some embodiments, each set of test pads further includes a signal exchange pad located between the second and third test pads adjacent along the first direction, and between the fifth and sixth test pads adjacent along the first direction, for changing the address sequence number of each address sub-pad of the first chip and the address sequence number of each address sub-pad of the second chip from central symmetry to mirror symmetry when the first electrical signal is received.

[0013] In some embodiments, there are four chips under test adjacent to the test pads along the second direction and the first direction, namely the first chip, the second chip, the third chip and the fourth chip, which share a set of test pads.

[0014] Another aspect of this disclosure provides a test system, including the test structure described in any one of the embodiments of this disclosure and a plurality of probe cards, each probe card being electrically connected to a group of test pads.

[0015] In the test system described above, the probe card is connected to the test pads, and one test pad can be connected to at least two chip pads. This allows one probe card to test at least two chips under test (DUTs), increasing the number of simultaneous tests on the wafer, saving probe card costs and space. Furthermore, the reduced number of test pads ensures a certain distance between adjacent probe cards, preventing them from squeezing each other and further improving test stability. This test system addresses the problems of low simultaneous test count, high test cost, low test efficiency, and probe card design failures associated with directly testing chip pads in related technologies. This disclosure, by placing the test pads within the dicing channel, allows one test pad to simultaneously electrically connect to at least two DUTs, meaning one probe card can test at least two DUTs simultaneously. The two adjacent DUTs along the second direction are set to be mutually centrosymmetrical, reducing wiring differences from the test pads to different DUTs and ensuring signal and power supply consistency. This improves the yield and efficiency of wafer probe testing and reduces test costs.

[0016] In some embodiments, two probe cards connected to two sets of test pads adjacent to each other along the first direction are located on opposite sides of the test pads along the second direction.

[0017] In some embodiments, each probe card includes a circuit board and a plurality of probes disposed on the same side of the circuit board, and the probes in each probe card correspond one-to-one with each set of test pads.

[0018] Another aspect of this disclosure provides a testing method for testing the test structure described in any one of the embodiments of this disclosure. The method includes: providing a test structure and probe cards; electrically connecting each probe card to each group of test pads; providing a first electrical signal to the test pads electrically connected to the probe cards to test the chip under test electrically connected to the test pads; and providing a second electrical signal to the test pads electrically connected to the probe cards to terminate the test.

[0019] In the testing method described in the above embodiments, a first electrical signal is provided to the test pads electrically connected to the probe card to test at least two chips under test (DUTs) electrically connected to the test pads. Furthermore, the same test pad and its adjacent chip pads along a second direction are electrically connected with equal channel lengths, ensuring no testing differences between the same test pad and different DUTs, thus improving testing accuracy and yield. This testing method addresses the problems in related technologies where a large number of test pads leads to smaller DUT capacity, slower testing progress, and lower testing yield. It can increase the number of DUTs tested simultaneously while improving testing stability and consistency, thereby simultaneously improving testing yield and efficiency, and reducing testing costs.

[0020] In some embodiments, electrically connecting each probe card to each set of test pads includes: electrically connecting each probe card to each set of test pads, such that two probe cards connected to two sets of test pads adjacent along a first direction are located on opposite sides of the test pads along a second direction.

[0021] In some embodiments, the first electrical signal is greater than the second electrical signal.

[0022] In some embodiments, there are two chips under test adjacent to the same test pad along the second direction, namely a first chip and a second chip, which share a set of test pads. The chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad, and a first ground pad arranged sequentially along the first direction. The chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad, and a second ground pad arranged sequentially along the first direction. Providing a first electrical signal to the test pads electrically connected to it based on the probe card includes: providing a first electrical signal to the test pads electrically connected to it based on the probe card, so that the address sequence numbers of each address sub-pad of the first chip and the address sequence numbers of each address sub-pad of the second chip are changed from central symmetry to mirror symmetry. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 The diagram shown is a cross-sectional schematic of a test structure in a related art provided in an embodiment of this disclosure.

[0025] Figure 2 The diagram shown is a cross-sectional schematic of a test system in a related art provided in an embodiment of this disclosure.

[0026] Figure 3 The diagram shown is a cross-sectional schematic of a test system in a related art provided by another embodiment of this disclosure;

[0027] Figure 4 The diagram shown is a cross-sectional schematic of a test structure provided in an embodiment of this disclosure.

[0028] Figure 5 The diagram shown is a cross-sectional schematic of a test structure provided in another embodiment of this disclosure;

[0029] Figure 6 The diagram shown is a cross-sectional schematic of a test structure provided in yet another embodiment of this disclosure.

[0030] Figure 7 The diagram shown is a cross-sectional schematic of a test structure provided in yet another embodiment of this disclosure.

[0031] Figure 8 The diagram shown is a cross-sectional schematic of a test structure provided in another embodiment of this disclosure;

[0032] Figure 9 The diagram shown is a cross-sectional schematic of a test system provided in an embodiment of this disclosure.

[0033] Figure 10 The diagram shown is a cross-sectional schematic of a test system provided in another embodiment of this disclosure;

[0034] Figure 11 The diagram shown is a flowchart illustrating a testing method provided in an embodiment of this disclosure.

[0035] Explanation of reference numerals in the attached figures:

[0036] 10 / 20, Wafer; 101, Chip; 1011, Pad; 11 / 21, Probe Card; 111 / 211, Circuit Board; 112 / 212, Probe; 201, Chip Under Test; 201a, First Chip; 201b, Second Chip; 201c, Third Chip; 201d, Fourth Chip; 2011, Chip Pad; 20111, First Ground Pad; 20112, First Voltage Pad; 20113, Power Pad; 201 14. Address pad; 20115. Second voltage pad; 20116. Second ground pad; 202. Cut track; 2021. Test pad; 20211. First test pad; 20212. Second test pad; 20213. Third test pad; 20214. Fourth test pad; 20215. Fifth test pad; 20216. Sixth test pad; 20217. Seventh test pad; 20218. Signal switching pad. Detailed Implementation

[0037] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0039] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0043] In semiconductor manufacturing, wafers undergo probe testing after production to verify their quality. This is achieved by a testing machine emitting test signals, which are then connected to test pads on each chip via probe cards to form a test path. The number and placement of these test pads are crucial aspects of chip design, directly impacting the placement of chips within the wafer, the maximum number of simultaneous tests, and the overall cost of the testing process. However, the number of test pads is limited by testing resources, testing methods, and the design and manufacturing of probe cards. Furthermore, after the wafer is packaged into chip particles, the test pads still need to test each particle to form the subsequent finished product test path.

[0044] However, with the development of semiconductor technology and the shrinking of process nodes, the design of test pads in the current testing of High Bandwidth Memory (HBM) chips still follows the common design method, which is to place the test pads inside each chip. However, because HBM chips have Through Silicon Via (TSV) structures, chip stacking is completed through TSVs. Therefore, the test pads of the wafer in HBM chips do not need to be reused in the package. If the test pads are set to test multiple chips at the same time, wiring differences will occur, which will affect the signal and power supply. This will cause different chips on the same wafer to have different test conditions. For example, wiring differences will cause delays, resulting in a decrease in the accuracy of test results and a decrease in test yield.

[0045] It should be noted that, in the embodiments of this disclosure, the first direction can be the ox direction in the accompanying drawings, and the second direction can be the oy direction in the accompanying drawings.

[0046] Please see Figure 1 , Figure 2 and Figure 3 In the test structure adopted by the relevant technologies, Figure 1 The wafer 10 shown includes multiple chips 101 arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oy direction), and each chip 101 has pads 1011. Please refer to [link / reference]. Figure 2 When performing probe testing on wafer 10, probe cards 11 are connected to pads 1011 to test chip 101. One probe card 11 corresponds to one chip 101. Please refer to [link / reference]. Figure 3The probe card 11 includes a circuit board 111 and probes 112. Since each chip 101 needs to be connected to the probe card 11, the circuit board 111 occupies a large space. The miniaturization technology of the probe card 11 has not yet reached the point where its size is smaller than that of the chip 101. The width of the circuit board 111 along the first direction (e.g., the ox direction) is even greater than the width of the chip 101 along the first direction (e.g., the ox direction). Therefore, it is impossible to test all chips 101 on a wafer 10 simultaneously. Only batch testing of chips at intervals is possible, resulting in a significant increase in testing time. Furthermore, in general wafer probe testing, the pads 1011 occupy a large space, and the number of chips tested simultaneously is small, reducing the yield and efficiency of wafer testing.

[0047] To address the aforementioned technical issues, this disclosure provides a test structure, system, and method that can save space occupied by test pads, increase the maximum number of simultaneous tests during wafer testing, ensure the stability and accuracy of the testing process, and thereby improve product yield.

[0048] For example, please refer to Figure 4 and Figure 5 One aspect of this disclosure provides a test structure, including a wafer 20 and a plurality of test pads 2021; wherein, the wafer 20 includes test chips 201 arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oy direction), wherein dicing channels 202 are provided between two adjacent test chips 201 along the first direction (e.g., the ox direction) and between two adjacent test chips 201 along the second direction (e.g., the oy direction), and two adjacent test chips 201 along the second direction (e.g., the oy direction) are centrally symmetrical to each other; wherein, the test chip 201 includes a plurality of test pads 2021 arranged along the first direction (e.g., the ox direction) and a second direction (e.g., the oy direction). Chip pads 2011 are arranged in the ox direction and are disposed on the side of the chip under test 201 along the second direction (e.g., the oy direction) near the dicing channel 202. Multiple test pads 2021 are disposed corresponding to the chip pads 2011 and are located in the dicing channel 202 between adjacent chip pads 2011 along the second direction (e.g., the oy direction). The same test pad 2021 and the chip pads 2011 adjacent to it along the second direction (e.g., the oy direction) are electrically connected and have the same channel length. The first direction (e.g., the ox direction) intersects with the second direction (e.g., the oy direction).

[0049] In the test structure described above, by placing multiple test pads 2021 within the cut-through channels 202 between adjacent chip pads 2011 along the second direction (e.g., the oy direction) and corresponding to the chip pads 2011, at least two chips under test (DUTs) 201 can be tested simultaneously based on one test pad 2021. This increases the number of simultaneous tests, thereby improving test efficiency. It also saves space within the DUTs 201 reserved for testing, increasing the capacity of the DUTs 201. Furthermore, the reduced number of test pads 2021 lowers test costs, reducing both the cost of the test equipment and the test process. Since two adjacent DUTs 201 along the second direction (e.g., the oy direction) are centrally symmetrical, the channel length is equal when testing multiple DUTs 201 with one test pad 2021, meaning the signal transmission path is of equal length. This ensures the consistency and stability of test results and improves test accuracy. The aforementioned test structure addresses the issues of low test count, high testing cost, and low testing efficiency associated with directly testing chip pads 2011 in related technologies. Furthermore, the large number of pads used in related technologies reduces the success rate of probe card design and lowers test accuracy. This disclosure, by placing the test pads 2021 within the dicing channel 202, allows one test pad 2021 to simultaneously electrically connect to at least two chips under test (DUTs) 201. Adjacent DUTs 201 along a second direction (e.g., the oy direction) are set to be mutually centrosymmetrical, reducing wiring differences from the test pads 2021 to different chips and ensuring signal and power supply consistency. This improves the yield and efficiency of wafer 20 probe testing, providing further assurance for improving wafer 20 quality.

[0050] As an example, please continue reading Figure 4 and Figure 5 Since the two adjacent chips under test 201 along the second direction (e.g., the oy direction) are centrally symmetrical, the structures in the two chips under test 201 are also centrally symmetrical. That is, the chip pads 2011 and circuit structures in the two chips under test 201 are symmetrical to each other, so as to ensure the stability and consistency of power supply during testing, eliminate the test differences between different chips under test 201 in the same wafer 20, and improve the test yield.

[0051] As an example, please continue reading Figure 4 and Figure 5 The same test pad 2021 corresponds to two adjacent chip pads 2011, meaning that a set of test pads 2021 can test two chips under test 201 at the same time. Compared with related technologies where a set of test pads 2021 can only test one set of chips, this improves testing efficiency.

[0052] For example, please refer to Figure 6The same test pad 2021 and the adjacent chip pad 2011 along the second direction (e.g., the oy direction) are connected by wires, and the length of the wires along the second direction (e.g., the oy direction) is equal, which ensures that the signal transmission path is of equal length, eliminates the test differences between different chips, and ensures the accuracy of the test.

[0053] As an example, please continue reading Figure 5 and Figure 6 There are two chips 201 to be tested adjacent to the same test pad 2021 along the second direction (e.g., the oy direction), namely the first chip 201a and the second chip 201b. The first chip 201a and the second chip 201b share a set of test pads 2021. The chip pads 2011 in the second chip 201b include a first ground pad 20111, a first voltage pad 20112, a power pad 20113, an address pad 20114, a second voltage pad 20115, and a second ground pad 20116 arranged sequentially along the first direction (e.g., the ox direction). The chip pads 2011 in the first chip 201a include a second ground pad 20116, a second voltage pad 20115, an address pad 20114, a power pad 20113, a first voltage pad 20112, and a first ground pad 20111 arranged sequentially along the first direction (e.g., the ox direction).

[0054] As an example, please continue reading Figure 6 The first ground pad 20111 can be abbreviated as VSS (VoltageSource) pad; the first voltage pad 20112 can be abbreviated as VDD (VoltageDrain) pad; the power pad 20113 can be abbreviated as TDQ (Test dataqueues) pad, where TDQA represents the power pad 20113 in the first chip 201a and TDQB represents the power pad 20113 in the second chip 201b; the address pad 20114 can be abbreviated as ADD (Address) pad; the second voltage pad 20115 can be abbreviated as VDD pad; and the second ground pad 20116 can be abbreviated as VSS pad.

[0055] As an example, please continue reading Figure 6Each test pad group 2021 includes a first test pad 20211, a second test pad 20212, a third test pad 20213, a fourth test pad 20214, a fifth test pad 20215, a sixth test pad 20216, and a seventh test pad 20217. The first test pad 20211 is electrically connected to the first ground pad 20111 of the second chip 201b and the second ground pad 20116 of the first chip 201a. The second test pad 20212 is electrically connected to the first voltage pad 20112 of the second chip 201b and the second voltage pad 20115 of the first chip 201a. The third test pad 2021... Test pad 20214 is electrically connected to the power pad 20113 of the second chip 201b; test pad 20214 is electrically connected to the address pad 20114 of the second chip 201b and the address pad 20114 of the first chip 201a; test pad 20215 is electrically connected to the power pad 20113 of the first chip 201a; test pad 20216 is electrically connected to the second voltage pad 20115 of the second chip 201b and the first voltage pad 20112 of the first chip 201a; test pad 20217 is electrically connected to the second ground pad 20116 of the second chip 201b and the first ground pad 20111 of the first chip 201a.

[0056] As an example, please continue reading Figure 6 The first test pad 20211 can be abbreviated as VSS pad, which is used to ground the first ground pad 20111 of the second chip 201b and the second ground pad 20116 of the first chip 201a.

[0057] As an example, please continue reading Figure 6 The second test pad 20212 can be abbreviated as VDD pad, which is used to provide electrical signals to the first voltage pad 20112 of the second chip 201b and the second voltage pad 20115 of the first chip 201a, so as to test the voltage pads of different chips under test 201.

[0058] As an example, please continue reading Figure 6 The third test pad 20213 can be abbreviated as TDQB pad, which is used to provide an enable electrical signal for the power pad 20113 of the second chip 201b.

[0059] As an example, please continue reading Figure 6 The fourth test pad 20214, abbreviated as ADD pad, is used to provide electrical signals to the address pads 20114 of the second chip 201b and the first chip 201a for testing the address pads 20114. These electrical signals include both high-level and low-level signals.

[0060] As an example, please continue reading Figure 6 The fifth test pad 20215 can be abbreviated as TDQA pad, which is used to provide an enable electrical signal for the power pad 20113 of the first chip 201a.

[0061] As an example, please continue reading Figure 6 The sixth test pad 20216 can be abbreviated as VDD pad, which is used to provide electrical signals to the second voltage pad 20115 of the second chip 201b and the first voltage pad 20112 of the first chip 201a, so as to test the voltage pads of different chips under test 201.

[0062] As an example, please continue reading Figure 6 The seventh test pad 20217 can be abbreviated as VSS pad, which is used to ground the second ground pad 20116 of the second chip 201b and the first ground pad 20111 of the first chip 201a.

[0063] As an example, please continue reading Figure 6 Address pad 20114 includes multiple address sub-pads arranged along a first direction (e.g., the ox direction), and each address sub-pad has an address number. The number of address sub-pads is N+1, where N is an integer greater than or equal to 1, and the address numbers of the address sub-pads are arranged in descending or ascending order along the first direction (e.g., the ox direction).

[0064] As an example, please continue reading Figure 6 The fourth test pad 20214 includes multiple fourth sub-test pads, the number and position of which correspond to the number and position of the address sub-pads in the first chip 201a and the second chip 201b, respectively, so as to perform signal testing on the address sub-pads.

[0065] As an example, please continue reading Figure 6 The address numbers of the address sub-pads of the first chip 201a and the address numbers of the address sub-pads of the second chip 201b are centrally symmetrical. Specifically, the address numbers of the address sub-pads of the first chip 201a are arranged in ascending order along a first direction (e.g., the ox direction), and the address numbers of the address sub-pads of the second chip 201b are arranged in descending order along the first direction (e.g., the ox direction). For example, the address numbers of the address sub-pads of the first chip 201a are 0, 1, ..., N along the first direction (e.g., the ox direction), and the address numbers of the address sub-pads of the second chip 201b are N, ..., 1, 0 along the first direction (e.g., the ox direction).

[0066] As an example, please continue reading Figure 6Each set of test pads 2021 also includes a signal exchange pad 20218, which is located between the second test pad 20212 and the third test pad 20213 adjacent along the first direction (e.g., the ox direction), and between the fifth test pad 20215 and the sixth test pad 20216 adjacent along the first direction (e.g., the ox direction). When the first electrical signal is received, the address sequence number of each address sub-pad of the first chip 201a and the address sequence number of each address sub-pad of the second chip 201b changes from central symmetry to mirror symmetry.

[0067] The aforementioned signal exchange pad 20218 can be abbreviated as WP (Wafer Probing) pad. The signal exchange pad 20218 controlling the first chip 201a can be abbreviated as WPA pad, and the signal exchange pad 20218 controlling the second chip 201b can be abbreviated as WPB pad. Since the first chip 201a and the second chip 201b are centrally symmetrical, the position of their address pads 20114 is also centrally symmetrical. Therefore, the address numbers of the address sub-pads on opposite sides of the same fourth sub-test pad along the second direction (e.g., the oy direction) are usually different. The signal exchange pad 20218 can make the address numbers of the address sub-pads on opposite sides of the same fourth sub-test pad along the second direction (e.g., the oy direction) the same, thereby making the signal transmission path length between the same fourth sub-test pad and different address sub-pads equal, thus eliminating the difference in signal transmission.

[0068] As an example, please continue reading Figure 6 When Figure 6 When testing the first chip 201a and the second chip 201b, a high level can first be provided to the WPB or WPA pad in the signal exchange pad 20218 to supply power to the VSS and VDD pads of the second chip 201b or the first chip 201a. This enables the TDQB or TDQA pad in the power supply pad 20113, allowing internal signal exchange of the address sub-pads of the second chip 201b or the first chip 201a. This ensures that the signal transmission path length between the same fourth sub-test pad and different address sub-pads is equal, eliminating signal transmission differences. When the signal exchange is complete, a low level is provided to the WPB or WPA pad in the signal exchange pad 20218 to disconnect the power supply to the VSS and VDD pads of the second chip 201b or the first chip 201a. The above signal exchange process ensures that the channel length from the test pad to different chips is equal when testing the wafer, thereby eliminating signal differences during testing, ensuring the consistency of test results, and improving test yield.

[0069] For example, please refer to Figure 7 and Figure 8The chip under test 201 adjacent to the test pad 2021 along the second direction (e.g., the oy direction) and the first direction (e.g., the ox direction) can also be four, namely the first chip 201a, the second chip 201b, the third chip 201c, and the fourth chip 201d. The first chip 201a, the second chip 201b, the third chip 201c, and the fourth chip 201d share a set of test pads 2021, which enables a set of test pads 2021 to test four chips under test at the same time, further improving the testing efficiency.

[0070] As an example, please continue reading Figure 7 The test pad 2021 is located in the dicing channel 202 shared by the first chip 201a, the second chip 201b, the third chip 201c, and the fourth chip 201d. The chip pads 2011 of the first chip 201a, the second chip 201b, the third chip 201c, and the fourth chip 201d are all located on one side close to their shared dicing channel 202. The first chip 201a and the second chip 201b are centrally symmetrical to each other, and the third chip 201c and the fourth chip 201d are centrally symmetrical to each other, so that the power supply to the chip 201 under test is stable when the test pad 2021 is located in the dicing channel 202.

[0071] As an example, please continue reading Figure 8 The chip pads 2011 in the second chip 201b and the fourth chip 201d each include a first ground pad 20111, a first voltage pad 20112, a power pad 20113, an address pad 20114, a second voltage pad 20115, and a second ground pad 20116 arranged sequentially along a first direction (e.g., the ox direction); the chip pads 2011 in the first chip 201a and the third chip 201c each include a second ground pad 20116, a second voltage pad 20115, an address pad 20114, a power pad 20113, a first voltage pad 20112, and a first ground pad 20111 arranged sequentially along a first direction (e.g., the ox direction).

[0072] As an example, please continue reading Figure 8The first ground pad 20111 can be abbreviated as VSS pad; the first voltage pad 20112 can be abbreviated as VDD pad; the power pad 20113 can be abbreviated as TDQ pad, TDQA represents the power pad 20113 in the first chip 201a, TDQB represents the power pad 20113 in the second chip 201b, TDQC represents the power pad 20113 in the third chip 201c, and TDQD represents the power pad 20113 in the fourth chip 201d; the address pad 20114 can be abbreviated as ADD pad; the second voltage pad 20115 can be abbreviated as VDD pad; and the second ground pad 20116 can be abbreviated as VSS pad.

[0073] As an example, please continue reading Figure 8Each set of test pads 2021 includes a first set of test pads arranged sequentially along a first direction (e.g., the ox direction) within a cleavage 202 between the first chip 201a and the second chip 201b. This first set includes a first test pad 20211, a second test pad 20212, a third test pad 20213, two signal exchange pads 20218, and a fifth test pad 20215. It also includes a second set of test pads arranged sequentially along the first direction (e.g., the ox direction) within a cleavage 202 between the third chip 201c and the fourth chip 201d. This second set includes a fifth test pad 2021. 5. Two signal exchange pads 20218, a third test pad 20213, a second test pad 20212, and a first test pad 20211. Each set of test pads 2021 also includes a fourth test pad 20214 located between the first set of test pads and the second set of test pads, a sixth test pad 20216 and a seventh test pad 20217 located in the dicing channel 202 between the second chip 201b and the fourth chip 201d, and a sixth test pad 20216 and a seventh test pad 20217 located in the dicing channel 202 between the first chip 201a and the third chip 201c. Specifically, the first test pad 20211 is electrically connected to the second ground pad 20116 of the first chip 201a and the fourth chip 201d, and the first ground pad 20111 of the second chip 201b and the third chip 201c; the second test pad 20212 is electrically connected to the second voltage pad 20115 of the first chip 201a and the fourth chip 201d, and the first voltage pad 20112 of the second chip 201b and the third chip 201c; the third test pad 20213 is electrically connected to the power pad 20113 of the second chip 201b and the third chip 201c; and the fourth test pad 20214 is electrically connected to the first chip 201a and the second chip 201b. The address pads 20114 of the third chip 201c and the fourth chip 201d are electrically connected; the fifth test pad 20215 is electrically connected to the power pads 20113 of the first chip 201a and the fourth chip 201d; the sixth test pad 20216 is electrically connected to the second voltage pads 20115 of the first chip 201a and the fourth chip 201d, and the first voltage pads 20112 of the second chip 201b and the third chip 201c; the seventh test pad 20217 is electrically connected to the second ground pads 20116 of the first chip 201a and the fourth chip 201d, and the first ground pads 20111 of the second chip 201b and the third chip 201c. This test structure allows a set of test pads to simultaneously test four adjacent chips under test, further improving the number of simultaneous tests and testing efficiency.

[0074] As an example, please continue reading Figure 8The first test pad 20211 can be abbreviated as VSS pad; the second test pad 20212 can be abbreviated as VDD pad; the third test pad 20213 can be abbreviated as TDQB or TDQC pad, used to provide enable signals for the power pads 20113 of the second chip 201b and the third chip 201c; the fourth test pad 20214 can be abbreviated as ADD pad, used to provide electrical signals for the address pads 20114 of the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d; the fifth test pad 20215 can be abbreviated as TDQA or TDQD pad, used to provide enable electrical signals for the power pads 20113 of the first chip 201a and the fourth chip 201d; the sixth test pad 20216 can be abbreviated as VDD pad; and the seventh test pad 20217 can be abbreviated as VSS pad.

[0075] As an example, please continue reading Figure 8 Address pad 20114 includes multiple address sub-pads arranged along a first direction (e.g., the ox direction), and each address sub-pad has an address number. The number of address sub-pads is N+1, where N is an integer greater than or equal to 1, and the address numbers of the address sub-pads are arranged in descending or ascending order along the first direction (e.g., the ox direction).

[0076] As an example, please continue reading Figure 8 The address numbers of the address sub-pads of the first chip 201a and the second chip 201b are centrally symmetrical, as are the address numbers of the address sub-pads of the third chip 201c and the fourth chip 201d. Specifically, the address numbers of the address sub-pads of the first chip 201a and the third chip 201c are arranged in ascending order along a first direction (e.g., the ox direction), while the address numbers of the address sub-pads of the second chip 201b and the fourth chip 201d are arranged in descending order along the first direction (e.g., the ox direction). For example, the address numbers of the address sub-pads of the first chip 201a and the third chip 201c are 0, 1, ..., N along the first direction (e.g., the ox direction), and the address numbers of the address sub-pads of the second chip 201b and the fourth chip 201d are N, ..., 1, 0 along the first direction (e.g., the ox direction).

[0077] As an example, please continue reading Figure 8Each set of test pads 2021 also includes a signal exchange pad 20218, which is located between the third test pad 20213 and the fifth test pad 20215 adjacent along the first direction (e.g., the ox direction). When the first electrical signal is received, the address sequence number of each address sub-pad of the first chip 201a and the address sequence number of each address sub-pad of the second chip 201b changes from central symmetry to mirror symmetry.

[0078] The signal exchange pad 20218 mentioned above can be abbreviated as WP pad, the signal exchange pad 20218 controlling the first chip 201a can be abbreviated as WPA pad, the signal exchange pad 20218 controlling the second chip 201b can be abbreviated as WPB pad, the signal exchange pad 20218 controlling the third chip 201c can be abbreviated as WPC pad, and the signal exchange pad 20218 controlling the fourth chip 201d can be abbreviated as WPD pad.

[0079] As an example, please continue reading Figure 8 The fourth test pad 20214 includes multiple fourth sub-test pads, the number of which is the same as the number of address sub-pads of the first chip 201a, second chip 201b, third chip 201c, and fourth chip 201d. Each fourth sub-test pad is connected to one address sub-pad of each of the first chip 201a, second chip 201b, third chip 201c, and fourth chip 201d. The signal exchange pad 20218 can change the address numbers of different address sub-pads connected to the same fourth sub-test pad to the same number, thereby making the signal transmission path lengths from the same fourth sub-test pad to different address sub-pads equal and eliminating signal transmission differences.

[0080] As an example, please continue reading Figure 8 When Figure 6 When testing the first chip 201a, second chip 201b, third chip 201c, and fourth chip 201d, firstly, a high level can be provided to one or more of the WPA, WPB, WPC, and WPD pads in the signal exchange pads 20218 to supply power to the corresponding chip under test 201. This enables one or more of the TDQA, TDQB, TDQC, and TDQD pads in the corresponding power supply pads 20113, allowing internal signal exchange of the address sub-pads of the corresponding chip under test 201. This ensures that the signal transmission path length between the same fourth sub-test pad and different address sub-pads is equal, eliminating signal transmission differences. Then, a low level is provided to one or more of the WPA, WPB, WPC, and WPD pads in the signal exchange pads 20218 to end the signal exchange process.

[0081] For example, please refer to Figure 9 Another aspect of this disclosure provides a test system, including the test structure described in any one of the embodiments of this disclosure and a plurality of probe cards 21, each probe card 21 being electrically connected to a group of test pads 2021.

[0082] In the testing system described above, the probe card 21 is connected to the test pads 2021 in the dicing channel 202, and one test pad 2021 can be connected to at least two chip pads 2011. This allows one probe card 21 to test at least two chips 201 under test, increasing the number of simultaneous tests on the wafer 20, saving the cost and space occupied by the probe card 21. Furthermore, the reduction in the number of test pads 2021 allows adjacent probe cards 21 to maintain a certain distance, preventing them from squeezing each other and further improving testing stability. The above testing system can improve upon the problems of low simultaneous test count, high testing cost, low testing efficiency, and probe card 21 design failures encountered in related technologies that directly test the chip pads 2011. This disclosure arranges the test pad 2021 within the dicing channel 202, so that one test pad 2021 can simultaneously electrically connect at least two chips under test 201, that is, one probe card 21 can simultaneously test at least two chips under test 201. Furthermore, by setting two adjacent chips under test 201 along the second direction (e.g., the oy direction) to be mutually centrally symmetrical, the wiring difference from the test pad 2021 to different chips under test 201 is reduced, and the consistency of signal and power supply is ensured, thereby improving the yield and efficiency of wafer 20 probe testing and reducing testing costs.

[0083] As an example, please continue reading Figure 9 Two probe cards 21 connected to two sets of test pads 2021 adjacent to each other along the first direction (e.g., the ox direction) are located on opposite sides of the test pads 2021 along the second direction (e.g., the oy direction), so that the probe cards 21 connected to the adjacent chip under test 201 have a gap between each other, which can simultaneously perform probe testing on all chips under test 201 in the same wafer 20 without the need for batch testing. The reduction in the number of probe cards 21 and the arrangement of their positions in this disclosure can save testing time and improve testing efficiency.

[0084] For example, please refer to Figure 10Each probe card 21 includes a circuit board 211 and a plurality of probes 212 disposed on the same side of the circuit board 211. The probes 212 in each probe card 21 correspond one-to-one with each group of test pads 2021. Since the two probe cards 21 connected to the two groups of test pads 2021 adjacent along the first direction (e.g., the ox direction) are located on opposite sides of the test pads 2021 along the second direction (e.g., the oy direction), the problem that adjacent chips cannot be tested simultaneously due to the large size of the probe card 21 is improved, thus saving test time.

[0085] For example, please refer to Figure 11 Another aspect of this disclosure provides a testing method for testing the test structure described in any one of the embodiments of this disclosure, the method comprising:

[0086] Step S2: Provide the test structure and probe card;

[0087] Step S4: Electrically connect each probe card to each group of test pads;

[0088] Step S6: Based on the probe card, a first electrical signal is provided to the test pads electrically connected to it to test the chip under test electrically connected to the test pads;

[0089] Step S8: Provide a second electrical signal to the test pads electrically connected to the probe card to end the test.

[0090] In the testing method described in the above embodiments, a first electrical signal is provided to the test pads electrically connected to the probe card to test at least two chips under test (DUTs) electrically connected to the test pads. Furthermore, the same test pad and its adjacent chip pads along a second direction are electrically connected with equal channel lengths, ensuring no testing differences between the same test pad and different DUTs, thus improving testing accuracy and yield. This testing method addresses the problems in related technologies where a large number of test pads leads to smaller DUT capacity, slower testing progress, and lower testing yield. It can increase the number of DUTs tested simultaneously while improving testing stability and consistency, thereby simultaneously improving testing yield and efficiency, and reducing testing costs.

[0091] For example, please refer to Figure 11 Step S4, in which each probe card is electrically connected to each group of test pads, includes:

[0092] Step S41: Connect each probe card to each set of test pads, such that the two probe cards connected to the two sets of test pads adjacent to each other along the first direction are located on opposite sides of the test pads along the second direction.

[0093] The above-mentioned probe card arrangement method allows for spacing between adjacent probe cards, avoiding the problem of probe cards squeezing each other and preventing adjacent chips from being tested simultaneously. This saves testing costs while improving testing efficiency.

[0094] As an example, the first electrical signal is greater than the second electrical signal, wherein the first electrical signal can be a high-level signal and the second electrical signal can be a low-level signal.

[0095] For example, please refer to Figure 11 In step S6, there are two chips under test adjacent to the same test pad along the second direction, namely the first chip and the second chip. The first chip and the second chip share a set of test pads. The chip pads of the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad, and a second ground pad arranged sequentially along the first direction. The chip pads of the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad, and a first ground pad arranged sequentially along the first direction. Step S6 includes:

[0096] Step S61: Provide a first electrical signal to the test pads electrically connected to it based on the probe card, including: provide a first electrical signal to the test pads electrically connected to it based on the probe card, so that the address sequence number of each address sub-pad of the first chip and the address sequence number of each address sub-pad of the second chip, which are located on the chip pads corresponding to the test pads, changes from central symmetry to mirror symmetry.

[0097] The above method enables the signal transmission paths of the same test pad and the address pad connected to it to be of equal length, thereby eliminating signal differences during the test and improving the stability and accuracy of the test.

[0098] In the above-mentioned test structure, system and method, by setting the test pads in the dicing channel, setting the chip under test as centrally symmetrical, and setting a signal exchange structure, it is possible to increase the number of simultaneous tests, improve test efficiency, increase chip capacity, increase the number of wafers per wafer (Dies Per Wafer, or DPW), reduce test costs, and at the same time ensure the consistency and accuracy of the test.

[0099] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0100] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above embodiments merely illustrate several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A test structure, characterized by, The application relates to a wafer including: a wafer including a plurality of chips to be tested arranged in an array along a first direction and a second direction, a cutting lane being arranged between two adjacent chips to be tested along the first direction and between two adjacent chips to be tested along the second direction, and the two adjacent chips to be tested along the second direction being mutually central symmetric; wherein the chip to be tested includes a plurality of chip pads arranged along the first direction, and the chip pads are arranged on a side of the chip to be tested close to the cutting lane along the second direction; a plurality of test pads corresponding to the chip pads and arranged in the cutting lane between the chip pads adjacent along the second direction; wherein the same test pad and the chip pads adjacent along the second direction are electrically connected and have equal channel lengths, and the first direction intersects the second direction; the chips to be tested adjacent along the second direction of the same test pad are two, namely a first chip and a second chip, and the first chip and the second chip share a group of test pads; the chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad and a first ground pad arranged along the first direction in sequence; the chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad and a second ground pad arranged along the first direction in sequence; each group of test pads includes: a first test pad electrically connected with the first ground pad of the second chip and the second ground pad of the first chip; a second test pad electrically connected with the first voltage pad of the second chip and the second voltage pad of the first chip; a third test pad electrically connected with the power pad of the second chip; a fourth test pad electrically connected with the address pad of the second chip and the address pad of the first chip; a fifth test pad electrically connected with the power pad of the first chip; a sixth test pad electrically connected with the second voltage pad of the second chip and the first voltage pad of the first chip; a seventh test pad electrically connected with the second ground pad of the second chip and the first ground pad of the first chip; the address pad of the first chip includes a plurality of address sub-pads arranged along the first direction, each address sub-pad has an address serial number, the address pad of the second chip includes a plurality of address sub-pads arranged along the first direction, the address serial number of each address sub-pad of the first chip and the address serial number of each address sub-pad of the second chip are mutually central symmetric, and the fourth test pad includes a plurality of fourth sub-test pads, each fourth sub-test pad is connected with one address sub-pad of the first chip and one address sub-pad of the second chip respectively; each group of test pads further includes: signal exchange pads between the second test pad and the third test pad adjacent to each other in the first direction, and between the fifth test pad and the sixth test pad adjacent to each other in the first direction, for changing the address sequence of the address sub-pads of the first chip and the address sequence of the address sub-pads of the second chip from center symmetry to mirror symmetry when a first electrical signal is received, so that the signal transmission path length between each fourth sub-test pad and the address sub-pads connected thereto is equal.

2. The test structure of claim 1, wherein, The test pad and the chip pad adjacent to each other in the second direction are connected by a wire, and the length of the wire in the second direction is equal.

3. The test structure of claim 1, wherein, The chip to be tested further comprises a third chip and a fourth chip, the third chip is adjacent to the first chip in the first direction, the fourth chip is adjacent to the second chip in the first direction, the third chip and the fourth chip are adjacent in the second direction, and the first chip, the second chip, the third chip and the fourth chip share a group of test pads.

4. A test system, characterized by Comprise: The test structure of any one of claims 1-3; And A plurality of probe cards, each of the probe cards being electrically connected with each group of test pads.

5. The test system of claim 4, wherein, The two probe cards connected with the two groups of test pads adjacent to each other in the first direction are respectively located on opposite sides of the test pads in the second direction.

6. The test system of claim 5, wherein, Each of the probe cards comprises a circuit board and a plurality of probes arranged on the same side of the circuit board, and the probes in each of the probe cards correspond to each group of test pads one by one.

7. A test method characterized by, The method for testing the test structure of any one of claims 1-3, the method comprising: Providing the test structure and the probe cards; Electrically connecting each of the probe cards with each group of test pads; Based on the probe cards, providing a first electrical signal to the test pads electrically connected therewith to test the chip to be tested electrically connected with the test pads; Based on the probe cards, providing a second electrical signal to the test pads electrically connected therewith to end the test.

8. The test method of claim 7, wherein, The electrically connecting each of the probe cards with each group of test pads comprises: Electrically connecting each of the probe cards with each group of test pads, and making the two probe cards connected with the two groups of test pads adjacent to each other in the first direction respectively located on opposite sides of the test pads in the second direction.

9. The test method of claim 7, wherein, The first electrical signal is greater than the second electrical signal.

10. The test method of claim 9, wherein The electrically connecting each of the probe cards with each group of test pads comprises: Based on the probe cards, providing a first electrical signal to the test pads electrically connected therewith, so that the address sequence of the address sub-pads of the first chip and the address sequence of the address sub-pads of the second chip corresponding to the chip pads arranged thereon are changed from center symmetry to mirror symmetry.

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