Field Programmable Gate Array Software Asynchronous Communication Rate Deviation Detection Method and Device

Abstract

A method and device for detecting asynchronous communication rate offsets in field programmable gate array (FPGA) software belongs to the field of field programmable gate array (FPGA) software verification technology. The method includes: determining a plurality of first rates based on a preset rate step length and a preset rate range; and performing the following steps for each first rate: in a digital simulation environment, inputting an excitation signal into a device under test (DUT) module at the first rate; the DUT module preprocessing the received excitation signal to obtain a preprocessed data frame; and determining whether the preprocessed data frame is consistent with a test frame, wherein the content transmitted in the excitation signal is an encoded test frame; if not, determining that the offset detection result for the first rate is a failure; if consistent, determining that the offset detection result for the first rate is a pass; and recording the first rate, theoretical rate, rate offset difference, and rate offset ratio to allow relevant personnel to quickly understand the boundary conditions of the FPGA software asynchronous communication rate.

Description

Technical Field

[0001] The present application relates to the technical field of field programmable gate array software verification, and in particular to a method, apparatus, device, and computer-readable storage medium for detecting asynchronous communication rate offset of field programmable gate array software. Background Art

[0002] With the development of digital electronic technology and chips, field-programmable gate arrays (FPGAs) are increasingly used in digital circuits. Asynchronous communication is a common communication method between FPGA software and other chips. Due to various reasons, the asynchronous communication rate may deviate from the theoretical value, and in some extreme cases, it may even lead to data loss, frame loss, packet loss, and the like. How to quickly and accurately detect the asynchronous communication rate deviation of FPGA software has become an urgent problem to be solved. In related technologies, the communication rate is determined by detecting the start bit and data bit edges of the serial interface of asynchronous communication. However, this method can only obtain the communication rate of the sending end of the asynchronous communication, that is, it can only obtain one communication rate, resulting in the relevant personnel being unable to understand the boundary conditions of the asynchronous communication rate of the FPGA software. Summary of the Invention

[0003] The present application provides a field programmable gate array software asynchronous communication rate offset detection method, device, equipment and computer-readable storage medium, which can solve the technical problem in the prior art that relevant personnel cannot understand the boundary conditions of FPGA software asynchronous communication rate.

[0004] In a first aspect, an embodiment of the present application provides a method for detecting an asynchronous communication rate offset of a field programmable gate array software. The method comprises:

[0005] Determining a plurality of first rates based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter;

[0006] For each first rate, perform the following steps:

[0007] In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested.

[0008] If they are inconsistent, determining that the offset detection result of the first rate is failed;

[0009] If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

[0010] In combination with the first aspect, in one embodiment, the first rates are determined based on the preset rate step length and the preset rate range, and the corresponding formula is:

[0011] a i+1 =a i +d

[0012] a1=V min

[0013] Where i is a positive integer, a i is the first rate of i, the maximum value of i is when a i ≤V max And a i+1 >V max The value of i when V min is the lower limit of the preset rate range, V max is the upper limit of the preset rate range, and d is the preset rate step length.

[0014] In combination with the first aspect, in one embodiment, the process of generating the excitation signal includes:

[0015] The test data driving module generates asynchronous communication interface data and uses the asynchronous communication interface data as an excitation signal.

[0016] In conjunction with the first aspect, in one embodiment, determining whether the preprocessed data frame is consistent with the test frame includes:

[0017] Determine whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame;

[0018] If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is judged to be consistent with the test frame, otherwise they are inconsistent.

[0019] In combination with the first aspect, in one implementation, the preprocessing includes decoding.

[0020] In a second aspect, an embodiment of the present application provides a field programmable gate array software asynchronous communication rate offset detection device, the field programmable gate array software asynchronous communication rate offset detection device comprising:

[0021] a determination module, configured to determine a plurality of first rates based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter;

[0022] The determining module is configured to perform the following steps for each first rate:

[0023] In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested.

[0024] If they are inconsistent, determining that the offset detection result of the first rate is failed;

[0025] If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

[0026] In conjunction with the second aspect, in one embodiment, the judgment module is specifically configured to:

[0027] Determine whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame;

[0028] If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is judged to be consistent with the test frame, otherwise they are inconsistent.

[0029] In combination with the second aspect, in one implementation, the preprocessing includes decoding.

[0030] In a third aspect, an embodiment of the present application provides a field programmable gate array software asynchronous communication rate offset detection device, wherein the field programmable gate array software asynchronous communication rate offset detection device includes a processor, a memory, and a field programmable gate array software asynchronous communication rate offset detection program stored in the memory and executable by the processor, wherein when the field programmable gate array software asynchronous communication rate offset detection program is executed by the processor, the steps of the field programmable gate array software asynchronous communication rate offset detection method as described in any one of the first aspects are implemented.

[0031] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a field programmable gate array software asynchronous communication rate offset detection program is stored. When the field programmable gate array software asynchronous communication rate offset detection program is executed by a processor, the steps of the field programmable gate array software asynchronous communication rate offset detection method as described in any one of the first aspects are implemented.

[0032] The beneficial effects of the technical solutions provided in the embodiments of the present application include:

[0033] A plurality of first rates are determined based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of communication of the field programmable gate array software and a preset offset parameter; for each first rate, the following steps are performed: in a digital simulation environment, an excitation signal is input to a device under test module at the first rate; after the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame; and whether the preprocessed data frame is consistent with a test frame is determined; the excitation signal is generated by a test data driving module, and the content transmitted in the excitation signal is an encoded test frame; The module under test is the field programmable gate array software to be tested; if there is inconsistency, the offset detection result of the first rate is determined to be failed; if there is consistency, the offset detection result of the first rate is determined to be passed, and the first rate, theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded. This method relies on a digital simulation environment and has low testing costs; no physical equipment is required and no damage is caused to the actual board equipment; this method can not only perform relevant tests before deploying the program on the actual chip, but can also be applied in the actual development process; the use of automated testing releases human resources and improves testing results, so that relevant personnel can quickly understand the boundary conditions of the asynchronous communication rate of the FPGA software. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A block diagram of the field programmable gate array software asynchronous communication rate offset detection principle provided by one embodiment of the present application;

[0035] Figure 2 This is a flow chart of the first embodiment of the method for detecting asynchronous communication rate offset of field programmable gate array software of the present application;

[0036] Figure 3 This is a functional module diagram of an embodiment of a field programmable gate array software asynchronous communication rate offset detection device of the present application;

[0037] Figure 4 This is a schematic diagram of the hardware structure of the field programmable gate array software asynchronous communication rate offset detection device involved in the embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The field programmable gate array software asynchronous communication rate offset detection method provided in this application is completed in a fully digital simulation environment. The tester builds a test platform in the fully digital simulation environment, effectively combining the functions of the device under test module, test data driver module, detector, data comparison module, scoreboard, etc., thereby completing the automated test of asynchronous communication rate offset. Figure 1 A block diagram of the principle of field programmable gate array software asynchronous communication rate offset detection provided by one embodiment of the present application.

[0040] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0041] In a first aspect, an embodiment of the present application provides a method for detecting a rate offset of asynchronous communication of field programmable gate array software.

[0042] In one embodiment, referring to Figure 2 , Figure 2 This is a flow chart of the first embodiment of the field programmable gate array software asynchronous communication rate offset detection method of the present application. Figure 2 As shown, the field programmable gate array software asynchronous communication rate offset detection method includes:

[0043] Step 210: Determine a plurality of first rates based on a preset rate step length and a preset rate range, where the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter.

[0044] During specific implementation, the tester configures the theoretical rate, preset rate step length, preset rate range, preset offset parameter, and data frame of the FPGA software asynchronous communication interface to be tested. For example, when the theoretical rate of the FPGA software asynchronous communication is set to 10,000 bps and the preset offset parameter is 5%, the lower limit of the preset rate range determined based on the theoretical rate of the FPGA software asynchronous communication and the preset offset parameter is 10,000*(1-5%)=9,500 bps, and the upper limit of the preset rate range is 10,000*(1+5%)=10,500 bps.

[0045] The preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the first rate is an asynchronous communication rate determined from the preset rate range according to the preset rate step length.

[0046] A plurality of first rates are determined from a preset rate range according to a preset rate step length, so as to subsequently determine whether an offset detection result of each first rate passes.

[0047] Furthermore, in one embodiment, the first rates are determined based on the preset rate step length and the preset rate range, and the corresponding formula is:

[0048] a i+1 =a i +d

[0049] a1=V min

[0050] Where i is a positive integer, a i is the first rate of i, the maximum value of i is when a i ≤V max And a i+1 >V max The value of i when V min is the lower limit of the preset rate range, V max is the upper limit of the preset rate range, and d is the preset rate step length.

[0051] In a specific implementation, a plurality of first rates are determined from a preset rate range according to a preset rate step length. For example, if the preset rate range is [9500, 10500], and d = 10, the plurality of first rates determined are a1 = 9500, a2 = 9510, a3 = 9520, etc.; preferably, if d = 1, the plurality of first rates determined are a1 = 9500, a2 = 9501, a3 = 9502, etc.

[0052] In this embodiment, when the rate range is set to be relatively large, a plurality of first rates can be automatically determined using the above formula, thereby improving the efficiency of determining the first rate.

[0053] Step 220: For each first rate, perform the following steps:

[0054] In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested.

[0055] If they are inconsistent, determining that the offset detection result of the first rate is failed;

[0056] If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

[0057] In specific implementation, after the tester completes the parameter configuration and runs the test, the software automatically determines several first rates and performs the following steps for each first rate:

[0058] The test data driving module generates an excitation signal and inputs the excitation signal to the device under test (DUT) module at a first rate, and simultaneously sends the data frame to the data comparison module;

[0059] After receiving the excitation signal, the DUT module performs preprocessing such as decoding on the received excitation signal to obtain a preprocessed data frame, which is then input into the detector module. It should be noted that the preprocessing in this application includes but is not limited to decoding.

[0060] The detector module inputs the received pre-processed data frame into the data comparison module;

[0061] The data comparison module compares the pre-processed data frame with the test frame to determine whether the pre-processed data frame is consistent with the test frame. If the pre-processed data frame is inconsistent with the test frame, it indicates that there is data loss, frame loss, packet loss, etc., and communication has failed. In this case, the offset detection result of the first rate is determined to be failed, and no data related to the first rate is recorded. If the pre-processed data frame is consistent with the test frame, it indicates that there is no data loss, frame loss, packet loss, etc., and communication is successful. In this case, the offset detection result of the first rate is determined to be passed, and the detection result is transmitted to the scoreboard module.

[0062] The scoreboard module is responsible for recording the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate, and forming a text document.

[0063] Exemplarily, the preset rate range is [9500, 10500], d=1 is taken, and the excitation signal is first input to the design under test (DUT) module at the first rate a1=9500; after the DUT module receives the excitation signal, the excitation signal received by the DUT module is decoded and other preprocessing is performed to obtain a preprocessed data frame; further, it is determined whether the preprocessed data frame is consistent with the test frame. If the preprocessed data frame is inconsistent with the test frame, the offset detection result of the first rate 9500 is determined to be failed, and the data related to the first rate is not recorded; if the preprocessed data frame is consistent with the test frame, the offset detection result of 9500 is determined to be passed, and the first rate 9500, the theoretical rate 10000, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded. At this time, the rate offset difference of the first rate relative to the theoretical rate, that is, the rate offset difference of 9500 relative to 10000, is 500, and the rate offset ratio of the first rate relative to the theoretical rate, that is, the rate offset ratio of 9500 relative to 10000 is -5%.

[0064] Then, an excitation signal is input to the DUT module at a first rate a2 = 9501. After receiving the excitation signal, the DUT module performs preprocessing such as decoding on the excitation signal to obtain a preprocessed data frame. A determination is then made as to whether the preprocessed data frame is consistent with the test frame. If the preprocessed data frame is inconsistent with the test frame, the offset detection result for the first rate 9501 is determined to have failed, and no data related to the first rate is recorded. If the preprocessed data frame is consistent with the test frame, the offset detection result for 9501 is determined to have passed, and the first rate 9501, the theoretical rate 10000, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset percentage relative to the theoretical rate are recorded. In this case, the rate offset difference of the first rate relative to the theoretical rate, i.e., the rate offset difference of 9501 relative to 10000, is 499, and the rate offset percentage of the first rate relative to the theoretical rate, i.e., the rate offset percentage of 9501 relative to 10000, is -4.99%.

[0065] Then, repeat the above steps to determine the offset detection results of the first rate a3=9502, a4=9503, a5=9504, etc., until a i The maximum value of i satisfies a i ≤V max And a i+1 >V max The test ends when

[0066] Assuming 800 first-rate offset tests pass, the recorded data will contain 800 data entries, each of which contains the first rate, the theoretical rate, the offset difference between the first rate and the theoretical rate, and the offset percentage. All recorded data is stored in a text file for testers and designers to analyze and understand the FPGA software asynchronous communication rate boundary conditions.

[0067] In this embodiment, a plurality of first rates are determined based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of communication of the field programmable gate array software and a preset offset parameter. For each first rate, the following steps are performed: in a digital simulation environment, an excitation signal is input to a device under test module at the first rate; after the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame; and it is determined whether the preprocessed data frame is consistent with the test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is the encoded test data frame. Test frame, the module under test is the field programmable gate array software to be tested; if they are inconsistent, the offset detection result of the first rate is determined to be failed; if they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded. This method relies on a digital simulation environment and has low testing costs; no physical equipment is required and no damage is caused to the actual board equipment; this method can not only perform relevant tests before deploying the program on the actual chip, but can also be applied in the actual development process; the use of automated testing releases human resources and improves test results, so that relevant personnel can quickly understand the boundary conditions of the asynchronous communication rate of the FPGA software.

[0068] Furthermore, in one embodiment, the process of generating the excitation signal includes:

[0069] The test data driving module generates asynchronous communication interface data and uses the asynchronous communication interface data as an excitation signal.

[0070] It can be understood that the communication protocol of the field programmable gate array software to be tested needs to be defined in advance, wherein the data format of the asynchronous communication is clearly defined.

[0071] The test data driving module generates asynchronous communication interface data using a hardware description language (such as Verilog or VHDL) according to the asynchronous communication data format defined in the communication protocol of the field programmable gate array software to be tested, and uses the asynchronous communication interface data as an excitation signal.

[0072] In this embodiment, the test data driving module generates asynchronous communication interface data and uses the asynchronous communication interface data as an excitation signal. Since the time calculation accuracy in the simulation test environment is at the picosecond level, the accuracy of the asynchronous communication rate offset detection result of the field programmable gate array software is relatively high.

[0073] Furthermore, in one embodiment, determining whether the preprocessed data frame is consistent with the test frame includes:

[0074] Step 310: determine whether the value of each data bit in the pre-processed data frame is the same as the value of the corresponding data bit in the test frame;

[0075] Step 320: If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then it is determined that the preprocessed data frame is consistent with the test frame; otherwise, they are inconsistent.

[0076] The structure of a data frame typically includes a header, a data portion, and a trailer. The data bits in a data frame are the number of bits that make up the data portion of the frame. Testers pre-configure the test data frame based on the communication protocol of the field programmable gate array software under test.

[0077] Exemplarily, the values ​​of the 6 data bits in the data frame pre-configured for testing are 1, 0, 0, 0, 0, 1, respectively. First, it is determined whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame; if the value of each data bit in the preprocessed data frame is 0, 0, 0, 0, 0, 1, that is, the value of each data bit in the preprocessed data frame is different from the value of the corresponding data bit in the test frame, then it is determined that the preprocessed data frame is inconsistent with the test frame; if the value of each data bit in the preprocessed data frame is 1, 0, 0, 0, 0, 1, that is, the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then it is determined that the preprocessed data frame is consistent with the test frame.

[0078] In this embodiment, it is determined whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame; if the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is determined to be consistent with the test frame, otherwise they are inconsistent, laying the foundation for determining the FPGA software asynchronous communication rate offset detection result.

[0079] In a second aspect, an embodiment of the present application further provides a field programmable gate array software asynchronous communication rate offset detection device.

[0080] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of an embodiment of the field programmable gate array software asynchronous communication rate offset detection device of the present application. Figure 3 As shown, the field programmable gate array software asynchronous communication rate deviation detection device 300 includes:

[0081] a determination module 301 configured to determine a plurality of first rates based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter;

[0082] The determination module 302 is configured to perform the following steps for each first rate:

[0083] In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested.

[0084] If they are inconsistent, determining that the offset detection result of the first rate is failed;

[0085] If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

[0086] Furthermore, in one embodiment, the determining module is specifically configured to determine a plurality of first rates according to the following formula:

[0087] a i+1 =a i +d

[0088] a1=V min

[0089] Where i is a positive integer, a i is the first rate of i, the maximum value of i is when a i ≤V max And a i+1 >V max The value of i when V min is the lower limit of the preset rate range, V max is the upper limit of the preset rate range, and d is the preset rate step length.

[0090] Furthermore, in one embodiment, the judgment module is specifically configured to:

[0091] Determine whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame;

[0092] If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is judged to be consistent with the test frame, otherwise they are inconsistent.

[0093] Furthermore, in one embodiment, the process of generating the excitation signal includes:

[0094] The test data driving module generates asynchronous communication interface data and uses the asynchronous communication interface data as an excitation signal.

[0095] Furthermore, in one embodiment, the preprocessing includes decoding.

[0096] Among them, the functional implementation of each module in the above-mentioned field programmable gate array software asynchronous communication rate offset detection device corresponds to the various steps in the above-mentioned field programmable gate array software asynchronous communication rate offset detection method embodiment, and their functions and implementation processes are no longer repeated here.

[0097] In a third aspect, an embodiment of the present application provides a field programmable gate array software asynchronous communication rate offset detection device, which can be a personal computer (PC), laptop computer, server, or other device that can run a digital simulation environment and has data processing capabilities.

[0098] Reference Figure 4 , Figure 4 The hardware structure diagram of the field programmable gate array software asynchronous communication rate deviation detection device involved in the embodiment of the present application is as follows. In the embodiment of the present application, the field programmable gate array software asynchronous communication rate deviation detection device may include a processor, a memory, a communication interface and a communication bus.

[0099] The communication bus may be of any type and is used to interconnect the processor, memory, and communication interface.

[0100] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces, used to interconnect components within the field programmable gate array (FPGA) software asynchronous communication rate deviation detection device, as well as interfaces used to interconnect the FPGA software asynchronous communication rate deviation detection device with other devices (e.g., other computing devices or user equipment). Physical interfaces can be Ethernet, fiber, or ATM interfaces; user equipment can be displays, keyboards, and other devices.

[0101] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0102] The processor may be a general-purpose processor that can invoke a field programmable gate array (FPGA) software asynchronous communication rate offset detection program stored in a memory and execute the field programmable gate array (FPGA) software asynchronous communication rate offset detection method provided in the embodiments of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the field programmable gate array (FPGA) software asynchronous communication rate offset detection program is invoked can be referenced from the various embodiments of the field programmable gate array (FPGA) software asynchronous communication rate offset detection method of the present application and will not be further described here.

[0103] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation to the present application and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0104] In a fourth aspect, an embodiment of the present application also provides a computer-readable storage medium.

[0105] The computer-readable storage medium of the present application stores a field programmable gate array software asynchronous communication rate offset detection program, wherein when the field programmable gate array software asynchronous communication rate offset detection program is executed by a processor, the steps of the field programmable gate array software asynchronous communication rate offset detection method as described above are implemented.

[0106] Among them, the method implemented when the field programmable gate array software asynchronous communication rate offset detection program is executed can refer to the various embodiments of the field programmable gate array software asynchronous communication rate offset detection method of this application, and will not be repeated here.

[0107] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0108] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0109] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0110] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0111] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0112] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of the present application.

[0113] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for detecting asynchronous communication rate offset of field programmable gate array software, characterized in that: The field programmable gate array software asynchronous communication rate offset detection method comprises: Determining a plurality of first rates based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter; For each first rate, perform the following steps: In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested. If they are inconsistent, determining that the offset detection result of the first rate is failed; If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

2. The method for detecting a field programmable gate array software asynchronous communication rate offset according to claim 1, wherein: The first rates are determined based on the preset rate step length and the preset rate range, and the corresponding formula is: a i+1 =a i +d a1=V min Where i is a positive integer, a i is the first rate of i, the maximum value of i is when a i ≤V max And a i+1 >V max The value of i when V min is the lower limit of the preset rate range, V max is the upper limit of the preset rate range, and d is the preset rate step length.

3. The method for detecting a field programmable gate array software asynchronous communication rate offset according to claim 1, wherein: The process of generating the excitation signal includes: The test data driving module generates asynchronous communication interface data and uses the asynchronous communication interface data as an excitation signal.

4. The method for detecting a field programmable gate array software asynchronous communication rate offset according to claim 1, wherein: The determining whether the preprocessed data frame is consistent with the test frame includes: Determine whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame; If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is judged to be consistent with the test frame, otherwise they are inconsistent.

5. The method for detecting a field programmable gate array software asynchronous communication rate offset according to claim 1, wherein: The pre-processing includes decoding.

6. A field programmable gate array software asynchronous communication rate deviation detection device, characterized in that: The field programmable gate array software asynchronous communication rate offset detection device comprises: a determination module, configured to determine a plurality of first rates based on a preset rate step length and a preset rate range, wherein the preset rate range is a preset asynchronous communication rate range of the field programmable gate array software to be tested, and the preset rate range is determined based on a theoretical rate of the field programmable gate array software communication and a preset offset parameter; The determining module is configured to perform the following steps for each first rate: In a digital simulation environment, an excitation signal is input to a device under test module at a first rate. After the device under test module receives the excitation signal, the device under test module preprocesses the received excitation signal to obtain a preprocessed data frame, and determines whether the preprocessed data frame is consistent with a test frame. The excitation signal is generated by a test data driver module, and the content transmitted in the excitation signal is an encoded test frame. The device under test module is a field programmable gate array software to be tested. If they are inconsistent, determining that the offset detection result of the first rate is failed; If they are consistent, the offset detection result of the first rate is determined to be passed, and the first rate, the theoretical rate, the rate offset difference of the first rate relative to the theoretical rate, and the rate offset ratio relative to the theoretical rate are recorded.

7. The field programmable gate array software asynchronous communication rate deviation detection device according to claim 6, characterized in that: The judgment module is specifically used for: Determine whether the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame; If the value of each data bit in the preprocessed data frame is the same as the value of the corresponding data bit in the test frame, then the preprocessed data frame is judged to be consistent with the test frame, otherwise they are inconsistent.

8. The field programmable gate array software asynchronous communication rate deviation detection device according to claim 6, wherein: The pre-processing includes decoding.

9. A field programmable gate array software asynchronous communication rate deviation detection device, characterized in that: The field programmable gate array software asynchronous communication rate offset detection device includes a processor, a memory, and a field programmable gate array software asynchronous communication rate offset detection program stored in the memory and executable by the processor. When the field programmable gate array software asynchronous communication rate offset detection program is executed by the processor, the steps of the field programmable gate array software asynchronous communication rate offset detection method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a field programmable gate array software asynchronous communication rate offset detection program, wherein when the field programmable gate array software asynchronous communication rate offset detection program is executed by a processor, the steps of the field programmable gate array software asynchronous communication rate offset detection method according to any one of claims 1 to 5 are implemented.

Images