Gate-all-around laterally diffused metal oxide semiconductor field effect transistor

Abstract

The invention relates to a gate-all-around laterally diffused metal oxide semiconductor field effect transistor. A gate-all-around laterally diffused metal oxide semiconductor device is provided. An apparatus includes a substrate, two or more first flakes disposed on the substrate, a gate disposed on the substrate and at least a portion of the two or more first flakes, and a first epitaxial layer disposed on the substrate on a first side of the gate and at least a portion of the two or more first flakes. At least a portion of the two or more first flakes extends longitudinally from the gate to the first epitaxial layer.

Description

[0001] Copyright Notice

[0002] Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for all-around gate lateral diffused metal oxide semiconductor field effect transistors. Background Art

[0004] The all-around gate (GAA) platform has become the paradigm of complementary metal oxide semiconductor (CMOS) technology. GAA continues to scale with advanced CMOS process nodes. In the context of laterally diffused metal oxide semiconductor (LDMOS), fin-based field effect transistors (LDMOS) have been used for scalability and space saving. However, as process nodes become smaller and smaller, fin-based structures can no longer scale accordingly.

[0005] Therefore, methods, systems, and apparatus for GAA LDMOS are provided. Summary of the invention

[0006] In one aspect, the present disclosure relates to a device comprising: a substrate; two or more first thin sheets disposed on the substrate; a gate disposed on the substrate and at least a portion of the two or more first thin sheets; a first epitaxial layer disposed on the substrate on a first side of the gate and at least a portion of the two or more first thin sheets; and wherein at least a portion of the two or more first thin sheets extends longitudinally from the gate to the first epitaxial layer.

[0007] On the other hand, the present disclosure relates to a semiconductor die comprising: a substrate; a laterally diffused metal oxide semiconductor transistor disposed on the substrate, the laterally diffused metal oxide semiconductor transistor comprising: a gate comprising a gate dielectric layer disposed on the substrate; a source comprising a first epitaxial layer disposed on the substrate on a first side of the gate dielectric layer; and two or more first thin sheets disposed on the substrate, wherein at least a portion of the two or more first thin sheets extends longitudinally from the gate dielectric layer to the first epitaxial layer.

[0008] On the other hand, the present disclosure relates to a semiconductor device, comprising: a gate disposed on a substrate and at least a portion of two or more first thin films; a source comprising a first epitaxial layer disposed on the substrate on a first side of the gate and at least a portion of the two or more first thin films; and two or more first thin films disposed on the substrate, wherein at least a portion of the two or more first thin films extends longitudinally from the gate to the first epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The nature and advantages of certain embodiments may be further understood by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to indicate one of a plurality of similar components. When a reference numeral is cited without specifying an existing sub-label, it refers to all such plurality of similar components.

[0010] Figure 1 is a schematic top view of a GAA LDMOS FET according to various embodiments;

[0011] Figure 2 is a schematic diagram of a cross section of a GAA LDMOS FET according to various embodiments;

[0012] Figure 3 is a schematic top view of an alternative GAA LDMOS FET according to various embodiments; and

[0013] Figure 4 is a schematic diagram of a cross-section of an alternative GAA LDMOS FET according to various embodiments. DETAILED DESCRIPTION

[0014] Various embodiments describe GAA LDMOS field effect transistors (FETs).

[0015] In some embodiments, a device for a GAA LDMOS FET is provided. The device includes a substrate, two or more first thin sheets disposed on the substrate, a gate disposed on the substrate and at least a portion of the two or more first thin sheets, and a first epitaxial layer disposed on the substrate on a first side of the gate and at least a portion of the two or more first thin sheets. The two or more first thin sheets may extend at least partially from the gate to the first epitaxial layer.

[0016] In other embodiments, a semiconductor die for a GAA LDMOS FET is provided. The semiconductor die includes a substrate and a laterally diffused metal oxide semiconductor transistor disposed on the substrate. The laterally diffused metal oxide semiconductor transistor includes a gate, a source, and two or more first thin sheets disposed on the substrate. The gate includes a gate dielectric layer disposed on the substrate, the source includes a first epitaxial layer disposed on the substrate on a first side of the gate dielectric layer, and the two or more first thin sheets extend at least partially from the gate dielectric layer to the first epitaxial layer.

[0017] In other embodiments, a semiconductor device for a GAA LDMOS FET is provided. The semiconductor device includes a gate, a source, and two or more thin sheets. The gate may be disposed on a substrate and at least a portion of the two or more first thin sheets. The source includes a first epitaxial layer disposed on a first side of the gate and at least a portion of the two or more first thin sheets on the substrate. The two or more thin sheets may be disposed on the substrate and extend at least partially from the gate to the first epitaxial layer.

[0018] In the following description, for the purpose of explanation, many details are set forth to provide a comprehensive understanding of the described embodiments. However, it will be appreciated by those skilled in the art that other embodiments may be implemented without some of these details. Several embodiments are described herein, and although different embodiments have different features, it should be understood that the features described for one embodiment may also be combined with other embodiments. However, by the same token, a single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0019] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections where there may be intervening elements.

[0020] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, adjacent, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances where there may be intervening elements.

[0021] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intermediate elements present between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections where intermediate elements may be present.

[0022] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0023] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described processes, and further various processes may be reordered, added, and / or omitted according to various embodiments.

[0024] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, and the like are to be understood as being modified in all instances by the term "about". In this application, unless otherwise indicated, the use of the singular includes the plural, and the use of the term "and" means "and / or" unless otherwise indicated. In addition, the use of the terms "comprising" and "having", as well as other forms such as "includes", "included", "has", "have", and "had", are to be considered non-exclusive. In addition, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit, unless otherwise specifically indicated.

[0025] As used herein, the phrase "at least one" preceding a series of items, with the terms "and" or "or" separating any item, modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any one item and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where selection of "at least one of each of A, B, and C," or alternatively, "at least one of A, at least one of B, and at least one of C," is intended, it is expressly described as such.

[0026] LDMOS transistors, and in particular fin-based LDMOS transistors (LDMOS LDMOS), cannot be scaled down in current and planned 3nm and 2nm process nodes. Therefore, GAA FETs in an LDMOS configuration are described below. Specifically, by using GAA to form LDMOS, high voltage (relative to CMOS) GAA devices can be realized at 2nm and 3nm CMOS process nodes without requiring changes or additional steps in the process.

[0027] Figure 1 1 is a schematic top view of a GAA LDMOS FET 100 (hereinafter referred to as “LDMOS 100”) according to various embodiments. LDMOS 100 includes a drain region 105, a gate 110, and a source region 115 disposed on a substrate 120. LDMOS 100 further includes one or more first nanosheet stacks 125a to 125d (collectively referred to as “first nanosheet stacks 125”), one or more second nanosheet stacks 135a to 135d (collectively referred to as “second nanosheet stacks 135”), a first drain-side dummy gate 140a and a second drain-side dummy gate 140b (collectively referred to as “drain-side dummy gate 140”), and a source-side dummy gate 145. It should be noted that the various components and elements of LDMOS 100 are described in detail in detail. Figure 1 Modifications to various components and other arrangements of LDMOS 100 are possible as schematically illustrated in FIG. 1 and according to various embodiments.

[0028] In various embodiments, the structure of LDMOS 100 may be disposed on a substrate 120. Thus, substrate 120 may be a semiconductor substrate, such as (but not limited to) bulk silicon. In some embodiments, substrate 120 includes a lightly doped ("p-" or "n-") silicon substrate. For example, in the case of an n-type LDMOS (NLDMOS), substrate 120 may be lightly boron doped (e.g., p-), in which well regions (e.g., p-well and n-well) may be formed. Thus, substrate 120 may further include more heavily doped ("p+" or "n+") regions, doped with n-type (e.g., phosphorus) and p-type dopants (e.g., boron), respectively. Thus, a well (interchangeably referred to as a "well region") refers to a doped region formed within the substrate 145, which serves as the "body" or "main body" of the LDMOS 100, on which (or in which) other portions of the device are formed, such as the drain region 105, the gate 110, the source region 115, the first nanosheet stack 125, the second nanosheet stack 135, the drain-side dummy gate 140, and the source-side dummy gate 145. A "p-well" refers to a well having p-type doping, and an "n-well" refers to a well having n-type doping.

[0029] In the above embodiments and other embodiments described below, boron and phosphorus are provided as non-limiting examples, and it should be understood that in other embodiments, other dopants may be used. For example, suitable dopants may include, but are not limited to, pentavalent atoms (such as arsenic, phosphorus, antimony, bismuth, lithium, etc.) for n-type doping and trivalent atoms (such as indium, aluminum, gallium, boron, etc.) for p-type doping.

[0030] In various embodiments, one or more first nanosheet stacks 125a to 125d and one or more second nanosheet stacks 135a to 135d may be disposed on the substrate 120. In some examples, the one or more first nanosheet stacks 125a to 125d and the one or more second nanosheet stacks 135a to 135d may include only a single respective nanosheet stack (e.g., one first nanosheet stack 125 and one second nanosheet stack 135). The nanosheet stacks may be formed using various processes, including, but not limited to, growing and / or depositing the nanosheet stacks on the substrate 120 (e.g., via an epitaxial process), forming the nanosheet stacks via lithography and / or etching, or a combination of processes.

[0031] As used herein, nanosheets refer to two-dimensional sheet-like nanostructures with a thickness ranging from 1 to 100 nm. In some examples, the nanosheet thickness may be in the range of 5 to 9 nm, while in other examples, the nanosheet may be less than 5 nm. The width and length of individual nanosheets may vary, as the size may be determined based on the respective application. In various examples, a nanosheet may be referred to as having a length extending in a "longitudinal direction" and a width extending in a "lateral direction". The nanosheet may be formed of a semiconductor material, as described above with respect to substrate 120.

[0032] Thus, as used herein, a nanosheet stack refers to a stack of two or more nanosheets. In some examples, a nanosheet stack may be referred to as a "vertical stack," where the nanosheets are disposed (e.g., stacked) above a "horizontal" plane defined by the top surface of substrate 120. In some examples, a nanosheet stack, such as first nanosheet stack 125 and second nanosheet stack 135, may be a nanosheet stack formed by alternating semiconductor materials. In one example, a nanosheet stack may include alternating layers of silicon (Si) and silicon germanium (SiGe) nanosheets, where each layer refers to a corresponding type of nanosheet. In yet further examples, the nanosheet may be formed of the same material as the substrate.

[0033] Furthermore, as previously described, in some embodiments, each layer of nanosheets may itself include one or more layers. For example, a Si nanosheet layer may itself be formed from one or more layers of Si nanosheets. Thus, in the nanosheet stack described above, a Si nanosheet layer may be followed by a SiGe layer that may each include one or more layers of SiGe nanosheets. In other embodiments, other materials may be utilized.

[0034] In yet other examples, individual nanosheet layers of a nanosheet stack (e.g., the first nanosheet stack 125 or the second nanosheet stack 135) may be separated by dielectric spacers (e.g., metal oxide spacers). For example, a nanosheet stack may include alternating layers of different materials, such as silicon nanosheets and dielectric spacers. Thus, in some embodiments, a nanosheet stack may include alternating layers of Si nanosheets and dielectric spacers.

[0035] In various embodiments, individual nanosheets may be configured to provide respective channels between the gate 110 and the source region 115. Alternatively, as will be referred to below Figure 3 In more detail, the channel between the drain region 105 (305) and the source region 1115 (315).

[0036] Compared to the fins commonly found in FinFETs, nanosheet stacks can provide improved direct current (DC) performance and better control of short channel effects (SCE).

[0037] Next, the gate 110, the drain side dummy gates 140a-140b, and the source side dummy gate 145 may be formed by depositing a gate oxide (e.g., a dielectric layer) over the first nanosheet stack 125 and the second nanosheet stack 135, followed by forming the gate 110 and the drain side dummy gates 140a-140b and the source side dummy gate 145 from the gate oxide. In some examples, the gate 110 and / or the drain side dummy gates 140a-140b and the source side dummy gate 145 may be first patterned and then deposited onto the substrate 120 and / or the first nanosheet stack 125 and the second nanosheet stack 135. In yet other examples, the physical dielectric structure of the gate 110 and / or the gate electrode may be referred to as a “gate dielectric layer,” and the drain side dummy gates 140a-140b and the source side dummy gate 145 may be referred to as a “dummy dielectric layer.”

[0038] As used herein, a dummy gate refers to a passive gate structure used for various purposes. In various examples, a dummy gate can be used as a structural support (e.g., Figure 2 and 4 As depicted in , to support raised source / drain (RSD) epitaxial structures and / or first and second nanosheet stacks 125, 135), electrically biased, electrically isolated, and / or placeholder structures that are later removed or replaced.

[0039] In various embodiments, the drain region 105 may be disposed on the first side of the gate 110, between the drain-side dummy gates 140a-140b. In some embodiments, the drain region 105 includes a highly doped portion of the first nanosheet stack 125. In various examples, the first nanosheet stack 125 may include a highly doped portion that is in-situ doped to form at least a portion of the drain region 105. In some examples, in the case of NLDMOS, all or part of the first nanosheet stack 125 may be in-situ phosphorus doped. In other examples, the nanosheets may be undoped nanosheets.

[0040] In some embodiments, a RSD epitaxial layer (hereinafter referred to as an "epitaxial layer") may be formed above the nanosheet stack. An epitaxial layer may refer to a structure / layer grown via an epitaxial process. In this example, the epitaxial layer may form at least a portion of the RSD. The epitaxial layer may be heavily doped to form a drain structure (also referred to as a "drain / source") of the drain region 105. The drain region 105 may be interchangeably referred to as the "drain" or "drain / source" of the LDMOS 100. In some examples, the epitaxial layer may be configured to laterally interconnect one or more first nanosheet stacks 125a to 125d. For example, the epitaxial layer may extend longitudinally so that the epitaxial layer traverses one or more first nanosheet stacks 125a to 125d, such as Figure 1 Described in.

[0041] Similarly, the source region 115 may be disposed on a second side of the gate 110 (e.g., opposite the first side of the gate 110). For example, in some embodiments, the source region 115 is disposed between the source-side dummy gate 145 and the gate 110. Like the drain region 105, the source region 115 may include a highly doped portion of the second nanosheet stack 135. Specifically, the second nanosheet stack 135 may include a first highly doped portion that is in-situ doped to form at least a portion of the source region 115. In some examples, in the case of NLDMOS, the first portion of the second nanosheet stack 135 may be in-situ phosphorus doped. In other examples, the nanosheets of the second nanosheet stack may be undoped.

[0042] A source-side epitaxial layer (e.g., an RSD epitaxial layer) may be formed over the second nanosheet stack 135 to form a source (also referred to as a "source / drain") as part of an in-situ doping process or as an additional process. The source region 115 may be interchangeably referred to as a "source" or "source / drain" of the LDMOS 100. In some examples, the source-side epitaxial layer may be configured to laterally connect one or more second nanosheet stacks 135a to 135d to each other. For example, the epitaxial layer of the source region 115 may extend in a longitudinal direction such that it crosses one or more second nanosheet stacks 135a to 135d extending in the longitudinal direction, such as Figure 1 Described in.

[0043] Figure 2 2 is a schematic diagram of a cross section of LDMOS 100 , 200 taken across line xx according to various embodiments. The cross-sectional view of LDMOS 200 shows the different parts and structures described above but obscured in the top view. Thus, LDMOS 200 includes a substrate 280 having an undoped / lightly doped region 205, a first well region 210 and a second well region 215, a first trench isolation region 220, a second trench isolation region 225 and a third trench isolation region 230, a drain region 235, a gate 240, a source region 245, a first nanosheet stack 255, a second nanosheet stack 265, drain-side dummy gates 270 a to 270 b, and a source-side dummy gate 275. It should be noted that the various parts and components of LDMOS 200 are shown in FIG. Figure 2 Modifications to various components and other arrangements of LDMOS 200 are possible as schematically illustrated in FIG. 1 and according to various embodiments.

[0044] As shown in the cross-sectional view, the substrate 280 may include an undoped / lightly doped region 205. In various examples, the substrate 280 may be lightly doped. For example, in NLDMOS, the undoped / lightly doped region 205 is lightly boron doped (e.g., p-type). In various examples, the substrate 280 further includes a first well region 210 and a second well region 215. In various examples, the well regions 210, 215 may be doped regions of the substrate 280. For example, in NLDMOS, the first well region 210 may be p-type doped (e.g., boron doped), and the second well region 215 may be n-type doped (e.g., phosphorus doped). In various examples, the substrate 280 further includes trench isolation regions, such as first to third trench isolation regions 220 to 230. The trench isolation region may be a trench formed in the substrate and filled with an oxide material. In some examples, one or more of the first, second, and third trench isolation regions 220 to 230 may be shallow trench isolation (STI) regions. In some examples, one or more of the first, second, and third trench isolation regions 220 - 230 can be deep trench isolation (DTI) regions.

[0045] The first nanosheet stack 255 and the second nanosheet stack 265 may be disposed on the substrate 280, wherein the first nanosheet stack 255 is disposed on the second well region 215, and the second nanosheet stack 265 is at least partially disposed on the first well region 210 and at least partially disposed on the second well region 215. In some examples, the second nanosheet stack 265 may serve as a channel for current between the gate and the source. Compared to the fin, the first nanosheet stack 255 may further provide a larger effective width, thereby allowing a higher drive current.

[0046] Thus, in various embodiments, the drain region may be disposed between the third trench isolation region 230 and the second trench isolation region 225, wherein the respective nanosheets 255a to 255c of the first nanosheet stack 225 are at least partially disposed above and across the second trench isolation region 225 and the third trench isolation region 230. By providing the drain region 235 adjacent to the second trench isolation region 225 and the third trench isolation region 230, a lightly doped drain (LDD) region may be formed directly below the drain region 230 in the second well region 215 between the second trench isolation region 225 and the third trench isolation region 230, creating a current path from the drain region 235 through the second well region 215 to the drain region 245. In this way, the GAA structure may be used for high voltage LDMOS operation.

[0047] Figure 33 is a schematic top view of an alternative configuration of a GAA LDMOS FET 300 (hereinafter referred to as “LDMOS 300”) according to various embodiments. LDMOS 300 includes a drain region 305, a gate 310, and a source region 315 disposed on a substrate 320. LDMOS 300 further includes one or more nanosheet stacks 325a to 325d (collectively referred to as “nanosheet stacks 325”), a first drain side dummy gate 340a and a second drain side dummy gate 340b (collectively referred to as “drain side dummy gate 340”), and a source side dummy gate 345. It should be noted that various parts and components of LDMOS 300 are described in detail in detail. Figure 3 Modifications to the various components and other arrangements of LDMOS 300 are schematically illustrated in FIG. 1 , and according to various embodiments, are possible.

[0048] As previously addressed Figure 1 As described, the structure of LDMOS 300 may be disposed on substrate 320. Thus, substrate 320 may be a semiconductor substrate, such as, but not limited to, bulk silicon. In various embodiments, one or more nanosheet stacks 325a to 325d may be disposed on substrate 320. In some examples, the one or more nanosheet stacks may include only a single nanosheet stack (e.g., one nanosheet stack 325).

[0049] In some examples, the nanosheet stack 325 may be a nanosheet stack formed of alternating semiconductor materials, as previously described. In yet other examples, the nanosheets may be formed of the same material as the substrate. In yet other examples, the nanosheet stack 325 may be formed of alternating layers of nanosheets and spacers. As previously described, the individual nanosheet layers of the nanosheet stack 325 may be separated by dielectric spacers, such as metal oxide spacers.

[0050] and Figure 1 Compared to the nanosheet stacks 125 and 135 of the LDMOS 100 of the embodiment of the present invention, the nanosheets of the nanosheet stack 325 of the LDMOS 300 span the drain region 305, the gate 310, and the source region 315. In some examples, the nanosheets may be continuous (e.g., structurally continuous) from the first drain-side dummy gate 340 (e.g., at least partially disposed within the first dummy gate 340) to the source-side dummy gate 345. In this way, individual nanosheets may be configured to provide respective channels from the source region 305 to the source region 315 (e.g., more specifically, from the drain region 305 to the gate 310, and from the gate 310 to the source region 315).

[0051] Next, the gate 310, the drain side dummy gates 340a-340b, and the source side dummy gate 345 may be formed by depositing a gate oxide (e.g., a dielectric layer) over the nanosheet stack 325, followed by forming the gate 310 and the drain side dummy gates 340a-340b and the source side dummy gate 345 from the gate oxide. In various embodiments, the drain region 305 may be disposed on the first side of the gate 310, between the drain side dummy gates 340a-340b. In some embodiments, the drain region 305 includes a highly doped portion of the nanosheet stack 325. In various examples, the nanosheet stack 325 may include a highly doped portion that is in-situ doped to form at least a portion of the drain region 305. In some examples, in the case of NLDMOS, all or part of the nanosheet stack 325 may be in-situ phosphorus doped. In other examples, the nanosheets may be undoped nanosheets.

[0052] In some embodiments, a RSD epitaxial layer (hereinafter referred to as "epilayer") may be formed above the nanosheet stack. The epitaxial layer may be heavily doped to form a drain structure (also referred to as "drain / source") of the drain region 305. In some examples, the epitaxial layer may be configured to laterally connect one or more nanosheet stacks 325a to 325d to each other.

[0053] The source region 315 may be disposed on a second side of the gate 310 (e.g., opposite the first side of the gate 310). For example, in some embodiments, the source region 315 is disposed between the source-side dummy gate 345 and the gate 310. Like the drain region 305, the source region 315 may include a highly doped portion of the nanosheet stack 325. Specifically, the nanosheet stack 325 may include a first highly doped portion that is in-situ doped to form at least a portion of the source region 315. In some examples, in the case of NLDMOS, the first portion of the nanosheet stack 325 may be in-situ phosphorus doped. In other examples, the nanosheets of the second nanosheet stack may be undoped.

[0054] A source-side epitaxial layer (e.g., RSD epitaxial layer) may be formed over the nanosheet stack 325 to form a source (also referred to as a "source / drain") as part of or in addition to the in-situ doping process. In some examples, the source-side epitaxial layer may be configured to laterally interconnect one or more nanosheet stacks 325a to 325d.

[0055] Figure 4is a schematic diagram of a cross section of LDMOS 300, 400 taken across line 11 according to various embodiments. The cross-sectional view of LDMOS 400 shows the different parts and structures described above but obscured in the top view. Thus, LDMOS 400 includes a substrate 480 having an undoped / lightly doped region 405, a first well region 410 and a second well region 415, a first trench isolation region 420, an LDD region 425 and a second trench isolation region 430, a drain region 435, a gate 440, a source region 445, a nanosheet stack 455, drain side dummy gates 470a to 470b, and a source side dummy gate 475. It should be noted that Figure 4 Various portions and components of LDMOS 400 are schematically illustrated in FIG. 4 , and modifications to the various components and other arrangements of LDMOS 400 are possible according to various embodiments.

[0056] and Figure 2 Compared to the LDMOS 200 of the embodiment of the present invention, the LDMOS 400 includes first and second trench isolation regions, such as a first trench isolation region 420 and a second trench isolation region 430, wherein the first trench isolation region 420 is disposed at one end of the first well region 410 and the second trench isolation region 430 is disposed at the opposite end of the second well region 415. It is worth noting that the trench isolation region between the first trench isolation region 420 and the second trench isolation region 430 has been removed, which is conducive to forming an LDD region 425 in the area between the gate 440 and the source region 435.

[0057] As previously described, the trench isolation region may be a trench formed in the substrate and filled with an oxide material. One or more of the first trench isolation region 420 and the second trench isolation region 430 may be a shallow trench isolation (STI) region. In some examples, one or more of the first trench isolation region 420 and the second trench isolation region 430 may be a deep trench isolation (DTI) region.

[0058] The nanosheet stack 455 may be disposed on the substrate 480, extending through the first well region 410 and the second well region 415. In various embodiments, individual nanosheets 455a-455c of the nanosheet stack 455 may be current channels between the drain and the gate, and further between the gate and the source.

[0059] By providing LDD 425 between drain region 405 and gate 445, a current path is created through nanosheets 455a to 455c and through second well region 415. LDD regions are provided through nanosheet stack 455. In this way, the GAA structure can be used for high voltage LDMOS operation, such as in LDMOS 300, while further having a reduced on-resistance (R on ) (relative to the LDD formed in the second well region 415 ), wherein the LDD 425 is formed by the nanosheet stack 455 .

[0060] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that a variety of modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Further, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functions belong to one or more system components, unless the context dictates otherwise, according to some embodiments, this functionality may be distributed among various other system components.

[0061] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context dictates otherwise. In addition, processes described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular architecture and / or with respect to one system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without some features are described for ease of description and explanation of aspects of those embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted in other described embodiments unless the context dictates otherwise. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: substrate; two or more first sheets disposed on the substrate; a gate disposed on the substrate and at least a portion of the two or more first sheets; a first epitaxial layer disposed on the substrate on a first side of the gate and on at least a portion of the two or more first sheets; and At least a portion of the two or more first thin slices extends longitudinally from the gate to the first epitaxial layer. 2 . The apparatus of claim 1 , wherein each of the two or more first sheets is separated by a respective dielectric spacer.

3. The apparatus according to claim 1, further comprising: two or more second sheets disposed on the substrate on a second side of the gate; and A second epitaxial layer is disposed on the second side of the gate and further disposed at least partially over the two or more second sheets. 4 . The apparatus of claim 3 , wherein each of the two or more second sheets are separated from each other by a respective dielectric spacer.

5. The apparatus of claim 3 , wherein each respective first sheet of the two or more first sheets and each respective second sheet of the two or more second sheets are connected as parts of the same sheet, wherein each sheet is continuous from the first epitaxial layer to the second epitaxial layer, and wherein the two or more first sheets and the two or more second sheets are parts of two or more channels coupling the first epitaxial layer and the second epitaxial layer, respectively.

6. The apparatus of claim 5, wherein the two or more channels form at least part of a lightly doped drain.

7. The apparatus of claim 5, wherein the two or more channels are disposed on the substrate.

8. The apparatus of claim 2, wherein the substrate further comprises a shallow trench isolation region disposed between the second epitaxial layer and the gate, wherein a lightly doped drain is formed in the substrate below the shallow trench isolation region, between the second epitaxial layer and the gate.

9. The apparatus of claim 1, further comprising one or more dummy dielectric layers disposed on the substrate, wherein the two or more first sheets are configured to extend into one or more field dielectric layers.

10. A semiconductor die, comprising: substrate; A laterally diffused metal oxide semiconductor transistor is disposed on the substrate, and the laterally diffused metal oxide semiconductor transistor comprises: a gate including a gate dielectric layer disposed on the substrate; a source comprising a first epitaxial layer disposed on the substrate on a first side of the gate dielectric layer; and Two or more first thin sheets are disposed on the substrate, wherein at least portions of the two or more first thin sheets extend longitudinally from the gate dielectric layer to the first epitaxial layer. 11 . The semiconductor die of claim 10 , wherein the two or more first thin slices are further disposed at least partially within the first epitaxial layer, wherein the first epitaxial layer is grown over the two or more first thin slices.

12. The semiconductor die of claim 10, further comprising: a drain comprising a second epitaxial layer disposed on the substrate on a second side of the gate dielectric layer; and Two or more second thin sheets are at least partially disposed within the second epitaxial layer, wherein the second epitaxial layer is grown over the two or more second thin sheets.

13. The semiconductor die of claim 12 , wherein each respective first sheet of the two or more first sheets and each respective second sheet of the two or more second sheets are connected as parts of the same sheet, wherein each sheet is continuous from the first epitaxial layer to the second epitaxial layer, and wherein the two or more first sheets and the two or more second sheets are parts of two or more channels coupling the first epitaxial layer and the second epitaxial layer, respectively.

14. The semiconductor die of claim 13, wherein the two or more channels are disposed on the substrate, and wherein between the gate dielectric layer and the second epitaxial layer, the two or more channels form at least a portion of a lightly doped drain region.

15. The semiconductor die of claim 10, wherein each first sheet of the two or more first sheets is separated by a respective dielectric spacer.

16. A semiconductor device comprising: a gate disposed on the substrate and at least a portion of the two or more first sheets; a source comprising a first epitaxial layer disposed on the substrate on a first side of the gate and on at least a portion of the two or more first sheets; and Two or more first thin sheets are disposed on the substrate, wherein at least portions of the two or more first thin sheets extend longitudinally from the gate to the first epitaxial layer.

17. The semiconductor device according to claim 16, further comprising: two or more second sheets disposed on the substrate on a second side of the gate; and A drain includes a second epitaxial layer disposed on the second side of the gate and further disposed at least partially over the two or more second sheets. 18 . The semiconductor device according to claim 17 , wherein each of the two or more second thin sheets are separated from each other by a dielectric spacer.

19. The semiconductor device of claim 17 , wherein each corresponding first thin sheet of the two or more first thin sheets and each corresponding second thin sheet of the two or more second thin sheets are connected as parts of the same thin sheet, wherein each thin sheet is continuous from the first epitaxial layer to the second epitaxial layer, and wherein the two or more first thin sheets and the two or more second thin sheets are parts of two or more channels coupling the first epitaxial layer and the second epitaxial layer, respectively.

20. The semiconductor device of claim 19, wherein the two or more channels are disposed at least partially above the substrate, and wherein the two or more channels form at least a portion of a lightly doped drain.

Images