A radiation hardened LDMOS device structure and preparation method

Abstract

The present invention discloses a radiation-hardened LDMOS device structure and a preparation method, which belongs to the field of integrated circuits, and includes a P-type silicon substrate, an N-type buried layer, a P-epitaxial layer, a P-body region, an N-drift region, a Psink heavily doped region, an N+ heavily doped region, a P+ heavily doped region, an STI region, and a polycrystalline gate region. The polycrystalline gate region is used to cut off the leakage channel between the drain and the source, thereby improving the total dose radiation resistance of the device; the N-type buried layer in the structure is located between the P-type silicon substrate and the P-epitaxial layer, so that the device forms potential isolation and realizes the high-side application of the device; the Psink heavily doped region is added at the P-body region position, and the injection depth of the heavily doped region is increased at the same time, so as to reduce the path length and resistivity of the non-equilibrium carrier flowing through the P-body region, and improve the single particle radiation resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a radiation-hardened LDMOS device structure and a preparation method thereof. Background Art

[0002] BCD process technology is an innovative integrated circuit process technology invented by SGS Thomson in the mid-1980s. BCD process technology integrates different devices such as bipolar devices with precise analog functions, digitally designed CMOS devices, and high-voltage and high-power DMOS devices on the same chip. The analog circuit serves as the interface between the outside world and the digital system, the CMOS logic circuit serves as the core of signal processing, and the high-voltage / power part is used to drive the external load.

[0003] LDMOS is widely used because it is more compatible with CMOS process. LDMOS is a power device with double diffusion structure. This technology is to implant twice in the same source / drain area, once with a higher concentration of arsenic (As) and the other with a lower concentration of boron (B). After the implantation, a high-temperature push-junction process is performed. Since boron diffuses faster than arsenic, it will diffuse farther laterally under the gate boundary to form a channel with a concentration gradient. Its channel length is determined by the difference in the distance of the two lateral diffusions. In order to increase the breakdown voltage, there is a drift region between the active region and the drain region. The drift region in LDMOS is the key to the design of this type of device. The impurity concentration in the drift region is relatively low. Therefore, when LDMOS is connected to high voltage, the drift region can withstand higher voltage due to its high resistance.

[0004] With the continuous development of aerospace systems, more and more power supply products are required to meet performance requirements such as wide voltage input range and high power driving capability. The radiation-resistant BCD process can be used to produce the main core components required for aerospace systems such as aerospace satellites, spacecraft, and space stations. However, the radiation-resistant power management chips developed using non-reinforced processes cannot meet the requirements of aerospace applications, which seriously restricts the development of radiation-resistant core components in this field in my country.

[0005] In the radiation-hardened BCD process, the radiation hardening of LDMOS devices is the core difficulty, and it is necessary to solve the device problems caused by the total dose radiation effect and single particle radiation effect of LDMOS devices.

[0006] The total dose radiation effect is due to the fact that the polysilicon gate produces a parasitic transistor in the transition region between the field oxygen and the gate oxide in the transistor made by the self-aligned process. This parasitic transistor is very sensitive to the total dose effect. Because the field oxygen and the gate oxide layer will ionize electron-hole pairs under radiation conditions; due to the capture effect of the trap, the Si / SiO 2System SiO 2 Positive charges accumulate on one side, forming interface states, which seriously affect the IV characteristics of the transistor. As the radiation dose increases, the leakage current of the edge parasitic transistor also rises rapidly. When the leakage current increases to a level close to the on-state current of the intrinsic transistor, the transistor will be permanently turned on, causing device failure. The total dose radiation effect of ionizing radiation on LDMOS devices is more significant than that on CMOS devices, mainly because the gate oxide of the device is thicker and the oxide layer isolation structure is relatively more. The radiation-induced oxide layer trap charges and their interface states will more obviously cause changes in electrical characteristics such as threshold voltage drift, transconductance drop, and breakdown voltage reduction, and even device failure.

[0007] The single event radiation effect mainly solves the single event gate breakdown and single event burnout effects of LDMOS devices. Since the single event gate breakdown (SEGR) of LDMOS devices is caused by the accumulation of Si / SiO in the gate-drain overlap region, 2 The local critical high electric field of the gate dielectric caused by the induced charge on the interface causes local dielectric breakdown, so the most direct and effective method is to reinforce the gate to increase the breakdown voltage of the gate dielectric; because the LDMOS device has an n+pn- parasitic transistor structure in the source region. When high-energy particles are incident from the source region or the channel region into the device, a large number of electron-hole pairs are ionized. The electrons drift to the drain region under the action of the lateral electric field, and some holes drift and diffuse to the p+ region under the action of the electric field, generating a voltage drop on the distributed resistance of the pp+ region, causing the parasitic transistor to turn on. Since the LDMOS device operates under high voltage and high current, it is easy to generate current overload after the parasitic transistor is turned on, causing the device to burn out. Summary of the invention

[0008] The object of the present invention is to provide a radiation-hardened LDMOS device structure and a preparation method thereof, so as to solve the problem of device failure caused by total dose radiation effect and single particle radiation effect of the device.

[0009] In order to solve the above technical problems, the present invention provides a radiation-hardened LDMOS device structure, including a P-type silicon substrate, an N-type buried layer, a P-epitaxial layer, a P-body region, an N-drift region, a Psink heavily doped region, an N+ heavily doped region, a P+ heavily doped region, an STI region, and a polycrystalline gate region;

[0010] The N-type buried layer is located above the P-type silicon substrate, and the P-epitaxial layer is located above the N-type buried layer; the P-body region, the N-drift region, the Psink heavily doped region, the N+ heavily doped region, the P+ heavily doped region, and the STI region are located in the P-epitaxial layer; the polycrystalline gate region is located on the outer surface of the P-epitaxial layer;

[0011] The P-body region and the N-drift region both have N+ heavily doped regions, the N+ heavily doped region in the P-body region is a source, and the N+ heavily doped region in the N-drift region is a drain; the P+ heavily doped region is located in the P-body region and serves as a body electrode;

[0012] The polycrystalline gate region serves as a gate and is an annular structure. The drain is located in the middle region of the annular structure, and the source is located at the periphery of the annular structure. The P+ heavily doped region contacts the N+ heavily doped region to form a source-body short-circuited structure.

[0013] Optionally, the N-drift region is located in a middle region of the P-epitaxial layer, the P-body region is located at the periphery of the N-drift region, and the Psink heavily doped region is located below the P-body region.

[0014] Optionally, the spacing L of the polycrystalline gate region space The gate longitudinal width W of the radiation-hardened LDMOS device structure is 2 to 10 μm; device The area L where the P-body region overlaps with the polycrystalline gate region is 20 to 100 μm; device is 0.2 to 0.5 μm; the lateral width L of the polycrystalline gate region gate The region L where the N-drift region overlaps with the polycrystalline gate region is 0.6 to 1.25 μm. drift It is 0.25~0.6μm.

[0015] Optionally, the concentration of the N-type buried layer is 1E16-1E17cm -3 ; The thickness of the P-epitaxial layer is 4 to 6 μm; The concentration of the P-epitaxial layer is 1E14 to 1E15 cm -3 ; The concentration of the N-drift region is 1E17~3E17cm -3 ;

[0016] The doping concentration of the Psink heavily doped region is greater than the doping concentration of the P-body region; the concentration of the P-body region is 5E17-1E18cm -3 The concentration of the Psink heavily doped region is 1E18 to 5E18 cm -3 .

[0017] Optionally, the doping concentration of the N+ heavily doped region is greater than the doping concentration of the N-drift region; and the doping concentration of the P+ heavily doped region is greater than the doping concentration of the P-body region.

[0018] Optionally, a cutting angle R of the polycrystalline gate region is 30° to 60°.

[0019] The present invention also provides a method for preparing a radiation-hardened LDMOS device structure, comprising:

[0020] Providing a P-type silicon substrate, and sequentially forming an N-type buried layer and a P-epitaxial layer on the surface thereof;

[0021] Performing an oxidation on the P-epitaxial layer to form a thin oxide buffer layer, and then depositing silicon nitride to form a hard mask layer;

[0022] The surface is coated with photoresist, and the hard mask layer, thin oxide buffer layer and P-epitaxial layer are etched in sequence to complete the STI shallow trench isolation and form the active area;

[0023] Remove the remaining photoresist, fill the STI groove by high-density plasma deposition, remove the hard mask layer and the thin oxide buffer layer by chemical mechanical polishing and planarization, and form an STI shallow trench isolation layer;

[0024] The surface is coated with photoresist, the Psink region is photolithographically processed, and boron ions are injected to form a Psink heavily doped region;

[0025] Removing the remaining photoresist, re-coating the surface with photoresist, performing N-drift region photolithography, and injecting phosphorus ions to form an N-drift region;

[0026] Remove the remaining photoresist, deposit polycrystalline on the surface, re-coat the photoresist, perform P-body photolithography, etch away the polycrystalline in the P-body region, implant boron ions and arsenic ions, and form the P-body region after annealing;

[0027] Then, gate photolithography is performed to etch away the polycrystalline outside the gate to form a gate region;

[0028] Remove the remaining photoresist, re-coat the surface with photoresist, perform P+ region photolithography, and inject boron ions to form a P+ region;

[0029] Remove the remaining photoresist, re-coat the surface with photoresist, perform N+ region photolithography, and inject phosphorus ions to form an N+ region;

[0030] Remove the remaining photoresist, re-coat the surface with photoresist, perform P+ area, N+ area and gate photolithography, deposit metal, use chemical mechanical polishing for flattening, remove the surface metal, remove the remaining photoresist, and complete the preparation of the metal electrode area.

[0031] Optionally, the method for forming the N-type buried layer is: implanting phosphorus ions on the surface of the P-type silicon substrate by a high-energy ion implanter, and annealing to form the N-type buried layer.

[0032] In the radiation-hardened LDMOS device structure and preparation method provided by the present invention, by optimizing the design of the LDMOS device layout, a ring gate structure is used to replace the strip gate structure, and the leakage channel at the edge of the field isolation is effectively cut off, thereby solving the source and drain leakage problem caused by the total dose radiation effect of the LDMOS device; by adding a P-type heavily doped area below the P-body region, the electric field distribution of the body region is optimized, and the on-resistance of the body region is reduced. The non-equilibrium holes ionized in the drift region and the P-well by the radiation effect can easily flow out from the body contact region through the low-resistance path of the P-type heavily doped area, thereby avoiding the opening of the parasitic tube and suppressing the occurrence of device burning caused by the parasitic opening current. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a cross-sectional schematic diagram of a radiation-hardened LDMOS device structure provided by the present invention;

[0034] Figure 2 is a top view schematic diagram of a radiation-hardened LDMOS device structure provided by the present invention;

[0035] Figure 3 It is a schematic diagram of forming an N-type buried layer and a P-epitaxial layer on the surface of a P-type silicon substrate;

[0036] Figure 4 is a schematic diagram of forming a thin oxide buffer layer and a hard mask layer on a P-epitaxial layer;

[0037] Figure 5 It is a schematic diagram of completing STI shallow trench isolation to form an active area;

[0038] Figure 6 It is a schematic diagram of removing the hard mask layer and the thin oxide buffer layer to form an STI shallow trench isolation layer;

[0039] Figure 7 It is a schematic diagram of injecting boron ions to form a heavily doped region of Psink;

[0040] Figure 8 is a schematic diagram of implanting phosphorus ions to form an N-drift region;

[0041] Fig. 9 is a schematic diagram of performing photolithography of the P-body region to form the P-body region;

[0042] Fig.10 It is a schematic diagram of etching away the polycrystalline outside the gate to form the gate region;

[0043] Fig.11 It is a schematic diagram of implanting boron ions to form a P+ region;

[0044] Fig.12 It is a schematic diagram of implanting phosphorus ions to form an N+ region;

[0045] Fig.13 Schematic diagram of completing the preparation of the metal electrode area. DETAILED DESCRIPTION

[0046] The radiation-hardened LDMOS device structure and preparation method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0047] Embodiment 1

[0048] The present invention provides a radiation-hardened LDMOS device structure, the cross section of which is as follows: Figure 1 As shown, it includes a P-type silicon substrate 1, an N-type buried layer 2, a P-epitaxial layer 3, a P-body region 4, an N-drift region 5, a Psink heavily doped region 6, an N+ heavily doped region 7, a P+ heavily doped region 8, an STI region 9, and a polycrystalline gate region 10; the N-type buried layer 2 is located above the P-type silicon substrate 1, and the P-epitaxial layer 3 is located above the N-type buried layer 2; the P-body region 4, the N-drift region 5, the Psink heavily doped region 6, the N+ heavily doped region 7, the P+ heavily doped region 8, and the STI region 9 are located in the P-epitaxial layer 3; the polycrystalline gate region 10 is located on the outer surface of the P-epitaxial layer 3.

[0049] Please continue reading Figure 1 Both the P-body region 4 and the N-drift region 5 have N+ heavily doped regions 7, the N+ heavily doped region 7 in the P-body region 4 is the source, and the N+ heavily doped region 7 in the N-drift region 5 is the drain; the P+ heavily doped region 8 is located in the P-body region 4 and serves as the body pole; the polycrystalline gate region 10 is the gate.

[0050] The polycrystalline gate region 10 is an annular structure, the drain is located in the middle region of the annular structure, the source is located at the periphery of the annular structure, the P+ heavily doped region 8 is in contact with the N+ heavily doped region 7, forming a source-body short-circuited structure. The N-drift region 5 is located in the middle region of the P-epitaxial layer 3, the P-body region 4 is located at the periphery of the N-drift region 5, and the Psink heavily doped region 6 is located below the P-body region 4.

[0051] The polycrystalline gate region 10 is used to cut off the leakage channel between the drain and the source, thereby improving the device's resistance to total radiation dose; in the structure, the N-type buried layer is located between the P-type silicon substrate and the P-epitaxial layer, so that the device forms potential isolation and realizes the high-side application of the device; a Psink heavily doped region 6 is added at the P-body region position, and the injection depth of the heavily doped region is increased at the same time, thereby reducing the path length and resistivity of the non-equilibrium carriers flowing through the P-body region 4, thereby improving the device's resistance to single-particle radiation.

[0052] The top view of the radiation hardened LDMOS device structure is shown in FIG. Figure 2 As shown, the spacing L of the polycrystalline gate region 10 space The gate longitudinal width W of the radiation-hardened LDMOS device structure is 2 to 10 μm; device The area L where the P-body region 4 overlaps with the polycrystalline gate region 10 is 20 to 100 μm; device The lateral width L of the polycrystalline gate region 10 is 0.2-0.5 μm; gate The region L where the N-drift region 5 overlaps with the polycrystalline gate region 10 is 0.6 to 1.25 μm. drift The concentration of the N-type buried layer 2 is 1E16-1E17cm -3 ; The thickness of the P-epitaxial layer 3 is 4 to 6 μm; The concentration of the P-epitaxial layer 3 is 1E14 to 1E15 cm -3 The concentration of the N-drift region 5 is 1E17 to 3E17 cm -3 ; The doping concentration of the Psink heavily doped region 6 is greater than the doping concentration of the P-body region 4; The concentration of the P-body region 4 is 5E17~1E18cm -3 The concentration of the Psink heavily doped region 6 is 1E18 to 5E18 cm -3 The doping concentration of the N+ heavily doped region 7 is greater than the doping concentration of the N-drift region 5; the doping concentration of the P+ heavily doped region 8 is greater than the doping concentration of the P-body region 4. The cutting angle R of the polycrystalline gate region 10 is 30° to 60°.

[0053] Embodiment 2

[0054] The present invention also provides a method for preparing a radiation-hardened LDMOS device structure, which is used to prepare Figure 1 He Ru Figure 2 The radiation hardened LDMOS device structure shown in the figure comprises the following steps:

[0055] like Figure 3 As shown, a P-type silicon substrate is provided, phosphorus ions are implanted on the surface of the substrate by a high-energy ion implanter, an N-type buried layer is formed by annealing, and a P-epitaxial layer is grown on the surface of the N-type buried layer;

[0056] like Figure 4 As shown, an oxidation is performed on the P-epitaxial layer to form a thin oxide buffer layer, and then silicon nitride is deposited to form a hard mask layer;

[0057] like Figure 5 As shown, the surface is coated with photoresist, and the hard mask layer, the thin oxide buffer layer and the P-epitaxial layer are etched in sequence to complete the STI shallow trench isolation and form an active area;

[0058] like Figure 6 As shown, the remaining photoresist is removed, the STI groove is filled by high-density plasma deposition, and the hard mask layer and the thin oxide buffer layer are removed by chemical mechanical polishing planarization to form an STI shallow trench isolation layer;

[0059] like Figure 7 As shown, the surface is coated with photoresist, the Psink region is photolithographically processed, and boron ions are injected to form a Psink heavily doped region;

[0060] like Figure 8 As shown, the remaining photoresist is removed, the surface is re-coated with photoresist, the N-drift region is photolithographically processed, and phosphorus ions are implanted to form the N-drift region;

[0061] like Fig. 9 As shown, the remaining photoresist is removed, polycrystalline is deposited on the surface, and then the photoresist is re-coated, and the P-body region is photolithographically etched, the polycrystalline in the P-body region is etched away, boron ions and arsenic ions are injected, and the P-body region is formed after annealing;

[0062] like Fig.10 As shown, gate photolithography is then performed to etch away the polycrystalline outside the gate to form a gate region;

[0063] like Fig.11 As shown, the remaining photoresist is removed, the surface is re-coated with photoresist, the P+ region is photolithographically processed, and boron ions are injected to form a P+ region;

[0064] like Fig.12 As shown, the remaining photoresist is removed, the surface is re-coated with photoresist, N+ region is photolithographically processed, phosphorus ions are implanted, and N+ region is formed;

[0065] like Fig.13 As shown, the remaining photoresist is removed, the surface is re-coated with photoresist, the P+ area, N+ area and gate are photolithographically processed, metal is deposited, chemical mechanical polishing is used for flattening, the surface metal is removed, the remaining photoresist is removed, and the preparation of the metal electrode area is completed.

[0066] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A radiation hardened LDMOS device structure, characterized in that: It comprises a P-type silicon substrate (1), an N-type buried layer (2), a P-epitaxial layer (3), a P-body region (4), an N-drift region (5), a Psink heavily doped region (6), an N+ heavily doped region (7), a P+ heavily doped region (8), an STI region (9), and a polycrystalline gate region (10); The N-type buried layer (2) is located above the P-type silicon substrate (1); the P-epitaxial layer (3) is located above the N-type buried layer (2); the P-body region (4), the N-drift region (5), the Psink heavily doped region (6), the N+ heavily doped region (7), the P+ heavily doped region (8), and the STI region (9) are located in the P-epitaxial layer (3); and the polycrystalline gate region (10) is located on the outer surface of the P-epitaxial layer (3); Both the P-body region (4) and the N-drift region (5) have N+ heavily doped regions (7), the N+ heavily doped region (7) in the P-body region (4) is a source, and the N+ heavily doped region (7) in the N-drift region (5) is a drain; the P+ heavily doped region (8) is located in the P-body region (4) and serves as a body electrode; The polycrystalline gate region (10) serves as a gate and is an annular structure, the drain is located in the middle region of the annular structure, the source is located at the periphery of the annular structure, and the P+ heavily doped region (8) is in contact with the N+ heavily doped region (7) to form a source-body short-circuited structure; The N-drift region (5) is located in the middle region of the P-epitaxial layer (3), the P-body region (4) is located at the periphery of the N-drift region (5), and the Psink heavily doped region (6) is located below the P-body region (4); The diameter L of the inner ring of the polycrystalline gate region (10) space 2~10μm; the gate longitudinal width W of the radiation-hardened LDMOS device structure device is 20 to 100 μm; the width L of the overlapping region between the P-body region (4) and the polycrystalline gate region (10) device is 0.2~0.5μm; the lateral width L of the polycrystalline gate region (10) gate is 0.6 to 1.25 μm; the width L of the overlapping region between the N-drift region (5) and the polycrystalline gate region (10) drift 0.25~0.6μm; The concentration of N-type buried layer (2) is 1E16~1E17cm -3 ; The thickness of the P-epitaxial layer (3) is 4~6μm; The concentration of the P-epitaxial layer (3) is 1E14~1E15 cm -3 ; The concentration of N-drift region (5) is 1E17~3E17cm -3 ; The doping concentration of the Psink heavily doped region (6) is greater than the doping concentration of the P-body region (4); the concentration of the P-body region (4) is 5E17~1E18 cm -3 , the concentration of Psink heavily doped region (6) is 1E18~5E18 cm -3 .

2. The radiation hardened LDMOS device structure according to claim 1, characterized in that: The doping concentration of the N+ heavily doped region (7) is greater than the doping concentration of the N-drift region (5); and the doping concentration of the P+ heavily doped region (8) is greater than the doping concentration of the P-body region (4).

3. The radiation hardened LDMOS device structure according to claim 1, wherein: The cutting angle R of the polycrystalline gate region (10) is 30° to 60°.

4. A method for preparing a radiation-hardened LDMOS device structure according to any one of claims 1 to 3, characterized in that: include: Providing a P-type silicon substrate, and sequentially forming an N-type buried layer and a P-epitaxial layer on the surface thereof; Performing an oxidation on the P-epitaxial layer to form a thin oxide buffer layer, and then depositing silicon nitride to form a hard mask layer; The surface is coated with photoresist, and the hard mask layer, thin oxide buffer layer and P-epitaxial layer are etched in sequence to complete the STI shallow trench isolation and form the active area; Remove the remaining photoresist, fill the STI groove by high-density plasma deposition, remove the hard mask layer and the thin oxide buffer layer by chemical mechanical polishing and planarization, and form an STI shallow trench isolation layer; The surface is coated with photoresist, the Psink region is photolithographically processed, and boron ions are injected to form a Psink heavily doped region; Removing the remaining photoresist, re-coating the surface with photoresist, performing N-drift region photolithography, and injecting phosphorus ions to form an N-drift region; Remove the remaining photoresist, deposit polycrystalline on the surface, re-coat the photoresist, perform P-body photolithography, etch away the polycrystalline in the P-body region, implant boron ions and arsenic ions, and form the P-body region after annealing; Then, gate photolithography is performed to etch away the polycrystalline outside the gate to form a gate region; Remove the remaining photoresist, re-coat the surface with photoresist, perform P+ region photolithography, and inject boron ions to form a P+ region; Remove the remaining photoresist, re-coat the surface with photoresist, perform N+ region photolithography, and inject phosphorus ions to form an N+ region; Remove the remaining photoresist, re-coat the surface with photoresist, perform P+ area, N+ area and gate photolithography, deposit metal, use chemical mechanical polishing for flattening, remove the surface metal, remove the remaining photoresist, and complete the preparation of the metal electrode area.

5. The method for preparing a radiation-hardened LDMOS device structure according to claim 4, characterized in that: The method for forming the N-type buried layer is as follows: phosphorus ions are implanted on the surface of a P-type silicon substrate by a high-energy ion implanter, and the N-type buried layer is formed by annealing.

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